drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_navi10.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "navi10_ppt.h"
  35 #include "smu_v11_0_pptable.h"
  36 #include "smu_v11_0_ppsmc.h"
  37
  38 #define MSG_MAP(msg, index) \
  39         [SMU_MSG_##msg] = index
  40
  41 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
  42         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  43         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  44         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  45         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  46         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  47         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  48         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  49         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  50         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  51         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  52         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  53         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  54         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  55         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  56         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  57         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  58         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  59         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  60         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  61         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  62         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  63         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  64         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  65         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  66         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  67         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  68         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  69         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  70         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  71         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  72         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  73         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  74         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  75         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  76         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  77         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  78         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  79         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  80         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  81         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  82         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  83         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  84         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  85         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
  86         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
  87         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
  88         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
  89         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
  90         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  91         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
  92         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
  93         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
  94         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
  95         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
  96         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
  97         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
  98         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
  99         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 100         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 101         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 102         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 103         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 104 };
 105
 106 static int navi10_clk_map[SMU_CLK_COUNT] = {
 107         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 108         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 109         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 110         CLK_MAP(FCLK, PPCLK_SOCCLK),
 111         CLK_MAP(UCLK, PPCLK_UCLK),
 112         CLK_MAP(MCLK, PPCLK_UCLK),
 113         CLK_MAP(DCLK, PPCLK_DCLK),
 114         CLK_MAP(VCLK, PPCLK_VCLK),
 115         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 116         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 117         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 118         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 119 };
 120
 121 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 122         FEA_MAP(DPM_PREFETCHER),
 123         FEA_MAP(DPM_GFXCLK),
 124         FEA_MAP(DPM_GFX_PACE),
 125         FEA_MAP(DPM_UCLK),
 126         FEA_MAP(DPM_SOCCLK),
 127         FEA_MAP(DPM_MP0CLK),
 128         FEA_MAP(DPM_LINK),
 129         FEA_MAP(DPM_DCEFCLK),
 130         FEA_MAP(MEM_VDDCI_SCALING),
 131         FEA_MAP(MEM_MVDD_SCALING),
 132         FEA_MAP(DS_GFXCLK),
 133         FEA_MAP(DS_SOCCLK),
 134         FEA_MAP(DS_LCLK),
 135         FEA_MAP(DS_DCEFCLK),
 136         FEA_MAP(DS_UCLK),
 137         FEA_MAP(GFX_ULV),
 138         FEA_MAP(FW_DSTATE),
 139         FEA_MAP(GFXOFF),
 140         FEA_MAP(BACO),
 141         FEA_MAP(VCN_PG),
 142         FEA_MAP(JPEG_PG),
 143         FEA_MAP(USB_PG),
 144         FEA_MAP(RSMU_SMN_CG),
 145         FEA_MAP(PPT),
 146         FEA_MAP(TDC),
 147         FEA_MAP(GFX_EDC),
 148         FEA_MAP(APCC_PLUS),
 149         FEA_MAP(GTHR),
 150         FEA_MAP(ACDC),
 151         FEA_MAP(VR0HOT),
 152         FEA_MAP(VR1HOT),
 153         FEA_MAP(FW_CTF),
 154         FEA_MAP(FAN_CONTROL),
 155         FEA_MAP(THERMAL),
 156         FEA_MAP(GFX_DCS),
 157         FEA_MAP(RM),
 158         FEA_MAP(LED_DISPLAY),
 159         FEA_MAP(GFX_SS),
 160         FEA_MAP(OUT_OF_BAND_MONITOR),
 161         FEA_MAP(TEMP_DEPENDENT_VMIN),
 162         FEA_MAP(MMHUB_PG),
 163         FEA_MAP(ATHUB_PG),
 164 };
 165
 166 static int navi10_table_map[SMU_TABLE_COUNT] = {
 167         TAB_MAP(PPTABLE),
 168         TAB_MAP(WATERMARKS),
 169         TAB_MAP(AVFS),
 170         TAB_MAP(AVFS_PSM_DEBUG),
 171         TAB_MAP(AVFS_FUSE_OVERRIDE),
 172         TAB_MAP(PMSTATUSLOG),
 173         TAB_MAP(SMU_METRICS),
 174         TAB_MAP(DRIVER_SMU_CONFIG),
 175         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 176         TAB_MAP(OVERDRIVE),
 177         TAB_MAP(I2C_COMMANDS),
 178         TAB_MAP(PACE),
 179 };
 180
 181 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 182         PWR_MAP(AC),
 183         PWR_MAP(DC),
 184 };
 185
 186 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 187 {
 188         int val;
 189         if (index > SMU_MSG_MAX_COUNT)
 190                 return -EINVAL;
 191
 192         val = navi10_message_map[index];
 193         if (val > PPSMC_Message_Count)
 194                 return -EINVAL;
 195
 196         return val;
 197 }
 198
 199 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 200 {
 201         int val;
 202         if (index >= SMU_CLK_COUNT)
 203                 return -EINVAL;
 204
 205         val = navi10_clk_map[index];
 206         if (val >= PPCLK_COUNT)
 207                 return -EINVAL;
 208
 209         return val;
 210 }
 211
 212 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 213 {
 214         int val;
 215         if (index >= SMU_FEATURE_COUNT)
 216                 return -EINVAL;
 217
 218         val = navi10_feature_mask_map[index];
 219         if (val > 64)
 220                 return -EINVAL;
 221
 222         return val;
 223 }
 224
 225 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 226 {
 227         int val;
 228         if (index >= SMU_TABLE_COUNT)
 229                 return -EINVAL;
 230
 231         val = navi10_table_map[index];
 232         if (val >= TABLE_COUNT)
 233                 return -EINVAL;
 234
 235         return val;
 236 }
 237
 238 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 239 {
 240         int val;
 241         if (index >= SMU_POWER_SOURCE_COUNT)
 242                 return -EINVAL;
 243
 244         val = navi10_pwr_src_map[index];
 245         if (val >= POWER_SOURCE_COUNT)
 246                 return -EINVAL;
 247
 248         return val;
 249 }
 250
 251 #define FEATURE_MASK(feature) (1UL << feature)
 252 static int
 253 navi10_get_allowed_feature_mask(struct smu_context *smu,
 254                                   uint32_t *feature_mask, uint32_t num)
 255 {
 256         struct amdgpu_device *adev = smu->adev;
 257
 258         if (num > 2)
 259                 return -EINVAL;
 260
 261         memset(feature_mask, 0, sizeof(uint32_t) * num);
 262
 263         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 264                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 265                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 266                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 267                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 268                                 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
 269                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 270                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 271                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 272                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 273                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 274                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 275                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 276                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 277                                 | FEATURE_MASK(FEATURE_MMHUB_PG_BIT)
 278                                 | FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
 279                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 280
 281         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 282                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 283                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 284                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 285
 286         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 287                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 288                                 | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 289
 290         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 291                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 292
 293         return 0;
 294 }
 295
 296 static int navi10_check_powerplay_table(struct smu_context *smu)
 297 {
 298         return 0;
 299 }
 300
 301 static int navi10_append_powerplay_table(struct smu_context *smu)
 302 {
 303         struct amdgpu_device *adev = smu->adev;
 304         struct smu_table_context *table_context = &smu->smu_table;
 305         PPTable_t *smc_pptable = table_context->driver_pptable;
 306         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 307         int index, ret;
 308
 309         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 310                                            smc_dpm_info);
 311
 312         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 313                                       (uint8_t **)&smc_dpm_table);
 314         if (ret)
 315                 return ret;
 316
 317         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 318                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 319
 320         /* SVI2 Board Parameters */
 321         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 322         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 323         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 324         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 325         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 326         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 327         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 328         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 329         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 330         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 331
 332         /* Telemetry Settings */
 333         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 334         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 335         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 336         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 337         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 338         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 339         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 340         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 341         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 342         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 343         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 344         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 345
 346         /* GPIO Settings */
 347         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 348         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 349         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 350         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 351         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 352         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 353         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 354         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 355
 356         /* LED Display Settings */
 357         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 358         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 359         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 360         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 361
 362         /* GFXCLK PLL Spread Spectrum */
 363         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 364         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 365         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 366
 367         /* GFXCLK DFLL Spread Spectrum */
 368         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 369         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 370         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 371
 372         /* UCLK Spread Spectrum */
 373         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 374         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 375         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 376
 377         /* SOCCLK Spread Spectrum */
 378         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 379         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 380         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 381
 382         /* Total board power */
 383         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 384         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 385
 386         /* Mvdd Svi2 Div Ratio Setting */
 387         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 388
 389         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 390                 *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 391                                         | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 392
 393                 /* TODO: remove it once SMU fw fix it */
 394                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int navi10_store_powerplay_table(struct smu_context *smu)
 401 {
 402         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 403         struct smu_table_context *table_context = &smu->smu_table;
 404
 405         if (!table_context->power_play_table)
 406                 return -EINVAL;
 407
 408         powerplay_table = table_context->power_play_table;
 409
 410         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 411                sizeof(PPTable_t));
 412
 413         return 0;
 414 }
 415
 416 static void navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 417 {
 418         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 419                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 420         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 421                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 422         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 423                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 424         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 425                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 426         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 427                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 428         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 429                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 430                        AMDGPU_GEM_DOMAIN_VRAM);
 431 }
 432
 433 static int navi10_allocate_dpm_context(struct smu_context *smu)
 434 {
 435         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 436
 437         if (smu_dpm->dpm_context)
 438                 return -EINVAL;
 439
 440         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 441                                        GFP_KERNEL);
 442         if (!smu_dpm->dpm_context)
 443                 return -ENOMEM;
 444
 445         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 446
 447         return 0;
 448 }
 449
 450 static int navi10_set_default_dpm_table(struct smu_context *smu)
 451 {
 452         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 453         struct smu_table_context *table_context = &smu->smu_table;
 454         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 455         PPTable_t *driver_ppt = NULL;
 456
 457         driver_ppt = table_context->driver_pptable;
 458
 459         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 460         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 461
 462         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 463         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 464
 465         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 466         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 467
 468         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 469         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 470
 471         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 472         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 473
 474         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 475         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 476
 477         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 478         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 479
 480         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 481         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 482
 483         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 484         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 485
 486         return 0;
 487 }
 488
 489 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 490 {
 491         int ret = 0;
 492
 493         if (enable) {
 494                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 495                 if (ret)
 496                         return ret;
 497         } else {
 498                 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 499                 if (ret)
 500                         return ret;
 501         }
 502
 503         return 0;
 504 }
 505
 506 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 507                                        enum smu_clk_type clk_type,
 508                                        uint32_t *value)
 509 {
 510         static SmuMetrics_t metrics = {0};
 511         int ret = 0, clk_id = 0;
 512
 513         if (!value)
 514                 return -EINVAL;
 515
 516         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
 517         if (ret)
 518                 return ret;
 519
 520         clk_id = smu_clk_get_index(smu, clk_type);
 521         if (clk_id < 0)
 522                 return clk_id;
 523
 524         *value = metrics.CurrClock[clk_id];
 525
 526         return ret;
 527 }
 528
 529 static int navi10_print_clk_levels(struct smu_context *smu,
 530                         enum smu_clk_type clk_type, char *buf)
 531 {
 532         int i, size = 0, ret = 0;
 533         uint32_t cur_value = 0, value = 0, count = 0;
 534
 535         switch (clk_type) {
 536         case SMU_GFXCLK:
 537         case SMU_SCLK:
 538         case SMU_SOCCLK:
 539         case SMU_MCLK:
 540         case SMU_UCLK:
 541         case SMU_FCLK:
 542         case SMU_DCEFCLK:
 543                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 544                 if (ret)
 545                         return size;
 546
 547                 size += sprintf(buf, "current clk: %uMhz\n", cur_value);
 548
 549                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 550                 if (ret)
 551                         return size;
 552
 553                 for (i = 0; i < count; i++) {
 554                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 555                         if (ret)
 556                                 return size;
 557
 558                         size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 559                                         cur_value == value ? "*" : "");
 560                 }
 561                 break;
 562         default:
 563                 break;
 564         }
 565
 566         return size;
 567 }
 568
 569 static int navi10_force_clk_levels(struct smu_context *smu,
 570                                    enum smu_clk_type clk_type, uint32_t mask)
 571 {
 572
 573         int ret = 0, size = 0;
 574         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 575
 576         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 577         soft_max_level = mask ? (fls(mask) - 1) : 0;
 578
 579         switch (clk_type) {
 580         case SMU_GFXCLK:
 581         case SMU_SOCCLK:
 582         case SMU_MCLK:
 583         case SMU_UCLK:
 584         case SMU_DCEFCLK:
 585         case SMU_FCLK:
 586                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 587                 if (ret)
 588                         return size;
 589
 590                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 591                 if (ret)
 592                         return size;
 593
 594                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 595                 if (ret)
 596                         return size;
 597                 break;
 598         default:
 599                 break;
 600         }
 601
 602         return size;
 603 }
 604
 605 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 606 {
 607         int ret = 0;
 608         uint32_t min_sclk_freq = 0;
 609
 610         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
 611         if (ret)
 612                 return ret;
 613
 614         smu->pstate_sclk = min_sclk_freq * 100;
 615
 616         return ret;
 617 }
 618
 619 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 620                                                  enum smu_clk_type clk_type,
 621                                                  struct pp_clock_levels_with_latency *clocks)
 622 {
 623         int ret = 0, i = 0;
 624         uint32_t level_count = 0, freq = 0;
 625
 626         switch (clk_type) {
 627         case SMU_GFXCLK:
 628         case SMU_DCEFCLK:
 629         case SMU_SOCCLK:
 630                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 631                 if (ret)
 632                         return ret;
 633
 634                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 635                 clocks->num_levels = level_count;
 636
 637                 for (i = 0; i < level_count; i++) {
 638                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 639                         if (ret)
 640                                 return ret;
 641
 642                         clocks->data[i].clocks_in_khz = freq * 1000;
 643                         clocks->data[i].latency_in_us = 0;
 644                 }
 645                 break;
 646         default:
 647                 break;
 648         }
 649
 650         return ret;
 651 }
 652
 653 static int navi10_pre_display_config_changed(struct smu_context *smu)
 654 {
 655         int ret = 0;
 656         uint32_t max_freq = 0;
 657
 658         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 659         if (ret)
 660                 return ret;
 661
 662         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 663                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
 664                 if (ret)
 665                         return ret;
 666                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 667                 if (ret)
 668                         return ret;
 669         }
 670
 671         return ret;
 672 }
 673
 674 static int navi10_display_config_changed(struct smu_context *smu)
 675 {
 676         int ret = 0;
 677
 678         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 679             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 680                 ret = smu_write_watermarks_table(smu);
 681                 if (ret)
 682                         return ret;
 683
 684                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 685         }
 686
 687         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 688             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 689             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 690                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 691                                                   smu->display_config->num_display);
 692                 if (ret)
 693                         return ret;
 694         }
 695
 696         return ret;
 697 }
 698
 699 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 700 {
 701         int ret = 0, i = 0;
 702         uint32_t min_freq, max_freq, force_freq;
 703         enum smu_clk_type clk_type;
 704
 705         enum smu_clk_type clks[] = {
 706                 SMU_GFXCLK,
 707                 SMU_MCLK,
 708                 SMU_SOCCLK,
 709         };
 710
 711         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 712                 clk_type = clks[i];
 713                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 714                 if (ret)
 715                         return ret;
 716
 717                 force_freq = highest ? max_freq : min_freq;
 718                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
 719                 if (ret)
 720                         return ret;
 721         }
 722
 723         return ret;
 724 }
 725
 726 static int navi10_unforce_dpm_levels(struct smu_context *smu) {
 727
 728         int ret = 0, i = 0;
 729         uint32_t min_freq, max_freq;
 730         enum smu_clk_type clk_type;
 731
 732         enum smu_clk_type clks[] = {
 733                 SMU_GFXCLK,
 734                 SMU_MCLK,
 735                 SMU_SOCCLK,
 736         };
 737
 738         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 739                 clk_type = clks[i];
 740                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 741                 if (ret)
 742                         return ret;
 743
 744                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 745                 if (ret)
 746                         return ret;
 747         }
 748
 749         return ret;
 750 }
 751
 752 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
 753 {
 754         int ret = 0;
 755         SmuMetrics_t metrics;
 756
 757         if (!value)
 758                 return -EINVAL;
 759
 760         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics,
 761                                false);
 762         if (ret)
 763                 return ret;
 764
 765         *value = metrics.CurrSocketPower << 8;
 766
 767         return 0;
 768 }
 769
 770 static int navi10_get_current_activity_percent(struct smu_context *smu,
 771                                                uint32_t *value)
 772 {
 773         int ret = 0;
 774         SmuMetrics_t metrics;
 775
 776         if (!value)
 777                 return -EINVAL;
 778
 779         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
 780                                (void *)&metrics, false);
 781         if (ret)
 782                 return ret;
 783
 784         *value = metrics.AverageGfxActivity;
 785
 786         return 0;
 787 }
 788
 789 static const struct pptable_funcs navi10_ppt_funcs = {
 790         .tables_init = navi10_tables_init,
 791         .alloc_dpm_context = navi10_allocate_dpm_context,
 792         .store_powerplay_table = navi10_store_powerplay_table,
 793         .check_powerplay_table = navi10_check_powerplay_table,
 794         .append_powerplay_table = navi10_append_powerplay_table,
 795         .get_smu_msg_index = navi10_get_smu_msg_index,
 796         .get_smu_clk_index = navi10_get_smu_clk_index,
 797         .get_smu_feature_index = navi10_get_smu_feature_index,
 798         .get_smu_table_index = navi10_get_smu_table_index,
 799         .get_smu_power_index = navi10_get_pwr_src_index,
 800         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
 801         .set_default_dpm_table = navi10_set_default_dpm_table,
 802         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
 803         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
 804         .print_clk_levels = navi10_print_clk_levels,
 805         .force_clk_levels = navi10_force_clk_levels,
 806         .populate_umd_state_clk = navi10_populate_umd_state_clk,
 807         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
 808         .pre_display_config_changed = navi10_pre_display_config_changed,
 809         .display_config_changed = navi10_display_config_changed,
 810         .force_dpm_limit_value = navi10_force_dpm_limit_value,
 811         .unforce_dpm_levels = navi10_unforce_dpm_levels,
 812         .get_gpu_power = navi10_get_gpu_power,
 813         .get_current_activity_percent = navi10_get_current_activity_percent,
 814 };
 815
 816 void navi10_set_ppt_funcs(struct smu_context *smu)
 817 {
 818         struct smu_table_context *smu_table = &smu->smu_table;
 819
 820         smu->ppt_funcs = &navi10_ppt_funcs;
 821         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
 822         smu_table->table_count = TABLE_COUNT;
 823 }