drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_navi10.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "navi10_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42
  43 #define FEATURE_MASK(feature) (1ULL << feature)
  44 #define SMC_DPM_FEATURE ( \
  45         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  46         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  48         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  50         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  51         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  52         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  53
  54 #define MSG_MAP(msg, index) \
  55         [SMU_MSG_##msg] = {1, (index)}
  56
  57 static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  58         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  59         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  60         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  61         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  62         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  63         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  64         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  65         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  66         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  67         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  68         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  69         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  70         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  71         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  72         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  73         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  74         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  75         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  76         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  77         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  78         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  79         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  80         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  81         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  82         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  83         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  84         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  85         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  86         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  87         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  88         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  89         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  90         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  91         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  92         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  93         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  94         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  95         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  96         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  97         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  98         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  99         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
 100         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
 101         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
 102         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 103         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 104         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 105         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 108         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 109         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 110         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 111         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 112         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 113         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 114         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 115         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 116         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 117         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 118         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 119         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 120         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),
 121         MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),
 122 };
 123
 124 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 125         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 126         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 127         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 128         CLK_MAP(FCLK, PPCLK_SOCCLK),
 129         CLK_MAP(UCLK, PPCLK_UCLK),
 130         CLK_MAP(MCLK, PPCLK_UCLK),
 131         CLK_MAP(DCLK, PPCLK_DCLK),
 132         CLK_MAP(VCLK, PPCLK_VCLK),
 133         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 134         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 135         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 136         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 137 };
 138
 139 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 140         FEA_MAP(DPM_PREFETCHER),
 141         FEA_MAP(DPM_GFXCLK),
 142         FEA_MAP(DPM_GFX_PACE),
 143         FEA_MAP(DPM_UCLK),
 144         FEA_MAP(DPM_SOCCLK),
 145         FEA_MAP(DPM_MP0CLK),
 146         FEA_MAP(DPM_LINK),
 147         FEA_MAP(DPM_DCEFCLK),
 148         FEA_MAP(MEM_VDDCI_SCALING),
 149         FEA_MAP(MEM_MVDD_SCALING),
 150         FEA_MAP(DS_GFXCLK),
 151         FEA_MAP(DS_SOCCLK),
 152         FEA_MAP(DS_LCLK),
 153         FEA_MAP(DS_DCEFCLK),
 154         FEA_MAP(DS_UCLK),
 155         FEA_MAP(GFX_ULV),
 156         FEA_MAP(FW_DSTATE),
 157         FEA_MAP(GFXOFF),
 158         FEA_MAP(BACO),
 159         FEA_MAP(VCN_PG),
 160         FEA_MAP(JPEG_PG),
 161         FEA_MAP(USB_PG),
 162         FEA_MAP(RSMU_SMN_CG),
 163         FEA_MAP(PPT),
 164         FEA_MAP(TDC),
 165         FEA_MAP(GFX_EDC),
 166         FEA_MAP(APCC_PLUS),
 167         FEA_MAP(GTHR),
 168         FEA_MAP(ACDC),
 169         FEA_MAP(VR0HOT),
 170         FEA_MAP(VR1HOT),
 171         FEA_MAP(FW_CTF),
 172         FEA_MAP(FAN_CONTROL),
 173         FEA_MAP(THERMAL),
 174         FEA_MAP(GFX_DCS),
 175         FEA_MAP(RM),
 176         FEA_MAP(LED_DISPLAY),
 177         FEA_MAP(GFX_SS),
 178         FEA_MAP(OUT_OF_BAND_MONITOR),
 179         FEA_MAP(TEMP_DEPENDENT_VMIN),
 180         FEA_MAP(MMHUB_PG),
 181         FEA_MAP(ATHUB_PG),
 182         FEA_MAP(APCC_DFLL),
 183 };
 184
 185 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 186         TAB_MAP(PPTABLE),
 187         TAB_MAP(WATERMARKS),
 188         TAB_MAP(AVFS),
 189         TAB_MAP(AVFS_PSM_DEBUG),
 190         TAB_MAP(AVFS_FUSE_OVERRIDE),
 191         TAB_MAP(PMSTATUSLOG),
 192         TAB_MAP(SMU_METRICS),
 193         TAB_MAP(DRIVER_SMU_CONFIG),
 194         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 195         TAB_MAP(OVERDRIVE),
 196         TAB_MAP(I2C_COMMANDS),
 197         TAB_MAP(PACE),
 198 };
 199
 200 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 201         PWR_MAP(AC),
 202         PWR_MAP(DC),
 203 };
 204
 205 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 213 };
 214
 215 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 216 {
 217         struct smu_11_0_cmn2aisc_mapping mapping;
 218
 219         if (index >= SMU_MSG_MAX_COUNT)
 220                 return -EINVAL;
 221
 222         mapping = navi10_message_map[index];
 223         if (!(mapping.valid_mapping)) {
 224                 return -EINVAL;
 225         }
 226
 227         return mapping.map_to;
 228 }
 229
 230 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 231 {
 232         struct smu_11_0_cmn2aisc_mapping mapping;
 233
 234         if (index >= SMU_CLK_COUNT)
 235                 return -EINVAL;
 236
 237         mapping = navi10_clk_map[index];
 238         if (!(mapping.valid_mapping)) {
 239                 return -EINVAL;
 240         }
 241
 242         return mapping.map_to;
 243 }
 244
 245 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 246 {
 247         struct smu_11_0_cmn2aisc_mapping mapping;
 248
 249         if (index >= SMU_FEATURE_COUNT)
 250                 return -EINVAL;
 251
 252         mapping = navi10_feature_mask_map[index];
 253         if (!(mapping.valid_mapping)) {
 254                 return -EINVAL;
 255         }
 256
 257         return mapping.map_to;
 258 }
 259
 260 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 261 {
 262         struct smu_11_0_cmn2aisc_mapping mapping;
 263
 264         if (index >= SMU_TABLE_COUNT)
 265                 return -EINVAL;
 266
 267         mapping = navi10_table_map[index];
 268         if (!(mapping.valid_mapping)) {
 269                 return -EINVAL;
 270         }
 271
 272         return mapping.map_to;
 273 }
 274
 275 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 276 {
 277         struct smu_11_0_cmn2aisc_mapping mapping;
 278
 279         if (index >= SMU_POWER_SOURCE_COUNT)
 280                 return -EINVAL;
 281
 282         mapping = navi10_pwr_src_map[index];
 283         if (!(mapping.valid_mapping)) {
 284                 return -EINVAL;
 285         }
 286
 287         return mapping.map_to;
 288 }
 289
 290
 291 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 292 {
 293         struct smu_11_0_cmn2aisc_mapping mapping;
 294
 295         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 296                 return -EINVAL;
 297
 298         mapping = navi10_workload_map[profile];
 299         if (!(mapping.valid_mapping)) {
 300                 return -EINVAL;
 301         }
 302
 303         return mapping.map_to;
 304 }
 305
 306 static bool is_asic_secure(struct smu_context *smu)
 307 {
 308         struct amdgpu_device *adev = smu->adev;
 309         bool is_secure = true;
 310         uint32_t mp0_fw_intf;
 311
 312         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 313                                    (smnMP0_FW_INTF & 0xffffffff));
 314
 315         if (!(mp0_fw_intf & (1 << 19)))
 316                 is_secure = false;
 317
 318         return is_secure;
 319 }
 320
 321 static int
 322 navi10_get_allowed_feature_mask(struct smu_context *smu,
 323                                   uint32_t *feature_mask, uint32_t num)
 324 {
 325         struct amdgpu_device *adev = smu->adev;
 326
 327         if (num > 2)
 328                 return -EINVAL;
 329
 330         memset(feature_mask, 0, sizeof(uint32_t) * num);
 331
 332         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 333                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 334                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 335                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 336                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 337                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 338                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 339                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 340                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 341                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 342                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 343                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 344                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 345                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 346                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 347                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 348                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 349                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 350                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 351                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 352                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 353
 354         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 355                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 356
 357         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 358                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 359
 360         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 361                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 362
 363         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 364                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 365
 366         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 367                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 368                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 369                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 370
 371         if (adev->pm.pp_feature & PP_ULV_MASK)
 372                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 373
 374         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 375                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 376
 377         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 378                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 379
 380         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 381                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 382
 383         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 384                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 385
 386         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 387                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 388
 389         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 390                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 391
 392         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 393         if (is_asic_secure(smu)) {
 394                 /* only for navi10 A0 */
 395                 if ((adev->asic_type == CHIP_NAVI10) &&
 396                         (adev->rev_id == 0)) {
 397                         *(uint64_t *)feature_mask &=
 398                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 399                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 400                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 401                         *(uint64_t *)feature_mask &=
 402                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 403                 }
 404         }
 405
 406         return 0;
 407 }
 408
 409 static int navi10_check_powerplay_table(struct smu_context *smu)
 410 {
 411         return 0;
 412 }
 413
 414 static int navi10_append_powerplay_table(struct smu_context *smu)
 415 {
 416         struct amdgpu_device *adev = smu->adev;
 417         struct smu_table_context *table_context = &smu->smu_table;
 418         PPTable_t *smc_pptable = table_context->driver_pptable;
 419         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 420         int index, ret;
 421
 422         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 423                                            smc_dpm_info);
 424
 425         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 426                                       (uint8_t **)&smc_dpm_table);
 427         if (ret)
 428                 return ret;
 429
 430         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 431                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 432
 433         /* SVI2 Board Parameters */
 434         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 435         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 436         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 437         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 438         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 439         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 440         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 441         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 442         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 443         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 444
 445         /* Telemetry Settings */
 446         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 447         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 448         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 449         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 450         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 451         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 452         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 453         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 454         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 455         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 456         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 457         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 458
 459         /* GPIO Settings */
 460         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 461         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 462         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 463         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 464         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 465         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 466         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 467         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 468
 469         /* LED Display Settings */
 470         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 471         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 472         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 473         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 474
 475         /* GFXCLK PLL Spread Spectrum */
 476         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 477         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 478         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 479
 480         /* GFXCLK DFLL Spread Spectrum */
 481         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 482         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 483         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 484
 485         /* UCLK Spread Spectrum */
 486         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 487         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 488         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 489
 490         /* SOCCLK Spread Spectrum */
 491         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 492         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 493         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 494
 495         /* Total board power */
 496         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 497         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 498
 499         /* Mvdd Svi2 Div Ratio Setting */
 500         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 501
 502         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 503                 /* TODO: remove it once SMU fw fix it */
 504                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static int navi10_store_powerplay_table(struct smu_context *smu)
 511 {
 512         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 513         struct smu_table_context *table_context = &smu->smu_table;
 514         struct smu_baco_context *smu_baco = &smu->smu_baco;
 515
 516         if (!table_context->power_play_table)
 517                 return -EINVAL;
 518
 519         powerplay_table = table_context->power_play_table;
 520
 521         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 522                sizeof(PPTable_t));
 523
 524         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 525
 526         mutex_lock(&smu_baco->mutex);
 527         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 528             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 529                 smu_baco->platform_support = true;
 530         mutex_unlock(&smu_baco->mutex);
 531
 532         return 0;
 533 }
 534
 535 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 536 {
 537         struct smu_table_context *smu_table = &smu->smu_table;
 538
 539         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 540                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 541         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 542                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 543         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 544                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 545         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 546                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 547         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 548                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 549         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 550                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 551                        AMDGPU_GEM_DOMAIN_VRAM);
 552
 553         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 554         if (!smu_table->metrics_table)
 555                 return -ENOMEM;
 556         smu_table->metrics_time = 0;
 557
 558         return 0;
 559 }
 560
 561 static int navi10_get_metrics_table(struct smu_context *smu,
 562                                     SmuMetrics_t *metrics_table)
 563 {
 564         struct smu_table_context *smu_table= &smu->smu_table;
 565         int ret = 0;
 566
 567         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 568                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 569                                 (void *)smu_table->metrics_table, false);
 570                 if (ret) {
 571                         pr_info("Failed to export SMU metrics table!\n");
 572                         return ret;
 573                 }
 574                 smu_table->metrics_time = jiffies;
 575         }
 576
 577         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 578
 579         return ret;
 580 }
 581
 582 static int navi10_allocate_dpm_context(struct smu_context *smu)
 583 {
 584         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 585
 586         if (smu_dpm->dpm_context)
 587                 return -EINVAL;
 588
 589         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 590                                        GFP_KERNEL);
 591         if (!smu_dpm->dpm_context)
 592                 return -ENOMEM;
 593
 594         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 595
 596         return 0;
 597 }
 598
 599 static int navi10_set_default_dpm_table(struct smu_context *smu)
 600 {
 601         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 602         struct smu_table_context *table_context = &smu->smu_table;
 603         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 604         PPTable_t *driver_ppt = NULL;
 605         int i;
 606
 607         driver_ppt = table_context->driver_pptable;
 608
 609         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 610         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 611
 612         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 613         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 614
 615         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 616         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 617
 618         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 619         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 620
 621         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 622         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 623
 624         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 625         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 626
 627         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 628         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 629
 630         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 631         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 632
 633         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 634         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 635
 636         for (i = 0; i < MAX_PCIE_CONF; i++) {
 637                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 638                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 645 {
 646         struct smu_power_context *smu_power = &smu->smu_power;
 647         struct smu_power_gate *power_gate = &smu_power->power_gate;
 648         int ret = 0;
 649
 650         if (enable) {
 651                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 652                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 653                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 654                         if (ret)
 655                                 return ret;
 656                 }
 657                 power_gate->vcn_gated = false;
 658         } else {
 659                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 660                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 661                         if (ret)
 662                                 return ret;
 663                 }
 664                 power_gate->vcn_gated = true;
 665         }
 666
 667         return ret;
 668 }
 669
 670 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 671 {
 672         struct smu_power_context *smu_power = &smu->smu_power;
 673         struct smu_power_gate *power_gate = &smu_power->power_gate;
 674         int ret = 0;
 675
 676         if (enable) {
 677                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 678                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
 679                         if (ret)
 680                                 return ret;
 681                 }
 682                 power_gate->jpeg_gated = false;
 683         } else {
 684                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 685                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
 686                         if (ret)
 687                                 return ret;
 688                 }
 689                 power_gate->jpeg_gated = true;
 690         }
 691
 692         return ret;
 693 }
 694
 695 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 696                                        enum smu_clk_type clk_type,
 697                                        uint32_t *value)
 698 {
 699         int ret = 0, clk_id = 0;
 700         SmuMetrics_t metrics;
 701
 702         ret = navi10_get_metrics_table(smu, &metrics);
 703         if (ret)
 704                 return ret;
 705
 706         clk_id = smu_clk_get_index(smu, clk_type);
 707         if (clk_id < 0)
 708                 return clk_id;
 709
 710         *value = metrics.CurrClock[clk_id];
 711
 712         return ret;
 713 }
 714
 715 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 716 {
 717         PPTable_t *pptable = smu->smu_table.driver_pptable;
 718         DpmDescriptor_t *dpm_desc = NULL;
 719         uint32_t clk_index = 0;
 720
 721         clk_index = smu_clk_get_index(smu, clk_type);
 722         dpm_desc = &pptable->DpmDescriptor[clk_index];
 723
 724         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 725         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 726 }
 727
 728 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
 729 {
 730         return od_table->cap[feature];
 731 }
 732
 733
 734 static int navi10_print_clk_levels(struct smu_context *smu,
 735                         enum smu_clk_type clk_type, char *buf)
 736 {
 737         uint16_t *curve_settings;
 738         int i, size = 0, ret = 0;
 739         uint32_t cur_value = 0, value = 0, count = 0;
 740         uint32_t freq_values[3] = {0};
 741         uint32_t mark_index = 0;
 742         struct smu_table_context *table_context = &smu->smu_table;
 743         uint32_t gen_speed, lane_width;
 744         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 745         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 746         struct amdgpu_device *adev = smu->adev;
 747         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 748         OverDriveTable_t *od_table =
 749                 (OverDriveTable_t *)table_context->overdrive_table;
 750         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
 751
 752         switch (clk_type) {
 753         case SMU_GFXCLK:
 754         case SMU_SCLK:
 755         case SMU_SOCCLK:
 756         case SMU_MCLK:
 757         case SMU_UCLK:
 758         case SMU_FCLK:
 759         case SMU_DCEFCLK:
 760                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 761                 if (ret)
 762                         return size;
 763
 764                 /* 10KHz -> MHz */
 765                 cur_value = cur_value / 100;
 766
 767                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 768                 if (ret)
 769                         return size;
 770
 771                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 772                         for (i = 0; i < count; i++) {
 773                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 774                                 if (ret)
 775                                         return size;
 776
 777                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 778                                                 cur_value == value ? "*" : "");
 779                         }
 780                 } else {
 781                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 782                         if (ret)
 783                                 return size;
 784                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 785                         if (ret)
 786                                 return size;
 787
 788                         freq_values[1] = cur_value;
 789                         mark_index = cur_value == freq_values[0] ? 0 :
 790                                      cur_value == freq_values[2] ? 2 : 1;
 791                         if (mark_index != 1)
 792                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 793
 794                         for (i = 0; i < 3; i++) {
 795                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 796                                                 i == mark_index ? "*" : "");
 797                         }
 798
 799                 }
 800                 break;
 801         case SMU_PCIE:
 802                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 803                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 804                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 805                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 806                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 807                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 808                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 809                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 810                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 811                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 812                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 813                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 814                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 815                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 816                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 817                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 818                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 819                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 820                                         pptable->LclkFreq[i],
 821                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 822                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 823                                         "*" : "");
 824                 break;
 825         case SMU_OD_SCLK:
 826                 if (!smu->od_enabled || !od_table || !od_settings)
 827                         break;
 828                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS))
 829                         break;
 830                 size += sprintf(buf + size, "OD_SCLK:\n");
 831                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
 832                 break;
 833         case SMU_OD_MCLK:
 834                 if (!smu->od_enabled || !od_table || !od_settings)
 835                         break;
 836                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX))
 837                         break;
 838                 size += sprintf(buf + size, "OD_MCLK:\n");
 839                 size += sprintf(buf + size, "0: %uMHz\n", od_table->UclkFmax);
 840                 break;
 841         case SMU_OD_VDDC_CURVE:
 842                 if (!smu->od_enabled || !od_table || !od_settings)
 843                         break;
 844                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE))
 845                         break;
 846                 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
 847                 for (i = 0; i < 3; i++) {
 848                         switch (i) {
 849                         case 0:
 850                                 curve_settings = &od_table->GfxclkFreq1;
 851                                 break;
 852                         case 1:
 853                                 curve_settings = &od_table->GfxclkFreq2;
 854                                 break;
 855                         case 2:
 856                                 curve_settings = &od_table->GfxclkFreq3;
 857                                 break;
 858                         default:
 859                                 break;
 860                         }
 861                         size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
 862                 }
 863                 break;
 864         default:
 865                 break;
 866         }
 867
 868         return size;
 869 }
 870
 871 static int navi10_force_clk_levels(struct smu_context *smu,
 872                                    enum smu_clk_type clk_type, uint32_t mask)
 873 {
 874
 875         int ret = 0, size = 0;
 876         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 877
 878         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 879         soft_max_level = mask ? (fls(mask) - 1) : 0;
 880
 881         switch (clk_type) {
 882         case SMU_GFXCLK:
 883         case SMU_SCLK:
 884         case SMU_SOCCLK:
 885         case SMU_MCLK:
 886         case SMU_UCLK:
 887         case SMU_DCEFCLK:
 888         case SMU_FCLK:
 889                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 890                 if (ret)
 891                         return size;
 892
 893                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 894                 if (ret)
 895                         return size;
 896
 897                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 898                 if (ret)
 899                         return size;
 900                 break;
 901         default:
 902                 break;
 903         }
 904
 905         return size;
 906 }
 907
 908 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 909 {
 910         int ret = 0;
 911         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 912
 913         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 914         if (ret)
 915                 return ret;
 916
 917         smu->pstate_sclk = min_sclk_freq * 100;
 918
 919         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 920         if (ret)
 921                 return ret;
 922
 923         smu->pstate_mclk = min_mclk_freq * 100;
 924
 925         return ret;
 926 }
 927
 928 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 929                                                  enum smu_clk_type clk_type,
 930                                                  struct pp_clock_levels_with_latency *clocks)
 931 {
 932         int ret = 0, i = 0;
 933         uint32_t level_count = 0, freq = 0;
 934
 935         switch (clk_type) {
 936         case SMU_GFXCLK:
 937         case SMU_DCEFCLK:
 938         case SMU_SOCCLK:
 939                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 940                 if (ret)
 941                         return ret;
 942
 943                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 944                 clocks->num_levels = level_count;
 945
 946                 for (i = 0; i < level_count; i++) {
 947                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 948                         if (ret)
 949                                 return ret;
 950
 951                         clocks->data[i].clocks_in_khz = freq * 1000;
 952                         clocks->data[i].latency_in_us = 0;
 953                 }
 954                 break;
 955         default:
 956                 break;
 957         }
 958
 959         return ret;
 960 }
 961
 962 static int navi10_pre_display_config_changed(struct smu_context *smu)
 963 {
 964         int ret = 0;
 965         uint32_t max_freq = 0;
 966
 967         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 968         if (ret)
 969                 return ret;
 970
 971         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 972                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
 973                 if (ret)
 974                         return ret;
 975                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 976                 if (ret)
 977                         return ret;
 978         }
 979
 980         return ret;
 981 }
 982
 983 static int navi10_display_config_changed(struct smu_context *smu)
 984 {
 985         int ret = 0;
 986
 987         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 988             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 989                 ret = smu_write_watermarks_table(smu);
 990                 if (ret)
 991                         return ret;
 992
 993                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 994         }
 995
 996         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 997             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 998             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 999                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1000                                                   smu->display_config->num_display);
1001                 if (ret)
1002                         return ret;
1003         }
1004
1005         return ret;
1006 }
1007
1008 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
1009 {
1010         int ret = 0, i = 0;
1011         uint32_t min_freq, max_freq, force_freq;
1012         enum smu_clk_type clk_type;
1013
1014         enum smu_clk_type clks[] = {
1015                 SMU_GFXCLK,
1016                 SMU_MCLK,
1017                 SMU_SOCCLK,
1018         };
1019
1020         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1021                 clk_type = clks[i];
1022                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1023                 if (ret)
1024                         return ret;
1025
1026                 force_freq = highest ? max_freq : min_freq;
1027                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
1028                 if (ret)
1029                         return ret;
1030         }
1031
1032         return ret;
1033 }
1034
1035 static int navi10_unforce_dpm_levels(struct smu_context *smu)
1036 {
1037         int ret = 0, i = 0;
1038         uint32_t min_freq, max_freq;
1039         enum smu_clk_type clk_type;
1040
1041         enum smu_clk_type clks[] = {
1042                 SMU_GFXCLK,
1043                 SMU_MCLK,
1044                 SMU_SOCCLK,
1045         };
1046
1047         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1048                 clk_type = clks[i];
1049                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1050                 if (ret)
1051                         return ret;
1052
1053                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
1054                 if (ret)
1055                         return ret;
1056         }
1057
1058         return ret;
1059 }
1060
1061 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1062 {
1063         int ret = 0;
1064         SmuMetrics_t metrics;
1065
1066         if (!value)
1067                 return -EINVAL;
1068
1069         ret = navi10_get_metrics_table(smu, &metrics);
1070         if (ret)
1071                 return ret;
1072
1073         *value = metrics.AverageSocketPower << 8;
1074
1075         return 0;
1076 }
1077
1078 static int navi10_get_current_activity_percent(struct smu_context *smu,
1079                                                enum amd_pp_sensors sensor,
1080                                                uint32_t *value)
1081 {
1082         int ret = 0;
1083         SmuMetrics_t metrics;
1084
1085         if (!value)
1086                 return -EINVAL;
1087
1088         ret = navi10_get_metrics_table(smu, &metrics);
1089         if (ret)
1090                 return ret;
1091
1092         switch (sensor) {
1093         case AMDGPU_PP_SENSOR_GPU_LOAD:
1094                 *value = metrics.AverageGfxActivity;
1095                 break;
1096         case AMDGPU_PP_SENSOR_MEM_LOAD:
1097                 *value = metrics.AverageUclkActivity;
1098                 break;
1099         default:
1100                 pr_err("Invalid sensor for retrieving clock activity\n");
1101                 return -EINVAL;
1102         }
1103
1104         return 0;
1105 }
1106
1107 static bool navi10_is_dpm_running(struct smu_context *smu)
1108 {
1109         int ret = 0;
1110         uint32_t feature_mask[2];
1111         unsigned long feature_enabled;
1112         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1113         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1114                            ((uint64_t)feature_mask[1] << 32));
1115         return !!(feature_enabled & SMC_DPM_FEATURE);
1116 }
1117
1118 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1119                                     uint32_t *speed)
1120 {
1121         SmuMetrics_t metrics;
1122         int ret = 0;
1123
1124         if (!speed)
1125                 return -EINVAL;
1126
1127         ret = navi10_get_metrics_table(smu, &metrics);
1128         if (ret)
1129                 return ret;
1130
1131         *speed = metrics.CurrFanSpeed;
1132
1133         return ret;
1134 }
1135
1136 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1137                                         uint32_t *speed)
1138 {
1139         int ret = 0;
1140         uint32_t percent = 0;
1141         uint32_t current_rpm;
1142         PPTable_t *pptable = smu->smu_table.driver_pptable;
1143
1144         ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
1145         if (ret)
1146                 return ret;
1147
1148         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1149         *speed = percent > 100 ? 100 : percent;
1150
1151         return ret;
1152 }
1153
1154 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1155 {
1156         DpmActivityMonitorCoeffInt_t activity_monitor;
1157         uint32_t i, size = 0;
1158         int16_t workload_type = 0;
1159         static const char *profile_name[] = {
1160                                         "BOOTUP_DEFAULT",
1161                                         "3D_FULL_SCREEN",
1162                                         "POWER_SAVING",
1163                                         "VIDEO",
1164                                         "VR",
1165                                         "COMPUTE",
1166                                         "CUSTOM"};
1167         static const char *title[] = {
1168                         "PROFILE_INDEX(NAME)",
1169                         "CLOCK_TYPE(NAME)",
1170                         "FPS",
1171                         "MinFreqType",
1172                         "MinActiveFreqType",
1173                         "MinActiveFreq",
1174                         "BoosterFreqType",
1175                         "BoosterFreq",
1176                         "PD_Data_limit_c",
1177                         "PD_Data_error_coeff",
1178                         "PD_Data_error_rate_coeff"};
1179         int result = 0;
1180
1181         if (!buf)
1182                 return -EINVAL;
1183
1184         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1185                         title[0], title[1], title[2], title[3], title[4], title[5],
1186                         title[6], title[7], title[8], title[9], title[10]);
1187
1188         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1189                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1190                 workload_type = smu_workload_get_type(smu, i);
1191                 if (workload_type < 0)
1192                         return -EINVAL;
1193
1194                 result = smu_update_table(smu,
1195                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1196                                           (void *)(&activity_monitor), false);
1197                 if (result) {
1198                         pr_err("[%s] Failed to get activity monitor!", __func__);
1199                         return result;
1200                 }
1201
1202                 size += sprintf(buf + size, "%2d %14s%s:\n",
1203                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1204
1205                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1206                         " ",
1207                         0,
1208                         "GFXCLK",
1209                         activity_monitor.Gfx_FPS,
1210                         activity_monitor.Gfx_MinFreqStep,
1211                         activity_monitor.Gfx_MinActiveFreqType,
1212                         activity_monitor.Gfx_MinActiveFreq,
1213                         activity_monitor.Gfx_BoosterFreqType,
1214                         activity_monitor.Gfx_BoosterFreq,
1215                         activity_monitor.Gfx_PD_Data_limit_c,
1216                         activity_monitor.Gfx_PD_Data_error_coeff,
1217                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1218
1219                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1220                         " ",
1221                         1,
1222                         "SOCCLK",
1223                         activity_monitor.Soc_FPS,
1224                         activity_monitor.Soc_MinFreqStep,
1225                         activity_monitor.Soc_MinActiveFreqType,
1226                         activity_monitor.Soc_MinActiveFreq,
1227                         activity_monitor.Soc_BoosterFreqType,
1228                         activity_monitor.Soc_BoosterFreq,
1229                         activity_monitor.Soc_PD_Data_limit_c,
1230                         activity_monitor.Soc_PD_Data_error_coeff,
1231                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1232
1233                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1234                         " ",
1235                         2,
1236                         "MEMLK",
1237                         activity_monitor.Mem_FPS,
1238                         activity_monitor.Mem_MinFreqStep,
1239                         activity_monitor.Mem_MinActiveFreqType,
1240                         activity_monitor.Mem_MinActiveFreq,
1241                         activity_monitor.Mem_BoosterFreqType,
1242                         activity_monitor.Mem_BoosterFreq,
1243                         activity_monitor.Mem_PD_Data_limit_c,
1244                         activity_monitor.Mem_PD_Data_error_coeff,
1245                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1246         }
1247
1248         return size;
1249 }
1250
1251 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1252 {
1253         DpmActivityMonitorCoeffInt_t activity_monitor;
1254         int workload_type, ret = 0;
1255
1256         smu->power_profile_mode = input[size];
1257
1258         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1259                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1260                 return -EINVAL;
1261         }
1262
1263         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1264                 if (size < 0)
1265                         return -EINVAL;
1266
1267                 ret = smu_update_table(smu,
1268                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1269                                        (void *)(&activity_monitor), false);
1270                 if (ret) {
1271                         pr_err("[%s] Failed to get activity monitor!", __func__);
1272                         return ret;
1273                 }
1274
1275                 switch (input[0]) {
1276                 case 0: /* Gfxclk */
1277                         activity_monitor.Gfx_FPS = input[1];
1278                         activity_monitor.Gfx_MinFreqStep = input[2];
1279                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1280                         activity_monitor.Gfx_MinActiveFreq = input[4];
1281                         activity_monitor.Gfx_BoosterFreqType = input[5];
1282                         activity_monitor.Gfx_BoosterFreq = input[6];
1283                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1284                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1285                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1286                         break;
1287                 case 1: /* Socclk */
1288                         activity_monitor.Soc_FPS = input[1];
1289                         activity_monitor.Soc_MinFreqStep = input[2];
1290                         activity_monitor.Soc_MinActiveFreqType = input[3];
1291                         activity_monitor.Soc_MinActiveFreq = input[4];
1292                         activity_monitor.Soc_BoosterFreqType = input[5];
1293                         activity_monitor.Soc_BoosterFreq = input[6];
1294                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1295                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1296                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1297                         break;
1298                 case 2: /* Memlk */
1299                         activity_monitor.Mem_FPS = input[1];
1300                         activity_monitor.Mem_MinFreqStep = input[2];
1301                         activity_monitor.Mem_MinActiveFreqType = input[3];
1302                         activity_monitor.Mem_MinActiveFreq = input[4];
1303                         activity_monitor.Mem_BoosterFreqType = input[5];
1304                         activity_monitor.Mem_BoosterFreq = input[6];
1305                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1306                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1307                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1308                         break;
1309                 }
1310
1311                 ret = smu_update_table(smu,
1312                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1313                                        (void *)(&activity_monitor), true);
1314                 if (ret) {
1315                         pr_err("[%s] Failed to set activity monitor!", __func__);
1316                         return ret;
1317                 }
1318         }
1319
1320         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1321         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1322         if (workload_type < 0)
1323                 return -EINVAL;
1324         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1325                                     1 << workload_type);
1326
1327         return ret;
1328 }
1329
1330 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1331                                          enum amd_dpm_forced_level level,
1332                                          uint32_t *sclk_mask,
1333                                          uint32_t *mclk_mask,
1334                                          uint32_t *soc_mask)
1335 {
1336         int ret = 0;
1337         uint32_t level_count = 0;
1338
1339         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1340                 if (sclk_mask)
1341                         *sclk_mask = 0;
1342         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1343                 if (mclk_mask)
1344                         *mclk_mask = 0;
1345         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1346                 if(sclk_mask) {
1347                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1348                         if (ret)
1349                                 return ret;
1350                         *sclk_mask = level_count - 1;
1351                 }
1352
1353                 if(mclk_mask) {
1354                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1355                         if (ret)
1356                                 return ret;
1357                         *mclk_mask = level_count - 1;
1358                 }
1359
1360                 if(soc_mask) {
1361                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1362                         if (ret)
1363                                 return ret;
1364                         *soc_mask = level_count - 1;
1365                 }
1366         }
1367
1368         return ret;
1369 }
1370
1371 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1372 {
1373         struct smu_clocks min_clocks = {0};
1374         struct pp_display_clock_request clock_req;
1375         int ret = 0;
1376
1377         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1378         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1379         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1380
1381         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1382                 clock_req.clock_type = amd_pp_dcef_clock;
1383                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1384
1385                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1386                 if (!ret) {
1387                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1388                                 ret = smu_send_smc_msg_with_param(smu,
1389                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1390                                                                   min_clocks.dcef_clock_in_sr/100);
1391                                 if (ret) {
1392                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1393                                         return ret;
1394                                 }
1395                         }
1396                 } else {
1397                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1398                 }
1399         }
1400
1401         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1402                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1403                 if (ret) {
1404                         pr_err("[%s] Set hard min uclk failed!", __func__);
1405                         return ret;
1406                 }
1407         }
1408
1409         return 0;
1410 }
1411
1412 static int navi10_set_watermarks_table(struct smu_context *smu,
1413                                        void *watermarks, struct
1414                                        dm_pp_wm_sets_with_clock_ranges_soc15
1415                                        *clock_ranges)
1416 {
1417         int i;
1418         Watermarks_t *table = watermarks;
1419
1420         if (!table || !clock_ranges)
1421                 return -EINVAL;
1422
1423         if (clock_ranges->num_wm_dmif_sets > 4 ||
1424             clock_ranges->num_wm_mcif_sets > 4)
1425                 return -EINVAL;
1426
1427         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1428                 table->WatermarkRow[1][i].MinClock =
1429                         cpu_to_le16((uint16_t)
1430                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1431                         1000));
1432                 table->WatermarkRow[1][i].MaxClock =
1433                         cpu_to_le16((uint16_t)
1434                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1435                         1000));
1436                 table->WatermarkRow[1][i].MinUclk =
1437                         cpu_to_le16((uint16_t)
1438                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1439                         1000));
1440                 table->WatermarkRow[1][i].MaxUclk =
1441                         cpu_to_le16((uint16_t)
1442                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1443                         1000));
1444                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1445                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1446         }
1447
1448         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1449                 table->WatermarkRow[0][i].MinClock =
1450                         cpu_to_le16((uint16_t)
1451                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1452                         1000));
1453                 table->WatermarkRow[0][i].MaxClock =
1454                         cpu_to_le16((uint16_t)
1455                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1456                         1000));
1457                 table->WatermarkRow[0][i].MinUclk =
1458                         cpu_to_le16((uint16_t)
1459                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1460                         1000));
1461                 table->WatermarkRow[0][i].MaxUclk =
1462                         cpu_to_le16((uint16_t)
1463                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1464                         1000));
1465                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1466                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int navi10_thermal_get_temperature(struct smu_context *smu,
1473                                              enum amd_pp_sensors sensor,
1474                                              uint32_t *value)
1475 {
1476         SmuMetrics_t metrics;
1477         int ret = 0;
1478
1479         if (!value)
1480                 return -EINVAL;
1481
1482         ret = navi10_get_metrics_table(smu, &metrics);
1483         if (ret)
1484                 return ret;
1485
1486         switch (sensor) {
1487         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1488                 *value = metrics.TemperatureHotspot *
1489                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1490                 break;
1491         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1492                 *value = metrics.TemperatureEdge *
1493                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1494                 break;
1495         case AMDGPU_PP_SENSOR_MEM_TEMP:
1496                 *value = metrics.TemperatureMem *
1497                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1498                 break;
1499         default:
1500                 pr_err("Invalid sensor for retrieving temp\n");
1501                 return -EINVAL;
1502         }
1503
1504         return 0;
1505 }
1506
1507 static int navi10_read_sensor(struct smu_context *smu,
1508                                  enum amd_pp_sensors sensor,
1509                                  void *data, uint32_t *size)
1510 {
1511         int ret = 0;
1512         struct smu_table_context *table_context = &smu->smu_table;
1513         PPTable_t *pptable = table_context->driver_pptable;
1514
1515         if(!data || !size)
1516                 return -EINVAL;
1517
1518         mutex_lock(&smu->sensor_lock);
1519         switch (sensor) {
1520         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1521                 *(uint32_t *)data = pptable->FanMaximumRpm;
1522                 *size = 4;
1523                 break;
1524         case AMDGPU_PP_SENSOR_MEM_LOAD:
1525         case AMDGPU_PP_SENSOR_GPU_LOAD:
1526                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1527                 *size = 4;
1528                 break;
1529         case AMDGPU_PP_SENSOR_GPU_POWER:
1530                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1531                 *size = 4;
1532                 break;
1533         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1534         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1535         case AMDGPU_PP_SENSOR_MEM_TEMP:
1536                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1537                 *size = 4;
1538                 break;
1539         default:
1540                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1541         }
1542         mutex_unlock(&smu->sensor_lock);
1543
1544         return ret;
1545 }
1546
1547 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1548 {
1549         uint32_t num_discrete_levels = 0;
1550         uint16_t *dpm_levels = NULL;
1551         uint16_t i = 0;
1552         struct smu_table_context *table_context = &smu->smu_table;
1553         PPTable_t *driver_ppt = NULL;
1554
1555         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1556                 return -EINVAL;
1557
1558         driver_ppt = table_context->driver_pptable;
1559         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1560         dpm_levels = driver_ppt->FreqTableUclk;
1561
1562         if (num_discrete_levels == 0 || dpm_levels == NULL)
1563                 return -EINVAL;
1564
1565         *num_states = num_discrete_levels;
1566         for (i = 0; i < num_discrete_levels; i++) {
1567                 /* convert to khz */
1568                 *clocks_in_khz = (*dpm_levels) * 1000;
1569                 clocks_in_khz++;
1570                 dpm_levels++;
1571         }
1572
1573         return 0;
1574 }
1575
1576 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
1577 {
1578         struct amdgpu_device *adev = smu->adev;
1579         int ret = 0;
1580         uint32_t sclk_freq = 0, uclk_freq = 0;
1581         uint32_t uclk_level = 0;
1582
1583         switch (adev->asic_type) {
1584         case CHIP_NAVI10:
1585                 switch (adev->pdev->revision) {
1586                 case 0xf0: /* XTX */
1587                 case 0xc0:
1588                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1589                         break;
1590                 case 0xf1: /* XT */
1591                 case 0xc1:
1592                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1593                         break;
1594                 default: /* XL */
1595                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1596                         break;
1597                 }
1598                 break;
1599         case CHIP_NAVI14:
1600                 switch (adev->pdev->revision) {
1601                 case 0xc7: /* XT */
1602                 case 0xf4:
1603                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1604                         break;
1605                 case 0xc1: /* XTM */
1606                 case 0xf2:
1607                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1608                         break;
1609                 case 0xc3: /* XLM */
1610                 case 0xf3:
1611                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1612                         break;
1613                 case 0xc5: /* XTX */
1614                 case 0xf6:
1615                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1616                         break;
1617                 default: /* XL */
1618                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1619                         break;
1620                 }
1621                 break;
1622         default:
1623                 return -EINVAL;
1624         }
1625
1626         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
1627         if (ret)
1628                 return ret;
1629         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
1630         if (ret)
1631                 return ret;
1632
1633         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1634         if (ret)
1635                 return ret;
1636         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1637         if (ret)
1638                 return ret;
1639
1640         return ret;
1641 }
1642
1643 static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1644 {
1645         int ret = 0;
1646
1647         switch (level) {
1648         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1649                 ret = navi10_set_peak_clock_by_device(smu);
1650                 break;
1651         default:
1652                 ret = -EINVAL;
1653                 break;
1654         }
1655
1656         return ret;
1657 }
1658
1659 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1660                                                 struct smu_temperature_range *range)
1661 {
1662         struct smu_table_context *table_context = &smu->smu_table;
1663         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1664
1665         if (!range || !powerplay_table)
1666                 return -EINVAL;
1667
1668         range->max = powerplay_table->software_shutdown_temp *
1669                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1670
1671         return 0;
1672 }
1673
1674 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1675                                                 bool disable_memory_clock_switch)
1676 {
1677         int ret = 0;
1678         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1679                 (struct smu_11_0_max_sustainable_clocks *)
1680                         smu->smu_table.max_sustainable_clocks;
1681         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1682         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1683
1684         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1685                 return 0;
1686
1687         if(disable_memory_clock_switch)
1688                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1689         else
1690                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1691
1692         if(!ret)
1693                 smu->disable_uclk_switch = disable_memory_clock_switch;
1694
1695         return ret;
1696 }
1697
1698 static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
1699 {
1700         PPTable_t *pptable = smu->smu_table.driver_pptable;
1701         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1702 }
1703
1704 static int navi10_get_power_limit(struct smu_context *smu,
1705                                      uint32_t *limit,
1706                                      bool cap)
1707 {
1708         PPTable_t *pptable = smu->smu_table.driver_pptable;
1709         uint32_t asic_default_power_limit = 0;
1710         int ret = 0;
1711         int power_src;
1712
1713         if (!smu->power_limit) {
1714                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1715                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1716                         if (power_src < 0)
1717                                 return -EINVAL;
1718
1719                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1720                                 power_src << 16);
1721                         if (ret) {
1722                                 pr_err("[%s] get PPT limit failed!", __func__);
1723                                 return ret;
1724                         }
1725                         smu_read_smc_arg(smu, &asic_default_power_limit);
1726                 } else {
1727                         /* the last hope to figure out the ppt limit */
1728                         if (!pptable) {
1729                                 pr_err("Cannot get PPT limit due to pptable missing!");
1730                                 return -EINVAL;
1731                         }
1732                         asic_default_power_limit =
1733                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1734                 }
1735
1736                 smu->power_limit = asic_default_power_limit;
1737         }
1738
1739         if (cap)
1740                 *limit = smu_v11_0_get_max_power_limit(smu);
1741         else
1742                 *limit = smu->power_limit;
1743
1744         return 0;
1745 }
1746
1747 static int navi10_update_pcie_parameters(struct smu_context *smu,
1748                                      uint32_t pcie_gen_cap,
1749                                      uint32_t pcie_width_cap)
1750 {
1751         PPTable_t *pptable = smu->smu_table.driver_pptable;
1752         int ret, i;
1753         uint32_t smu_pcie_arg;
1754
1755         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1756         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1757
1758         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1759                 smu_pcie_arg = (i << 16) |
1760                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1761                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1762                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1763                 ret = smu_send_smc_msg_with_param(smu,
1764                                           SMU_MSG_OverridePcieParameters,
1765                                           smu_pcie_arg);
1766
1767                 if (ret)
1768                         return ret;
1769
1770                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1771                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1772                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1773                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1774         }
1775
1776         return 0;
1777 }
1778
1779 static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
1780         pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1781         pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1782         pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1783         pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1784         pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
1785         pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1786 }
1787
1788 static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
1789 {
1790         if (value < od_table->min[setting]) {
1791                 pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
1792                 return -EINVAL;
1793         }
1794         if (value > od_table->max[setting]) {
1795                 pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
1796                 return -EINVAL;
1797         }
1798         return 0;
1799 }
1800
1801 static int navi10_setup_od_limits(struct smu_context *smu) {
1802         struct smu_11_0_overdrive_table *overdrive_table = NULL;
1803         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1804
1805         if (!smu->smu_table.power_play_table) {
1806                 pr_err("powerplay table uninitialized!\n");
1807                 return -ENOENT;
1808         }
1809         powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1810         overdrive_table = &powerplay_table->overdrive_table;
1811         if (!smu->od_settings) {
1812                 smu->od_settings = kmemdup(overdrive_table, sizeof(struct smu_11_0_overdrive_table), GFP_KERNEL);
1813         } else {
1814                 memcpy(smu->od_settings, overdrive_table, sizeof(struct smu_11_0_overdrive_table));
1815         }
1816         return 0;
1817 }
1818
1819 static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
1820         OverDriveTable_t *od_table;
1821         int ret = 0;
1822
1823         ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
1824         if (ret)
1825                 return ret;
1826
1827         if (initialize) {
1828                 ret = navi10_setup_od_limits(smu);
1829                 if (ret) {
1830                         pr_err("Failed to retrieve board OD limits\n");
1831                         return ret;
1832                 }
1833
1834         }
1835
1836         od_table = (OverDriveTable_t *)smu->smu_table.overdrive_table;
1837         if (od_table) {
1838                 navi10_dump_od_table(od_table);
1839         }
1840
1841         return ret;
1842 }
1843
1844 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
1845         int i;
1846         int ret = 0;
1847         struct smu_table_context *table_context = &smu->smu_table;
1848         OverDriveTable_t *od_table;
1849         struct smu_11_0_overdrive_table *od_settings;
1850         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
1851         uint16_t *freq_ptr, *voltage_ptr;
1852         od_table = (OverDriveTable_t *)table_context->overdrive_table;
1853
1854         if (!smu->od_enabled) {
1855                 pr_warn("OverDrive is not enabled!\n");
1856                 return -EINVAL;
1857         }
1858
1859         if (!smu->od_settings) {
1860                 pr_err("OD board limits are not set!\n");
1861                 return -ENOENT;
1862         }
1863
1864         od_settings = smu->od_settings;
1865
1866         switch (type) {
1867         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1868                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
1869                         pr_warn("GFXCLK_LIMITS not supported!\n");
1870                         return -ENOTSUPP;
1871                 }
1872                 if (!table_context->overdrive_table) {
1873                         pr_err("Overdrive is not initialized\n");
1874                         return -EINVAL;
1875                 }
1876                 for (i = 0; i < size; i += 2) {
1877                         if (i + 2 > size) {
1878                                 pr_info("invalid number of input parameters %d\n", size);
1879                                 return -EINVAL;
1880                         }
1881                         switch (input[i]) {
1882                         case 0:
1883                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
1884                                 freq_ptr = &od_table->GfxclkFmin;
1885                                 if (input[i + 1] > od_table->GfxclkFmax) {
1886                                         pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1887                                                 input[i + 1],
1888                                                 od_table->GfxclkFmin);
1889                                         return -EINVAL;
1890                                 }
1891                                 break;
1892                         case 1:
1893                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
1894                                 freq_ptr = &od_table->GfxclkFmax;
1895                                 if (input[i + 1] < od_table->GfxclkFmin) {
1896                                         pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
1897                                                 input[i + 1],
1898                                                 od_table->GfxclkFmax);
1899                                         return -EINVAL;
1900                                 }
1901                                 break;
1902                         default:
1903                                 pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1904                                 pr_info("Supported indices: [0:min,1:max]\n");
1905                                 return -EINVAL;
1906                         }
1907                         ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
1908                         if (ret)
1909                                 return ret;
1910                         *freq_ptr = input[i + 1];
1911                 }
1912                 break;
1913         case PP_OD_EDIT_MCLK_VDDC_TABLE:
1914                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
1915                         pr_warn("UCLK_MAX not supported!\n");
1916                         return -ENOTSUPP;
1917                 }
1918                 if (size < 2) {
1919                         pr_info("invalid number of parameters: %d\n", size);
1920                         return -EINVAL;
1921                 }
1922                 if (input[0] != 1) {
1923                         pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
1924                         pr_info("Supported indices: [1:max]\n");
1925                         return -EINVAL;
1926                 }
1927                 ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
1928                 if (ret)
1929                         return ret;
1930                 od_table->UclkFmax = input[1];
1931                 break;
1932         case PP_OD_COMMIT_DPM_TABLE:
1933                 navi10_dump_od_table(od_table);
1934                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
1935                 if (ret) {
1936                         pr_err("Failed to import overdrive table!\n");
1937                         return ret;
1938                 }
1939                 // no lock needed because smu_od_edit_dpm_table has it
1940                 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
1941                         AMD_PP_TASK_READJUST_POWER_STATE,
1942                         false);
1943                 if (ret) {
1944                         return ret;
1945                 }
1946                 break;
1947         case PP_OD_EDIT_VDDC_CURVE:
1948                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
1949                         pr_warn("GFXCLK_CURVE not supported!\n");
1950                         return -ENOTSUPP;
1951                 }
1952                 if (size < 3) {
1953                         pr_info("invalid number of parameters: %d\n", size);
1954                         return -EINVAL;
1955                 }
1956                 if (!od_table) {
1957                         pr_info("Overdrive is not initialized\n");
1958                         return -EINVAL;
1959                 }
1960
1961                 switch (input[0]) {
1962                 case 0:
1963                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
1964                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
1965                         freq_ptr = &od_table->GfxclkFreq1;
1966                         voltage_ptr = &od_table->GfxclkVolt1;
1967                         break;
1968                 case 1:
1969                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
1970                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
1971                         freq_ptr = &od_table->GfxclkFreq2;
1972                         voltage_ptr = &od_table->GfxclkVolt2;
1973                         break;
1974                 case 2:
1975                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
1976                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
1977                         freq_ptr = &od_table->GfxclkFreq3;
1978                         voltage_ptr = &od_table->GfxclkVolt3;
1979                         break;
1980                 default:
1981                         pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
1982                         pr_info("Supported indices: [0, 1, 2]\n");
1983                         return -EINVAL;
1984                 }
1985                 ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
1986                 if (ret)
1987                         return ret;
1988                 // Allow setting zero to disable the OverDrive VDDC curve
1989                 if (input[2] != 0) {
1990                         ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
1991                         if (ret)
1992                                 return ret;
1993                         *freq_ptr = input[1];
1994                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
1995                         pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
1996                 } else {
1997                         // If setting 0, disable all voltage curve settings
1998                         od_table->GfxclkVolt1 = 0;
1999                         od_table->GfxclkVolt2 = 0;
2000                         od_table->GfxclkVolt3 = 0;
2001                 }
2002                 navi10_dump_od_table(od_table);
2003                 break;
2004         default:
2005                 return -ENOSYS;
2006         }
2007         return ret;
2008 }
2009
2010 static const struct pptable_funcs navi10_ppt_funcs = {
2011         .tables_init = navi10_tables_init,
2012         .alloc_dpm_context = navi10_allocate_dpm_context,
2013         .store_powerplay_table = navi10_store_powerplay_table,
2014         .check_powerplay_table = navi10_check_powerplay_table,
2015         .append_powerplay_table = navi10_append_powerplay_table,
2016         .get_smu_msg_index = navi10_get_smu_msg_index,
2017         .get_smu_clk_index = navi10_get_smu_clk_index,
2018         .get_smu_feature_index = navi10_get_smu_feature_index,
2019         .get_smu_table_index = navi10_get_smu_table_index,
2020         .get_smu_power_index = navi10_get_pwr_src_index,
2021         .get_workload_type = navi10_get_workload_type,
2022         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2023         .set_default_dpm_table = navi10_set_default_dpm_table,
2024         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
2025         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2026         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
2027         .print_clk_levels = navi10_print_clk_levels,
2028         .force_clk_levels = navi10_force_clk_levels,
2029         .populate_umd_state_clk = navi10_populate_umd_state_clk,
2030         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2031         .pre_display_config_changed = navi10_pre_display_config_changed,
2032         .display_config_changed = navi10_display_config_changed,
2033         .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
2034         .force_dpm_limit_value = navi10_force_dpm_limit_value,
2035         .unforce_dpm_levels = navi10_unforce_dpm_levels,
2036         .is_dpm_running = navi10_is_dpm_running,
2037         .get_fan_speed_percent = navi10_get_fan_speed_percent,
2038         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2039         .get_power_profile_mode = navi10_get_power_profile_mode,
2040         .set_power_profile_mode = navi10_set_power_profile_mode,
2041         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
2042         .set_watermarks_table = navi10_set_watermarks_table,
2043         .read_sensor = navi10_read_sensor,
2044         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2045         .set_performance_level = navi10_set_performance_level,
2046         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2047         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2048         .get_power_limit = navi10_get_power_limit,
2049         .update_pcie_parameters = navi10_update_pcie_parameters,
2050         .init_microcode = smu_v11_0_init_microcode,
2051         .load_microcode = smu_v11_0_load_microcode,
2052         .init_smc_tables = smu_v11_0_init_smc_tables,
2053         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2054         .init_power = smu_v11_0_init_power,
2055         .fini_power = smu_v11_0_fini_power,
2056         .check_fw_status = smu_v11_0_check_fw_status,
2057         .setup_pptable = smu_v11_0_setup_pptable,
2058         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2059         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2060         .check_pptable = smu_v11_0_check_pptable,
2061         .parse_pptable = smu_v11_0_parse_pptable,
2062         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2063         .check_fw_version = smu_v11_0_check_fw_version,
2064         .write_pptable = smu_v11_0_write_pptable,
2065         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2066         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2067         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2068         .system_features_control = smu_v11_0_system_features_control,
2069         .send_smc_msg = smu_v11_0_send_msg,
2070         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2071         .read_smc_arg = smu_v11_0_read_arg,
2072         .init_display_count = smu_v11_0_init_display_count,
2073         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2074         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2075         .notify_display_change = smu_v11_0_notify_display_change,
2076         .set_power_limit = smu_v11_0_set_power_limit,
2077         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2078         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2079         .start_thermal_control = smu_v11_0_start_thermal_control,
2080         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2081         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2082         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2083         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2084         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2085         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2086         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2087         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2088         .gfx_off_control = smu_v11_0_gfx_off_control,
2089         .register_irq_handler = smu_v11_0_register_irq_handler,
2090         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2091         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2092         .baco_is_support= smu_v11_0_baco_is_support,
2093         .baco_get_state = smu_v11_0_baco_get_state,
2094         .baco_set_state = smu_v11_0_baco_set_state,
2095         .baco_reset = smu_v11_0_baco_reset,
2096         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2097         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2098         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2099         .set_default_od_settings = navi10_set_default_od_settings,
2100         .od_edit_dpm_table = navi10_od_edit_dpm_table,
2101         .get_pptable_power_limit = navi10_get_pptable_power_limit,
2102 };
2103
2104 void navi10_set_ppt_funcs(struct smu_context *smu)
2105 {
2106         smu->ppt_funcs = &navi10_ppt_funcs;
2107 }