drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_navi10.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "navi10_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_ppsmc.h"
  39
  40 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  41
  42 #define FEATURE_MASK(feature) (1ULL << feature)
  43 #define SMC_DPM_FEATURE ( \
  44         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  45         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  46         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  47         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  48         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  49         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  50         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  51         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  52
  53 #define MSG_MAP(msg, index) \
  54         [SMU_MSG_##msg] = {1, (index)}
  55
  56 static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  57         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  58         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  59         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  60         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  61         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  62         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  63         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  64         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  65         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  66         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  67         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  68         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  69         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  70         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  71         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  72         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  73         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  74         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  75         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  76         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  77         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  78         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  79         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  80         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  81         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  82         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  83         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  84         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  85         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  86         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  87         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  88         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  89         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  90         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  91         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  92         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  93         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  94         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  95         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  96         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  97         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  98         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  99         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
 100         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
 101         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 102         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 103         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 104         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 105         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 106         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 107         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 108         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 109         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 110         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 111         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 112         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 113         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 114         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 115         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 116         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 117         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 118         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 119         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),
 120         MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),
 121 };
 122
 123 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 124         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 125         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 126         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 127         CLK_MAP(FCLK, PPCLK_SOCCLK),
 128         CLK_MAP(UCLK, PPCLK_UCLK),
 129         CLK_MAP(MCLK, PPCLK_UCLK),
 130         CLK_MAP(DCLK, PPCLK_DCLK),
 131         CLK_MAP(VCLK, PPCLK_VCLK),
 132         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 133         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 134         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 135         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 136 };
 137
 138 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 139         FEA_MAP(DPM_PREFETCHER),
 140         FEA_MAP(DPM_GFXCLK),
 141         FEA_MAP(DPM_GFX_PACE),
 142         FEA_MAP(DPM_UCLK),
 143         FEA_MAP(DPM_SOCCLK),
 144         FEA_MAP(DPM_MP0CLK),
 145         FEA_MAP(DPM_LINK),
 146         FEA_MAP(DPM_DCEFCLK),
 147         FEA_MAP(MEM_VDDCI_SCALING),
 148         FEA_MAP(MEM_MVDD_SCALING),
 149         FEA_MAP(DS_GFXCLK),
 150         FEA_MAP(DS_SOCCLK),
 151         FEA_MAP(DS_LCLK),
 152         FEA_MAP(DS_DCEFCLK),
 153         FEA_MAP(DS_UCLK),
 154         FEA_MAP(GFX_ULV),
 155         FEA_MAP(FW_DSTATE),
 156         FEA_MAP(GFXOFF),
 157         FEA_MAP(BACO),
 158         FEA_MAP(VCN_PG),
 159         FEA_MAP(JPEG_PG),
 160         FEA_MAP(USB_PG),
 161         FEA_MAP(RSMU_SMN_CG),
 162         FEA_MAP(PPT),
 163         FEA_MAP(TDC),
 164         FEA_MAP(GFX_EDC),
 165         FEA_MAP(APCC_PLUS),
 166         FEA_MAP(GTHR),
 167         FEA_MAP(ACDC),
 168         FEA_MAP(VR0HOT),
 169         FEA_MAP(VR1HOT),
 170         FEA_MAP(FW_CTF),
 171         FEA_MAP(FAN_CONTROL),
 172         FEA_MAP(THERMAL),
 173         FEA_MAP(GFX_DCS),
 174         FEA_MAP(RM),
 175         FEA_MAP(LED_DISPLAY),
 176         FEA_MAP(GFX_SS),
 177         FEA_MAP(OUT_OF_BAND_MONITOR),
 178         FEA_MAP(TEMP_DEPENDENT_VMIN),
 179         FEA_MAP(MMHUB_PG),
 180         FEA_MAP(ATHUB_PG),
 181         FEA_MAP(APCC_DFLL),
 182 };
 183
 184 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 185         TAB_MAP(PPTABLE),
 186         TAB_MAP(WATERMARKS),
 187         TAB_MAP(AVFS),
 188         TAB_MAP(AVFS_PSM_DEBUG),
 189         TAB_MAP(AVFS_FUSE_OVERRIDE),
 190         TAB_MAP(PMSTATUSLOG),
 191         TAB_MAP(SMU_METRICS),
 192         TAB_MAP(DRIVER_SMU_CONFIG),
 193         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 194         TAB_MAP(OVERDRIVE),
 195         TAB_MAP(I2C_COMMANDS),
 196         TAB_MAP(PACE),
 197 };
 198
 199 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 200         PWR_MAP(AC),
 201         PWR_MAP(DC),
 202 };
 203
 204 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 205         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 212 };
 213
 214 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 215 {
 216         struct smu_11_0_cmn2aisc_mapping mapping;
 217
 218         if (index >= SMU_MSG_MAX_COUNT)
 219                 return -EINVAL;
 220
 221         mapping = navi10_message_map[index];
 222         if (!(mapping.valid_mapping)) {
 223                 return -EINVAL;
 224         }
 225
 226         return mapping.map_to;
 227 }
 228
 229 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 230 {
 231         struct smu_11_0_cmn2aisc_mapping mapping;
 232
 233         if (index >= SMU_CLK_COUNT)
 234                 return -EINVAL;
 235
 236         mapping = navi10_clk_map[index];
 237         if (!(mapping.valid_mapping)) {
 238                 return -EINVAL;
 239         }
 240
 241         return mapping.map_to;
 242 }
 243
 244 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 245 {
 246         struct smu_11_0_cmn2aisc_mapping mapping;
 247
 248         if (index >= SMU_FEATURE_COUNT)
 249                 return -EINVAL;
 250
 251         mapping = navi10_feature_mask_map[index];
 252         if (!(mapping.valid_mapping)) {
 253                 return -EINVAL;
 254         }
 255
 256         return mapping.map_to;
 257 }
 258
 259 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 260 {
 261         struct smu_11_0_cmn2aisc_mapping mapping;
 262
 263         if (index >= SMU_TABLE_COUNT)
 264                 return -EINVAL;
 265
 266         mapping = navi10_table_map[index];
 267         if (!(mapping.valid_mapping)) {
 268                 return -EINVAL;
 269         }
 270
 271         return mapping.map_to;
 272 }
 273
 274 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 275 {
 276         struct smu_11_0_cmn2aisc_mapping mapping;
 277
 278         if (index >= SMU_POWER_SOURCE_COUNT)
 279                 return -EINVAL;
 280
 281         mapping = navi10_pwr_src_map[index];
 282         if (!(mapping.valid_mapping)) {
 283                 return -EINVAL;
 284         }
 285
 286         return mapping.map_to;
 287 }
 288
 289
 290 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 291 {
 292         struct smu_11_0_cmn2aisc_mapping mapping;
 293
 294         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 295                 return -EINVAL;
 296
 297         mapping = navi10_workload_map[profile];
 298         if (!(mapping.valid_mapping)) {
 299                 return -EINVAL;
 300         }
 301
 302         return mapping.map_to;
 303 }
 304
 305 static bool is_asic_secure(struct smu_context *smu)
 306 {
 307         struct amdgpu_device *adev = smu->adev;
 308         bool is_secure = true;
 309         uint32_t mp0_fw_intf;
 310
 311         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 312                                    (smnMP0_FW_INTF & 0xffffffff));
 313
 314         if (!(mp0_fw_intf & (1 << 19)))
 315                 is_secure = false;
 316
 317         return is_secure;
 318 }
 319
 320 static int
 321 navi10_get_allowed_feature_mask(struct smu_context *smu,
 322                                   uint32_t *feature_mask, uint32_t num)
 323 {
 324         struct amdgpu_device *adev = smu->adev;
 325
 326         if (num > 2)
 327                 return -EINVAL;
 328
 329         memset(feature_mask, 0, sizeof(uint32_t) * num);
 330
 331         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 332                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 333                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 334                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 335                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 336                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 337                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 338                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 339                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 340                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 341                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 342                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 343                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 344                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 345                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 346                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 347                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 348                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 349                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 350                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 351                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 352
 353         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 354                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 355
 356         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 357                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 358
 359         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 360                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 361
 362         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 363                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 364
 365         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 366                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 367                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 368                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 369
 370         if (adev->pm.pp_feature & PP_ULV_MASK)
 371                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 372
 373         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 374                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 375
 376         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 377                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 378
 379         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 380                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 381
 382         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 383                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 384
 385         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 386                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
 387                                 | FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 388
 389         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 390         if (is_asic_secure(smu)) {
 391                 /* only for navi10 A0 */
 392                 if ((adev->asic_type == CHIP_NAVI10) &&
 393                         (adev->rev_id == 0)) {
 394                         *(uint64_t *)feature_mask &=
 395                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 396                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 397                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 398                         *(uint64_t *)feature_mask &=
 399                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 400                 }
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int navi10_check_powerplay_table(struct smu_context *smu)
 407 {
 408         return 0;
 409 }
 410
 411 static int navi10_append_powerplay_table(struct smu_context *smu)
 412 {
 413         struct amdgpu_device *adev = smu->adev;
 414         struct smu_table_context *table_context = &smu->smu_table;
 415         PPTable_t *smc_pptable = table_context->driver_pptable;
 416         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 417         int index, ret;
 418
 419         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 420                                            smc_dpm_info);
 421
 422         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 423                                       (uint8_t **)&smc_dpm_table);
 424         if (ret)
 425                 return ret;
 426
 427         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 428                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 429
 430         /* SVI2 Board Parameters */
 431         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 432         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 433         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 434         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 435         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 436         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 437         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 438         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 439         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 440         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 441
 442         /* Telemetry Settings */
 443         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 444         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 445         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 446         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 447         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 448         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 449         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 450         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 451         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 452         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 453         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 454         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 455
 456         /* GPIO Settings */
 457         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 458         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 459         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 460         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 461         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 462         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 463         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 464         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 465
 466         /* LED Display Settings */
 467         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 468         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 469         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 470         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 471
 472         /* GFXCLK PLL Spread Spectrum */
 473         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 474         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 475         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 476
 477         /* GFXCLK DFLL Spread Spectrum */
 478         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 479         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 480         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 481
 482         /* UCLK Spread Spectrum */
 483         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 484         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 485         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 486
 487         /* SOCCLK Spread Spectrum */
 488         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 489         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 490         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 491
 492         /* Total board power */
 493         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 494         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 495
 496         /* Mvdd Svi2 Div Ratio Setting */
 497         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 498
 499         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 500                 /* TODO: remove it once SMU fw fix it */
 501                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int navi10_store_powerplay_table(struct smu_context *smu)
 508 {
 509         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 510         struct smu_table_context *table_context = &smu->smu_table;
 511         struct smu_baco_context *smu_baco = &smu->smu_baco;
 512
 513         if (!table_context->power_play_table)
 514                 return -EINVAL;
 515
 516         powerplay_table = table_context->power_play_table;
 517
 518         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 519                sizeof(PPTable_t));
 520
 521         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 522
 523         mutex_lock(&smu_baco->mutex);
 524         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 525             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 526                 smu_baco->platform_support = true;
 527         mutex_unlock(&smu_baco->mutex);
 528
 529         return 0;
 530 }
 531
 532 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 533 {
 534         struct smu_table_context *smu_table = &smu->smu_table;
 535
 536         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 537                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 538         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 539                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 540         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 541                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 542         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 543                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 544         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 545                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 546         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 547                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 548                        AMDGPU_GEM_DOMAIN_VRAM);
 549
 550         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 551         if (!smu_table->metrics_table)
 552                 return -ENOMEM;
 553         smu_table->metrics_time = 0;
 554
 555         return 0;
 556 }
 557
 558 static int navi10_get_metrics_table(struct smu_context *smu,
 559                                     SmuMetrics_t *metrics_table)
 560 {
 561         struct smu_table_context *smu_table= &smu->smu_table;
 562         int ret = 0;
 563
 564         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 565                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 566                                 (void *)smu_table->metrics_table, false);
 567                 if (ret) {
 568                         pr_info("Failed to export SMU metrics table!\n");
 569                         return ret;
 570                 }
 571                 smu_table->metrics_time = jiffies;
 572         }
 573
 574         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 575
 576         return ret;
 577 }
 578
 579 static int navi10_allocate_dpm_context(struct smu_context *smu)
 580 {
 581         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 582
 583         if (smu_dpm->dpm_context)
 584                 return -EINVAL;
 585
 586         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 587                                        GFP_KERNEL);
 588         if (!smu_dpm->dpm_context)
 589                 return -ENOMEM;
 590
 591         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 592
 593         return 0;
 594 }
 595
 596 static int navi10_set_default_dpm_table(struct smu_context *smu)
 597 {
 598         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 599         struct smu_table_context *table_context = &smu->smu_table;
 600         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 601         PPTable_t *driver_ppt = NULL;
 602
 603         driver_ppt = table_context->driver_pptable;
 604
 605         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 606         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 607
 608         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 609         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 610
 611         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 612         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 613
 614         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 615         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 616
 617         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 618         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 619
 620         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 621         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 622
 623         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 624         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 625
 626         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 627         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 628
 629         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 630         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 631
 632         return 0;
 633 }
 634
 635 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 636 {
 637         struct smu_power_context *smu_power = &smu->smu_power;
 638         struct smu_power_gate *power_gate = &smu_power->power_gate;
 639         int ret = 0;
 640
 641         if (enable) {
 642                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 643                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 644                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 645                         if (ret)
 646                                 return ret;
 647                 }
 648                 power_gate->vcn_gated = false;
 649         } else {
 650                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 651                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 652                         if (ret)
 653                                 return ret;
 654                 }
 655                 power_gate->vcn_gated = true;
 656         }
 657
 658         return ret;
 659 }
 660
 661 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 662                                        enum smu_clk_type clk_type,
 663                                        uint32_t *value)
 664 {
 665         int ret = 0, clk_id = 0;
 666         SmuMetrics_t metrics;
 667
 668         ret = navi10_get_metrics_table(smu, &metrics);
 669         if (ret)
 670                 return ret;
 671
 672         clk_id = smu_clk_get_index(smu, clk_type);
 673         if (clk_id < 0)
 674                 return clk_id;
 675
 676         *value = metrics.CurrClock[clk_id];
 677
 678         return ret;
 679 }
 680
 681 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 682 {
 683         PPTable_t *pptable = smu->smu_table.driver_pptable;
 684         DpmDescriptor_t *dpm_desc = NULL;
 685         uint32_t clk_index = 0;
 686
 687         clk_index = smu_clk_get_index(smu, clk_type);
 688         dpm_desc = &pptable->DpmDescriptor[clk_index];
 689
 690         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 691         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 692 }
 693
 694 static int navi10_print_clk_levels(struct smu_context *smu,
 695                         enum smu_clk_type clk_type, char *buf)
 696 {
 697         int i, size = 0, ret = 0;
 698         uint32_t cur_value = 0, value = 0, count = 0;
 699         uint32_t freq_values[3] = {0};
 700         uint32_t mark_index = 0;
 701
 702         switch (clk_type) {
 703         case SMU_GFXCLK:
 704         case SMU_SCLK:
 705         case SMU_SOCCLK:
 706         case SMU_MCLK:
 707         case SMU_UCLK:
 708         case SMU_FCLK:
 709         case SMU_DCEFCLK:
 710                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 711                 if (ret)
 712                         return size;
 713
 714                 /* 10KHz -> MHz */
 715                 cur_value = cur_value / 100;
 716
 717                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 718                 if (ret)
 719                         return size;
 720
 721                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 722                         for (i = 0; i < count; i++) {
 723                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 724                                 if (ret)
 725                                         return size;
 726
 727                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 728                                                 cur_value == value ? "*" : "");
 729                         }
 730                 } else {
 731                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 732                         if (ret)
 733                                 return size;
 734                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 735                         if (ret)
 736                                 return size;
 737
 738                         freq_values[1] = cur_value;
 739                         mark_index = cur_value == freq_values[0] ? 0 :
 740                                      cur_value == freq_values[2] ? 2 : 1;
 741                         if (mark_index != 1)
 742                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 743
 744                         for (i = 0; i < 3; i++) {
 745                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 746                                                 i == mark_index ? "*" : "");
 747                         }
 748
 749                 }
 750                 break;
 751         default:
 752                 break;
 753         }
 754
 755         return size;
 756 }
 757
 758 static int navi10_force_clk_levels(struct smu_context *smu,
 759                                    enum smu_clk_type clk_type, uint32_t mask)
 760 {
 761
 762         int ret = 0, size = 0;
 763         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 764
 765         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 766         soft_max_level = mask ? (fls(mask) - 1) : 0;
 767
 768         switch (clk_type) {
 769         case SMU_GFXCLK:
 770         case SMU_SCLK:
 771         case SMU_SOCCLK:
 772         case SMU_MCLK:
 773         case SMU_UCLK:
 774         case SMU_DCEFCLK:
 775         case SMU_FCLK:
 776                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 777                 if (ret)
 778                         return size;
 779
 780                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 781                 if (ret)
 782                         return size;
 783
 784                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 785                 if (ret)
 786                         return size;
 787                 break;
 788         default:
 789                 break;
 790         }
 791
 792         return size;
 793 }
 794
 795 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 796 {
 797         int ret = 0;
 798         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 799
 800         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 801         if (ret)
 802                 return ret;
 803
 804         smu->pstate_sclk = min_sclk_freq * 100;
 805
 806         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 807         if (ret)
 808                 return ret;
 809
 810         smu->pstate_mclk = min_mclk_freq * 100;
 811
 812         return ret;
 813 }
 814
 815 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 816                                                  enum smu_clk_type clk_type,
 817                                                  struct pp_clock_levels_with_latency *clocks)
 818 {
 819         int ret = 0, i = 0;
 820         uint32_t level_count = 0, freq = 0;
 821
 822         switch (clk_type) {
 823         case SMU_GFXCLK:
 824         case SMU_DCEFCLK:
 825         case SMU_SOCCLK:
 826                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 827                 if (ret)
 828                         return ret;
 829
 830                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 831                 clocks->num_levels = level_count;
 832
 833                 for (i = 0; i < level_count; i++) {
 834                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 835                         if (ret)
 836                                 return ret;
 837
 838                         clocks->data[i].clocks_in_khz = freq * 1000;
 839                         clocks->data[i].latency_in_us = 0;
 840                 }
 841                 break;
 842         default:
 843                 break;
 844         }
 845
 846         return ret;
 847 }
 848
 849 static int navi10_pre_display_config_changed(struct smu_context *smu)
 850 {
 851         int ret = 0;
 852         uint32_t max_freq = 0;
 853
 854         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 855         if (ret)
 856                 return ret;
 857
 858         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 859                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
 860                 if (ret)
 861                         return ret;
 862                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 863                 if (ret)
 864                         return ret;
 865         }
 866
 867         return ret;
 868 }
 869
 870 static int navi10_display_config_changed(struct smu_context *smu)
 871 {
 872         int ret = 0;
 873
 874         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 875             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 876                 ret = smu_write_watermarks_table(smu);
 877                 if (ret)
 878                         return ret;
 879
 880                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 881         }
 882
 883         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 884             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 885             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 886                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 887                                                   smu->display_config->num_display);
 888                 if (ret)
 889                         return ret;
 890         }
 891
 892         return ret;
 893 }
 894
 895 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 896 {
 897         int ret = 0, i = 0;
 898         uint32_t min_freq, max_freq, force_freq;
 899         enum smu_clk_type clk_type;
 900
 901         enum smu_clk_type clks[] = {
 902                 SMU_GFXCLK,
 903                 SMU_MCLK,
 904                 SMU_SOCCLK,
 905         };
 906
 907         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 908                 clk_type = clks[i];
 909                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 910                 if (ret)
 911                         return ret;
 912
 913                 force_freq = highest ? max_freq : min_freq;
 914                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
 915                 if (ret)
 916                         return ret;
 917         }
 918
 919         return ret;
 920 }
 921
 922 static int navi10_unforce_dpm_levels(struct smu_context *smu)
 923 {
 924         int ret = 0, i = 0;
 925         uint32_t min_freq, max_freq;
 926         enum smu_clk_type clk_type;
 927
 928         enum smu_clk_type clks[] = {
 929                 SMU_GFXCLK,
 930                 SMU_MCLK,
 931                 SMU_SOCCLK,
 932         };
 933
 934         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 935                 clk_type = clks[i];
 936                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 937                 if (ret)
 938                         return ret;
 939
 940                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 941                 if (ret)
 942                         return ret;
 943         }
 944
 945         return ret;
 946 }
 947
 948 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
 949 {
 950         int ret = 0;
 951         SmuMetrics_t metrics;
 952
 953         if (!value)
 954                 return -EINVAL;
 955
 956         ret = navi10_get_metrics_table(smu, &metrics);
 957         if (ret)
 958                 return ret;
 959
 960         *value = metrics.AverageSocketPower << 8;
 961
 962         return 0;
 963 }
 964
 965 static int navi10_get_current_activity_percent(struct smu_context *smu,
 966                                                enum amd_pp_sensors sensor,
 967                                                uint32_t *value)
 968 {
 969         int ret = 0;
 970         SmuMetrics_t metrics;
 971
 972         if (!value)
 973                 return -EINVAL;
 974
 975         ret = navi10_get_metrics_table(smu, &metrics);
 976         if (ret)
 977                 return ret;
 978
 979         switch (sensor) {
 980         case AMDGPU_PP_SENSOR_GPU_LOAD:
 981                 *value = metrics.AverageGfxActivity;
 982                 break;
 983         case AMDGPU_PP_SENSOR_MEM_LOAD:
 984                 *value = metrics.AverageUclkActivity;
 985                 break;
 986         default:
 987                 pr_err("Invalid sensor for retrieving clock activity\n");
 988                 return -EINVAL;
 989         }
 990
 991         return 0;
 992 }
 993
 994 static bool navi10_is_dpm_running(struct smu_context *smu)
 995 {
 996         int ret = 0;
 997         uint32_t feature_mask[2];
 998         unsigned long feature_enabled;
 999         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1000         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1001                            ((uint64_t)feature_mask[1] << 32));
1002         return !!(feature_enabled & SMC_DPM_FEATURE);
1003 }
1004
1005 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1006                                     uint32_t *speed)
1007 {
1008         SmuMetrics_t metrics;
1009         int ret = 0;
1010
1011         if (!speed)
1012                 return -EINVAL;
1013
1014         ret = navi10_get_metrics_table(smu, &metrics);
1015         if (ret)
1016                 return ret;
1017
1018         *speed = metrics.CurrFanSpeed;
1019
1020         return ret;
1021 }
1022
1023 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1024                                         uint32_t *speed)
1025 {
1026         int ret = 0;
1027         uint32_t percent = 0;
1028         uint32_t current_rpm;
1029         PPTable_t *pptable = smu->smu_table.driver_pptable;
1030
1031         ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
1032         if (ret)
1033                 return ret;
1034
1035         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1036         *speed = percent > 100 ? 100 : percent;
1037
1038         return ret;
1039 }
1040
1041 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1042 {
1043         DpmActivityMonitorCoeffInt_t activity_monitor;
1044         uint32_t i, size = 0;
1045         int16_t workload_type = 0;
1046         static const char *profile_name[] = {
1047                                         "BOOTUP_DEFAULT",
1048                                         "3D_FULL_SCREEN",
1049                                         "POWER_SAVING",
1050                                         "VIDEO",
1051                                         "VR",
1052                                         "COMPUTE",
1053                                         "CUSTOM"};
1054         static const char *title[] = {
1055                         "PROFILE_INDEX(NAME)",
1056                         "CLOCK_TYPE(NAME)",
1057                         "FPS",
1058                         "MinFreqType",
1059                         "MinActiveFreqType",
1060                         "MinActiveFreq",
1061                         "BoosterFreqType",
1062                         "BoosterFreq",
1063                         "PD_Data_limit_c",
1064                         "PD_Data_error_coeff",
1065                         "PD_Data_error_rate_coeff"};
1066         int result = 0;
1067
1068         if (!buf)
1069                 return -EINVAL;
1070
1071         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1072                         title[0], title[1], title[2], title[3], title[4], title[5],
1073                         title[6], title[7], title[8], title[9], title[10]);
1074
1075         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1076                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1077                 workload_type = smu_workload_get_type(smu, i);
1078                 if (workload_type < 0)
1079                         return -EINVAL;
1080
1081                 result = smu_update_table(smu,
1082                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1083                                           (void *)(&activity_monitor), false);
1084                 if (result) {
1085                         pr_err("[%s] Failed to get activity monitor!", __func__);
1086                         return result;
1087                 }
1088
1089                 size += sprintf(buf + size, "%2d %14s%s:\n",
1090                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1091
1092                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1093                         " ",
1094                         0,
1095                         "GFXCLK",
1096                         activity_monitor.Gfx_FPS,
1097                         activity_monitor.Gfx_MinFreqStep,
1098                         activity_monitor.Gfx_MinActiveFreqType,
1099                         activity_monitor.Gfx_MinActiveFreq,
1100                         activity_monitor.Gfx_BoosterFreqType,
1101                         activity_monitor.Gfx_BoosterFreq,
1102                         activity_monitor.Gfx_PD_Data_limit_c,
1103                         activity_monitor.Gfx_PD_Data_error_coeff,
1104                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1105
1106                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1107                         " ",
1108                         1,
1109                         "SOCCLK",
1110                         activity_monitor.Soc_FPS,
1111                         activity_monitor.Soc_MinFreqStep,
1112                         activity_monitor.Soc_MinActiveFreqType,
1113                         activity_monitor.Soc_MinActiveFreq,
1114                         activity_monitor.Soc_BoosterFreqType,
1115                         activity_monitor.Soc_BoosterFreq,
1116                         activity_monitor.Soc_PD_Data_limit_c,
1117                         activity_monitor.Soc_PD_Data_error_coeff,
1118                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1119
1120                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1121                         " ",
1122                         2,
1123                         "MEMLK",
1124                         activity_monitor.Mem_FPS,
1125                         activity_monitor.Mem_MinFreqStep,
1126                         activity_monitor.Mem_MinActiveFreqType,
1127                         activity_monitor.Mem_MinActiveFreq,
1128                         activity_monitor.Mem_BoosterFreqType,
1129                         activity_monitor.Mem_BoosterFreq,
1130                         activity_monitor.Mem_PD_Data_limit_c,
1131                         activity_monitor.Mem_PD_Data_error_coeff,
1132                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1133         }
1134
1135         return size;
1136 }
1137
1138 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1139 {
1140         DpmActivityMonitorCoeffInt_t activity_monitor;
1141         int workload_type, ret = 0;
1142
1143         smu->power_profile_mode = input[size];
1144
1145         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1146                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1147                 return -EINVAL;
1148         }
1149
1150         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1151                 if (size < 0)
1152                         return -EINVAL;
1153
1154                 ret = smu_update_table(smu,
1155                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1156                                        (void *)(&activity_monitor), false);
1157                 if (ret) {
1158                         pr_err("[%s] Failed to get activity monitor!", __func__);
1159                         return ret;
1160                 }
1161
1162                 switch (input[0]) {
1163                 case 0: /* Gfxclk */
1164                         activity_monitor.Gfx_FPS = input[1];
1165                         activity_monitor.Gfx_MinFreqStep = input[2];
1166                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1167                         activity_monitor.Gfx_MinActiveFreq = input[4];
1168                         activity_monitor.Gfx_BoosterFreqType = input[5];
1169                         activity_monitor.Gfx_BoosterFreq = input[6];
1170                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1171                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1172                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1173                         break;
1174                 case 1: /* Socclk */
1175                         activity_monitor.Soc_FPS = input[1];
1176                         activity_monitor.Soc_MinFreqStep = input[2];
1177                         activity_monitor.Soc_MinActiveFreqType = input[3];
1178                         activity_monitor.Soc_MinActiveFreq = input[4];
1179                         activity_monitor.Soc_BoosterFreqType = input[5];
1180                         activity_monitor.Soc_BoosterFreq = input[6];
1181                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1182                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1183                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1184                         break;
1185                 case 2: /* Memlk */
1186                         activity_monitor.Mem_FPS = input[1];
1187                         activity_monitor.Mem_MinFreqStep = input[2];
1188                         activity_monitor.Mem_MinActiveFreqType = input[3];
1189                         activity_monitor.Mem_MinActiveFreq = input[4];
1190                         activity_monitor.Mem_BoosterFreqType = input[5];
1191                         activity_monitor.Mem_BoosterFreq = input[6];
1192                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1193                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1194                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1195                         break;
1196                 }
1197
1198                 ret = smu_update_table(smu,
1199                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1200                                        (void *)(&activity_monitor), true);
1201                 if (ret) {
1202                         pr_err("[%s] Failed to set activity monitor!", __func__);
1203                         return ret;
1204                 }
1205         }
1206
1207         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1208         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1209         if (workload_type < 0)
1210                 return -EINVAL;
1211         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1212                                     1 << workload_type);
1213
1214         return ret;
1215 }
1216
1217 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1218                                          enum amd_dpm_forced_level level,
1219                                          uint32_t *sclk_mask,
1220                                          uint32_t *mclk_mask,
1221                                          uint32_t *soc_mask)
1222 {
1223         int ret = 0;
1224         uint32_t level_count = 0;
1225
1226         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1227                 if (sclk_mask)
1228                         *sclk_mask = 0;
1229         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1230                 if (mclk_mask)
1231                         *mclk_mask = 0;
1232         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1233                 if(sclk_mask) {
1234                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1235                         if (ret)
1236                                 return ret;
1237                         *sclk_mask = level_count - 1;
1238                 }
1239
1240                 if(mclk_mask) {
1241                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1242                         if (ret)
1243                                 return ret;
1244                         *mclk_mask = level_count - 1;
1245                 }
1246
1247                 if(soc_mask) {
1248                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1249                         if (ret)
1250                                 return ret;
1251                         *soc_mask = level_count - 1;
1252                 }
1253         }
1254
1255         return ret;
1256 }
1257
1258 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1259 {
1260         struct smu_clocks min_clocks = {0};
1261         struct pp_display_clock_request clock_req;
1262         int ret = 0;
1263
1264         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1265         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1266         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1267
1268         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1269                 clock_req.clock_type = amd_pp_dcef_clock;
1270                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1271
1272                 if (smu->funcs->display_clock_voltage_request)
1273                         ret = smu->funcs->display_clock_voltage_request(smu, &clock_req);
1274                 if (!ret) {
1275                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1276                                 ret = smu_send_smc_msg_with_param(smu,
1277                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1278                                                                   min_clocks.dcef_clock_in_sr/100);
1279                                 if (ret) {
1280                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1281                                         return ret;
1282                                 }
1283                         }
1284                 } else {
1285                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1286                 }
1287         }
1288
1289         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1290                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1291                 if (ret) {
1292                         pr_err("[%s] Set hard min uclk failed!", __func__);
1293                         return ret;
1294                 }
1295         }
1296
1297         return 0;
1298 }
1299
1300 static int navi10_set_watermarks_table(struct smu_context *smu,
1301                                        void *watermarks, struct
1302                                        dm_pp_wm_sets_with_clock_ranges_soc15
1303                                        *clock_ranges)
1304 {
1305         int i;
1306         Watermarks_t *table = watermarks;
1307
1308         if (!table || !clock_ranges)
1309                 return -EINVAL;
1310
1311         if (clock_ranges->num_wm_dmif_sets > 4 ||
1312             clock_ranges->num_wm_mcif_sets > 4)
1313                 return -EINVAL;
1314
1315         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1316                 table->WatermarkRow[1][i].MinClock =
1317                         cpu_to_le16((uint16_t)
1318                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1319                         1000));
1320                 table->WatermarkRow[1][i].MaxClock =
1321                         cpu_to_le16((uint16_t)
1322                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1323                         1000));
1324                 table->WatermarkRow[1][i].MinUclk =
1325                         cpu_to_le16((uint16_t)
1326                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1327                         1000));
1328                 table->WatermarkRow[1][i].MaxUclk =
1329                         cpu_to_le16((uint16_t)
1330                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1331                         1000));
1332                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1333                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1334         }
1335
1336         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1337                 table->WatermarkRow[0][i].MinClock =
1338                         cpu_to_le16((uint16_t)
1339                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1340                         1000));
1341                 table->WatermarkRow[0][i].MaxClock =
1342                         cpu_to_le16((uint16_t)
1343                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1344                         1000));
1345                 table->WatermarkRow[0][i].MinUclk =
1346                         cpu_to_le16((uint16_t)
1347                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1348                         1000));
1349                 table->WatermarkRow[0][i].MaxUclk =
1350                         cpu_to_le16((uint16_t)
1351                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1352                         1000));
1353                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1354                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1355         }
1356
1357         return 0;
1358 }
1359
1360 static int navi10_thermal_get_temperature(struct smu_context *smu,
1361                                              enum amd_pp_sensors sensor,
1362                                              uint32_t *value)
1363 {
1364         SmuMetrics_t metrics;
1365         int ret = 0;
1366
1367         if (!value)
1368                 return -EINVAL;
1369
1370         ret = navi10_get_metrics_table(smu, &metrics);
1371         if (ret)
1372                 return ret;
1373
1374         switch (sensor) {
1375         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1376                 *value = metrics.TemperatureHotspot *
1377                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1378                 break;
1379         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1380                 *value = metrics.TemperatureEdge *
1381                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1382                 break;
1383         case AMDGPU_PP_SENSOR_MEM_TEMP:
1384                 *value = metrics.TemperatureMem *
1385                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1386                 break;
1387         default:
1388                 pr_err("Invalid sensor for retrieving temp\n");
1389                 return -EINVAL;
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int navi10_read_sensor(struct smu_context *smu,
1396                                  enum amd_pp_sensors sensor,
1397                                  void *data, uint32_t *size)
1398 {
1399         int ret = 0;
1400         struct smu_table_context *table_context = &smu->smu_table;
1401         PPTable_t *pptable = table_context->driver_pptable;
1402
1403         if(!data || !size)
1404                 return -EINVAL;
1405
1406         mutex_lock(&smu->sensor_lock);
1407         switch (sensor) {
1408         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1409                 *(uint32_t *)data = pptable->FanMaximumRpm;
1410                 *size = 4;
1411                 break;
1412         case AMDGPU_PP_SENSOR_MEM_LOAD:
1413         case AMDGPU_PP_SENSOR_GPU_LOAD:
1414                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1415                 *size = 4;
1416                 break;
1417         case AMDGPU_PP_SENSOR_GPU_POWER:
1418                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1419                 *size = 4;
1420                 break;
1421         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1422         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1423         case AMDGPU_PP_SENSOR_MEM_TEMP:
1424                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1425                 *size = 4;
1426                 break;
1427         default:
1428                 ret = smu_smc_read_sensor(smu, sensor, data, size);
1429         }
1430         mutex_unlock(&smu->sensor_lock);
1431
1432         return ret;
1433 }
1434
1435 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1436 {
1437         uint32_t num_discrete_levels = 0;
1438         uint16_t *dpm_levels = NULL;
1439         uint16_t i = 0;
1440         struct smu_table_context *table_context = &smu->smu_table;
1441         PPTable_t *driver_ppt = NULL;
1442
1443         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1444                 return -EINVAL;
1445
1446         driver_ppt = table_context->driver_pptable;
1447         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1448         dpm_levels = driver_ppt->FreqTableUclk;
1449
1450         if (num_discrete_levels == 0 || dpm_levels == NULL)
1451                 return -EINVAL;
1452
1453         *num_states = num_discrete_levels;
1454         for (i = 0; i < num_discrete_levels; i++) {
1455                 /* convert to khz */
1456                 *clocks_in_khz = (*dpm_levels) * 1000;
1457                 clocks_in_khz++;
1458                 dpm_levels++;
1459         }
1460
1461         return 0;
1462 }
1463
1464 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
1465 {
1466         struct amdgpu_device *adev = smu->adev;
1467         int ret = 0;
1468         uint32_t sclk_freq = 0, uclk_freq = 0;
1469         uint32_t uclk_level = 0;
1470
1471         switch (adev->asic_type) {
1472         case CHIP_NAVI10:
1473                 switch (adev->pdev->revision) {
1474                 case 0xf0: /* XTX */
1475                 case 0xc0:
1476                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1477                         break;
1478                 case 0xf1: /* XT */
1479                 case 0xc1:
1480                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1481                         break;
1482                 default: /* XL */
1483                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1484                         break;
1485                 }
1486                 break;
1487         case CHIP_NAVI14:
1488                 switch (adev->pdev->revision) {
1489                 case 0xc7: /* XT */
1490                 case 0xf4:
1491                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1492                         break;
1493                 case 0xc1: /* XTM */
1494                 case 0xf2:
1495                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1496                         break;
1497                 case 0xc3: /* XLM */
1498                 case 0xf3:
1499                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1500                         break;
1501                 case 0xc5: /* XTX */
1502                 case 0xf6:
1503                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1504                         break;
1505                 default: /* XL */
1506                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1507                         break;
1508                 }
1509                 break;
1510         default:
1511                 return -EINVAL;
1512         }
1513
1514         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
1515         if (ret)
1516                 return ret;
1517         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
1518         if (ret)
1519                 return ret;
1520
1521         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1522         if (ret)
1523                 return ret;
1524         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1525         if (ret)
1526                 return ret;
1527
1528         return ret;
1529 }
1530
1531 static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1532 {
1533         int ret = 0;
1534
1535         switch (level) {
1536         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1537                 ret = navi10_set_peak_clock_by_device(smu);
1538                 break;
1539         default:
1540                 ret = -EINVAL;
1541                 break;
1542         }
1543
1544         return ret;
1545 }
1546
1547 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1548                                                 struct smu_temperature_range *range)
1549 {
1550         struct smu_table_context *table_context = &smu->smu_table;
1551         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1552
1553         if (!range || !powerplay_table)
1554                 return -EINVAL;
1555
1556         range->max = powerplay_table->software_shutdown_temp *
1557                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1558
1559         return 0;
1560 }
1561
1562 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1563                                                 bool disable_memory_clock_switch)
1564 {
1565         int ret = 0;
1566         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1567                 (struct smu_11_0_max_sustainable_clocks *)
1568                         smu->smu_table.max_sustainable_clocks;
1569         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1570         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1571
1572         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1573                 return 0;
1574
1575         if(disable_memory_clock_switch)
1576                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1577         else
1578                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1579
1580         if(!ret)
1581                 smu->disable_uclk_switch = disable_memory_clock_switch;
1582
1583         return ret;
1584 }
1585
1586 static int navi10_get_power_limit(struct smu_context *smu,
1587                                      uint32_t *limit,
1588                                      bool asic_default)
1589 {
1590         PPTable_t *pptable = smu->smu_table.driver_pptable;
1591         uint32_t asic_default_power_limit = 0;
1592         int ret = 0;
1593         int power_src;
1594
1595         if (!smu->default_power_limit ||
1596             !smu->power_limit) {
1597                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1598                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1599                         if (power_src < 0)
1600                                 return -EINVAL;
1601
1602                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1603                                 power_src << 16);
1604                         if (ret) {
1605                                 pr_err("[%s] get PPT limit failed!", __func__);
1606                                 return ret;
1607                         }
1608                         smu_read_smc_arg(smu, &asic_default_power_limit);
1609                 } else {
1610                         /* the last hope to figure out the ppt limit */
1611                         if (!pptable) {
1612                                 pr_err("Cannot get PPT limit due to pptable missing!");
1613                                 return -EINVAL;
1614                         }
1615                         asic_default_power_limit =
1616                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1617                 }
1618
1619                 if (smu->od_enabled) {
1620                         asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
1621                         asic_default_power_limit /= 100;
1622                 }
1623
1624                 smu->default_power_limit = asic_default_power_limit;
1625                 smu->power_limit = asic_default_power_limit;
1626         }
1627
1628         if (asic_default)
1629                 *limit = smu->default_power_limit;
1630         else
1631                 *limit = smu->power_limit;
1632
1633         return 0;
1634 }
1635
1636 static int navi10_update_pcie_parameters(struct smu_context *smu,
1637                                      uint32_t pcie_gen_cap,
1638                                      uint32_t pcie_width_cap)
1639 {
1640         PPTable_t *pptable = smu->smu_table.driver_pptable;
1641         int ret, i;
1642         uint32_t smu_pcie_arg;
1643
1644         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1645                 smu_pcie_arg = (i << 16) |
1646                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1647                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1648                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1649                 ret = smu_send_smc_msg_with_param(smu,
1650                                           SMU_MSG_OverridePcieParameters,
1651                                           smu_pcie_arg);
1652         }
1653
1654         return ret;
1655 }
1656
1657
1658 static const struct pptable_funcs navi10_ppt_funcs = {
1659         .tables_init = navi10_tables_init,
1660         .alloc_dpm_context = navi10_allocate_dpm_context,
1661         .store_powerplay_table = navi10_store_powerplay_table,
1662         .check_powerplay_table = navi10_check_powerplay_table,
1663         .append_powerplay_table = navi10_append_powerplay_table,
1664         .get_smu_msg_index = navi10_get_smu_msg_index,
1665         .get_smu_clk_index = navi10_get_smu_clk_index,
1666         .get_smu_feature_index = navi10_get_smu_feature_index,
1667         .get_smu_table_index = navi10_get_smu_table_index,
1668         .get_smu_power_index = navi10_get_pwr_src_index,
1669         .get_workload_type = navi10_get_workload_type,
1670         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
1671         .set_default_dpm_table = navi10_set_default_dpm_table,
1672         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
1673         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
1674         .print_clk_levels = navi10_print_clk_levels,
1675         .force_clk_levels = navi10_force_clk_levels,
1676         .populate_umd_state_clk = navi10_populate_umd_state_clk,
1677         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
1678         .pre_display_config_changed = navi10_pre_display_config_changed,
1679         .display_config_changed = navi10_display_config_changed,
1680         .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
1681         .force_dpm_limit_value = navi10_force_dpm_limit_value,
1682         .unforce_dpm_levels = navi10_unforce_dpm_levels,
1683         .is_dpm_running = navi10_is_dpm_running,
1684         .get_fan_speed_percent = navi10_get_fan_speed_percent,
1685         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
1686         .get_power_profile_mode = navi10_get_power_profile_mode,
1687         .set_power_profile_mode = navi10_set_power_profile_mode,
1688         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
1689         .set_watermarks_table = navi10_set_watermarks_table,
1690         .read_sensor = navi10_read_sensor,
1691         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
1692         .set_performance_level = navi10_set_performance_level,
1693         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
1694         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
1695         .get_power_limit = navi10_get_power_limit,
1696         .update_pcie_parameters = navi10_update_pcie_parameters,
1697 };
1698
1699 void navi10_set_ppt_funcs(struct smu_context *smu)
1700 {
1701         smu->ppt_funcs = &navi10_ppt_funcs;
1702 }