2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "atomfirmware.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "smu_v11_0.h"
31 #include "smu11_driver_if_navi10.h"
32 #include "soc15_common.h"
34 #include "navi10_ppt.h"
35 #include "smu_v11_0_pptable.h"
36 #include "smu_v11_0_ppsmc.h"
38 #define FEATURE_MASK(feature) (1UL << feature)
39 #define SMC_DPM_FEATURE ( \
40 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
41 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
42 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
43 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
44 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
45 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
46 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
47 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
49 #define MSG_MAP(msg, index) \
50 [SMU_MSG_##msg] = index
52 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
53 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
54 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
55 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
56 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
57 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
58 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
59 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
60 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
61 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
62 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
63 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
64 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
65 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
66 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
67 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
68 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
69 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
70 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
71 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
72 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
73 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
74 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
75 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
76 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc),
77 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
78 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
79 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
80 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
81 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
82 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
83 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
84 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
85 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig),
86 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
87 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
88 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
89 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
90 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk),
91 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
92 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
93 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
94 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
95 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
96 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
97 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
98 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
99 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt),
100 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays),
101 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
102 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
103 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
104 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
105 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
106 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
107 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
108 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
109 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
110 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
111 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
112 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
113 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
114 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
117 static int navi10_clk_map[SMU_CLK_COUNT] = {
118 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
119 CLK_MAP(SCLK, PPCLK_GFXCLK),
120 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
121 CLK_MAP(FCLK, PPCLK_SOCCLK),
122 CLK_MAP(UCLK, PPCLK_UCLK),
123 CLK_MAP(MCLK, PPCLK_UCLK),
124 CLK_MAP(DCLK, PPCLK_DCLK),
125 CLK_MAP(VCLK, PPCLK_VCLK),
126 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
127 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
128 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
129 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
132 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
133 FEA_MAP(DPM_PREFETCHER),
135 FEA_MAP(DPM_GFX_PACE),
140 FEA_MAP(DPM_DCEFCLK),
141 FEA_MAP(MEM_VDDCI_SCALING),
142 FEA_MAP(MEM_MVDD_SCALING),
155 FEA_MAP(RSMU_SMN_CG),
165 FEA_MAP(FAN_CONTROL),
169 FEA_MAP(LED_DISPLAY),
171 FEA_MAP(OUT_OF_BAND_MONITOR),
172 FEA_MAP(TEMP_DEPENDENT_VMIN),
177 static int navi10_table_map[SMU_TABLE_COUNT] = {
181 TAB_MAP(AVFS_PSM_DEBUG),
182 TAB_MAP(AVFS_FUSE_OVERRIDE),
183 TAB_MAP(PMSTATUSLOG),
184 TAB_MAP(SMU_METRICS),
185 TAB_MAP(DRIVER_SMU_CONFIG),
186 TAB_MAP(ACTIVITY_MONITOR_COEFF),
188 TAB_MAP(I2C_COMMANDS),
192 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
197 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
200 if (index > SMU_MSG_MAX_COUNT)
203 val = navi10_message_map[index];
204 if (val > PPSMC_Message_Count)
210 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
213 if (index >= SMU_CLK_COUNT)
216 val = navi10_clk_map[index];
217 if (val >= PPCLK_COUNT)
223 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
226 if (index >= SMU_FEATURE_COUNT)
229 val = navi10_feature_mask_map[index];
236 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
239 if (index >= SMU_TABLE_COUNT)
242 val = navi10_table_map[index];
243 if (val >= TABLE_COUNT)
249 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
252 if (index >= SMU_POWER_SOURCE_COUNT)
255 val = navi10_pwr_src_map[index];
256 if (val >= POWER_SOURCE_COUNT)
263 navi10_get_allowed_feature_mask(struct smu_context *smu,
264 uint32_t *feature_mask, uint32_t num)
266 struct amdgpu_device *adev = smu->adev;
271 memset(feature_mask, 0, sizeof(uint32_t) * num);
273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
274 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
275 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
276 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
277 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
278 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
279 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
280 | FEATURE_MASK(FEATURE_PPT_BIT)
281 | FEATURE_MASK(FEATURE_TDC_BIT)
282 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
283 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
284 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
285 | FEATURE_MASK(FEATURE_THERMAL_BIT)
286 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
287 | FEATURE_MASK(FEATURE_MMHUB_PG_BIT)
288 | FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
289 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
291 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
293 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
294 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
296 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
298 | FEATURE_MASK(FEATURE_GFXOFF_BIT);
300 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
301 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
306 static int navi10_check_powerplay_table(struct smu_context *smu)
311 static int navi10_append_powerplay_table(struct smu_context *smu)
313 struct amdgpu_device *adev = smu->adev;
314 struct smu_table_context *table_context = &smu->smu_table;
315 PPTable_t *smc_pptable = table_context->driver_pptable;
316 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
319 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
322 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
323 (uint8_t **)&smc_dpm_table);
327 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
328 sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
330 /* SVI2 Board Parameters */
331 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
332 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
333 smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
334 smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
335 smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
336 smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
337 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
338 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
339 smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
340 smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
342 /* Telemetry Settings */
343 smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
344 smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
345 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
346 smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
347 smc_pptable->SocOffset = smc_dpm_table->SocOffset;
348 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
349 smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
350 smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
351 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
352 smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
353 smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
354 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
357 smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
358 smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
359 smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
360 smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
361 smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
362 smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
363 smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
364 smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
366 /* LED Display Settings */
367 smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
368 smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
369 smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
370 smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
372 /* GFXCLK PLL Spread Spectrum */
373 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
374 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
375 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
377 /* GFXCLK DFLL Spread Spectrum */
378 smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
379 smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
380 smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
382 /* UCLK Spread Spectrum */
383 smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
384 smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
385 smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
387 /* SOCCLK Spread Spectrum */
388 smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
389 smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
390 smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
392 /* Total board power */
393 smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
394 smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
396 /* Mvdd Svi2 Div Ratio Setting */
397 smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
399 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
400 *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
401 | FEATURE_MASK(FEATURE_GFXOFF_BIT);
403 /* TODO: remove it once SMU fw fix it */
404 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
410 static int navi10_store_powerplay_table(struct smu_context *smu)
412 struct smu_11_0_powerplay_table *powerplay_table = NULL;
413 struct smu_table_context *table_context = &smu->smu_table;
415 if (!table_context->power_play_table)
418 powerplay_table = table_context->power_play_table;
420 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
426 static void navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
428 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
429 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
430 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
431 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
432 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
433 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
434 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
435 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
436 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
437 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
438 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
439 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
440 AMDGPU_GEM_DOMAIN_VRAM);
443 static int navi10_allocate_dpm_context(struct smu_context *smu)
445 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
447 if (smu_dpm->dpm_context)
450 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
452 if (!smu_dpm->dpm_context)
455 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
460 static int navi10_set_default_dpm_table(struct smu_context *smu)
462 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
463 struct smu_table_context *table_context = &smu->smu_table;
464 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
465 PPTable_t *driver_ppt = NULL;
467 driver_ppt = table_context->driver_pptable;
469 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
470 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
472 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
473 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
475 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
476 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
478 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
479 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
481 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
482 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
484 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
485 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
487 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
488 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
490 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
491 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
493 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
494 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
499 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
504 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
508 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
516 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
517 enum smu_clk_type clk_type,
520 static SmuMetrics_t metrics = {0};
521 int ret = 0, clk_id = 0;
526 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
530 clk_id = smu_clk_get_index(smu, clk_type);
534 *value = metrics.CurrClock[clk_id];
539 static int navi10_print_clk_levels(struct smu_context *smu,
540 enum smu_clk_type clk_type, char *buf)
542 int i, size = 0, ret = 0;
543 uint32_t cur_value = 0, value = 0, count = 0;
553 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
557 size += sprintf(buf, "current clk: %uMhz\n", cur_value);
559 ret = smu_get_dpm_level_count(smu, clk_type, &count);
563 for (i = 0; i < count; i++) {
564 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
568 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
569 cur_value == value ? "*" : "");
579 static int navi10_force_clk_levels(struct smu_context *smu,
580 enum smu_clk_type clk_type, uint32_t mask)
583 int ret = 0, size = 0;
584 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
586 soft_min_level = mask ? (ffs(mask) - 1) : 0;
587 soft_max_level = mask ? (fls(mask) - 1) : 0;
596 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
600 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
604 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
615 static int navi10_populate_umd_state_clk(struct smu_context *smu)
618 uint32_t min_sclk_freq = 0;
620 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
624 smu->pstate_sclk = min_sclk_freq * 100;
629 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
630 enum smu_clk_type clk_type,
631 struct pp_clock_levels_with_latency *clocks)
634 uint32_t level_count = 0, freq = 0;
640 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
644 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
645 clocks->num_levels = level_count;
647 for (i = 0; i < level_count; i++) {
648 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
652 clocks->data[i].clocks_in_khz = freq * 1000;
653 clocks->data[i].latency_in_us = 0;
663 static int navi10_pre_display_config_changed(struct smu_context *smu)
666 uint32_t max_freq = 0;
668 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
672 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
673 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
676 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
684 static int navi10_display_config_changed(struct smu_context *smu)
688 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
689 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
690 ret = smu_write_watermarks_table(smu);
694 smu->watermarks_bitmap |= WATERMARKS_LOADED;
697 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
698 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
699 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
700 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
701 smu->display_config->num_display);
709 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
712 uint32_t min_freq, max_freq, force_freq;
713 enum smu_clk_type clk_type;
715 enum smu_clk_type clks[] = {
721 for (i = 0; i < ARRAY_SIZE(clks); i++) {
723 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
727 force_freq = highest ? max_freq : min_freq;
728 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
736 static int navi10_unforce_dpm_levels(struct smu_context *smu) {
739 uint32_t min_freq, max_freq;
740 enum smu_clk_type clk_type;
742 enum smu_clk_type clks[] = {
748 for (i = 0; i < ARRAY_SIZE(clks); i++) {
750 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
754 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
762 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
765 SmuMetrics_t metrics;
770 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics,
775 *value = metrics.CurrSocketPower << 8;
780 static int navi10_get_current_activity_percent(struct smu_context *smu,
784 SmuMetrics_t metrics;
789 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
790 (void *)&metrics, false);
794 *value = metrics.AverageGfxActivity;
799 static bool navi10_is_dpm_running(struct smu_context *smu)
802 uint32_t feature_mask[2];
803 unsigned long feature_enabled;
804 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
805 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
806 ((uint64_t)feature_mask[1] << 32));
807 return !!(feature_enabled & SMC_DPM_FEATURE);
810 static const struct pptable_funcs navi10_ppt_funcs = {
811 .tables_init = navi10_tables_init,
812 .alloc_dpm_context = navi10_allocate_dpm_context,
813 .store_powerplay_table = navi10_store_powerplay_table,
814 .check_powerplay_table = navi10_check_powerplay_table,
815 .append_powerplay_table = navi10_append_powerplay_table,
816 .get_smu_msg_index = navi10_get_smu_msg_index,
817 .get_smu_clk_index = navi10_get_smu_clk_index,
818 .get_smu_feature_index = navi10_get_smu_feature_index,
819 .get_smu_table_index = navi10_get_smu_table_index,
820 .get_smu_power_index = navi10_get_pwr_src_index,
821 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
822 .set_default_dpm_table = navi10_set_default_dpm_table,
823 .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
824 .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
825 .print_clk_levels = navi10_print_clk_levels,
826 .force_clk_levels = navi10_force_clk_levels,
827 .populate_umd_state_clk = navi10_populate_umd_state_clk,
828 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
829 .pre_display_config_changed = navi10_pre_display_config_changed,
830 .display_config_changed = navi10_display_config_changed,
831 .force_dpm_limit_value = navi10_force_dpm_limit_value,
832 .unforce_dpm_levels = navi10_unforce_dpm_levels,
833 .get_gpu_power = navi10_get_gpu_power,
834 .get_current_activity_percent = navi10_get_current_activity_percent,
835 .is_dpm_running = navi10_is_dpm_running,
838 void navi10_set_ppt_funcs(struct smu_context *smu)
840 struct smu_table_context *smu_table = &smu->smu_table;
842 smu->ppt_funcs = &navi10_ppt_funcs;
843 smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
844 smu_table->table_count = TABLE_COUNT;