drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_navi10.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "navi10_ppt.h"
  35 #include "smu_v11_0_pptable.h"
  36 #include "smu_v11_0_ppsmc.h"
  37
  38 #define FEATURE_MASK(feature) (1UL << feature)
  39 #define SMC_DPM_FEATURE ( \
  40         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  41         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  42         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  43         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  44         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  45         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  46         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  47         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  48
  49 #define MSG_MAP(msg, index) \
  50         [SMU_MSG_##msg] = index
  51
  52 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
  53         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  54         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  55         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  56         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  57         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  58         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  59         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  60         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  61         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  62         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  63         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  64         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  65         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  66         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  67         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  68         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  69         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  70         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  71         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  72         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  73         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  74         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  75         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  76         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  77         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  78         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  79         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  80         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  81         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  82         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  83         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  84         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  85         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  86         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  87         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  88         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  89         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  90         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  91         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  92         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  93         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  94         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  95         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  96         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
  97         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
  98         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
  99         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 100         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 101         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 102         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 103         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 104         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 105         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 106         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 107         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 108         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 109         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 110         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 111         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 112         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 113         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 114         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 115 };
 116
 117 static int navi10_clk_map[SMU_CLK_COUNT] = {
 118         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 119         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 120         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 121         CLK_MAP(FCLK, PPCLK_SOCCLK),
 122         CLK_MAP(UCLK, PPCLK_UCLK),
 123         CLK_MAP(MCLK, PPCLK_UCLK),
 124         CLK_MAP(DCLK, PPCLK_DCLK),
 125         CLK_MAP(VCLK, PPCLK_VCLK),
 126         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 127         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 128         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 129         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 130 };
 131
 132 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 133         FEA_MAP(DPM_PREFETCHER),
 134         FEA_MAP(DPM_GFXCLK),
 135         FEA_MAP(DPM_GFX_PACE),
 136         FEA_MAP(DPM_UCLK),
 137         FEA_MAP(DPM_SOCCLK),
 138         FEA_MAP(DPM_MP0CLK),
 139         FEA_MAP(DPM_LINK),
 140         FEA_MAP(DPM_DCEFCLK),
 141         FEA_MAP(MEM_VDDCI_SCALING),
 142         FEA_MAP(MEM_MVDD_SCALING),
 143         FEA_MAP(DS_GFXCLK),
 144         FEA_MAP(DS_SOCCLK),
 145         FEA_MAP(DS_LCLK),
 146         FEA_MAP(DS_DCEFCLK),
 147         FEA_MAP(DS_UCLK),
 148         FEA_MAP(GFX_ULV),
 149         FEA_MAP(FW_DSTATE),
 150         FEA_MAP(GFXOFF),
 151         FEA_MAP(BACO),
 152         FEA_MAP(VCN_PG),
 153         FEA_MAP(JPEG_PG),
 154         FEA_MAP(USB_PG),
 155         FEA_MAP(RSMU_SMN_CG),
 156         FEA_MAP(PPT),
 157         FEA_MAP(TDC),
 158         FEA_MAP(GFX_EDC),
 159         FEA_MAP(APCC_PLUS),
 160         FEA_MAP(GTHR),
 161         FEA_MAP(ACDC),
 162         FEA_MAP(VR0HOT),
 163         FEA_MAP(VR1HOT),
 164         FEA_MAP(FW_CTF),
 165         FEA_MAP(FAN_CONTROL),
 166         FEA_MAP(THERMAL),
 167         FEA_MAP(GFX_DCS),
 168         FEA_MAP(RM),
 169         FEA_MAP(LED_DISPLAY),
 170         FEA_MAP(GFX_SS),
 171         FEA_MAP(OUT_OF_BAND_MONITOR),
 172         FEA_MAP(TEMP_DEPENDENT_VMIN),
 173         FEA_MAP(MMHUB_PG),
 174         FEA_MAP(ATHUB_PG),
 175 };
 176
 177 static int navi10_table_map[SMU_TABLE_COUNT] = {
 178         TAB_MAP(PPTABLE),
 179         TAB_MAP(WATERMARKS),
 180         TAB_MAP(AVFS),
 181         TAB_MAP(AVFS_PSM_DEBUG),
 182         TAB_MAP(AVFS_FUSE_OVERRIDE),
 183         TAB_MAP(PMSTATUSLOG),
 184         TAB_MAP(SMU_METRICS),
 185         TAB_MAP(DRIVER_SMU_CONFIG),
 186         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 187         TAB_MAP(OVERDRIVE),
 188         TAB_MAP(I2C_COMMANDS),
 189         TAB_MAP(PACE),
 190 };
 191
 192 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 193         PWR_MAP(AC),
 194         PWR_MAP(DC),
 195 };
 196
 197 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 198 {
 199         int val;
 200         if (index > SMU_MSG_MAX_COUNT)
 201                 return -EINVAL;
 202
 203         val = navi10_message_map[index];
 204         if (val > PPSMC_Message_Count)
 205                 return -EINVAL;
 206
 207         return val;
 208 }
 209
 210 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 211 {
 212         int val;
 213         if (index >= SMU_CLK_COUNT)
 214                 return -EINVAL;
 215
 216         val = navi10_clk_map[index];
 217         if (val >= PPCLK_COUNT)
 218                 return -EINVAL;
 219
 220         return val;
 221 }
 222
 223 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 224 {
 225         int val;
 226         if (index >= SMU_FEATURE_COUNT)
 227                 return -EINVAL;
 228
 229         val = navi10_feature_mask_map[index];
 230         if (val > 64)
 231                 return -EINVAL;
 232
 233         return val;
 234 }
 235
 236 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 237 {
 238         int val;
 239         if (index >= SMU_TABLE_COUNT)
 240                 return -EINVAL;
 241
 242         val = navi10_table_map[index];
 243         if (val >= TABLE_COUNT)
 244                 return -EINVAL;
 245
 246         return val;
 247 }
 248
 249 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 250 {
 251         int val;
 252         if (index >= SMU_POWER_SOURCE_COUNT)
 253                 return -EINVAL;
 254
 255         val = navi10_pwr_src_map[index];
 256         if (val >= POWER_SOURCE_COUNT)
 257                 return -EINVAL;
 258
 259         return val;
 260 }
 261
 262 static int
 263 navi10_get_allowed_feature_mask(struct smu_context *smu,
 264                                   uint32_t *feature_mask, uint32_t num)
 265 {
 266         struct amdgpu_device *adev = smu->adev;
 267
 268         if (num > 2)
 269                 return -EINVAL;
 270
 271         memset(feature_mask, 0, sizeof(uint32_t) * num);
 272
 273         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 274                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 275                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 276                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 277                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 278                                 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
 279                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 280                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 281                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 282                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 283                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 284                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 285                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 286                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 287                                 | FEATURE_MASK(FEATURE_MMHUB_PG_BIT)
 288                                 | FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
 289                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 290
 291         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 292                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 293                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 294                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 295
 296         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 297                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 298                                 | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 299
 300         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 301                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 302
 303         return 0;
 304 }
 305
 306 static int navi10_check_powerplay_table(struct smu_context *smu)
 307 {
 308         return 0;
 309 }
 310
 311 static int navi10_append_powerplay_table(struct smu_context *smu)
 312 {
 313         struct amdgpu_device *adev = smu->adev;
 314         struct smu_table_context *table_context = &smu->smu_table;
 315         PPTable_t *smc_pptable = table_context->driver_pptable;
 316         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 317         int index, ret;
 318
 319         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 320                                            smc_dpm_info);
 321
 322         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 323                                       (uint8_t **)&smc_dpm_table);
 324         if (ret)
 325                 return ret;
 326
 327         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 328                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 329
 330         /* SVI2 Board Parameters */
 331         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 332         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 333         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 334         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 335         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 336         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 337         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 338         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 339         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 340         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 341
 342         /* Telemetry Settings */
 343         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 344         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 345         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 346         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 347         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 348         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 349         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 350         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 351         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 352         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 353         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 354         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 355
 356         /* GPIO Settings */
 357         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 358         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 359         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 360         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 361         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 362         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 363         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 364         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 365
 366         /* LED Display Settings */
 367         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 368         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 369         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 370         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 371
 372         /* GFXCLK PLL Spread Spectrum */
 373         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 374         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 375         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 376
 377         /* GFXCLK DFLL Spread Spectrum */
 378         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 379         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 380         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 381
 382         /* UCLK Spread Spectrum */
 383         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 384         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 385         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 386
 387         /* SOCCLK Spread Spectrum */
 388         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 389         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 390         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 391
 392         /* Total board power */
 393         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 394         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 395
 396         /* Mvdd Svi2 Div Ratio Setting */
 397         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 398
 399         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 400                 *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 401                                         | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 402
 403                 /* TODO: remove it once SMU fw fix it */
 404                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int navi10_store_powerplay_table(struct smu_context *smu)
 411 {
 412         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 413         struct smu_table_context *table_context = &smu->smu_table;
 414
 415         if (!table_context->power_play_table)
 416                 return -EINVAL;
 417
 418         powerplay_table = table_context->power_play_table;
 419
 420         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 421                sizeof(PPTable_t));
 422
 423         return 0;
 424 }
 425
 426 static void navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 427 {
 428         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 429                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 430         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 431                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 432         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 433                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 434         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 435                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 436         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 437                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 438         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 439                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 440                        AMDGPU_GEM_DOMAIN_VRAM);
 441 }
 442
 443 static int navi10_allocate_dpm_context(struct smu_context *smu)
 444 {
 445         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 446
 447         if (smu_dpm->dpm_context)
 448                 return -EINVAL;
 449
 450         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 451                                        GFP_KERNEL);
 452         if (!smu_dpm->dpm_context)
 453                 return -ENOMEM;
 454
 455         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 456
 457         return 0;
 458 }
 459
 460 static int navi10_set_default_dpm_table(struct smu_context *smu)
 461 {
 462         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 463         struct smu_table_context *table_context = &smu->smu_table;
 464         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 465         PPTable_t *driver_ppt = NULL;
 466
 467         driver_ppt = table_context->driver_pptable;
 468
 469         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 470         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 471
 472         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 473         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 474
 475         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 476         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 477
 478         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 479         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 480
 481         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 482         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 483
 484         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 485         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 486
 487         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 488         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 489
 490         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 491         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 492
 493         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 494         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 495
 496         return 0;
 497 }
 498
 499 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 500 {
 501         int ret = 0;
 502
 503         if (enable) {
 504                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 505                 if (ret)
 506                         return ret;
 507         } else {
 508                 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 509                 if (ret)
 510                         return ret;
 511         }
 512
 513         return 0;
 514 }
 515
 516 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 517                                        enum smu_clk_type clk_type,
 518                                        uint32_t *value)
 519 {
 520         static SmuMetrics_t metrics = {0};
 521         int ret = 0, clk_id = 0;
 522
 523         if (!value)
 524                 return -EINVAL;
 525
 526         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
 527         if (ret)
 528                 return ret;
 529
 530         clk_id = smu_clk_get_index(smu, clk_type);
 531         if (clk_id < 0)
 532                 return clk_id;
 533
 534         *value = metrics.CurrClock[clk_id];
 535
 536         return ret;
 537 }
 538
 539 static int navi10_print_clk_levels(struct smu_context *smu,
 540                         enum smu_clk_type clk_type, char *buf)
 541 {
 542         int i, size = 0, ret = 0;
 543         uint32_t cur_value = 0, value = 0, count = 0;
 544
 545         switch (clk_type) {
 546         case SMU_GFXCLK:
 547         case SMU_SCLK:
 548         case SMU_SOCCLK:
 549         case SMU_MCLK:
 550         case SMU_UCLK:
 551         case SMU_FCLK:
 552         case SMU_DCEFCLK:
 553                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 554                 if (ret)
 555                         return size;
 556
 557                 size += sprintf(buf, "current clk: %uMhz\n", cur_value);
 558
 559                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 560                 if (ret)
 561                         return size;
 562
 563                 for (i = 0; i < count; i++) {
 564                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 565                         if (ret)
 566                                 return size;
 567
 568                         size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 569                                         cur_value == value ? "*" : "");
 570                 }
 571                 break;
 572         default:
 573                 break;
 574         }
 575
 576         return size;
 577 }
 578
 579 static int navi10_force_clk_levels(struct smu_context *smu,
 580                                    enum smu_clk_type clk_type, uint32_t mask)
 581 {
 582
 583         int ret = 0, size = 0;
 584         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 585
 586         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 587         soft_max_level = mask ? (fls(mask) - 1) : 0;
 588
 589         switch (clk_type) {
 590         case SMU_GFXCLK:
 591         case SMU_SOCCLK:
 592         case SMU_MCLK:
 593         case SMU_UCLK:
 594         case SMU_DCEFCLK:
 595         case SMU_FCLK:
 596                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 597                 if (ret)
 598                         return size;
 599
 600                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 601                 if (ret)
 602                         return size;
 603
 604                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 605                 if (ret)
 606                         return size;
 607                 break;
 608         default:
 609                 break;
 610         }
 611
 612         return size;
 613 }
 614
 615 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 616 {
 617         int ret = 0;
 618         uint32_t min_sclk_freq = 0;
 619
 620         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
 621         if (ret)
 622                 return ret;
 623
 624         smu->pstate_sclk = min_sclk_freq * 100;
 625
 626         return ret;
 627 }
 628
 629 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 630                                                  enum smu_clk_type clk_type,
 631                                                  struct pp_clock_levels_with_latency *clocks)
 632 {
 633         int ret = 0, i = 0;
 634         uint32_t level_count = 0, freq = 0;
 635
 636         switch (clk_type) {
 637         case SMU_GFXCLK:
 638         case SMU_DCEFCLK:
 639         case SMU_SOCCLK:
 640                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 641                 if (ret)
 642                         return ret;
 643
 644                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 645                 clocks->num_levels = level_count;
 646
 647                 for (i = 0; i < level_count; i++) {
 648                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 649                         if (ret)
 650                                 return ret;
 651
 652                         clocks->data[i].clocks_in_khz = freq * 1000;
 653                         clocks->data[i].latency_in_us = 0;
 654                 }
 655                 break;
 656         default:
 657                 break;
 658         }
 659
 660         return ret;
 661 }
 662
 663 static int navi10_pre_display_config_changed(struct smu_context *smu)
 664 {
 665         int ret = 0;
 666         uint32_t max_freq = 0;
 667
 668         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 669         if (ret)
 670                 return ret;
 671
 672         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 673                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
 674                 if (ret)
 675                         return ret;
 676                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 677                 if (ret)
 678                         return ret;
 679         }
 680
 681         return ret;
 682 }
 683
 684 static int navi10_display_config_changed(struct smu_context *smu)
 685 {
 686         int ret = 0;
 687
 688         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 689             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 690                 ret = smu_write_watermarks_table(smu);
 691                 if (ret)
 692                         return ret;
 693
 694                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 695         }
 696
 697         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 698             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 699             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 700                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 701                                                   smu->display_config->num_display);
 702                 if (ret)
 703                         return ret;
 704         }
 705
 706         return ret;
 707 }
 708
 709 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 710 {
 711         int ret = 0, i = 0;
 712         uint32_t min_freq, max_freq, force_freq;
 713         enum smu_clk_type clk_type;
 714
 715         enum smu_clk_type clks[] = {
 716                 SMU_GFXCLK,
 717                 SMU_MCLK,
 718                 SMU_SOCCLK,
 719         };
 720
 721         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 722                 clk_type = clks[i];
 723                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 724                 if (ret)
 725                         return ret;
 726
 727                 force_freq = highest ? max_freq : min_freq;
 728                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
 729                 if (ret)
 730                         return ret;
 731         }
 732
 733         return ret;
 734 }
 735
 736 static int navi10_unforce_dpm_levels(struct smu_context *smu) {
 737
 738         int ret = 0, i = 0;
 739         uint32_t min_freq, max_freq;
 740         enum smu_clk_type clk_type;
 741
 742         enum smu_clk_type clks[] = {
 743                 SMU_GFXCLK,
 744                 SMU_MCLK,
 745                 SMU_SOCCLK,
 746         };
 747
 748         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 749                 clk_type = clks[i];
 750                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 751                 if (ret)
 752                         return ret;
 753
 754                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 755                 if (ret)
 756                         return ret;
 757         }
 758
 759         return ret;
 760 }
 761
 762 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
 763 {
 764         int ret = 0;
 765         SmuMetrics_t metrics;
 766
 767         if (!value)
 768                 return -EINVAL;
 769
 770         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics,
 771                                false);
 772         if (ret)
 773                 return ret;
 774
 775         *value = metrics.CurrSocketPower << 8;
 776
 777         return 0;
 778 }
 779
 780 static int navi10_get_current_activity_percent(struct smu_context *smu,
 781                                                uint32_t *value)
 782 {
 783         int ret = 0;
 784         SmuMetrics_t metrics;
 785
 786         if (!value)
 787                 return -EINVAL;
 788
 789         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
 790                                (void *)&metrics, false);
 791         if (ret)
 792                 return ret;
 793
 794         *value = metrics.AverageGfxActivity;
 795
 796         return 0;
 797 }
 798
 799 static bool navi10_is_dpm_running(struct smu_context *smu)
 800 {
 801         int ret = 0;
 802         uint32_t feature_mask[2];
 803         unsigned long feature_enabled;
 804         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 805         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
 806                            ((uint64_t)feature_mask[1] << 32));
 807         return !!(feature_enabled & SMC_DPM_FEATURE);
 808 }
 809
 810 static int navi10_set_thermal_fan_table(struct smu_context *smu)
 811 {
 812         int ret;
 813         struct smu_table_context *table_context = &smu->smu_table;
 814         PPTable_t *pptable = table_context->driver_pptable;
 815
 816         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
 817                         (uint32_t)pptable->FanTargetTemperature);
 818
 819         return ret;
 820 }
 821
 822 static const struct pptable_funcs navi10_ppt_funcs = {
 823         .tables_init = navi10_tables_init,
 824         .alloc_dpm_context = navi10_allocate_dpm_context,
 825         .store_powerplay_table = navi10_store_powerplay_table,
 826         .check_powerplay_table = navi10_check_powerplay_table,
 827         .append_powerplay_table = navi10_append_powerplay_table,
 828         .get_smu_msg_index = navi10_get_smu_msg_index,
 829         .get_smu_clk_index = navi10_get_smu_clk_index,
 830         .get_smu_feature_index = navi10_get_smu_feature_index,
 831         .get_smu_table_index = navi10_get_smu_table_index,
 832         .get_smu_power_index = navi10_get_pwr_src_index,
 833         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
 834         .set_default_dpm_table = navi10_set_default_dpm_table,
 835         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
 836         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
 837         .print_clk_levels = navi10_print_clk_levels,
 838         .force_clk_levels = navi10_force_clk_levels,
 839         .populate_umd_state_clk = navi10_populate_umd_state_clk,
 840         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
 841         .pre_display_config_changed = navi10_pre_display_config_changed,
 842         .display_config_changed = navi10_display_config_changed,
 843         .force_dpm_limit_value = navi10_force_dpm_limit_value,
 844         .unforce_dpm_levels = navi10_unforce_dpm_levels,
 845         .get_gpu_power = navi10_get_gpu_power,
 846         .get_current_activity_percent = navi10_get_current_activity_percent,
 847         .is_dpm_running = navi10_is_dpm_running,
 848         .set_thermal_fan_table = navi10_set_thermal_fan_table,
 849 };
 850
 851 void navi10_set_ppt_funcs(struct smu_context *smu)
 852 {
 853         struct smu_table_context *smu_table = &smu->smu_table;
 854
 855         smu->ppt_funcs = &navi10_ppt_funcs;
 856         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
 857         smu_table->table_count = TABLE_COUNT;
 858 }