drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_navi10.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "navi10_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42
  43 #define FEATURE_MASK(feature) (1ULL << feature)
  44 #define SMC_DPM_FEATURE ( \
  45         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  46         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  48         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  50         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  51         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  52         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  53
  54 #define MSG_MAP(msg, index) \
  55         [SMU_MSG_##msg] = {1, (index)}
  56
  57 static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  58         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  59         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  60         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  61         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  62         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  63         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  64         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  65         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  66         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  67         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  68         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  69         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  70         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  71         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  72         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  73         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  74         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  75         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  76         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  77         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  78         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  79         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  80         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  81         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  82         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  83         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  84         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  85         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  86         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  87         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  88         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  89         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  90         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  91         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  92         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  93         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  94         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  95         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  96         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  97         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  98         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  99         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
 100         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
 101         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
 102         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 103         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 104         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 105         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 108         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 109         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 110         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 111         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 112         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 113         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 114         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 115         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 116         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 117         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 118         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 119         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 120         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),
 121         MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),
 122 };
 123
 124 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 125         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 126         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 127         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 128         CLK_MAP(FCLK, PPCLK_SOCCLK),
 129         CLK_MAP(UCLK, PPCLK_UCLK),
 130         CLK_MAP(MCLK, PPCLK_UCLK),
 131         CLK_MAP(DCLK, PPCLK_DCLK),
 132         CLK_MAP(VCLK, PPCLK_VCLK),
 133         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 134         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 135         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 136         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 137 };
 138
 139 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 140         FEA_MAP(DPM_PREFETCHER),
 141         FEA_MAP(DPM_GFXCLK),
 142         FEA_MAP(DPM_GFX_PACE),
 143         FEA_MAP(DPM_UCLK),
 144         FEA_MAP(DPM_SOCCLK),
 145         FEA_MAP(DPM_MP0CLK),
 146         FEA_MAP(DPM_LINK),
 147         FEA_MAP(DPM_DCEFCLK),
 148         FEA_MAP(MEM_VDDCI_SCALING),
 149         FEA_MAP(MEM_MVDD_SCALING),
 150         FEA_MAP(DS_GFXCLK),
 151         FEA_MAP(DS_SOCCLK),
 152         FEA_MAP(DS_LCLK),
 153         FEA_MAP(DS_DCEFCLK),
 154         FEA_MAP(DS_UCLK),
 155         FEA_MAP(GFX_ULV),
 156         FEA_MAP(FW_DSTATE),
 157         FEA_MAP(GFXOFF),
 158         FEA_MAP(BACO),
 159         FEA_MAP(VCN_PG),
 160         FEA_MAP(JPEG_PG),
 161         FEA_MAP(USB_PG),
 162         FEA_MAP(RSMU_SMN_CG),
 163         FEA_MAP(PPT),
 164         FEA_MAP(TDC),
 165         FEA_MAP(GFX_EDC),
 166         FEA_MAP(APCC_PLUS),
 167         FEA_MAP(GTHR),
 168         FEA_MAP(ACDC),
 169         FEA_MAP(VR0HOT),
 170         FEA_MAP(VR1HOT),
 171         FEA_MAP(FW_CTF),
 172         FEA_MAP(FAN_CONTROL),
 173         FEA_MAP(THERMAL),
 174         FEA_MAP(GFX_DCS),
 175         FEA_MAP(RM),
 176         FEA_MAP(LED_DISPLAY),
 177         FEA_MAP(GFX_SS),
 178         FEA_MAP(OUT_OF_BAND_MONITOR),
 179         FEA_MAP(TEMP_DEPENDENT_VMIN),
 180         FEA_MAP(MMHUB_PG),
 181         FEA_MAP(ATHUB_PG),
 182         FEA_MAP(APCC_DFLL),
 183 };
 184
 185 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 186         TAB_MAP(PPTABLE),
 187         TAB_MAP(WATERMARKS),
 188         TAB_MAP(AVFS),
 189         TAB_MAP(AVFS_PSM_DEBUG),
 190         TAB_MAP(AVFS_FUSE_OVERRIDE),
 191         TAB_MAP(PMSTATUSLOG),
 192         TAB_MAP(SMU_METRICS),
 193         TAB_MAP(DRIVER_SMU_CONFIG),
 194         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 195         TAB_MAP(OVERDRIVE),
 196         TAB_MAP(I2C_COMMANDS),
 197         TAB_MAP(PACE),
 198 };
 199
 200 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 201         PWR_MAP(AC),
 202         PWR_MAP(DC),
 203 };
 204
 205 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 213 };
 214
 215 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 216 {
 217         struct smu_11_0_cmn2aisc_mapping mapping;
 218
 219         if (index >= SMU_MSG_MAX_COUNT)
 220                 return -EINVAL;
 221
 222         mapping = navi10_message_map[index];
 223         if (!(mapping.valid_mapping)) {
 224                 return -EINVAL;
 225         }
 226
 227         return mapping.map_to;
 228 }
 229
 230 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 231 {
 232         struct smu_11_0_cmn2aisc_mapping mapping;
 233
 234         if (index >= SMU_CLK_COUNT)
 235                 return -EINVAL;
 236
 237         mapping = navi10_clk_map[index];
 238         if (!(mapping.valid_mapping)) {
 239                 return -EINVAL;
 240         }
 241
 242         return mapping.map_to;
 243 }
 244
 245 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 246 {
 247         struct smu_11_0_cmn2aisc_mapping mapping;
 248
 249         if (index >= SMU_FEATURE_COUNT)
 250                 return -EINVAL;
 251
 252         mapping = navi10_feature_mask_map[index];
 253         if (!(mapping.valid_mapping)) {
 254                 return -EINVAL;
 255         }
 256
 257         return mapping.map_to;
 258 }
 259
 260 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 261 {
 262         struct smu_11_0_cmn2aisc_mapping mapping;
 263
 264         if (index >= SMU_TABLE_COUNT)
 265                 return -EINVAL;
 266
 267         mapping = navi10_table_map[index];
 268         if (!(mapping.valid_mapping)) {
 269                 return -EINVAL;
 270         }
 271
 272         return mapping.map_to;
 273 }
 274
 275 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 276 {
 277         struct smu_11_0_cmn2aisc_mapping mapping;
 278
 279         if (index >= SMU_POWER_SOURCE_COUNT)
 280                 return -EINVAL;
 281
 282         mapping = navi10_pwr_src_map[index];
 283         if (!(mapping.valid_mapping)) {
 284                 return -EINVAL;
 285         }
 286
 287         return mapping.map_to;
 288 }
 289
 290
 291 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 292 {
 293         struct smu_11_0_cmn2aisc_mapping mapping;
 294
 295         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 296                 return -EINVAL;
 297
 298         mapping = navi10_workload_map[profile];
 299         if (!(mapping.valid_mapping)) {
 300                 return -EINVAL;
 301         }
 302
 303         return mapping.map_to;
 304 }
 305
 306 static bool is_asic_secure(struct smu_context *smu)
 307 {
 308         struct amdgpu_device *adev = smu->adev;
 309         bool is_secure = true;
 310         uint32_t mp0_fw_intf;
 311
 312         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 313                                    (smnMP0_FW_INTF & 0xffffffff));
 314
 315         if (!(mp0_fw_intf & (1 << 19)))
 316                 is_secure = false;
 317
 318         return is_secure;
 319 }
 320
 321 static int
 322 navi10_get_allowed_feature_mask(struct smu_context *smu,
 323                                   uint32_t *feature_mask, uint32_t num)
 324 {
 325         struct amdgpu_device *adev = smu->adev;
 326
 327         if (num > 2)
 328                 return -EINVAL;
 329
 330         memset(feature_mask, 0, sizeof(uint32_t) * num);
 331
 332         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 333                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 334                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 335                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 336                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 337                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 338                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 339                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 340                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 341                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 342                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 343                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 344                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 345                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 346                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 347                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 348                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 349                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 350                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 351                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 352                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 353
 354         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 355                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 356
 357         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 358                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 359
 360         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 361                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 362
 363         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 364                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 365
 366         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 367                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 368                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 369                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 370
 371         if (adev->pm.pp_feature & PP_ULV_MASK)
 372                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 373
 374         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 375                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 376
 377         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 378                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 379
 380         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 381                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 382
 383         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 384                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 385
 386         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 387                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 388
 389         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 390                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 391
 392         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 393         if (is_asic_secure(smu)) {
 394                 /* only for navi10 A0 */
 395                 if ((adev->asic_type == CHIP_NAVI10) &&
 396                         (adev->rev_id == 0)) {
 397                         *(uint64_t *)feature_mask &=
 398                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 399                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 400                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 401                         *(uint64_t *)feature_mask &=
 402                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 403                 }
 404         }
 405
 406         return 0;
 407 }
 408
 409 static int navi10_check_powerplay_table(struct smu_context *smu)
 410 {
 411         return 0;
 412 }
 413
 414 static int navi10_append_powerplay_table(struct smu_context *smu)
 415 {
 416         struct amdgpu_device *adev = smu->adev;
 417         struct smu_table_context *table_context = &smu->smu_table;
 418         PPTable_t *smc_pptable = table_context->driver_pptable;
 419         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 420         int index, ret;
 421
 422         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 423                                            smc_dpm_info);
 424
 425         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 426                                       (uint8_t **)&smc_dpm_table);
 427         if (ret)
 428                 return ret;
 429
 430         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 431                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 432
 433         /* SVI2 Board Parameters */
 434         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 435         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 436         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 437         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 438         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 439         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 440         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 441         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 442         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 443         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 444
 445         /* Telemetry Settings */
 446         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 447         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 448         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 449         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 450         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 451         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 452         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 453         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 454         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 455         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 456         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 457         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 458
 459         /* GPIO Settings */
 460         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 461         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 462         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 463         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 464         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 465         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 466         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 467         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 468
 469         /* LED Display Settings */
 470         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 471         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 472         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 473         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 474
 475         /* GFXCLK PLL Spread Spectrum */
 476         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 477         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 478         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 479
 480         /* GFXCLK DFLL Spread Spectrum */
 481         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 482         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 483         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 484
 485         /* UCLK Spread Spectrum */
 486         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 487         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 488         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 489
 490         /* SOCCLK Spread Spectrum */
 491         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 492         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 493         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 494
 495         /* Total board power */
 496         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 497         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 498
 499         /* Mvdd Svi2 Div Ratio Setting */
 500         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 501
 502         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 503                 /* TODO: remove it once SMU fw fix it */
 504                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static int navi10_store_powerplay_table(struct smu_context *smu)
 511 {
 512         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 513         struct smu_table_context *table_context = &smu->smu_table;
 514         struct smu_baco_context *smu_baco = &smu->smu_baco;
 515
 516         if (!table_context->power_play_table)
 517                 return -EINVAL;
 518
 519         powerplay_table = table_context->power_play_table;
 520
 521         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 522                sizeof(PPTable_t));
 523
 524         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 525
 526         mutex_lock(&smu_baco->mutex);
 527         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 528             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 529                 smu_baco->platform_support = true;
 530         mutex_unlock(&smu_baco->mutex);
 531
 532         return 0;
 533 }
 534
 535 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 536 {
 537         struct smu_table_context *smu_table = &smu->smu_table;
 538
 539         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 540                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 541         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 542                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 543         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 544                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 545         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 546                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 547         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 548                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 549         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 550                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 551                        AMDGPU_GEM_DOMAIN_VRAM);
 552
 553         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 554         if (!smu_table->metrics_table)
 555                 return -ENOMEM;
 556         smu_table->metrics_time = 0;
 557
 558         return 0;
 559 }
 560
 561 static int navi10_get_metrics_table(struct smu_context *smu,
 562                                     SmuMetrics_t *metrics_table)
 563 {
 564         struct smu_table_context *smu_table= &smu->smu_table;
 565         int ret = 0;
 566
 567         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 568                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 569                                 (void *)smu_table->metrics_table, false);
 570                 if (ret) {
 571                         pr_info("Failed to export SMU metrics table!\n");
 572                         return ret;
 573                 }
 574                 smu_table->metrics_time = jiffies;
 575         }
 576
 577         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 578
 579         return ret;
 580 }
 581
 582 static int navi10_allocate_dpm_context(struct smu_context *smu)
 583 {
 584         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 585
 586         if (smu_dpm->dpm_context)
 587                 return -EINVAL;
 588
 589         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 590                                        GFP_KERNEL);
 591         if (!smu_dpm->dpm_context)
 592                 return -ENOMEM;
 593
 594         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 595
 596         return 0;
 597 }
 598
 599 static int navi10_set_default_dpm_table(struct smu_context *smu)
 600 {
 601         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 602         struct smu_table_context *table_context = &smu->smu_table;
 603         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 604         PPTable_t *driver_ppt = NULL;
 605         int i;
 606
 607         driver_ppt = table_context->driver_pptable;
 608
 609         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 610         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 611
 612         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 613         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 614
 615         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 616         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 617
 618         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 619         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 620
 621         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 622         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 623
 624         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 625         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 626
 627         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 628         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 629
 630         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 631         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 632
 633         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 634         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 635
 636         for (i = 0; i < MAX_PCIE_CONF; i++) {
 637                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 638                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 645 {
 646         struct smu_power_context *smu_power = &smu->smu_power;
 647         struct smu_power_gate *power_gate = &smu_power->power_gate;
 648         int ret = 0;
 649
 650         if (enable) {
 651                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 652                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 653                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 654                         if (ret)
 655                                 return ret;
 656                 }
 657                 power_gate->vcn_gated = false;
 658         } else {
 659                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 660                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 661                         if (ret)
 662                                 return ret;
 663                 }
 664                 power_gate->vcn_gated = true;
 665         }
 666
 667         return ret;
 668 }
 669
 670 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 671 {
 672         struct smu_power_context *smu_power = &smu->smu_power;
 673         struct smu_power_gate *power_gate = &smu_power->power_gate;
 674         int ret = 0;
 675
 676         if (enable) {
 677                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 678                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
 679                         if (ret)
 680                                 return ret;
 681                 }
 682                 power_gate->jpeg_gated = false;
 683         } else {
 684                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 685                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
 686                         if (ret)
 687                                 return ret;
 688                 }
 689                 power_gate->jpeg_gated = true;
 690         }
 691
 692         return ret;
 693 }
 694
 695 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 696                                        enum smu_clk_type clk_type,
 697                                        uint32_t *value)
 698 {
 699         int ret = 0, clk_id = 0;
 700         SmuMetrics_t metrics;
 701
 702         ret = navi10_get_metrics_table(smu, &metrics);
 703         if (ret)
 704                 return ret;
 705
 706         clk_id = smu_clk_get_index(smu, clk_type);
 707         if (clk_id < 0)
 708                 return clk_id;
 709
 710         *value = metrics.CurrClock[clk_id];
 711
 712         return ret;
 713 }
 714
 715 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 716 {
 717         PPTable_t *pptable = smu->smu_table.driver_pptable;
 718         DpmDescriptor_t *dpm_desc = NULL;
 719         uint32_t clk_index = 0;
 720
 721         clk_index = smu_clk_get_index(smu, clk_type);
 722         dpm_desc = &pptable->DpmDescriptor[clk_index];
 723
 724         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 725         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 726 }
 727
 728 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
 729 {
 730         return od_table->cap[feature];
 731 }
 732
 733
 734 static int navi10_print_clk_levels(struct smu_context *smu,
 735                         enum smu_clk_type clk_type, char *buf)
 736 {
 737         uint16_t *curve_settings;
 738         int i, size = 0, ret = 0;
 739         uint32_t cur_value = 0, value = 0, count = 0;
 740         uint32_t freq_values[3] = {0};
 741         uint32_t mark_index = 0;
 742         struct smu_table_context *table_context = &smu->smu_table;
 743         uint32_t gen_speed, lane_width;
 744         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 745         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 746         struct amdgpu_device *adev = smu->adev;
 747         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 748         OverDriveTable_t *od_table =
 749                 (OverDriveTable_t *)table_context->overdrive_table;
 750         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
 751
 752         switch (clk_type) {
 753         case SMU_GFXCLK:
 754         case SMU_SCLK:
 755         case SMU_SOCCLK:
 756         case SMU_MCLK:
 757         case SMU_UCLK:
 758         case SMU_FCLK:
 759         case SMU_DCEFCLK:
 760                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 761                 if (ret)
 762                         return size;
 763
 764                 /* 10KHz -> MHz */
 765                 cur_value = cur_value / 100;
 766
 767                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 768                 if (ret)
 769                         return size;
 770
 771                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 772                         for (i = 0; i < count; i++) {
 773                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 774                                 if (ret)
 775                                         return size;
 776
 777                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 778                                                 cur_value == value ? "*" : "");
 779                         }
 780                 } else {
 781                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 782                         if (ret)
 783                                 return size;
 784                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 785                         if (ret)
 786                                 return size;
 787
 788                         freq_values[1] = cur_value;
 789                         mark_index = cur_value == freq_values[0] ? 0 :
 790                                      cur_value == freq_values[2] ? 2 : 1;
 791                         if (mark_index != 1)
 792                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 793
 794                         for (i = 0; i < 3; i++) {
 795                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 796                                                 i == mark_index ? "*" : "");
 797                         }
 798
 799                 }
 800                 break;
 801         case SMU_PCIE:
 802                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 803                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 804                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 805                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 806                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 807                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 808                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 809                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 810                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 811                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 812                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 813                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 814                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 815                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 816                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 817                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 818                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 819                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 820                                         pptable->LclkFreq[i],
 821                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 822                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 823                                         "*" : "");
 824                 break;
 825         case SMU_OD_SCLK:
 826                 if (!smu->od_enabled || !od_table || !od_settings)
 827                         break;
 828                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS))
 829                         break;
 830                 size += sprintf(buf + size, "OD_SCLK:\n");
 831                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
 832                 break;
 833         case SMU_OD_MCLK:
 834                 if (!smu->od_enabled || !od_table || !od_settings)
 835                         break;
 836                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX))
 837                         break;
 838                 size += sprintf(buf + size, "OD_MCLK:\n");
 839                 size += sprintf(buf + size, "0: %uMHz\n", od_table->UclkFmax);
 840                 break;
 841         case SMU_OD_VDDC_CURVE:
 842                 if (!smu->od_enabled || !od_table || !od_settings)
 843                         break;
 844                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE))
 845                         break;
 846                 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
 847                 for (i = 0; i < 3; i++) {
 848                         switch (i) {
 849                         case 0:
 850                                 curve_settings = &od_table->GfxclkFreq1;
 851                                 break;
 852                         case 1:
 853                                 curve_settings = &od_table->GfxclkFreq2;
 854                                 break;
 855                         case 2:
 856                                 curve_settings = &od_table->GfxclkFreq3;
 857                                 break;
 858                         default:
 859                                 break;
 860                         }
 861                         size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
 862                 }
 863                 break;
 864         default:
 865                 break;
 866         }
 867
 868         return size;
 869 }
 870
 871 static int navi10_force_clk_levels(struct smu_context *smu,
 872                                    enum smu_clk_type clk_type, uint32_t mask)
 873 {
 874
 875         int ret = 0, size = 0;
 876         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 877
 878         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 879         soft_max_level = mask ? (fls(mask) - 1) : 0;
 880
 881         switch (clk_type) {
 882         case SMU_GFXCLK:
 883         case SMU_SCLK:
 884         case SMU_SOCCLK:
 885         case SMU_MCLK:
 886         case SMU_UCLK:
 887         case SMU_DCEFCLK:
 888         case SMU_FCLK:
 889                 /* There is only 2 levels for fine grained DPM */
 890                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 891                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
 892                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
 893                 }
 894
 895                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 896                 if (ret)
 897                         return size;
 898
 899                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 900                 if (ret)
 901                         return size;
 902
 903                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 904                 if (ret)
 905                         return size;
 906                 break;
 907         default:
 908                 break;
 909         }
 910
 911         return size;
 912 }
 913
 914 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 915 {
 916         int ret = 0;
 917         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 918
 919         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 920         if (ret)
 921                 return ret;
 922
 923         smu->pstate_sclk = min_sclk_freq * 100;
 924
 925         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 926         if (ret)
 927                 return ret;
 928
 929         smu->pstate_mclk = min_mclk_freq * 100;
 930
 931         return ret;
 932 }
 933
 934 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 935                                                  enum smu_clk_type clk_type,
 936                                                  struct pp_clock_levels_with_latency *clocks)
 937 {
 938         int ret = 0, i = 0;
 939         uint32_t level_count = 0, freq = 0;
 940
 941         switch (clk_type) {
 942         case SMU_GFXCLK:
 943         case SMU_DCEFCLK:
 944         case SMU_SOCCLK:
 945                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 946                 if (ret)
 947                         return ret;
 948
 949                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 950                 clocks->num_levels = level_count;
 951
 952                 for (i = 0; i < level_count; i++) {
 953                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 954                         if (ret)
 955                                 return ret;
 956
 957                         clocks->data[i].clocks_in_khz = freq * 1000;
 958                         clocks->data[i].latency_in_us = 0;
 959                 }
 960                 break;
 961         default:
 962                 break;
 963         }
 964
 965         return ret;
 966 }
 967
 968 static int navi10_pre_display_config_changed(struct smu_context *smu)
 969 {
 970         int ret = 0;
 971         uint32_t max_freq = 0;
 972
 973         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 974         if (ret)
 975                 return ret;
 976
 977         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 978                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
 979                 if (ret)
 980                         return ret;
 981                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 982                 if (ret)
 983                         return ret;
 984         }
 985
 986         return ret;
 987 }
 988
 989 static int navi10_display_config_changed(struct smu_context *smu)
 990 {
 991         int ret = 0;
 992
 993         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 994             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 995                 ret = smu_write_watermarks_table(smu);
 996                 if (ret)
 997                         return ret;
 998
 999                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1000         }
1001
1002         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1003             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1004             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1005                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1006                                                   smu->display_config->num_display);
1007                 if (ret)
1008                         return ret;
1009         }
1010
1011         return ret;
1012 }
1013
1014 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
1015 {
1016         int ret = 0, i = 0;
1017         uint32_t min_freq, max_freq, force_freq;
1018         enum smu_clk_type clk_type;
1019
1020         enum smu_clk_type clks[] = {
1021                 SMU_GFXCLK,
1022                 SMU_MCLK,
1023                 SMU_SOCCLK,
1024         };
1025
1026         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1027                 clk_type = clks[i];
1028                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1029                 if (ret)
1030                         return ret;
1031
1032                 force_freq = highest ? max_freq : min_freq;
1033                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
1034                 if (ret)
1035                         return ret;
1036         }
1037
1038         return ret;
1039 }
1040
1041 static int navi10_unforce_dpm_levels(struct smu_context *smu)
1042 {
1043         int ret = 0, i = 0;
1044         uint32_t min_freq, max_freq;
1045         enum smu_clk_type clk_type;
1046
1047         enum smu_clk_type clks[] = {
1048                 SMU_GFXCLK,
1049                 SMU_MCLK,
1050                 SMU_SOCCLK,
1051         };
1052
1053         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1054                 clk_type = clks[i];
1055                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1056                 if (ret)
1057                         return ret;
1058
1059                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
1060                 if (ret)
1061                         return ret;
1062         }
1063
1064         return ret;
1065 }
1066
1067 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1068 {
1069         int ret = 0;
1070         SmuMetrics_t metrics;
1071
1072         if (!value)
1073                 return -EINVAL;
1074
1075         ret = navi10_get_metrics_table(smu, &metrics);
1076         if (ret)
1077                 return ret;
1078
1079         *value = metrics.AverageSocketPower << 8;
1080
1081         return 0;
1082 }
1083
1084 static int navi10_get_current_activity_percent(struct smu_context *smu,
1085                                                enum amd_pp_sensors sensor,
1086                                                uint32_t *value)
1087 {
1088         int ret = 0;
1089         SmuMetrics_t metrics;
1090
1091         if (!value)
1092                 return -EINVAL;
1093
1094         ret = navi10_get_metrics_table(smu, &metrics);
1095         if (ret)
1096                 return ret;
1097
1098         switch (sensor) {
1099         case AMDGPU_PP_SENSOR_GPU_LOAD:
1100                 *value = metrics.AverageGfxActivity;
1101                 break;
1102         case AMDGPU_PP_SENSOR_MEM_LOAD:
1103                 *value = metrics.AverageUclkActivity;
1104                 break;
1105         default:
1106                 pr_err("Invalid sensor for retrieving clock activity\n");
1107                 return -EINVAL;
1108         }
1109
1110         return 0;
1111 }
1112
1113 static bool navi10_is_dpm_running(struct smu_context *smu)
1114 {
1115         int ret = 0;
1116         uint32_t feature_mask[2];
1117         unsigned long feature_enabled;
1118         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1119         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1120                            ((uint64_t)feature_mask[1] << 32));
1121         return !!(feature_enabled & SMC_DPM_FEATURE);
1122 }
1123
1124 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1125                                     uint32_t *speed)
1126 {
1127         SmuMetrics_t metrics;
1128         int ret = 0;
1129
1130         if (!speed)
1131                 return -EINVAL;
1132
1133         ret = navi10_get_metrics_table(smu, &metrics);
1134         if (ret)
1135                 return ret;
1136
1137         *speed = metrics.CurrFanSpeed;
1138
1139         return ret;
1140 }
1141
1142 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1143                                         uint32_t *speed)
1144 {
1145         int ret = 0;
1146         uint32_t percent = 0;
1147         uint32_t current_rpm;
1148         PPTable_t *pptable = smu->smu_table.driver_pptable;
1149
1150         ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
1151         if (ret)
1152                 return ret;
1153
1154         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1155         *speed = percent > 100 ? 100 : percent;
1156
1157         return ret;
1158 }
1159
1160 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1161 {
1162         DpmActivityMonitorCoeffInt_t activity_monitor;
1163         uint32_t i, size = 0;
1164         int16_t workload_type = 0;
1165         static const char *profile_name[] = {
1166                                         "BOOTUP_DEFAULT",
1167                                         "3D_FULL_SCREEN",
1168                                         "POWER_SAVING",
1169                                         "VIDEO",
1170                                         "VR",
1171                                         "COMPUTE",
1172                                         "CUSTOM"};
1173         static const char *title[] = {
1174                         "PROFILE_INDEX(NAME)",
1175                         "CLOCK_TYPE(NAME)",
1176                         "FPS",
1177                         "MinFreqType",
1178                         "MinActiveFreqType",
1179                         "MinActiveFreq",
1180                         "BoosterFreqType",
1181                         "BoosterFreq",
1182                         "PD_Data_limit_c",
1183                         "PD_Data_error_coeff",
1184                         "PD_Data_error_rate_coeff"};
1185         int result = 0;
1186
1187         if (!buf)
1188                 return -EINVAL;
1189
1190         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1191                         title[0], title[1], title[2], title[3], title[4], title[5],
1192                         title[6], title[7], title[8], title[9], title[10]);
1193
1194         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1195                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1196                 workload_type = smu_workload_get_type(smu, i);
1197                 if (workload_type < 0)
1198                         return -EINVAL;
1199
1200                 result = smu_update_table(smu,
1201                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1202                                           (void *)(&activity_monitor), false);
1203                 if (result) {
1204                         pr_err("[%s] Failed to get activity monitor!", __func__);
1205                         return result;
1206                 }
1207
1208                 size += sprintf(buf + size, "%2d %14s%s:\n",
1209                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1210
1211                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1212                         " ",
1213                         0,
1214                         "GFXCLK",
1215                         activity_monitor.Gfx_FPS,
1216                         activity_monitor.Gfx_MinFreqStep,
1217                         activity_monitor.Gfx_MinActiveFreqType,
1218                         activity_monitor.Gfx_MinActiveFreq,
1219                         activity_monitor.Gfx_BoosterFreqType,
1220                         activity_monitor.Gfx_BoosterFreq,
1221                         activity_monitor.Gfx_PD_Data_limit_c,
1222                         activity_monitor.Gfx_PD_Data_error_coeff,
1223                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1224
1225                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1226                         " ",
1227                         1,
1228                         "SOCCLK",
1229                         activity_monitor.Soc_FPS,
1230                         activity_monitor.Soc_MinFreqStep,
1231                         activity_monitor.Soc_MinActiveFreqType,
1232                         activity_monitor.Soc_MinActiveFreq,
1233                         activity_monitor.Soc_BoosterFreqType,
1234                         activity_monitor.Soc_BoosterFreq,
1235                         activity_monitor.Soc_PD_Data_limit_c,
1236                         activity_monitor.Soc_PD_Data_error_coeff,
1237                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1238
1239                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1240                         " ",
1241                         2,
1242                         "MEMLK",
1243                         activity_monitor.Mem_FPS,
1244                         activity_monitor.Mem_MinFreqStep,
1245                         activity_monitor.Mem_MinActiveFreqType,
1246                         activity_monitor.Mem_MinActiveFreq,
1247                         activity_monitor.Mem_BoosterFreqType,
1248                         activity_monitor.Mem_BoosterFreq,
1249                         activity_monitor.Mem_PD_Data_limit_c,
1250                         activity_monitor.Mem_PD_Data_error_coeff,
1251                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1252         }
1253
1254         return size;
1255 }
1256
1257 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1258 {
1259         DpmActivityMonitorCoeffInt_t activity_monitor;
1260         int workload_type, ret = 0;
1261
1262         smu->power_profile_mode = input[size];
1263
1264         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1265                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1266                 return -EINVAL;
1267         }
1268
1269         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1270                 if (size < 0)
1271                         return -EINVAL;
1272
1273                 ret = smu_update_table(smu,
1274                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1275                                        (void *)(&activity_monitor), false);
1276                 if (ret) {
1277                         pr_err("[%s] Failed to get activity monitor!", __func__);
1278                         return ret;
1279                 }
1280
1281                 switch (input[0]) {
1282                 case 0: /* Gfxclk */
1283                         activity_monitor.Gfx_FPS = input[1];
1284                         activity_monitor.Gfx_MinFreqStep = input[2];
1285                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1286                         activity_monitor.Gfx_MinActiveFreq = input[4];
1287                         activity_monitor.Gfx_BoosterFreqType = input[5];
1288                         activity_monitor.Gfx_BoosterFreq = input[6];
1289                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1290                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1291                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1292                         break;
1293                 case 1: /* Socclk */
1294                         activity_monitor.Soc_FPS = input[1];
1295                         activity_monitor.Soc_MinFreqStep = input[2];
1296                         activity_monitor.Soc_MinActiveFreqType = input[3];
1297                         activity_monitor.Soc_MinActiveFreq = input[4];
1298                         activity_monitor.Soc_BoosterFreqType = input[5];
1299                         activity_monitor.Soc_BoosterFreq = input[6];
1300                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1301                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1302                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1303                         break;
1304                 case 2: /* Memlk */
1305                         activity_monitor.Mem_FPS = input[1];
1306                         activity_monitor.Mem_MinFreqStep = input[2];
1307                         activity_monitor.Mem_MinActiveFreqType = input[3];
1308                         activity_monitor.Mem_MinActiveFreq = input[4];
1309                         activity_monitor.Mem_BoosterFreqType = input[5];
1310                         activity_monitor.Mem_BoosterFreq = input[6];
1311                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1312                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1313                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1314                         break;
1315                 }
1316
1317                 ret = smu_update_table(smu,
1318                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1319                                        (void *)(&activity_monitor), true);
1320                 if (ret) {
1321                         pr_err("[%s] Failed to set activity monitor!", __func__);
1322                         return ret;
1323                 }
1324         }
1325
1326         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1327         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1328         if (workload_type < 0)
1329                 return -EINVAL;
1330         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1331                                     1 << workload_type);
1332
1333         return ret;
1334 }
1335
1336 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1337                                          enum amd_dpm_forced_level level,
1338                                          uint32_t *sclk_mask,
1339                                          uint32_t *mclk_mask,
1340                                          uint32_t *soc_mask)
1341 {
1342         int ret = 0;
1343         uint32_t level_count = 0;
1344
1345         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1346                 if (sclk_mask)
1347                         *sclk_mask = 0;
1348         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1349                 if (mclk_mask)
1350                         *mclk_mask = 0;
1351         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1352                 if(sclk_mask) {
1353                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1354                         if (ret)
1355                                 return ret;
1356                         *sclk_mask = level_count - 1;
1357                 }
1358
1359                 if(mclk_mask) {
1360                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1361                         if (ret)
1362                                 return ret;
1363                         *mclk_mask = level_count - 1;
1364                 }
1365
1366                 if(soc_mask) {
1367                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1368                         if (ret)
1369                                 return ret;
1370                         *soc_mask = level_count - 1;
1371                 }
1372         }
1373
1374         return ret;
1375 }
1376
1377 static int navi10_notify_smc_display_config(struct smu_context *smu)
1378 {
1379         struct smu_clocks min_clocks = {0};
1380         struct pp_display_clock_request clock_req;
1381         int ret = 0;
1382
1383         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1384         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1385         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1386
1387         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1388                 clock_req.clock_type = amd_pp_dcef_clock;
1389                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1390
1391                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1392                 if (!ret) {
1393                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1394                                 ret = smu_send_smc_msg_with_param(smu,
1395                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1396                                                                   min_clocks.dcef_clock_in_sr/100);
1397                                 if (ret) {
1398                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1399                                         return ret;
1400                                 }
1401                         }
1402                 } else {
1403                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1404                 }
1405         }
1406
1407         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1408                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1409                 if (ret) {
1410                         pr_err("[%s] Set hard min uclk failed!", __func__);
1411                         return ret;
1412                 }
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int navi10_set_watermarks_table(struct smu_context *smu,
1419                                        void *watermarks, struct
1420                                        dm_pp_wm_sets_with_clock_ranges_soc15
1421                                        *clock_ranges)
1422 {
1423         int i;
1424         Watermarks_t *table = watermarks;
1425
1426         if (!table || !clock_ranges)
1427                 return -EINVAL;
1428
1429         if (clock_ranges->num_wm_dmif_sets > 4 ||
1430             clock_ranges->num_wm_mcif_sets > 4)
1431                 return -EINVAL;
1432
1433         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1434                 table->WatermarkRow[1][i].MinClock =
1435                         cpu_to_le16((uint16_t)
1436                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1437                         1000));
1438                 table->WatermarkRow[1][i].MaxClock =
1439                         cpu_to_le16((uint16_t)
1440                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1441                         1000));
1442                 table->WatermarkRow[1][i].MinUclk =
1443                         cpu_to_le16((uint16_t)
1444                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1445                         1000));
1446                 table->WatermarkRow[1][i].MaxUclk =
1447                         cpu_to_le16((uint16_t)
1448                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1449                         1000));
1450                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1451                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1452         }
1453
1454         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1455                 table->WatermarkRow[0][i].MinClock =
1456                         cpu_to_le16((uint16_t)
1457                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1458                         1000));
1459                 table->WatermarkRow[0][i].MaxClock =
1460                         cpu_to_le16((uint16_t)
1461                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1462                         1000));
1463                 table->WatermarkRow[0][i].MinUclk =
1464                         cpu_to_le16((uint16_t)
1465                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1466                         1000));
1467                 table->WatermarkRow[0][i].MaxUclk =
1468                         cpu_to_le16((uint16_t)
1469                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1470                         1000));
1471                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1472                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int navi10_thermal_get_temperature(struct smu_context *smu,
1479                                              enum amd_pp_sensors sensor,
1480                                              uint32_t *value)
1481 {
1482         SmuMetrics_t metrics;
1483         int ret = 0;
1484
1485         if (!value)
1486                 return -EINVAL;
1487
1488         ret = navi10_get_metrics_table(smu, &metrics);
1489         if (ret)
1490                 return ret;
1491
1492         switch (sensor) {
1493         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1494                 *value = metrics.TemperatureHotspot *
1495                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1496                 break;
1497         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1498                 *value = metrics.TemperatureEdge *
1499                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1500                 break;
1501         case AMDGPU_PP_SENSOR_MEM_TEMP:
1502                 *value = metrics.TemperatureMem *
1503                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1504                 break;
1505         default:
1506                 pr_err("Invalid sensor for retrieving temp\n");
1507                 return -EINVAL;
1508         }
1509
1510         return 0;
1511 }
1512
1513 static int navi10_read_sensor(struct smu_context *smu,
1514                                  enum amd_pp_sensors sensor,
1515                                  void *data, uint32_t *size)
1516 {
1517         int ret = 0;
1518         struct smu_table_context *table_context = &smu->smu_table;
1519         PPTable_t *pptable = table_context->driver_pptable;
1520
1521         if(!data || !size)
1522                 return -EINVAL;
1523
1524         mutex_lock(&smu->sensor_lock);
1525         switch (sensor) {
1526         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1527                 *(uint32_t *)data = pptable->FanMaximumRpm;
1528                 *size = 4;
1529                 break;
1530         case AMDGPU_PP_SENSOR_MEM_LOAD:
1531         case AMDGPU_PP_SENSOR_GPU_LOAD:
1532                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1533                 *size = 4;
1534                 break;
1535         case AMDGPU_PP_SENSOR_GPU_POWER:
1536                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1537                 *size = 4;
1538                 break;
1539         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1540         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1541         case AMDGPU_PP_SENSOR_MEM_TEMP:
1542                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1543                 *size = 4;
1544                 break;
1545         default:
1546                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1547         }
1548         mutex_unlock(&smu->sensor_lock);
1549
1550         return ret;
1551 }
1552
1553 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1554 {
1555         uint32_t num_discrete_levels = 0;
1556         uint16_t *dpm_levels = NULL;
1557         uint16_t i = 0;
1558         struct smu_table_context *table_context = &smu->smu_table;
1559         PPTable_t *driver_ppt = NULL;
1560
1561         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1562                 return -EINVAL;
1563
1564         driver_ppt = table_context->driver_pptable;
1565         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1566         dpm_levels = driver_ppt->FreqTableUclk;
1567
1568         if (num_discrete_levels == 0 || dpm_levels == NULL)
1569                 return -EINVAL;
1570
1571         *num_states = num_discrete_levels;
1572         for (i = 0; i < num_discrete_levels; i++) {
1573                 /* convert to khz */
1574                 *clocks_in_khz = (*dpm_levels) * 1000;
1575                 clocks_in_khz++;
1576                 dpm_levels++;
1577         }
1578
1579         return 0;
1580 }
1581
1582 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
1583 {
1584         struct amdgpu_device *adev = smu->adev;
1585         int ret = 0;
1586         uint32_t sclk_freq = 0, uclk_freq = 0;
1587         uint32_t uclk_level = 0;
1588
1589         switch (adev->asic_type) {
1590         case CHIP_NAVI10:
1591                 switch (adev->pdev->revision) {
1592                 case 0xf0: /* XTX */
1593                 case 0xc0:
1594                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1595                         break;
1596                 case 0xf1: /* XT */
1597                 case 0xc1:
1598                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1599                         break;
1600                 default: /* XL */
1601                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1602                         break;
1603                 }
1604                 break;
1605         case CHIP_NAVI14:
1606                 switch (adev->pdev->revision) {
1607                 case 0xc7: /* XT */
1608                 case 0xf4:
1609                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1610                         break;
1611                 case 0xc1: /* XTM */
1612                 case 0xf2:
1613                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1614                         break;
1615                 case 0xc3: /* XLM */
1616                 case 0xf3:
1617                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1618                         break;
1619                 case 0xc5: /* XTX */
1620                 case 0xf6:
1621                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1622                         break;
1623                 default: /* XL */
1624                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1625                         break;
1626                 }
1627                 break;
1628         default:
1629                 return -EINVAL;
1630         }
1631
1632         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
1633         if (ret)
1634                 return ret;
1635         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
1636         if (ret)
1637                 return ret;
1638
1639         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1640         if (ret)
1641                 return ret;
1642         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1643         if (ret)
1644                 return ret;
1645
1646         return ret;
1647 }
1648
1649 static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1650 {
1651         int ret = 0;
1652
1653         switch (level) {
1654         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1655                 ret = navi10_set_peak_clock_by_device(smu);
1656                 break;
1657         default:
1658                 ret = -EINVAL;
1659                 break;
1660         }
1661
1662         return ret;
1663 }
1664
1665 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1666                                                 struct smu_temperature_range *range)
1667 {
1668         struct smu_table_context *table_context = &smu->smu_table;
1669         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1670
1671         if (!range || !powerplay_table)
1672                 return -EINVAL;
1673
1674         range->max = powerplay_table->software_shutdown_temp *
1675                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1676
1677         return 0;
1678 }
1679
1680 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1681                                                 bool disable_memory_clock_switch)
1682 {
1683         int ret = 0;
1684         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1685                 (struct smu_11_0_max_sustainable_clocks *)
1686                         smu->smu_table.max_sustainable_clocks;
1687         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1688         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1689
1690         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1691                 return 0;
1692
1693         if(disable_memory_clock_switch)
1694                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1695         else
1696                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1697
1698         if(!ret)
1699                 smu->disable_uclk_switch = disable_memory_clock_switch;
1700
1701         return ret;
1702 }
1703
1704 static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
1705 {
1706         PPTable_t *pptable = smu->smu_table.driver_pptable;
1707         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1708 }
1709
1710 static int navi10_get_power_limit(struct smu_context *smu,
1711                                      uint32_t *limit,
1712                                      bool cap)
1713 {
1714         PPTable_t *pptable = smu->smu_table.driver_pptable;
1715         uint32_t asic_default_power_limit = 0;
1716         int ret = 0;
1717         int power_src;
1718
1719         if (!smu->power_limit) {
1720                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1721                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1722                         if (power_src < 0)
1723                                 return -EINVAL;
1724
1725                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1726                                 power_src << 16);
1727                         if (ret) {
1728                                 pr_err("[%s] get PPT limit failed!", __func__);
1729                                 return ret;
1730                         }
1731                         smu_read_smc_arg(smu, &asic_default_power_limit);
1732                 } else {
1733                         /* the last hope to figure out the ppt limit */
1734                         if (!pptable) {
1735                                 pr_err("Cannot get PPT limit due to pptable missing!");
1736                                 return -EINVAL;
1737                         }
1738                         asic_default_power_limit =
1739                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1740                 }
1741
1742                 smu->power_limit = asic_default_power_limit;
1743         }
1744
1745         if (cap)
1746                 *limit = smu_v11_0_get_max_power_limit(smu);
1747         else
1748                 *limit = smu->power_limit;
1749
1750         return 0;
1751 }
1752
1753 static int navi10_update_pcie_parameters(struct smu_context *smu,
1754                                      uint32_t pcie_gen_cap,
1755                                      uint32_t pcie_width_cap)
1756 {
1757         PPTable_t *pptable = smu->smu_table.driver_pptable;
1758         int ret, i;
1759         uint32_t smu_pcie_arg;
1760
1761         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1762         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1763
1764         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1765                 smu_pcie_arg = (i << 16) |
1766                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1767                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1768                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1769                 ret = smu_send_smc_msg_with_param(smu,
1770                                           SMU_MSG_OverridePcieParameters,
1771                                           smu_pcie_arg);
1772
1773                 if (ret)
1774                         return ret;
1775
1776                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1777                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1778                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1779                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1780         }
1781
1782         return 0;
1783 }
1784
1785 static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
1786         pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1787         pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1788         pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1789         pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1790         pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
1791         pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1792 }
1793
1794 static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
1795 {
1796         if (value < od_table->min[setting]) {
1797                 pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
1798                 return -EINVAL;
1799         }
1800         if (value > od_table->max[setting]) {
1801                 pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
1802                 return -EINVAL;
1803         }
1804         return 0;
1805 }
1806
1807 static int navi10_setup_od_limits(struct smu_context *smu) {
1808         struct smu_11_0_overdrive_table *overdrive_table = NULL;
1809         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1810
1811         if (!smu->smu_table.power_play_table) {
1812                 pr_err("powerplay table uninitialized!\n");
1813                 return -ENOENT;
1814         }
1815         powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1816         overdrive_table = &powerplay_table->overdrive_table;
1817         if (!smu->od_settings) {
1818                 smu->od_settings = kmemdup(overdrive_table, sizeof(struct smu_11_0_overdrive_table), GFP_KERNEL);
1819         } else {
1820                 memcpy(smu->od_settings, overdrive_table, sizeof(struct smu_11_0_overdrive_table));
1821         }
1822         return 0;
1823 }
1824
1825 static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
1826         OverDriveTable_t *od_table;
1827         int ret = 0;
1828
1829         ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
1830         if (ret)
1831                 return ret;
1832
1833         if (initialize) {
1834                 ret = navi10_setup_od_limits(smu);
1835                 if (ret) {
1836                         pr_err("Failed to retrieve board OD limits\n");
1837                         return ret;
1838                 }
1839
1840         }
1841
1842         od_table = (OverDriveTable_t *)smu->smu_table.overdrive_table;
1843         if (od_table) {
1844                 navi10_dump_od_table(od_table);
1845         }
1846
1847         return ret;
1848 }
1849
1850 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
1851         int i;
1852         int ret = 0;
1853         struct smu_table_context *table_context = &smu->smu_table;
1854         OverDriveTable_t *od_table;
1855         struct smu_11_0_overdrive_table *od_settings;
1856         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
1857         uint16_t *freq_ptr, *voltage_ptr;
1858         od_table = (OverDriveTable_t *)table_context->overdrive_table;
1859
1860         if (!smu->od_enabled) {
1861                 pr_warn("OverDrive is not enabled!\n");
1862                 return -EINVAL;
1863         }
1864
1865         if (!smu->od_settings) {
1866                 pr_err("OD board limits are not set!\n");
1867                 return -ENOENT;
1868         }
1869
1870         od_settings = smu->od_settings;
1871
1872         switch (type) {
1873         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1874                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
1875                         pr_warn("GFXCLK_LIMITS not supported!\n");
1876                         return -ENOTSUPP;
1877                 }
1878                 if (!table_context->overdrive_table) {
1879                         pr_err("Overdrive is not initialized\n");
1880                         return -EINVAL;
1881                 }
1882                 for (i = 0; i < size; i += 2) {
1883                         if (i + 2 > size) {
1884                                 pr_info("invalid number of input parameters %d\n", size);
1885                                 return -EINVAL;
1886                         }
1887                         switch (input[i]) {
1888                         case 0:
1889                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
1890                                 freq_ptr = &od_table->GfxclkFmin;
1891                                 if (input[i + 1] > od_table->GfxclkFmax) {
1892                                         pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1893                                                 input[i + 1],
1894                                                 od_table->GfxclkFmin);
1895                                         return -EINVAL;
1896                                 }
1897                                 break;
1898                         case 1:
1899                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
1900                                 freq_ptr = &od_table->GfxclkFmax;
1901                                 if (input[i + 1] < od_table->GfxclkFmin) {
1902                                         pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
1903                                                 input[i + 1],
1904                                                 od_table->GfxclkFmax);
1905                                         return -EINVAL;
1906                                 }
1907                                 break;
1908                         default:
1909                                 pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1910                                 pr_info("Supported indices: [0:min,1:max]\n");
1911                                 return -EINVAL;
1912                         }
1913                         ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
1914                         if (ret)
1915                                 return ret;
1916                         *freq_ptr = input[i + 1];
1917                 }
1918                 break;
1919         case PP_OD_EDIT_MCLK_VDDC_TABLE:
1920                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
1921                         pr_warn("UCLK_MAX not supported!\n");
1922                         return -ENOTSUPP;
1923                 }
1924                 if (size < 2) {
1925                         pr_info("invalid number of parameters: %d\n", size);
1926                         return -EINVAL;
1927                 }
1928                 if (input[0] != 1) {
1929                         pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
1930                         pr_info("Supported indices: [1:max]\n");
1931                         return -EINVAL;
1932                 }
1933                 ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
1934                 if (ret)
1935                         return ret;
1936                 od_table->UclkFmax = input[1];
1937                 break;
1938         case PP_OD_COMMIT_DPM_TABLE:
1939                 navi10_dump_od_table(od_table);
1940                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
1941                 if (ret) {
1942                         pr_err("Failed to import overdrive table!\n");
1943                         return ret;
1944                 }
1945                 // no lock needed because smu_od_edit_dpm_table has it
1946                 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
1947                         AMD_PP_TASK_READJUST_POWER_STATE,
1948                         false);
1949                 if (ret) {
1950                         return ret;
1951                 }
1952                 break;
1953         case PP_OD_EDIT_VDDC_CURVE:
1954                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
1955                         pr_warn("GFXCLK_CURVE not supported!\n");
1956                         return -ENOTSUPP;
1957                 }
1958                 if (size < 3) {
1959                         pr_info("invalid number of parameters: %d\n", size);
1960                         return -EINVAL;
1961                 }
1962                 if (!od_table) {
1963                         pr_info("Overdrive is not initialized\n");
1964                         return -EINVAL;
1965                 }
1966
1967                 switch (input[0]) {
1968                 case 0:
1969                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
1970                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
1971                         freq_ptr = &od_table->GfxclkFreq1;
1972                         voltage_ptr = &od_table->GfxclkVolt1;
1973                         break;
1974                 case 1:
1975                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
1976                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
1977                         freq_ptr = &od_table->GfxclkFreq2;
1978                         voltage_ptr = &od_table->GfxclkVolt2;
1979                         break;
1980                 case 2:
1981                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
1982                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
1983                         freq_ptr = &od_table->GfxclkFreq3;
1984                         voltage_ptr = &od_table->GfxclkVolt3;
1985                         break;
1986                 default:
1987                         pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
1988                         pr_info("Supported indices: [0, 1, 2]\n");
1989                         return -EINVAL;
1990                 }
1991                 ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
1992                 if (ret)
1993                         return ret;
1994                 // Allow setting zero to disable the OverDrive VDDC curve
1995                 if (input[2] != 0) {
1996                         ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
1997                         if (ret)
1998                                 return ret;
1999                         *freq_ptr = input[1];
2000                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2001                         pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2002                 } else {
2003                         // If setting 0, disable all voltage curve settings
2004                         od_table->GfxclkVolt1 = 0;
2005                         od_table->GfxclkVolt2 = 0;
2006                         od_table->GfxclkVolt3 = 0;
2007                 }
2008                 navi10_dump_od_table(od_table);
2009                 break;
2010         default:
2011                 return -ENOSYS;
2012         }
2013         return ret;
2014 }
2015
2016 static int navi10_run_btc(struct smu_context *smu)
2017 {
2018         int ret = 0;
2019
2020         ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc);
2021         if (ret)
2022                 pr_err("RunBtc failed!\n");
2023
2024         return ret;
2025 }
2026
2027 static const struct pptable_funcs navi10_ppt_funcs = {
2028         .tables_init = navi10_tables_init,
2029         .alloc_dpm_context = navi10_allocate_dpm_context,
2030         .store_powerplay_table = navi10_store_powerplay_table,
2031         .check_powerplay_table = navi10_check_powerplay_table,
2032         .append_powerplay_table = navi10_append_powerplay_table,
2033         .get_smu_msg_index = navi10_get_smu_msg_index,
2034         .get_smu_clk_index = navi10_get_smu_clk_index,
2035         .get_smu_feature_index = navi10_get_smu_feature_index,
2036         .get_smu_table_index = navi10_get_smu_table_index,
2037         .get_smu_power_index = navi10_get_pwr_src_index,
2038         .get_workload_type = navi10_get_workload_type,
2039         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2040         .set_default_dpm_table = navi10_set_default_dpm_table,
2041         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
2042         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2043         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
2044         .print_clk_levels = navi10_print_clk_levels,
2045         .force_clk_levels = navi10_force_clk_levels,
2046         .populate_umd_state_clk = navi10_populate_umd_state_clk,
2047         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2048         .pre_display_config_changed = navi10_pre_display_config_changed,
2049         .display_config_changed = navi10_display_config_changed,
2050         .notify_smc_display_config = navi10_notify_smc_display_config,
2051         .force_dpm_limit_value = navi10_force_dpm_limit_value,
2052         .unforce_dpm_levels = navi10_unforce_dpm_levels,
2053         .is_dpm_running = navi10_is_dpm_running,
2054         .get_fan_speed_percent = navi10_get_fan_speed_percent,
2055         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2056         .get_power_profile_mode = navi10_get_power_profile_mode,
2057         .set_power_profile_mode = navi10_set_power_profile_mode,
2058         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
2059         .set_watermarks_table = navi10_set_watermarks_table,
2060         .read_sensor = navi10_read_sensor,
2061         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2062         .set_performance_level = navi10_set_performance_level,
2063         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2064         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2065         .get_power_limit = navi10_get_power_limit,
2066         .update_pcie_parameters = navi10_update_pcie_parameters,
2067         .init_microcode = smu_v11_0_init_microcode,
2068         .load_microcode = smu_v11_0_load_microcode,
2069         .init_smc_tables = smu_v11_0_init_smc_tables,
2070         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2071         .init_power = smu_v11_0_init_power,
2072         .fini_power = smu_v11_0_fini_power,
2073         .check_fw_status = smu_v11_0_check_fw_status,
2074         .setup_pptable = smu_v11_0_setup_pptable,
2075         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2076         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2077         .check_pptable = smu_v11_0_check_pptable,
2078         .parse_pptable = smu_v11_0_parse_pptable,
2079         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2080         .check_fw_version = smu_v11_0_check_fw_version,
2081         .write_pptable = smu_v11_0_write_pptable,
2082         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2083         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2084         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2085         .system_features_control = smu_v11_0_system_features_control,
2086         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2087         .read_smc_arg = smu_v11_0_read_arg,
2088         .init_display_count = smu_v11_0_init_display_count,
2089         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2090         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2091         .notify_display_change = smu_v11_0_notify_display_change,
2092         .set_power_limit = smu_v11_0_set_power_limit,
2093         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2094         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2095         .start_thermal_control = smu_v11_0_start_thermal_control,
2096         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2097         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2098         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2099         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2100         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2101         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2102         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2103         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2104         .gfx_off_control = smu_v11_0_gfx_off_control,
2105         .register_irq_handler = smu_v11_0_register_irq_handler,
2106         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2107         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2108         .baco_is_support= smu_v11_0_baco_is_support,
2109         .baco_get_state = smu_v11_0_baco_get_state,
2110         .baco_set_state = smu_v11_0_baco_set_state,
2111         .baco_enter = smu_v11_0_baco_enter,
2112         .baco_exit = smu_v11_0_baco_exit,
2113         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2114         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2115         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2116         .set_default_od_settings = navi10_set_default_od_settings,
2117         .od_edit_dpm_table = navi10_od_edit_dpm_table,
2118         .get_pptable_power_limit = navi10_get_pptable_power_limit,
2119         .run_btc = navi10_run_btc,
2120 };
2121
2122 void navi10_set_ppt_funcs(struct smu_context *smu)
2123 {
2124         smu->ppt_funcs = &navi10_ppt_funcs;
2125 }