2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
28 #include "amdgpu_smu.h"
29 #include "smu_internal.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "smu_v11_0.h"
33 #include "smu11_driver_if_navi10.h"
34 #include "soc15_common.h"
36 #include "navi10_ppt.h"
37 #include "smu_v11_0_pptable.h"
38 #include "smu_v11_0_ppsmc.h"
39 #include "nbio/nbio_7_4_sh_mask.h"
41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
43 #define FEATURE_MASK(feature) (1ULL << feature)
44 #define SMC_DPM_FEATURE ( \
45 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
46 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
47 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
48 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
49 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
50 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
51 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
52 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
54 #define MSG_MAP(msg, index) \
55 [SMU_MSG_##msg] = {1, (index)}
57 static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
58 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
59 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
60 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
61 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
62 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
63 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
64 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
65 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
66 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
67 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
68 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
69 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
70 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
71 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
72 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
73 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
74 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
75 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
76 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
77 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
78 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
79 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
80 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
81 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc),
82 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
83 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
84 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
85 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
86 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
87 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
88 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
89 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
90 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig),
91 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
92 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
93 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
94 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
95 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk),
96 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
97 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
98 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
99 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
100 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
101 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
102 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
103 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
104 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt),
105 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays),
106 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
107 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
108 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
109 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
110 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
111 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
112 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
113 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
114 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
115 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
116 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
117 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
118 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
119 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
120 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
121 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
124 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
125 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
126 CLK_MAP(SCLK, PPCLK_GFXCLK),
127 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
128 CLK_MAP(FCLK, PPCLK_SOCCLK),
129 CLK_MAP(UCLK, PPCLK_UCLK),
130 CLK_MAP(MCLK, PPCLK_UCLK),
131 CLK_MAP(DCLK, PPCLK_DCLK),
132 CLK_MAP(VCLK, PPCLK_VCLK),
133 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
134 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
135 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
136 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
139 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
140 FEA_MAP(DPM_PREFETCHER),
142 FEA_MAP(DPM_GFX_PACE),
147 FEA_MAP(DPM_DCEFCLK),
148 FEA_MAP(MEM_VDDCI_SCALING),
149 FEA_MAP(MEM_MVDD_SCALING),
162 FEA_MAP(RSMU_SMN_CG),
172 FEA_MAP(FAN_CONTROL),
176 FEA_MAP(LED_DISPLAY),
178 FEA_MAP(OUT_OF_BAND_MONITOR),
179 FEA_MAP(TEMP_DEPENDENT_VMIN),
185 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
189 TAB_MAP(AVFS_PSM_DEBUG),
190 TAB_MAP(AVFS_FUSE_OVERRIDE),
191 TAB_MAP(PMSTATUSLOG),
192 TAB_MAP(SMU_METRICS),
193 TAB_MAP(DRIVER_SMU_CONFIG),
194 TAB_MAP(ACTIVITY_MONITOR_COEFF),
196 TAB_MAP(I2C_COMMANDS),
200 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
205 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
215 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
217 struct smu_11_0_cmn2aisc_mapping mapping;
219 if (index >= SMU_MSG_MAX_COUNT)
222 mapping = navi10_message_map[index];
223 if (!(mapping.valid_mapping)) {
227 return mapping.map_to;
230 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
232 struct smu_11_0_cmn2aisc_mapping mapping;
234 if (index >= SMU_CLK_COUNT)
237 mapping = navi10_clk_map[index];
238 if (!(mapping.valid_mapping)) {
242 return mapping.map_to;
245 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
247 struct smu_11_0_cmn2aisc_mapping mapping;
249 if (index >= SMU_FEATURE_COUNT)
252 mapping = navi10_feature_mask_map[index];
253 if (!(mapping.valid_mapping)) {
257 return mapping.map_to;
260 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
262 struct smu_11_0_cmn2aisc_mapping mapping;
264 if (index >= SMU_TABLE_COUNT)
267 mapping = navi10_table_map[index];
268 if (!(mapping.valid_mapping)) {
272 return mapping.map_to;
275 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
277 struct smu_11_0_cmn2aisc_mapping mapping;
279 if (index >= SMU_POWER_SOURCE_COUNT)
282 mapping = navi10_pwr_src_map[index];
283 if (!(mapping.valid_mapping)) {
287 return mapping.map_to;
291 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
293 struct smu_11_0_cmn2aisc_mapping mapping;
295 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
298 mapping = navi10_workload_map[profile];
299 if (!(mapping.valid_mapping)) {
303 return mapping.map_to;
306 static bool is_asic_secure(struct smu_context *smu)
308 struct amdgpu_device *adev = smu->adev;
309 bool is_secure = true;
310 uint32_t mp0_fw_intf;
312 mp0_fw_intf = RREG32_PCIE(MP0_Public |
313 (smnMP0_FW_INTF & 0xffffffff));
315 if (!(mp0_fw_intf & (1 << 19)))
322 navi10_get_allowed_feature_mask(struct smu_context *smu,
323 uint32_t *feature_mask, uint32_t num)
325 struct amdgpu_device *adev = smu->adev;
330 memset(feature_mask, 0, sizeof(uint32_t) * num);
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
333 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
334 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
335 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
336 | FEATURE_MASK(FEATURE_PPT_BIT)
337 | FEATURE_MASK(FEATURE_TDC_BIT)
338 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
339 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
340 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
341 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
342 | FEATURE_MASK(FEATURE_THERMAL_BIT)
343 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
344 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
345 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
346 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
347 | FEATURE_MASK(FEATURE_BACO_BIT)
348 | FEATURE_MASK(FEATURE_ACDC_BIT)
349 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
350 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
351 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
352 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
354 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
355 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
357 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
358 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
360 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
361 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
363 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
364 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
366 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
367 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
368 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
369 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
371 if (adev->pm.pp_feature & PP_ULV_MASK)
372 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
374 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
375 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
377 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
378 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
380 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
381 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
383 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
384 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
386 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
387 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
389 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
390 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
392 /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
393 if (is_asic_secure(smu)) {
394 /* only for navi10 A0 */
395 if ((adev->asic_type == CHIP_NAVI10) &&
396 (adev->rev_id == 0)) {
397 *(uint64_t *)feature_mask &=
398 ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
399 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
400 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
401 *(uint64_t *)feature_mask &=
402 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
409 static int navi10_check_powerplay_table(struct smu_context *smu)
414 static int navi10_append_powerplay_table(struct smu_context *smu)
416 struct amdgpu_device *adev = smu->adev;
417 struct smu_table_context *table_context = &smu->smu_table;
418 PPTable_t *smc_pptable = table_context->driver_pptable;
419 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
422 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
425 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
426 (uint8_t **)&smc_dpm_table);
430 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
431 sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
433 /* SVI2 Board Parameters */
434 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
435 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
436 smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
437 smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
438 smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
439 smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
440 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
441 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
442 smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
443 smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
445 /* Telemetry Settings */
446 smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
447 smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
448 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
449 smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
450 smc_pptable->SocOffset = smc_dpm_table->SocOffset;
451 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
452 smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
453 smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
454 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
455 smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
456 smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
457 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
460 smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
461 smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
462 smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
463 smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
464 smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
465 smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
466 smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
467 smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
469 /* LED Display Settings */
470 smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
471 smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
472 smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
473 smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
475 /* GFXCLK PLL Spread Spectrum */
476 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
477 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
478 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
480 /* GFXCLK DFLL Spread Spectrum */
481 smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
482 smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
483 smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
485 /* UCLK Spread Spectrum */
486 smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
487 smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
488 smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
490 /* SOCCLK Spread Spectrum */
491 smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
492 smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
493 smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
495 /* Total board power */
496 smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
497 smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
499 /* Mvdd Svi2 Div Ratio Setting */
500 smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
502 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
503 /* TODO: remove it once SMU fw fix it */
504 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
510 static int navi10_store_powerplay_table(struct smu_context *smu)
512 struct smu_11_0_powerplay_table *powerplay_table = NULL;
513 struct smu_table_context *table_context = &smu->smu_table;
514 struct smu_baco_context *smu_baco = &smu->smu_baco;
516 if (!table_context->power_play_table)
519 powerplay_table = table_context->power_play_table;
521 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
524 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
526 mutex_lock(&smu_baco->mutex);
527 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
528 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
529 smu_baco->platform_support = true;
530 mutex_unlock(&smu_baco->mutex);
535 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
537 struct smu_table_context *smu_table = &smu->smu_table;
539 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
540 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
541 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
542 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
543 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
544 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
545 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
546 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
547 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
548 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
549 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
550 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
551 AMDGPU_GEM_DOMAIN_VRAM);
553 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
554 if (!smu_table->metrics_table)
556 smu_table->metrics_time = 0;
561 static int navi10_get_metrics_table(struct smu_context *smu,
562 SmuMetrics_t *metrics_table)
564 struct smu_table_context *smu_table= &smu->smu_table;
567 mutex_lock(&smu->metrics_lock);
568 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
569 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
570 (void *)smu_table->metrics_table, false);
572 pr_info("Failed to export SMU metrics table!\n");
573 mutex_unlock(&smu->metrics_lock);
576 smu_table->metrics_time = jiffies;
579 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
580 mutex_unlock(&smu->metrics_lock);
585 static int navi10_allocate_dpm_context(struct smu_context *smu)
587 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
589 if (smu_dpm->dpm_context)
592 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
594 if (!smu_dpm->dpm_context)
597 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
602 static int navi10_set_default_dpm_table(struct smu_context *smu)
604 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
605 struct smu_table_context *table_context = &smu->smu_table;
606 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
607 PPTable_t *driver_ppt = NULL;
610 driver_ppt = table_context->driver_pptable;
612 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
613 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
615 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
616 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
618 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
619 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
621 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
622 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
624 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
625 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
627 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
628 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
630 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
631 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
633 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
634 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
636 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
637 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
639 for (i = 0; i < MAX_PCIE_CONF; i++) {
640 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
641 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
647 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
649 struct smu_power_context *smu_power = &smu->smu_power;
650 struct smu_power_gate *power_gate = &smu_power->power_gate;
654 /* vcn dpm on is a prerequisite for vcn power gate messages */
655 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
656 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
660 power_gate->vcn_gated = false;
662 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
663 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
667 power_gate->vcn_gated = true;
673 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
675 struct smu_power_context *smu_power = &smu->smu_power;
676 struct smu_power_gate *power_gate = &smu_power->power_gate;
680 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
681 ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
685 power_gate->jpeg_gated = false;
687 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
688 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
692 power_gate->jpeg_gated = true;
698 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
699 enum smu_clk_type clk_type,
702 int ret = 0, clk_id = 0;
703 SmuMetrics_t metrics;
705 ret = navi10_get_metrics_table(smu, &metrics);
709 clk_id = smu_clk_get_index(smu, clk_type);
713 *value = metrics.CurrClock[clk_id];
718 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
720 PPTable_t *pptable = smu->smu_table.driver_pptable;
721 DpmDescriptor_t *dpm_desc = NULL;
722 uint32_t clk_index = 0;
724 clk_index = smu_clk_get_index(smu, clk_type);
725 dpm_desc = &pptable->DpmDescriptor[clk_index];
727 /* 0 - Fine grained DPM, 1 - Discrete DPM */
728 return dpm_desc->SnapToDiscrete == 0 ? true : false;
731 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
733 return od_table->cap[feature];
737 static int navi10_print_clk_levels(struct smu_context *smu,
738 enum smu_clk_type clk_type, char *buf)
740 uint16_t *curve_settings;
741 int i, size = 0, ret = 0;
742 uint32_t cur_value = 0, value = 0, count = 0;
743 uint32_t freq_values[3] = {0};
744 uint32_t mark_index = 0;
745 struct smu_table_context *table_context = &smu->smu_table;
746 uint32_t gen_speed, lane_width;
747 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
748 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
749 struct amdgpu_device *adev = smu->adev;
750 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
751 OverDriveTable_t *od_table =
752 (OverDriveTable_t *)table_context->overdrive_table;
753 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
763 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
768 cur_value = cur_value / 100;
770 ret = smu_get_dpm_level_count(smu, clk_type, &count);
774 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
775 for (i = 0; i < count; i++) {
776 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
780 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
781 cur_value == value ? "*" : "");
784 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
787 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
791 freq_values[1] = cur_value;
792 mark_index = cur_value == freq_values[0] ? 0 :
793 cur_value == freq_values[2] ? 2 : 1;
795 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
797 for (i = 0; i < 3; i++) {
798 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
799 i == mark_index ? "*" : "");
805 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
806 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
807 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
808 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
809 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
810 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
811 for (i = 0; i < NUM_LINK_LEVELS; i++)
812 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
813 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
814 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
815 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
816 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
817 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
818 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
819 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
820 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
821 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
822 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
823 pptable->LclkFreq[i],
824 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
825 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
829 if (!smu->od_enabled || !od_table || !od_settings)
831 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS))
833 size += sprintf(buf + size, "OD_SCLK:\n");
834 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
837 if (!smu->od_enabled || !od_table || !od_settings)
839 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX))
841 size += sprintf(buf + size, "OD_MCLK:\n");
842 size += sprintf(buf + size, "0: %uMHz\n", od_table->UclkFmax);
844 case SMU_OD_VDDC_CURVE:
845 if (!smu->od_enabled || !od_table || !od_settings)
847 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE))
849 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
850 for (i = 0; i < 3; i++) {
853 curve_settings = &od_table->GfxclkFreq1;
856 curve_settings = &od_table->GfxclkFreq2;
859 curve_settings = &od_table->GfxclkFreq3;
864 size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
874 static int navi10_force_clk_levels(struct smu_context *smu,
875 enum smu_clk_type clk_type, uint32_t mask)
878 int ret = 0, size = 0;
879 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
881 soft_min_level = mask ? (ffs(mask) - 1) : 0;
882 soft_max_level = mask ? (fls(mask) - 1) : 0;
892 /* There is only 2 levels for fine grained DPM */
893 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
894 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
895 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
898 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
902 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
906 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
917 static int navi10_populate_umd_state_clk(struct smu_context *smu)
920 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
922 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
926 smu->pstate_sclk = min_sclk_freq * 100;
928 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
932 smu->pstate_mclk = min_mclk_freq * 100;
937 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
938 enum smu_clk_type clk_type,
939 struct pp_clock_levels_with_latency *clocks)
942 uint32_t level_count = 0, freq = 0;
948 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
952 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
953 clocks->num_levels = level_count;
955 for (i = 0; i < level_count; i++) {
956 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
960 clocks->data[i].clocks_in_khz = freq * 1000;
961 clocks->data[i].latency_in_us = 0;
971 static int navi10_pre_display_config_changed(struct smu_context *smu)
974 uint32_t max_freq = 0;
976 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
980 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
981 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
984 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
992 static int navi10_display_config_changed(struct smu_context *smu)
996 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
997 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
998 ret = smu_write_watermarks_table(smu);
1002 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1005 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1006 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1007 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1008 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1009 smu->display_config->num_display);
1017 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
1020 uint32_t min_freq, max_freq, force_freq;
1021 enum smu_clk_type clk_type;
1023 enum smu_clk_type clks[] = {
1029 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1031 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1035 force_freq = highest ? max_freq : min_freq;
1036 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
1044 static int navi10_unforce_dpm_levels(struct smu_context *smu)
1047 uint32_t min_freq, max_freq;
1048 enum smu_clk_type clk_type;
1050 enum smu_clk_type clks[] = {
1056 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1058 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1062 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
1070 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1073 SmuMetrics_t metrics;
1078 ret = navi10_get_metrics_table(smu, &metrics);
1082 *value = metrics.AverageSocketPower << 8;
1087 static int navi10_get_current_activity_percent(struct smu_context *smu,
1088 enum amd_pp_sensors sensor,
1092 SmuMetrics_t metrics;
1097 ret = navi10_get_metrics_table(smu, &metrics);
1102 case AMDGPU_PP_SENSOR_GPU_LOAD:
1103 *value = metrics.AverageGfxActivity;
1105 case AMDGPU_PP_SENSOR_MEM_LOAD:
1106 *value = metrics.AverageUclkActivity;
1109 pr_err("Invalid sensor for retrieving clock activity\n");
1116 static bool navi10_is_dpm_running(struct smu_context *smu)
1119 uint32_t feature_mask[2];
1120 unsigned long feature_enabled;
1121 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1122 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1123 ((uint64_t)feature_mask[1] << 32));
1124 return !!(feature_enabled & SMC_DPM_FEATURE);
1127 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1130 SmuMetrics_t metrics;
1136 ret = navi10_get_metrics_table(smu, &metrics);
1140 *speed = metrics.CurrFanSpeed;
1145 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1149 uint32_t percent = 0;
1150 uint32_t current_rpm;
1151 PPTable_t *pptable = smu->smu_table.driver_pptable;
1153 ret = navi10_get_fan_speed_rpm(smu, ¤t_rpm);
1157 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1158 *speed = percent > 100 ? 100 : percent;
1163 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1165 DpmActivityMonitorCoeffInt_t activity_monitor;
1166 uint32_t i, size = 0;
1167 int16_t workload_type = 0;
1168 static const char *profile_name[] = {
1176 static const char *title[] = {
1177 "PROFILE_INDEX(NAME)",
1181 "MinActiveFreqType",
1186 "PD_Data_error_coeff",
1187 "PD_Data_error_rate_coeff"};
1193 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1194 title[0], title[1], title[2], title[3], title[4], title[5],
1195 title[6], title[7], title[8], title[9], title[10]);
1197 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1198 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1199 workload_type = smu_workload_get_type(smu, i);
1200 if (workload_type < 0)
1203 result = smu_update_table(smu,
1204 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1205 (void *)(&activity_monitor), false);
1207 pr_err("[%s] Failed to get activity monitor!", __func__);
1211 size += sprintf(buf + size, "%2d %14s%s:\n",
1212 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1214 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1218 activity_monitor.Gfx_FPS,
1219 activity_monitor.Gfx_MinFreqStep,
1220 activity_monitor.Gfx_MinActiveFreqType,
1221 activity_monitor.Gfx_MinActiveFreq,
1222 activity_monitor.Gfx_BoosterFreqType,
1223 activity_monitor.Gfx_BoosterFreq,
1224 activity_monitor.Gfx_PD_Data_limit_c,
1225 activity_monitor.Gfx_PD_Data_error_coeff,
1226 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1228 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1232 activity_monitor.Soc_FPS,
1233 activity_monitor.Soc_MinFreqStep,
1234 activity_monitor.Soc_MinActiveFreqType,
1235 activity_monitor.Soc_MinActiveFreq,
1236 activity_monitor.Soc_BoosterFreqType,
1237 activity_monitor.Soc_BoosterFreq,
1238 activity_monitor.Soc_PD_Data_limit_c,
1239 activity_monitor.Soc_PD_Data_error_coeff,
1240 activity_monitor.Soc_PD_Data_error_rate_coeff);
1242 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1246 activity_monitor.Mem_FPS,
1247 activity_monitor.Mem_MinFreqStep,
1248 activity_monitor.Mem_MinActiveFreqType,
1249 activity_monitor.Mem_MinActiveFreq,
1250 activity_monitor.Mem_BoosterFreqType,
1251 activity_monitor.Mem_BoosterFreq,
1252 activity_monitor.Mem_PD_Data_limit_c,
1253 activity_monitor.Mem_PD_Data_error_coeff,
1254 activity_monitor.Mem_PD_Data_error_rate_coeff);
1260 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1262 DpmActivityMonitorCoeffInt_t activity_monitor;
1263 int workload_type, ret = 0;
1265 smu->power_profile_mode = input[size];
1267 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1268 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1272 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1276 ret = smu_update_table(smu,
1277 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1278 (void *)(&activity_monitor), false);
1280 pr_err("[%s] Failed to get activity monitor!", __func__);
1285 case 0: /* Gfxclk */
1286 activity_monitor.Gfx_FPS = input[1];
1287 activity_monitor.Gfx_MinFreqStep = input[2];
1288 activity_monitor.Gfx_MinActiveFreqType = input[3];
1289 activity_monitor.Gfx_MinActiveFreq = input[4];
1290 activity_monitor.Gfx_BoosterFreqType = input[5];
1291 activity_monitor.Gfx_BoosterFreq = input[6];
1292 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1293 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1294 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1296 case 1: /* Socclk */
1297 activity_monitor.Soc_FPS = input[1];
1298 activity_monitor.Soc_MinFreqStep = input[2];
1299 activity_monitor.Soc_MinActiveFreqType = input[3];
1300 activity_monitor.Soc_MinActiveFreq = input[4];
1301 activity_monitor.Soc_BoosterFreqType = input[5];
1302 activity_monitor.Soc_BoosterFreq = input[6];
1303 activity_monitor.Soc_PD_Data_limit_c = input[7];
1304 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1305 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1308 activity_monitor.Mem_FPS = input[1];
1309 activity_monitor.Mem_MinFreqStep = input[2];
1310 activity_monitor.Mem_MinActiveFreqType = input[3];
1311 activity_monitor.Mem_MinActiveFreq = input[4];
1312 activity_monitor.Mem_BoosterFreqType = input[5];
1313 activity_monitor.Mem_BoosterFreq = input[6];
1314 activity_monitor.Mem_PD_Data_limit_c = input[7];
1315 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1316 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1320 ret = smu_update_table(smu,
1321 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1322 (void *)(&activity_monitor), true);
1324 pr_err("[%s] Failed to set activity monitor!", __func__);
1329 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1330 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1331 if (workload_type < 0)
1333 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1334 1 << workload_type);
1339 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1340 enum amd_dpm_forced_level level,
1341 uint32_t *sclk_mask,
1342 uint32_t *mclk_mask,
1346 uint32_t level_count = 0;
1348 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1351 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1354 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1356 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1359 *sclk_mask = level_count - 1;
1363 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1366 *mclk_mask = level_count - 1;
1370 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1373 *soc_mask = level_count - 1;
1380 static int navi10_notify_smc_display_config(struct smu_context *smu)
1382 struct smu_clocks min_clocks = {0};
1383 struct pp_display_clock_request clock_req;
1386 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1387 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1388 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1390 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1391 clock_req.clock_type = amd_pp_dcef_clock;
1392 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1394 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1396 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1397 ret = smu_send_smc_msg_with_param(smu,
1398 SMU_MSG_SetMinDeepSleepDcefclk,
1399 min_clocks.dcef_clock_in_sr/100);
1401 pr_err("Attempt to set divider for DCEFCLK Failed!");
1406 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1410 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1411 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1413 pr_err("[%s] Set hard min uclk failed!", __func__);
1421 static int navi10_set_watermarks_table(struct smu_context *smu,
1422 void *watermarks, struct
1423 dm_pp_wm_sets_with_clock_ranges_soc15
1427 Watermarks_t *table = watermarks;
1429 if (!table || !clock_ranges)
1432 if (clock_ranges->num_wm_dmif_sets > 4 ||
1433 clock_ranges->num_wm_mcif_sets > 4)
1436 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1437 table->WatermarkRow[1][i].MinClock =
1438 cpu_to_le16((uint16_t)
1439 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1441 table->WatermarkRow[1][i].MaxClock =
1442 cpu_to_le16((uint16_t)
1443 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1445 table->WatermarkRow[1][i].MinUclk =
1446 cpu_to_le16((uint16_t)
1447 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1449 table->WatermarkRow[1][i].MaxUclk =
1450 cpu_to_le16((uint16_t)
1451 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1453 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1454 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1457 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1458 table->WatermarkRow[0][i].MinClock =
1459 cpu_to_le16((uint16_t)
1460 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1462 table->WatermarkRow[0][i].MaxClock =
1463 cpu_to_le16((uint16_t)
1464 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1466 table->WatermarkRow[0][i].MinUclk =
1467 cpu_to_le16((uint16_t)
1468 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1470 table->WatermarkRow[0][i].MaxUclk =
1471 cpu_to_le16((uint16_t)
1472 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1474 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1475 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1481 static int navi10_thermal_get_temperature(struct smu_context *smu,
1482 enum amd_pp_sensors sensor,
1485 SmuMetrics_t metrics;
1491 ret = navi10_get_metrics_table(smu, &metrics);
1496 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1497 *value = metrics.TemperatureHotspot *
1498 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1500 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1501 *value = metrics.TemperatureEdge *
1502 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1504 case AMDGPU_PP_SENSOR_MEM_TEMP:
1505 *value = metrics.TemperatureMem *
1506 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1509 pr_err("Invalid sensor for retrieving temp\n");
1516 static int navi10_read_sensor(struct smu_context *smu,
1517 enum amd_pp_sensors sensor,
1518 void *data, uint32_t *size)
1521 struct smu_table_context *table_context = &smu->smu_table;
1522 PPTable_t *pptable = table_context->driver_pptable;
1527 mutex_lock(&smu->sensor_lock);
1529 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1530 *(uint32_t *)data = pptable->FanMaximumRpm;
1533 case AMDGPU_PP_SENSOR_MEM_LOAD:
1534 case AMDGPU_PP_SENSOR_GPU_LOAD:
1535 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1538 case AMDGPU_PP_SENSOR_GPU_POWER:
1539 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1542 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1543 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1544 case AMDGPU_PP_SENSOR_MEM_TEMP:
1545 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1549 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1551 mutex_unlock(&smu->sensor_lock);
1556 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1558 uint32_t num_discrete_levels = 0;
1559 uint16_t *dpm_levels = NULL;
1561 struct smu_table_context *table_context = &smu->smu_table;
1562 PPTable_t *driver_ppt = NULL;
1564 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1567 driver_ppt = table_context->driver_pptable;
1568 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1569 dpm_levels = driver_ppt->FreqTableUclk;
1571 if (num_discrete_levels == 0 || dpm_levels == NULL)
1574 *num_states = num_discrete_levels;
1575 for (i = 0; i < num_discrete_levels; i++) {
1576 /* convert to khz */
1577 *clocks_in_khz = (*dpm_levels) * 1000;
1585 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
1587 struct amdgpu_device *adev = smu->adev;
1589 uint32_t sclk_freq = 0, uclk_freq = 0;
1591 switch (adev->asic_type) {
1593 switch (adev->pdev->revision) {
1594 case 0xf0: /* XTX */
1596 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1600 sclk_freq = NAVI10_PEAK_SCLK_XT;
1603 sclk_freq = NAVI10_PEAK_SCLK_XL;
1608 switch (adev->pdev->revision) {
1611 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1613 case 0xc1: /* XTM */
1615 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1617 case 0xc3: /* XLM */
1619 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1621 case 0xc5: /* XTX */
1623 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1626 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1631 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1634 ret = smu_get_dpm_level_range(smu, SMU_SCLK, NULL, &sclk_freq);
1639 ret = smu_get_dpm_level_range(smu, SMU_UCLK, NULL, &uclk_freq);
1643 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1646 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1653 static int navi10_set_performance_level(struct smu_context *smu,
1654 enum amd_dpm_forced_level level)
1657 uint32_t sclk_mask, mclk_mask, soc_mask;
1660 case AMD_DPM_FORCED_LEVEL_HIGH:
1661 ret = smu_force_dpm_limit_value(smu, true);
1663 case AMD_DPM_FORCED_LEVEL_LOW:
1664 ret = smu_force_dpm_limit_value(smu, false);
1666 case AMD_DPM_FORCED_LEVEL_AUTO:
1667 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1668 ret = smu_unforce_dpm_levels(smu);
1670 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1671 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1672 ret = smu_get_profiling_clk_mask(smu, level,
1678 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1679 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1680 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1682 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1683 ret = navi10_set_peak_clock_by_device(smu);
1685 case AMD_DPM_FORCED_LEVEL_MANUAL:
1686 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1693 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1694 struct smu_temperature_range *range)
1696 struct smu_table_context *table_context = &smu->smu_table;
1697 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1699 if (!range || !powerplay_table)
1702 range->max = powerplay_table->software_shutdown_temp *
1703 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1708 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1709 bool disable_memory_clock_switch)
1712 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1713 (struct smu_11_0_max_sustainable_clocks *)
1714 smu->smu_table.max_sustainable_clocks;
1715 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1716 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1718 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1721 if(disable_memory_clock_switch)
1722 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1724 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1727 smu->disable_uclk_switch = disable_memory_clock_switch;
1732 static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
1734 PPTable_t *pptable = smu->smu_table.driver_pptable;
1735 return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1738 static int navi10_get_power_limit(struct smu_context *smu,
1742 PPTable_t *pptable = smu->smu_table.driver_pptable;
1743 uint32_t asic_default_power_limit = 0;
1747 if (!smu->power_limit) {
1748 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1749 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1753 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1756 pr_err("[%s] get PPT limit failed!", __func__);
1759 smu_read_smc_arg(smu, &asic_default_power_limit);
1761 /* the last hope to figure out the ppt limit */
1763 pr_err("Cannot get PPT limit due to pptable missing!");
1766 asic_default_power_limit =
1767 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1770 smu->power_limit = asic_default_power_limit;
1774 *limit = smu_v11_0_get_max_power_limit(smu);
1776 *limit = smu->power_limit;
1781 static int navi10_update_pcie_parameters(struct smu_context *smu,
1782 uint32_t pcie_gen_cap,
1783 uint32_t pcie_width_cap)
1785 PPTable_t *pptable = smu->smu_table.driver_pptable;
1787 uint32_t smu_pcie_arg;
1789 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1790 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1792 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1793 smu_pcie_arg = (i << 16) |
1794 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1795 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1796 pptable->PcieLaneCount[i] : pcie_width_cap);
1797 ret = smu_send_smc_msg_with_param(smu,
1798 SMU_MSG_OverridePcieParameters,
1804 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1805 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1806 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1807 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1813 static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
1814 pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1815 pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1816 pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1817 pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1818 pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
1819 pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1822 static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
1824 if (value < od_table->min[setting]) {
1825 pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
1828 if (value > od_table->max[setting]) {
1829 pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
1835 static int navi10_setup_od_limits(struct smu_context *smu) {
1836 struct smu_11_0_overdrive_table *overdrive_table = NULL;
1837 struct smu_11_0_powerplay_table *powerplay_table = NULL;
1839 if (!smu->smu_table.power_play_table) {
1840 pr_err("powerplay table uninitialized!\n");
1843 powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1844 overdrive_table = &powerplay_table->overdrive_table;
1845 if (!smu->od_settings) {
1846 smu->od_settings = kmemdup(overdrive_table, sizeof(struct smu_11_0_overdrive_table), GFP_KERNEL);
1848 memcpy(smu->od_settings, overdrive_table, sizeof(struct smu_11_0_overdrive_table));
1853 static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
1854 OverDriveTable_t *od_table;
1857 ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
1862 ret = navi10_setup_od_limits(smu);
1864 pr_err("Failed to retrieve board OD limits\n");
1870 od_table = (OverDriveTable_t *)smu->smu_table.overdrive_table;
1872 navi10_dump_od_table(od_table);
1878 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
1881 struct smu_table_context *table_context = &smu->smu_table;
1882 OverDriveTable_t *od_table;
1883 struct smu_11_0_overdrive_table *od_settings;
1884 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
1885 uint16_t *freq_ptr, *voltage_ptr;
1886 od_table = (OverDriveTable_t *)table_context->overdrive_table;
1888 if (!smu->od_enabled) {
1889 pr_warn("OverDrive is not enabled!\n");
1893 if (!smu->od_settings) {
1894 pr_err("OD board limits are not set!\n");
1898 od_settings = smu->od_settings;
1901 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1902 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
1903 pr_warn("GFXCLK_LIMITS not supported!\n");
1906 if (!table_context->overdrive_table) {
1907 pr_err("Overdrive is not initialized\n");
1910 for (i = 0; i < size; i += 2) {
1912 pr_info("invalid number of input parameters %d\n", size);
1917 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
1918 freq_ptr = &od_table->GfxclkFmin;
1919 if (input[i + 1] > od_table->GfxclkFmax) {
1920 pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1922 od_table->GfxclkFmin);
1927 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
1928 freq_ptr = &od_table->GfxclkFmax;
1929 if (input[i + 1] < od_table->GfxclkFmin) {
1930 pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
1932 od_table->GfxclkFmax);
1937 pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1938 pr_info("Supported indices: [0:min,1:max]\n");
1941 ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
1944 *freq_ptr = input[i + 1];
1947 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1948 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
1949 pr_warn("UCLK_MAX not supported!\n");
1953 pr_info("invalid number of parameters: %d\n", size);
1956 if (input[0] != 1) {
1957 pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
1958 pr_info("Supported indices: [1:max]\n");
1961 ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
1964 od_table->UclkFmax = input[1];
1966 case PP_OD_COMMIT_DPM_TABLE:
1967 navi10_dump_od_table(od_table);
1968 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
1970 pr_err("Failed to import overdrive table!\n");
1973 // no lock needed because smu_od_edit_dpm_table has it
1974 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
1975 AMD_PP_TASK_READJUST_POWER_STATE,
1981 case PP_OD_EDIT_VDDC_CURVE:
1982 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
1983 pr_warn("GFXCLK_CURVE not supported!\n");
1987 pr_info("invalid number of parameters: %d\n", size);
1991 pr_info("Overdrive is not initialized\n");
1997 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
1998 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
1999 freq_ptr = &od_table->GfxclkFreq1;
2000 voltage_ptr = &od_table->GfxclkVolt1;
2003 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2004 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2005 freq_ptr = &od_table->GfxclkFreq2;
2006 voltage_ptr = &od_table->GfxclkVolt2;
2009 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2010 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2011 freq_ptr = &od_table->GfxclkFreq3;
2012 voltage_ptr = &od_table->GfxclkVolt3;
2015 pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
2016 pr_info("Supported indices: [0, 1, 2]\n");
2019 ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
2022 // Allow setting zero to disable the OverDrive VDDC curve
2023 if (input[2] != 0) {
2024 ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
2027 *freq_ptr = input[1];
2028 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2029 pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2031 // If setting 0, disable all voltage curve settings
2032 od_table->GfxclkVolt1 = 0;
2033 od_table->GfxclkVolt2 = 0;
2034 od_table->GfxclkVolt3 = 0;
2036 navi10_dump_od_table(od_table);
2044 static int navi10_run_btc(struct smu_context *smu)
2048 ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc);
2050 pr_err("RunBtc failed!\n");
2055 static const struct pptable_funcs navi10_ppt_funcs = {
2056 .tables_init = navi10_tables_init,
2057 .alloc_dpm_context = navi10_allocate_dpm_context,
2058 .store_powerplay_table = navi10_store_powerplay_table,
2059 .check_powerplay_table = navi10_check_powerplay_table,
2060 .append_powerplay_table = navi10_append_powerplay_table,
2061 .get_smu_msg_index = navi10_get_smu_msg_index,
2062 .get_smu_clk_index = navi10_get_smu_clk_index,
2063 .get_smu_feature_index = navi10_get_smu_feature_index,
2064 .get_smu_table_index = navi10_get_smu_table_index,
2065 .get_smu_power_index = navi10_get_pwr_src_index,
2066 .get_workload_type = navi10_get_workload_type,
2067 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2068 .set_default_dpm_table = navi10_set_default_dpm_table,
2069 .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
2070 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2071 .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
2072 .print_clk_levels = navi10_print_clk_levels,
2073 .force_clk_levels = navi10_force_clk_levels,
2074 .populate_umd_state_clk = navi10_populate_umd_state_clk,
2075 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2076 .pre_display_config_changed = navi10_pre_display_config_changed,
2077 .display_config_changed = navi10_display_config_changed,
2078 .notify_smc_display_config = navi10_notify_smc_display_config,
2079 .force_dpm_limit_value = navi10_force_dpm_limit_value,
2080 .unforce_dpm_levels = navi10_unforce_dpm_levels,
2081 .is_dpm_running = navi10_is_dpm_running,
2082 .get_fan_speed_percent = navi10_get_fan_speed_percent,
2083 .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2084 .get_power_profile_mode = navi10_get_power_profile_mode,
2085 .set_power_profile_mode = navi10_set_power_profile_mode,
2086 .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
2087 .set_watermarks_table = navi10_set_watermarks_table,
2088 .read_sensor = navi10_read_sensor,
2089 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2090 .set_performance_level = navi10_set_performance_level,
2091 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2092 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2093 .get_power_limit = navi10_get_power_limit,
2094 .update_pcie_parameters = navi10_update_pcie_parameters,
2095 .init_microcode = smu_v11_0_init_microcode,
2096 .load_microcode = smu_v11_0_load_microcode,
2097 .init_smc_tables = smu_v11_0_init_smc_tables,
2098 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2099 .init_power = smu_v11_0_init_power,
2100 .fini_power = smu_v11_0_fini_power,
2101 .check_fw_status = smu_v11_0_check_fw_status,
2102 .setup_pptable = smu_v11_0_setup_pptable,
2103 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2104 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2105 .check_pptable = smu_v11_0_check_pptable,
2106 .parse_pptable = smu_v11_0_parse_pptable,
2107 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2108 .check_fw_version = smu_v11_0_check_fw_version,
2109 .write_pptable = smu_v11_0_write_pptable,
2110 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2111 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2112 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2113 .system_features_control = smu_v11_0_system_features_control,
2114 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2115 .read_smc_arg = smu_v11_0_read_arg,
2116 .init_display_count = smu_v11_0_init_display_count,
2117 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2118 .get_enabled_mask = smu_v11_0_get_enabled_mask,
2119 .notify_display_change = smu_v11_0_notify_display_change,
2120 .set_power_limit = smu_v11_0_set_power_limit,
2121 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2122 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2123 .start_thermal_control = smu_v11_0_start_thermal_control,
2124 .stop_thermal_control = smu_v11_0_stop_thermal_control,
2125 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2126 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2127 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2128 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2129 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2130 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2131 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2132 .gfx_off_control = smu_v11_0_gfx_off_control,
2133 .register_irq_handler = smu_v11_0_register_irq_handler,
2134 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2135 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2136 .baco_is_support= smu_v11_0_baco_is_support,
2137 .baco_get_state = smu_v11_0_baco_get_state,
2138 .baco_set_state = smu_v11_0_baco_set_state,
2139 .baco_enter = smu_v11_0_baco_enter,
2140 .baco_exit = smu_v11_0_baco_exit,
2141 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2142 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2143 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2144 .set_default_od_settings = navi10_set_default_od_settings,
2145 .od_edit_dpm_table = navi10_od_edit_dpm_table,
2146 .get_pptable_power_limit = navi10_get_pptable_power_limit,
2147 .run_btc = navi10_run_btc,
2150 void navi10_set_ppt_funcs(struct smu_context *smu)
2152 smu->ppt_funcs = &navi10_ppt_funcs;