drivers/gpu/drm/amd/powerplay/renoir_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "amdgpu_smu.h"
  26 #include "smu_internal.h"
  27 #include "soc15_common.h"
  28 #include "smu_v12_0_ppsmc.h"
  29 #include "smu12_driver_if.h"
  30 #include "smu_v12_0.h"
  31 #include "renoir_ppt.h"
  32
  33
  34 #define CLK_MAP(clk, index) \
  35         [SMU_##clk] = {1, (index)}
  36
  37 #define MSG_MAP(msg, index) \
  38         [SMU_MSG_##msg] = {1, (index)}
  39
  40 #define TAB_MAP_VALID(tab) \
  41         [SMU_TABLE_##tab] = {1, TABLE_##tab}
  42
  43 #define TAB_MAP_INVALID(tab) \
  44         [SMU_TABLE_##tab] = {0, TABLE_##tab}
  45
  46 static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
  47         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  48         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  49         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  50         MSG_MAP(PowerUpGfx,                     PPSMC_MSG_PowerUpGfx),
  51         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_EnableGfxOff),
  52         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisableGfxOff),
  53         MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile),
  54         MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile),
  55         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn),
  56         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn),
  57         MSG_MAP(PowerDownSdma,                  PPSMC_MSG_PowerDownSdma),
  58         MSG_MAP(PowerUpSdma,                    PPSMC_MSG_PowerUpSdma),
  59         MSG_MAP(SetHardMinIspclkByFreq,         PPSMC_MSG_SetHardMinIspclkByFreq),
  60         MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn),
  61         MSG_MAP(Spare1,                         PPSMC_MSG_spare1),
  62         MSG_MAP(Spare2,                         PPSMC_MSG_spare2),
  63         MSG_MAP(SetAllowFclkSwitch,             PPSMC_MSG_SetAllowFclkSwitch),
  64         MSG_MAP(SetMinVideoGfxclkFreq,          PPSMC_MSG_SetMinVideoGfxclkFreq),
  65         MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify),
  66         MSG_MAP(SetCustomPolicy,                PPSMC_MSG_SetCustomPolicy),
  67         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  68         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_SetDisplayCount),
  69         MSG_MAP(QueryPowerLimit,                PPSMC_MSG_QueryPowerLimit),
  70         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  71         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  72         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  73         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  74         MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset),
  75         MSG_MAP(SetGfxclkOverdriveByFreqVid,    PPSMC_MSG_SetGfxclkOverdriveByFreqVid),
  76         MSG_MAP(SetHardMinDcfclkByFreq,         PPSMC_MSG_SetHardMinDcfclkByFreq),
  77         MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq),
  78         MSG_MAP(ControlIgpuATS,                 PPSMC_MSG_ControlIgpuATS),
  79         MSG_MAP(SetMinVideoFclkFreq,            PPSMC_MSG_SetMinVideoFclkFreq),
  80         MSG_MAP(SetMinDeepSleepDcfclk,          PPSMC_MSG_SetMinDeepSleepDcfclk),
  81         MSG_MAP(ForcePowerDownGfx,              PPSMC_MSG_ForcePowerDownGfx),
  82         MSG_MAP(SetPhyclkVoltageByFreq,         PPSMC_MSG_SetPhyclkVoltageByFreq),
  83         MSG_MAP(SetDppclkVoltageByFreq,         PPSMC_MSG_SetDppclkVoltageByFreq),
  84         MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn),
  85         MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode),
  86         MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency),
  87         MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency),
  88         MSG_MAP(GetMinGfxclkFrequency,          PPSMC_MSG_GetMinGfxclkFrequency),
  89         MSG_MAP(GetMaxGfxclkFrequency,          PPSMC_MSG_GetMaxGfxclkFrequency),
  90         MSG_MAP(SoftReset,                      PPSMC_MSG_SoftReset),
  91         MSG_MAP(SetGfxCGPG,                     PPSMC_MSG_SetGfxCGPG),
  92         MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk),
  93         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk),
  94         MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq),
  95         MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq),
  96         MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn),
  97         MSG_MAP(PowerGateMmHub,                 PPSMC_MSG_PowerGateMmHub),
  98         MSG_MAP(UpdatePmeRestore,               PPSMC_MSG_UpdatePmeRestore),
  99         MSG_MAP(GpuChangeState,                 PPSMC_MSG_GpuChangeState),
 100         MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage),
 101         MSG_MAP(ForceGfxContentSave,            PPSMC_MSG_ForceGfxContentSave),
 102         MSG_MAP(EnableTmdp48MHzRefclkPwrDown,   PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown),
 103         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg),
 104         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg),
 105         MSG_MAP(PowerGateAtHub,                 PPSMC_MSG_PowerGateAtHub),
 106         MSG_MAP(SetSoftMinJpeg,                 PPSMC_MSG_SetSoftMinJpeg),
 107         MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq),
 108 };
 109
 110 static struct smu_12_0_cmn2aisc_mapping renoir_clk_map[SMU_CLK_COUNT] = {
 111         CLK_MAP(GFXCLK, CLOCK_GFXCLK),
 112         CLK_MAP(SCLK,   CLOCK_GFXCLK),
 113         CLK_MAP(SOCCLK, CLOCK_SOCCLK),
 114         CLK_MAP(UCLK, CLOCK_UMCCLK),
 115         CLK_MAP(MCLK, CLOCK_UMCCLK),
 116 };
 117
 118 static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
 119         TAB_MAP_VALID(WATERMARKS),
 120         TAB_MAP_INVALID(CUSTOM_DPM),
 121         TAB_MAP_VALID(DPMCLOCKS),
 122         TAB_MAP_VALID(SMU_METRICS),
 123 };
 124
 125 static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 126 {
 127         struct smu_12_0_cmn2aisc_mapping mapping;
 128
 129         if (index >= SMU_MSG_MAX_COUNT)
 130                 return -EINVAL;
 131
 132         mapping = renoir_message_map[index];
 133         if (!(mapping.valid_mapping))
 134                 return -EINVAL;
 135
 136         return mapping.map_to;
 137 }
 138
 139 static int renoir_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 140 {
 141         struct smu_12_0_cmn2aisc_mapping mapping;
 142
 143         if (index >= SMU_CLK_COUNT)
 144                 return -EINVAL;
 145
 146         mapping = renoir_clk_map[index];
 147         if (!(mapping.valid_mapping)) {
 148                 return -EINVAL;
 149         }
 150
 151         return mapping.map_to;
 152 }
 153
 154 static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
 155 {
 156         struct smu_12_0_cmn2aisc_mapping mapping;
 157
 158         if (index >= SMU_TABLE_COUNT)
 159                 return -EINVAL;
 160
 161         mapping = renoir_table_map[index];
 162         if (!(mapping.valid_mapping))
 163                 return -EINVAL;
 164
 165         return mapping.map_to;
 166 }
 167
 168 static int renoir_get_metrics_table(struct smu_context *smu,
 169                                     SmuMetrics_t *metrics_table)
 170 {
 171         struct smu_table_context *smu_table= &smu->smu_table;
 172         int ret = 0;
 173
 174         mutex_lock(&smu->metrics_lock);
 175         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 176                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 177                                 (void *)smu_table->metrics_table, false);
 178                 if (ret) {
 179                         pr_info("Failed to export SMU metrics table!\n");
 180                         mutex_unlock(&smu->metrics_lock);
 181                         return ret;
 182                 }
 183                 smu_table->metrics_time = jiffies;
 184         }
 185
 186         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 187         mutex_unlock(&smu->metrics_lock);
 188
 189         return ret;
 190 }
 191
 192 static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
 193 {
 194         struct smu_table_context *smu_table = &smu->smu_table;
 195
 196         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 197                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 198         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
 199                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 200         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 201                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 202
 203         smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
 204         if (!smu_table->clocks_table)
 205                 return -ENOMEM;
 206
 207         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 208         if (!smu_table->metrics_table)
 209                 return -ENOMEM;
 210         smu_table->metrics_time = 0;
 211
 212         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 213         if (!smu_table->watermarks_table)
 214                 return -ENOMEM;
 215
 216         return 0;
 217 }
 218
 219 /**
 220  * This interface just for getting uclk ultimate freq and should't introduce
 221  * other likewise function result in overmuch callback.
 222  */
 223 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
 224                                                 uint32_t dpm_level, uint32_t *freq)
 225 {
 226         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 227
 228         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 229                 return -EINVAL;
 230
 231         GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
 232
 233         return 0;
 234 }
 235
 236 static int renoir_print_clk_levels(struct smu_context *smu,
 237                         enum smu_clk_type clk_type, char *buf)
 238 {
 239         int i, size = 0, ret = 0;
 240         uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
 241         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 242         SmuMetrics_t metrics;
 243
 244         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 245                 return -EINVAL;
 246
 247         memset(&metrics, 0, sizeof(metrics));
 248
 249         ret = renoir_get_metrics_table(smu, &metrics);
 250         if (ret)
 251                 return ret;
 252
 253         switch (clk_type) {
 254         case SMU_GFXCLK:
 255         case SMU_SCLK:
 256                 /* retirve table returned paramters unit is MHz */
 257                 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
 258                 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max, false);
 259                 if (!ret) {
 260                         /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
 261                         if (cur_value  == max)
 262                                 i = 2;
 263                         else if (cur_value == min)
 264                                 i = 0;
 265                         else
 266                                 i = 1;
 267
 268                         size += sprintf(buf + size, "0: %uMhz %s\n", min,
 269                                         i == 0 ? "*" : "");
 270                         size += sprintf(buf + size, "1: %uMhz %s\n",
 271                                         i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
 272                                         i == 1 ? "*" : "");
 273                         size += sprintf(buf + size, "2: %uMhz %s\n", max,
 274                                         i == 2 ? "*" : "");
 275                 }
 276                 return size;
 277         case SMU_SOCCLK:
 278                 count = NUM_SOCCLK_DPM_LEVELS;
 279                 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
 280                 break;
 281         case SMU_MCLK:
 282                 count = NUM_MEMCLK_DPM_LEVELS;
 283                 cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
 284                 break;
 285         case SMU_DCEFCLK:
 286                 count = NUM_DCFCLK_DPM_LEVELS;
 287                 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
 288                 break;
 289         case SMU_FCLK:
 290                 count = NUM_FCLK_DPM_LEVELS;
 291                 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
 292                 break;
 293         default:
 294                 return -EINVAL;
 295         }
 296
 297         for (i = 0; i < count; i++) {
 298                 GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
 299                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 300                                 cur_value == value ? "*" : "");
 301         }
 302
 303         return size;
 304 }
 305
 306 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
 307 {
 308         enum amd_pm_state_type pm_type;
 309         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 310
 311         if (!smu_dpm_ctx->dpm_context ||
 312             !smu_dpm_ctx->dpm_current_power_state)
 313                 return -EINVAL;
 314
 315         switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
 316         case SMU_STATE_UI_LABEL_BATTERY:
 317                 pm_type = POWER_STATE_TYPE_BATTERY;
 318                 break;
 319         case SMU_STATE_UI_LABEL_BALLANCED:
 320                 pm_type = POWER_STATE_TYPE_BALANCED;
 321                 break;
 322         case SMU_STATE_UI_LABEL_PERFORMANCE:
 323                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
 324                 break;
 325         default:
 326                 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
 327                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 328                 else
 329                         pm_type = POWER_STATE_TYPE_DEFAULT;
 330                 break;
 331         }
 332
 333         return pm_type;
 334 }
 335
 336 static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 337 {
 338         struct smu_power_context *smu_power = &smu->smu_power;
 339         struct smu_power_gate *power_gate = &smu_power->power_gate;
 340         int ret = 0;
 341
 342         if (enable) {
 343                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 344                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 345                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0);
 346                         if (ret)
 347                                 return ret;
 348                 }
 349                 power_gate->vcn_gated = false;
 350         } else {
 351                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 352                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 353                         if (ret)
 354                                 return ret;
 355                 }
 356                 power_gate->vcn_gated = true;
 357         }
 358
 359         return ret;
 360 }
 361
 362 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 363 {
 364         struct smu_power_context *smu_power = &smu->smu_power;
 365         struct smu_power_gate *power_gate = &smu_power->power_gate;
 366         int ret = 0;
 367
 368         if (enable) {
 369                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 370                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0);
 371                         if (ret)
 372                                 return ret;
 373                 }
 374                 power_gate->jpeg_gated = false;
 375         } else {
 376                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 377                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0);
 378                         if (ret)
 379                                 return ret;
 380                 }
 381                 power_gate->jpeg_gated = true;
 382         }
 383
 384         return ret;
 385 }
 386
 387 static int renoir_get_current_clk_freq_by_table(struct smu_context *smu,
 388                                        enum smu_clk_type clk_type,
 389                                        uint32_t *value)
 390 {
 391         int ret = 0, clk_id = 0;
 392         SmuMetrics_t metrics;
 393
 394         ret = renoir_get_metrics_table(smu, &metrics);
 395         if (ret)
 396                 return ret;
 397
 398         clk_id = smu_clk_get_index(smu, clk_type);
 399         if (clk_id < 0)
 400                 return clk_id;
 401
 402         *value = metrics.ClockFrequency[clk_id];
 403
 404         return ret;
 405 }
 406
 407 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
 408 {
 409         int ret = 0, i = 0;
 410         uint32_t min_freq, max_freq, force_freq;
 411         enum smu_clk_type clk_type;
 412
 413         enum smu_clk_type clks[] = {
 414                 SMU_GFXCLK,
 415                 SMU_MCLK,
 416                 SMU_SOCCLK,
 417         };
 418
 419         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 420                 clk_type = clks[i];
 421                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 422                 if (ret)
 423                         return ret;
 424
 425                 force_freq = highest ? max_freq : min_freq;
 426                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
 427                 if (ret)
 428                         return ret;
 429         }
 430
 431         return ret;
 432 }
 433
 434 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
 435
 436         int ret = 0, i = 0;
 437         uint32_t min_freq, max_freq;
 438         enum smu_clk_type clk_type;
 439
 440         struct clk_feature_map {
 441                 enum smu_clk_type clk_type;
 442                 uint32_t        feature;
 443         } clk_feature_map[] = {
 444                 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
 445                 {SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
 446                 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
 447         };
 448
 449         for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
 450                 if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
 451                     continue;
 452
 453                 clk_type = clk_feature_map[i].clk_type;
 454
 455                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 456                 if (ret)
 457                         return ret;
 458
 459                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 460                 if (ret)
 461                         return ret;
 462         }
 463
 464         return ret;
 465 }
 466
 467 static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
 468 {
 469         int ret = 0;
 470         SmuMetrics_t metrics;
 471
 472         if (!value)
 473                 return -EINVAL;
 474
 475         ret = renoir_get_metrics_table(smu, &metrics);
 476         if (ret)
 477                 return ret;
 478
 479         *value = (metrics.GfxTemperature / 100) *
 480                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 481
 482         return 0;
 483 }
 484
 485 static int renoir_get_current_activity_percent(struct smu_context *smu,
 486                                                enum amd_pp_sensors sensor,
 487                                                uint32_t *value)
 488 {
 489         int ret = 0;
 490         SmuMetrics_t metrics;
 491
 492         if (!value)
 493                 return -EINVAL;
 494
 495         ret = renoir_get_metrics_table(smu, &metrics);
 496         if (ret)
 497                 return ret;
 498
 499         switch (sensor) {
 500         case AMDGPU_PP_SENSOR_GPU_LOAD:
 501                 *value = metrics.AverageGfxActivity / 100;
 502                 break;
 503         default:
 504                 pr_err("Invalid sensor for retrieving clock activity\n");
 505                 return -EINVAL;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
 512 {
 513
 514         uint32_t  pplib_workload = 0;
 515
 516         switch (profile) {
 517         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
 518                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
 519                 break;
 520         case PP_SMC_POWER_PROFILE_CUSTOM:
 521                 pplib_workload = WORKLOAD_PPLIB_COUNT;
 522                 break;
 523         case PP_SMC_POWER_PROFILE_VIDEO:
 524                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
 525                 break;
 526         case PP_SMC_POWER_PROFILE_VR:
 527                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
 528                 break;
 529         case PP_SMC_POWER_PROFILE_COMPUTE:
 530                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
 531                 break;
 532         default:
 533                 return -EINVAL;
 534         }
 535
 536         return pplib_workload;
 537 }
 538
 539 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
 540                                          enum amd_dpm_forced_level level,
 541                                          uint32_t *sclk_mask,
 542                                          uint32_t *mclk_mask,
 543                                          uint32_t *soc_mask)
 544 {
 545
 546         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
 547                 if (sclk_mask)
 548                         *sclk_mask = 0;
 549         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
 550                 if (mclk_mask)
 551                         *mclk_mask = 0;
 552         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
 553                 if(sclk_mask)
 554                         /* The sclk as gfxclk and has three level about max/min/current */
 555                         *sclk_mask = 3 - 1;
 556
 557                 if(mclk_mask)
 558                         *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
 559
 560                 if(soc_mask)
 561                         *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
 562         }
 563
 564         return 0;
 565 }
 566
 567 /**
 568  * This interface get dpm clock table for dc
 569  */
 570 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
 571 {
 572         DpmClocks_t *table = smu->smu_table.clocks_table;
 573         int i;
 574
 575         if (!clock_table || !table)
 576                 return -EINVAL;
 577
 578         for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
 579                 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
 580                 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
 581         }
 582
 583         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
 584                 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
 585                 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
 586         }
 587
 588         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
 589                 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
 590                 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
 591         }
 592
 593         for (i = 0; i<  NUM_MEMCLK_DPM_LEVELS; i++) {
 594                 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
 595                 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int renoir_force_clk_levels(struct smu_context *smu,
 602                                    enum smu_clk_type clk_type, uint32_t mask)
 603 {
 604
 605         int ret = 0 ;
 606         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 607         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 608
 609         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 610         soft_max_level = mask ? (fls(mask) - 1) : 0;
 611
 612         switch (clk_type) {
 613         case SMU_GFXCLK:
 614         case SMU_SCLK:
 615                 if (soft_min_level > 2 || soft_max_level > 2) {
 616                         pr_info("Currently sclk only support 3 levels on APU\n");
 617                         return -EINVAL;
 618                 }
 619
 620                 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min_freq, &max_freq, false);
 621                 if (ret)
 622                         return ret;
 623                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
 624                                         soft_max_level == 0 ? min_freq :
 625                                         soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq);
 626                 if (ret)
 627                         return ret;
 628                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
 629                                         soft_min_level == 2 ? max_freq :
 630                                         soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq);
 631                 if (ret)
 632                         return ret;
 633                 break;
 634         case SMU_SOCCLK:
 635                 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);
 636                 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);
 637                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq);
 638                 if (ret)
 639                         return ret;
 640                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq);
 641                 if (ret)
 642                         return ret;
 643                 break;
 644         case SMU_MCLK:
 645         case SMU_FCLK:
 646                 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_min_level, min_freq);
 647                 GET_DPM_CUR_FREQ(clk_table, clk_type, soft_max_level, max_freq);
 648                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq);
 649                 if (ret)
 650                         return ret;
 651                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq);
 652                 if (ret)
 653                         return ret;
 654                 break;
 655         default:
 656                 break;
 657         }
 658
 659         return ret;
 660 }
 661
 662 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
 663 {
 664         int workload_type, ret;
 665         uint32_t profile_mode = input[size];
 666
 667         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
 668                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
 669                 return -EINVAL;
 670         }
 671
 672         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 673         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
 674         if (workload_type < 0) {
 675                 pr_err("Unsupported power profile mode %d on RENOIR\n",smu->power_profile_mode);
 676                 return -EINVAL;
 677         }
 678
 679         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
 680                                     1 << workload_type);
 681         if (ret) {
 682                 pr_err("Fail to set workload type %d\n", workload_type);
 683                 return ret;
 684         }
 685
 686         smu->power_profile_mode = profile_mode;
 687
 688         return 0;
 689 }
 690
 691 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
 692 {
 693         int ret = 0;
 694         uint32_t sclk_freq = 0, uclk_freq = 0;
 695
 696         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq, false);
 697         if (ret)
 698                 return ret;
 699
 700         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
 701         if (ret)
 702                 return ret;
 703
 704         ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq, false);
 705         if (ret)
 706                 return ret;
 707
 708         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
 709         if (ret)
 710                 return ret;
 711
 712         return ret;
 713 }
 714
 715 static int renoir_set_performance_level(struct smu_context *smu,
 716                                         enum amd_dpm_forced_level level)
 717 {
 718         int ret = 0;
 719         uint32_t sclk_mask, mclk_mask, soc_mask;
 720
 721         switch (level) {
 722         case AMD_DPM_FORCED_LEVEL_HIGH:
 723                 ret = smu_force_dpm_limit_value(smu, true);
 724                 break;
 725         case AMD_DPM_FORCED_LEVEL_LOW:
 726                 ret = smu_force_dpm_limit_value(smu, false);
 727                 break;
 728         case AMD_DPM_FORCED_LEVEL_AUTO:
 729         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
 730                 ret = smu_unforce_dpm_levels(smu);
 731                 break;
 732         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
 733         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
 734                 ret = smu_get_profiling_clk_mask(smu, level,
 735                                                  &sclk_mask,
 736                                                  &mclk_mask,
 737                                                  &soc_mask);
 738                 if (ret)
 739                         return ret;
 740                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
 741                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
 742                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
 743                 break;
 744         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
 745                 ret = renoir_set_peak_clock_by_device(smu);
 746                 break;
 747         case AMD_DPM_FORCED_LEVEL_MANUAL:
 748         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 749         default:
 750                 break;
 751         }
 752         return ret;
 753 }
 754
 755 /* save watermark settings into pplib smu structure,
 756  * also pass data to smu controller
 757  */
 758 static int renoir_set_watermarks_table(
 759                 struct smu_context *smu,
 760                 void *watermarks,
 761                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
 762 {
 763         int i;
 764         int ret = 0;
 765         Watermarks_t *table = watermarks;
 766
 767         if (!table || !clock_ranges)
 768                 return -EINVAL;
 769
 770         if (clock_ranges->num_wm_dmif_sets > 4 ||
 771                         clock_ranges->num_wm_mcif_sets > 4)
 772                 return -EINVAL;
 773
 774         /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
 775         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
 776                 table->WatermarkRow[WM_DCFCLK][i].MinClock =
 777                         cpu_to_le16((uint16_t)
 778                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
 779                 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
 780                         cpu_to_le16((uint16_t)
 781                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
 782                 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
 783                         cpu_to_le16((uint16_t)
 784                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
 785                 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
 786                         cpu_to_le16((uint16_t)
 787                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
 788                 table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
 789                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
 790         }
 791
 792         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
 793                 table->WatermarkRow[WM_SOCCLK][i].MinClock =
 794                         cpu_to_le16((uint16_t)
 795                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
 796                 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
 797                         cpu_to_le16((uint16_t)
 798                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
 799                 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
 800                         cpu_to_le16((uint16_t)
 801                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
 802                 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
 803                         cpu_to_le16((uint16_t)
 804                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
 805                 table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
 806                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
 807         }
 808
 809         /* pass data to smu controller */
 810         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 811                         !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 812                 ret = smu_write_watermarks_table(smu);
 813                 if (ret) {
 814                         pr_err("Failed to update WMTABLE!");
 815                         return ret;
 816                 }
 817                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 818         }
 819
 820         return 0;
 821 }
 822
 823 static int renoir_get_power_profile_mode(struct smu_context *smu,
 824                                            char *buf)
 825 {
 826         static const char *profile_name[] = {
 827                                         "BOOTUP_DEFAULT",
 828                                         "3D_FULL_SCREEN",
 829                                         "POWER_SAVING",
 830                                         "VIDEO",
 831                                         "VR",
 832                                         "COMPUTE",
 833                                         "CUSTOM"};
 834         uint32_t i, size = 0;
 835         int16_t workload_type = 0;
 836
 837         if (!smu->pm_enabled || !buf)
 838                 return -EINVAL;
 839
 840         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
 841                 /*
 842                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
 843                  * Not all profile modes are supported on arcturus.
 844                  */
 845                 workload_type = smu_workload_get_type(smu, i);
 846                 if (workload_type < 0)
 847                         continue;
 848
 849                 size += sprintf(buf + size, "%2d %14s%s\n",
 850                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 851         }
 852
 853         return size;
 854 }
 855
 856 static int renoir_read_sensor(struct smu_context *smu,
 857                                  enum amd_pp_sensors sensor,
 858                                  void *data, uint32_t *size)
 859 {
 860         int ret = 0;
 861
 862         if (!data || !size)
 863                 return -EINVAL;
 864
 865         mutex_lock(&smu->sensor_lock);
 866         switch (sensor) {
 867         case AMDGPU_PP_SENSOR_GPU_LOAD:
 868                 ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
 869                 *size = 4;
 870                 break;
 871         case AMDGPU_PP_SENSOR_GPU_TEMP:
 872                 ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
 873                 *size = 4;
 874                 break;
 875         default:
 876                 ret = smu_v12_0_read_sensor(smu, sensor, data, size);
 877         }
 878         mutex_unlock(&smu->sensor_lock);
 879
 880         return ret;
 881 }
 882
 883 static const struct pptable_funcs renoir_ppt_funcs = {
 884         .get_smu_msg_index = renoir_get_smu_msg_index,
 885         .get_smu_clk_index = renoir_get_smu_clk_index,
 886         .get_smu_table_index = renoir_get_smu_table_index,
 887         .tables_init = renoir_tables_init,
 888         .set_power_state = NULL,
 889         .get_dpm_clk_limited = renoir_get_dpm_clk_limited,
 890         .print_clk_levels = renoir_print_clk_levels,
 891         .get_current_power_state = renoir_get_current_power_state,
 892         .dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
 893         .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
 894         .get_current_clk_freq_by_table = renoir_get_current_clk_freq_by_table,
 895         .force_dpm_limit_value = renoir_force_dpm_limit_value,
 896         .unforce_dpm_levels = renoir_unforce_dpm_levels,
 897         .get_workload_type = renoir_get_workload_type,
 898         .get_profiling_clk_mask = renoir_get_profiling_clk_mask,
 899         .force_clk_levels = renoir_force_clk_levels,
 900         .set_power_profile_mode = renoir_set_power_profile_mode,
 901         .set_performance_level = renoir_set_performance_level,
 902         .get_dpm_clock_table = renoir_get_dpm_clock_table,
 903         .set_watermarks_table = renoir_set_watermarks_table,
 904         .get_power_profile_mode = renoir_get_power_profile_mode,
 905         .read_sensor = renoir_read_sensor,
 906         .check_fw_status = smu_v12_0_check_fw_status,
 907         .check_fw_version = smu_v12_0_check_fw_version,
 908         .powergate_sdma = smu_v12_0_powergate_sdma,
 909         .powergate_vcn = smu_v12_0_powergate_vcn,
 910         .powergate_jpeg = smu_v12_0_powergate_jpeg,
 911         .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
 912         .read_smc_arg = smu_v12_0_read_arg,
 913         .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
 914         .gfx_off_control = smu_v12_0_gfx_off_control,
 915         .init_smc_tables = smu_v12_0_init_smc_tables,
 916         .fini_smc_tables = smu_v12_0_fini_smc_tables,
 917         .populate_smc_tables = smu_v12_0_populate_smc_tables,
 918         .get_enabled_mask = smu_v12_0_get_enabled_mask,
 919         .get_current_clk_freq = smu_v12_0_get_current_clk_freq,
 920         .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
 921         .mode2_reset = smu_v12_0_mode2_reset,
 922         .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
 923         .set_driver_table_location = smu_v12_0_set_driver_table_location,
 924 };
 925
 926 void renoir_set_ppt_funcs(struct smu_context *smu)
 927 {
 928         smu->ppt_funcs = &renoir_ppt_funcs;
 929         smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
 930         smu->is_apu = true;
 931 }