2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
26 #include "amdgpu_smu.h"
27 #include "atomfirmware.h"
28 #include "amdgpu_atomfirmware.h"
29 #include "smu_v11_0.h"
30 #include "soc15_common.h"
32 #include "vega20_ppt.h"
33 #include "navi10_ppt.h"
34 #include "pp_thermal.h"
36 #include "asic_reg/thm/thm_11_0_2_offset.h"
37 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
38 #include "asic_reg/mp/mp_11_0_offset.h"
39 #include "asic_reg/mp/mp_11_0_sh_mask.h"
40 #include "asic_reg/nbio/nbio_7_4_offset.h"
41 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
42 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
44 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
45 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
47 #define SMU11_THERMAL_MINIMUM_ALERT_TEMP 0
48 #define SMU11_THERMAL_MAXIMUM_ALERT_TEMP 255
50 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
51 #define SMU11_VOLTAGE_SCALE 4
53 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
56 struct amdgpu_device *adev = smu->adev;
57 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
61 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
63 struct amdgpu_device *adev = smu->adev;
65 *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
69 static int smu_v11_0_wait_for_response(struct smu_context *smu)
71 struct amdgpu_device *adev = smu->adev;
72 uint32_t cur_value, i;
74 for (i = 0; i < adev->usec_timeout; i++) {
75 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
76 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
81 /* timeout means wrong logic */
82 if (i == adev->usec_timeout)
85 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
88 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
90 struct amdgpu_device *adev = smu->adev;
91 int ret = 0, index = 0;
93 index = smu_msg_get_index(smu, msg);
97 smu_v11_0_wait_for_response(smu);
99 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
101 smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
103 ret = smu_v11_0_wait_for_response(smu);
106 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
114 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
118 struct amdgpu_device *adev = smu->adev;
119 int ret = 0, index = 0;
121 index = smu_msg_get_index(smu, msg);
125 ret = smu_v11_0_wait_for_response(smu);
127 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
130 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
132 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
134 smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
136 ret = smu_v11_0_wait_for_response(smu);
138 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
144 static int smu_v11_0_init_microcode(struct smu_context *smu)
146 struct amdgpu_device *adev = smu->adev;
147 const char *chip_name;
150 const struct smc_firmware_header_v1_0 *hdr;
151 const struct common_firmware_header *header;
152 struct amdgpu_firmware_info *ucode = NULL;
154 switch (adev->asic_type) {
156 chip_name = "vega20";
159 chip_name = "navi10";
165 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
167 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
170 err = amdgpu_ucode_validate(adev->pm.fw);
174 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
175 amdgpu_ucode_print_smc_hdr(&hdr->header);
176 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
178 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
179 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
180 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
181 ucode->fw = adev->pm.fw;
182 header = (const struct common_firmware_header *)ucode->fw->data;
183 adev->firmware.fw_size +=
184 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
189 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
191 release_firmware(adev->pm.fw);
197 static int smu_v11_0_load_microcode(struct smu_context *smu)
199 struct amdgpu_device *adev = smu->adev;
201 const struct smc_firmware_header_v1_0 *hdr;
202 uint32_t addr_start = MP1_SRAM;
204 uint32_t mp1_fw_flags;
206 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
207 src = (const uint32_t *)(adev->pm.fw->data +
208 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
210 for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
211 WREG32_PCIE(addr_start, src[i]);
215 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
216 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
217 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
218 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
220 for (i = 0; i < adev->usec_timeout; i++) {
221 mp1_fw_flags = RREG32_PCIE(MP1_Public |
222 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
223 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
224 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
229 if (i == adev->usec_timeout)
235 static int smu_v11_0_check_fw_status(struct smu_context *smu)
237 struct amdgpu_device *adev = smu->adev;
238 uint32_t mp1_fw_flags;
240 mp1_fw_flags = RREG32_PCIE(MP1_Public |
241 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
243 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
244 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
250 static int smu_v11_0_check_fw_version(struct smu_context *smu)
252 uint32_t if_version = 0xff, smu_version = 0xff;
254 uint8_t smu_minor, smu_debug;
257 ret = smu_get_smc_version(smu, &if_version, &smu_version);
261 smu_major = (smu_version >> 16) & 0xffff;
262 smu_minor = (smu_version >> 8) & 0xff;
263 smu_debug = (smu_version >> 0) & 0xff;
265 pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x (%d.%d.%d)\n",
266 if_version, smu_version, smu_major, smu_minor, smu_debug);
268 if (if_version != smu->smc_if_version) {
269 pr_err("SMU driver if version not matched\n");
276 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
278 struct amdgpu_device *adev = smu->adev;
279 uint32_t ppt_offset_bytes;
280 const struct smc_firmware_header_v2_0 *v2;
282 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
284 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
285 *size = le32_to_cpu(v2->ppt_size_bytes);
286 *table = (uint8_t *)v2 + ppt_offset_bytes;
291 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
293 struct amdgpu_device *adev = smu->adev;
294 const struct smc_firmware_header_v2_1 *v2_1;
295 struct smc_soft_pptable_entry *entries;
296 uint32_t pptable_count = 0;
299 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
300 entries = (struct smc_soft_pptable_entry *)
301 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
302 pptable_count = le32_to_cpu(v2_1->pptable_count);
303 for (i = 0; i < pptable_count; i++) {
304 if (le32_to_cpu(entries[i].id) == pptable_id) {
305 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
306 *size = le32_to_cpu(entries[i].ppt_size_bytes);
311 if (i == pptable_count)
317 static int smu_v11_0_setup_pptable(struct smu_context *smu)
319 struct amdgpu_device *adev = smu->adev;
320 const struct smc_firmware_header_v1_0 *hdr;
325 uint16_t version_major, version_minor;
327 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
328 version_major = le16_to_cpu(hdr->header.header_version_major);
329 version_minor = le16_to_cpu(hdr->header.header_version_minor);
330 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
331 switch (version_minor) {
333 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
336 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
337 smu->smu_table.boot_values.pp_table_id);
347 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
350 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
356 if (!smu->smu_table.power_play_table)
357 smu->smu_table.power_play_table = table;
358 if (!smu->smu_table.power_play_table_size)
359 smu->smu_table.power_play_table_size = size;
364 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
366 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
368 if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
371 return smu_alloc_dpm_context(smu);
374 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
376 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
378 if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
381 kfree(smu_dpm->dpm_context);
382 kfree(smu_dpm->golden_dpm_context);
383 kfree(smu_dpm->dpm_current_power_state);
384 kfree(smu_dpm->dpm_request_power_state);
385 smu_dpm->dpm_context = NULL;
386 smu_dpm->golden_dpm_context = NULL;
387 smu_dpm->dpm_context_size = 0;
388 smu_dpm->dpm_current_power_state = NULL;
389 smu_dpm->dpm_request_power_state = NULL;
394 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
396 struct smu_table_context *smu_table = &smu->smu_table;
397 struct smu_table *tables = NULL;
400 if (smu_table->tables || smu_table->table_count == 0)
403 tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
408 smu_table->tables = tables;
410 smu_tables_init(smu, tables);
412 ret = smu_v11_0_init_dpm_context(smu);
419 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
421 struct smu_table_context *smu_table = &smu->smu_table;
424 if (!smu_table->tables || smu_table->table_count == 0)
427 kfree(smu_table->tables);
428 smu_table->tables = NULL;
429 smu_table->table_count = 0;
431 ret = smu_v11_0_fini_dpm_context(smu);
437 static int smu_v11_0_init_power(struct smu_context *smu)
439 struct smu_power_context *smu_power = &smu->smu_power;
441 if (!smu->pm_enabled)
443 if (smu_power->power_context || smu_power->power_context_size != 0)
446 smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
448 if (!smu_power->power_context)
450 smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
452 smu->metrics_time = 0;
453 smu->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
454 if (!smu->metrics_table) {
455 kfree(smu_power->power_context);
462 static int smu_v11_0_fini_power(struct smu_context *smu)
464 struct smu_power_context *smu_power = &smu->smu_power;
466 if (!smu->pm_enabled)
468 if (!smu_power->power_context || smu_power->power_context_size == 0)
471 kfree(smu->metrics_table);
472 kfree(smu_power->power_context);
473 smu->metrics_table = NULL;
474 smu_power->power_context = NULL;
475 smu_power->power_context_size = 0;
480 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
485 struct atom_common_table_header *header;
486 struct atom_firmware_info_v3_3 *v_3_3;
487 struct atom_firmware_info_v3_1 *v_3_1;
489 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
492 ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
493 (uint8_t **)&header);
497 if (header->format_revision != 3) {
498 pr_err("unknown atom_firmware_info version! for smu11\n");
502 switch (header->content_revision) {
506 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
507 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
508 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
509 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
510 smu->smu_table.boot_values.socclk = 0;
511 smu->smu_table.boot_values.dcefclk = 0;
512 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
513 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
514 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
515 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
516 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
517 smu->smu_table.boot_values.pp_table_id = 0;
521 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
522 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
523 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
524 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
525 smu->smu_table.boot_values.socclk = 0;
526 smu->smu_table.boot_values.dcefclk = 0;
527 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
528 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
529 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
530 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
531 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
532 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
538 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
541 struct amdgpu_device *adev = smu->adev;
542 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
543 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
545 input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
546 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
547 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
550 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
555 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
556 smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
558 memset(&input, 0, sizeof(input));
559 input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
560 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
561 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
564 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
569 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
570 smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
572 memset(&input, 0, sizeof(input));
573 input.clk_id = SMU11_SYSPLL0_ECLK_ID;
574 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
575 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
578 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
583 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
584 smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
586 memset(&input, 0, sizeof(input));
587 input.clk_id = SMU11_SYSPLL0_VCLK_ID;
588 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
589 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
592 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
597 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
598 smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
600 memset(&input, 0, sizeof(input));
601 input.clk_id = SMU11_SYSPLL0_DCLK_ID;
602 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
603 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
606 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
611 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
612 smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
617 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
619 struct smu_table_context *smu_table = &smu->smu_table;
620 struct smu_table *memory_pool = &smu_table->memory_pool;
623 uint32_t address_low, address_high;
625 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
628 address = (uintptr_t)memory_pool->cpu_addr;
629 address_high = (uint32_t)upper_32_bits(address);
630 address_low = (uint32_t)lower_32_bits(address);
632 ret = smu_send_smc_msg_with_param(smu,
633 SMU_MSG_SetSystemVirtualDramAddrHigh,
637 ret = smu_send_smc_msg_with_param(smu,
638 SMU_MSG_SetSystemVirtualDramAddrLow,
643 address = memory_pool->mc_address;
644 address_high = (uint32_t)upper_32_bits(address);
645 address_low = (uint32_t)lower_32_bits(address);
647 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
651 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
655 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
656 (uint32_t)memory_pool->size);
663 static int smu_v11_0_check_pptable(struct smu_context *smu)
667 ret = smu_check_powerplay_table(smu);
671 static int smu_v11_0_parse_pptable(struct smu_context *smu)
675 struct smu_table_context *table_context = &smu->smu_table;
676 struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
678 if (table_context->driver_pptable)
681 table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
683 if (!table_context->driver_pptable)
686 ret = smu_store_powerplay_table(smu);
690 ret = smu_append_powerplay_table(smu);
695 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
699 ret = smu_set_default_dpm_table(smu);
704 static int smu_v11_0_write_pptable(struct smu_context *smu)
706 struct smu_table_context *table_context = &smu->smu_table;
709 ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
710 table_context->driver_pptable, true);
715 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
718 struct smu_table_context *smu_table = &smu->smu_table;
719 struct smu_table *table = NULL;
721 table = &smu_table->tables[SMU_TABLE_WATERMARKS];
725 if (!table->cpu_addr)
728 ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
734 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
738 ret = smu_send_smc_msg_with_param(smu,
739 SMU_MSG_SetMinDeepSleepDcefclk, clk);
741 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
746 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
748 struct smu_table_context *table_context = &smu->smu_table;
750 if (!smu->pm_enabled)
755 return smu_set_deep_sleep_dcefclk(smu,
756 table_context->boot_values.dcefclk / 100);
759 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
762 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
764 if (tool_table->mc_address) {
765 ret = smu_send_smc_msg_with_param(smu,
766 SMU_MSG_SetToolsDramAddrHigh,
767 upper_32_bits(tool_table->mc_address));
769 ret = smu_send_smc_msg_with_param(smu,
770 SMU_MSG_SetToolsDramAddrLow,
771 lower_32_bits(tool_table->mc_address));
777 static int smu_v11_0_init_display(struct smu_context *smu)
781 if (!smu->pm_enabled)
783 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
787 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
789 uint32_t feature_low = 0, feature_high = 0;
792 if (!smu->pm_enabled)
794 if (feature_id >= 0 && feature_id < 31)
795 feature_low = (1 << feature_id);
796 else if (feature_id > 31 && feature_id < 63)
797 feature_high = (1 << feature_id);
802 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
806 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
812 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
816 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
826 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
828 struct smu_feature *feature = &smu->smu_feature;
830 uint32_t feature_mask[2];
832 mutex_lock(&feature->mutex);
833 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
836 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
838 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
843 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
849 mutex_unlock(&feature->mutex);
853 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
854 uint32_t *feature_mask, uint32_t num)
856 uint32_t feature_mask_high = 0, feature_mask_low = 0;
859 if (!feature_mask || num < 2)
862 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
865 ret = smu_read_smc_arg(smu, &feature_mask_high);
869 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
872 ret = smu_read_smc_arg(smu, &feature_mask_low);
876 feature_mask[0] = feature_mask_low;
877 feature_mask[1] = feature_mask_high;
882 static int smu_v11_0_system_features_control(struct smu_context *smu,
885 struct smu_feature *feature = &smu->smu_feature;
886 uint32_t feature_mask[2];
889 if (smu->pm_enabled) {
890 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
891 SMU_MSG_DisableAllSmuFeatures));
896 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
900 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
901 feature->feature_num);
902 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
903 feature->feature_num);
908 static int smu_v11_0_notify_display_change(struct smu_context *smu)
912 if (!smu->pm_enabled)
914 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
915 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
916 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
922 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
923 enum smu_clk_type clock_select)
927 if (!smu->pm_enabled)
929 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
930 smu_clk_get_index(smu, clock_select) << 16);
932 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
936 ret = smu_read_smc_arg(smu, clock);
943 /* if DC limit is zero, return AC limit */
944 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
945 smu_clk_get_index(smu, clock_select) << 16);
947 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
951 ret = smu_read_smc_arg(smu, clock);
956 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
958 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
961 max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
963 smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
965 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
966 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
967 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
968 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
969 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
970 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
972 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
973 ret = smu_v11_0_get_max_sustainable_clock(smu,
974 &(max_sustainable_clocks->uclock),
977 pr_err("[%s] failed to get max UCLK from SMC!",
983 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
984 ret = smu_v11_0_get_max_sustainable_clock(smu,
985 &(max_sustainable_clocks->soc_clock),
988 pr_err("[%s] failed to get max SOCCLK from SMC!",
994 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
995 ret = smu_v11_0_get_max_sustainable_clock(smu,
996 &(max_sustainable_clocks->dcef_clock),
999 pr_err("[%s] failed to get max DCEFCLK from SMC!",
1004 ret = smu_v11_0_get_max_sustainable_clock(smu,
1005 &(max_sustainable_clocks->display_clock),
1008 pr_err("[%s] failed to get max DISPCLK from SMC!",
1012 ret = smu_v11_0_get_max_sustainable_clock(smu,
1013 &(max_sustainable_clocks->phy_clock),
1016 pr_err("[%s] failed to get max PHYCLK from SMC!",
1020 ret = smu_v11_0_get_max_sustainable_clock(smu,
1021 &(max_sustainable_clocks->pixel_clock),
1024 pr_err("[%s] failed to get max PIXCLK from SMC!",
1030 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1031 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1036 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1043 mutex_lock(&smu->mutex);
1044 *limit = smu->default_power_limit;
1045 if (smu->od_enabled) {
1046 *limit *= (100 + smu->smu_table.TDPODLimit);
1049 mutex_unlock(&smu->mutex);
1051 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1052 smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
1054 pr_err("[%s] get PPT limit failed!", __func__);
1057 smu_read_smc_arg(smu, limit);
1058 smu->power_limit = *limit;
1064 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1066 uint32_t max_power_limit;
1070 n = smu->default_power_limit;
1072 max_power_limit = smu->default_power_limit;
1074 if (smu->od_enabled) {
1075 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1076 max_power_limit /= 100;
1079 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1080 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1082 pr_err("[%s] Set power limit Failed!", __func__);
1089 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1090 enum smu_clk_type clk_id,
1096 if (clk_id >= SMU_CLK_COUNT || !value)
1099 /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1100 if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
1101 ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1103 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1104 (smu_clk_get_index(smu, clk_id) << 16));
1108 ret = smu_read_smc_arg(smu, &freq);
1119 static int smu_v11_0_get_thermal_range(struct smu_context *smu,
1120 struct PP_TemperatureRange *range)
1122 PPTable_t *pptable = smu->smu_table.driver_pptable;
1123 memcpy(range, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
1125 range->max = pptable->TedgeLimit *
1126 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1127 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1128 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1129 range->hotspot_crit_max = pptable->ThotspotLimit *
1130 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1131 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1132 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1133 range->mem_crit_max = pptable->ThbmLimit *
1134 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1135 range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
1136 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1141 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1142 struct PP_TemperatureRange *range)
1144 struct amdgpu_device *adev = smu->adev;
1145 int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
1146 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1147 int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
1148 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1151 if (low < range->min)
1153 if (high > range->max)
1159 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1160 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1161 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1162 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1163 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1164 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1166 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1171 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1173 struct amdgpu_device *adev = smu->adev;
1176 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1177 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1178 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1180 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1185 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1188 struct PP_TemperatureRange range = {
1198 struct amdgpu_device *adev = smu->adev;
1200 if (!smu->pm_enabled)
1202 smu_v11_0_get_thermal_range(smu, &range);
1204 if (smu->smu_table.thermal_controller_type) {
1205 ret = smu_v11_0_set_thermal_range(smu, &range);
1209 ret = smu_v11_0_enable_thermal_alert(smu);
1212 ret = smu_set_thermal_fan_table(smu);
1217 adev->pm.dpm.thermal.min_temp = range.min;
1218 adev->pm.dpm.thermal.max_temp = range.max;
1219 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1220 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1221 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1222 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1223 adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1224 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1225 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1230 static int smu_v11_0_get_metrics_table(struct smu_context *smu,
1231 SmuMetrics_t *metrics_table)
1235 if (!smu->metrics_time || time_after(jiffies, smu->metrics_time + HZ / 1000)) {
1236 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
1237 (void *)metrics_table, false);
1239 pr_info("Failed to export SMU metrics table!\n");
1242 memcpy(smu->metrics_table, metrics_table, sizeof(SmuMetrics_t));
1243 smu->metrics_time = jiffies;
1245 memcpy(metrics_table, smu->metrics_table, sizeof(SmuMetrics_t));
1250 static int smu_v11_0_thermal_get_temperature(struct smu_context *smu,
1251 enum amd_pp_sensors sensor,
1254 struct amdgpu_device *adev = smu->adev;
1255 SmuMetrics_t metrics;
1262 ret = smu_v11_0_get_metrics_table(smu, &metrics);
1267 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1268 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
1269 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
1270 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
1272 temp = temp & 0x1ff;
1273 temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
1277 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1278 *value = metrics.TemperatureEdge *
1279 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1281 case AMDGPU_PP_SENSOR_MEM_TEMP:
1282 *value = metrics.TemperatureHBM *
1283 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1286 pr_err("Invalid sensor for retrieving temp\n");
1293 static uint16_t convert_to_vddc(uint8_t vid)
1295 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1298 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1300 struct amdgpu_device *adev = smu->adev;
1301 uint32_t vdd = 0, val_vid = 0;
1305 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1306 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1307 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1309 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1317 static int smu_v11_0_read_sensor(struct smu_context *smu,
1318 enum amd_pp_sensors sensor,
1319 void *data, uint32_t *size)
1323 case AMDGPU_PP_SENSOR_GFX_MCLK:
1324 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1327 case AMDGPU_PP_SENSOR_GFX_SCLK:
1328 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1331 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1332 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1333 case AMDGPU_PP_SENSOR_MEM_TEMP:
1334 ret = smu_v11_0_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1337 case AMDGPU_PP_SENSOR_VDDGFX:
1338 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1341 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1342 *(uint32_t *)data = 0;
1346 ret = smu_common_read_sensor(smu, sensor, data, size);
1350 /* try get sensor data by asic */
1352 ret = smu_asic_read_sensor(smu, sensor, data, size);
1361 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1362 struct pp_display_clock_request
1365 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1367 enum smu_clk_type clk_select = 0;
1368 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1370 if (!smu->pm_enabled)
1372 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1374 case amd_pp_dcef_clock:
1375 clk_select = SMU_DCEFCLK;
1377 case amd_pp_disp_clock:
1378 clk_select = SMU_DISPCLK;
1380 case amd_pp_pixel_clock:
1381 clk_select = SMU_PIXCLK;
1383 case amd_pp_phy_clock:
1384 clk_select = SMU_PHYCLK;
1387 pr_info("[%s] Invalid Clock Type!", __func__);
1395 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1396 (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1404 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1405 dm_pp_wm_sets_with_clock_ranges_soc15
1409 struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1410 void *table = watermarks->cpu_addr;
1412 if (!smu->disable_watermark &&
1413 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1414 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1415 smu_set_watermarks_table(smu, table, clock_ranges);
1416 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1417 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1423 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1426 struct amdgpu_device *adev = smu->adev;
1428 switch (adev->asic_type) {
1432 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1434 mutex_lock(&smu->mutex);
1436 ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1438 ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1439 mutex_unlock(&smu->mutex);
1449 static int smu_v11_0_get_clock_ranges(struct smu_context *smu,
1451 enum smu_clk_type clock_select,
1457 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
1458 smu_clk_get_index(smu, clock_select) << 16);
1460 pr_err("[GetClockRanges] Failed to get max clock from SMC!\n");
1463 smu_read_smc_arg(smu, clock);
1465 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq,
1466 smu_clk_get_index(smu, clock_select) << 16);
1468 pr_err("[GetClockRanges] Failed to get min clock from SMC!\n");
1471 smu_read_smc_arg(smu, clock);
1477 static uint32_t smu_v11_0_dpm_get_sclk(struct smu_context *smu, bool low)
1482 if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1483 pr_err("[GetSclks]: gfxclk dpm not enabled!\n");
1488 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, false);
1490 pr_err("[GetSclks]: fail to get min SMU_GFXCLK\n");
1494 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, true);
1496 pr_err("[GetSclks]: fail to get max SMU_GFXCLK\n");
1501 return (gfx_clk * 100);
1504 static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low)
1509 if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1510 pr_err("[GetMclks]: memclk dpm not enabled!\n");
1515 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_UCLK, false);
1517 pr_err("[GetMclks]: fail to get min SMU_UCLK\n");
1521 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_GFXCLK, true);
1523 pr_err("[GetMclks]: fail to get max SMU_UCLK\n");
1528 return (mem_clk * 100);
1531 static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
1534 struct smu_table_context *table_context = &smu->smu_table;
1535 struct smu_table *table = &table_context->tables[SMU_TABLE_OVERDRIVE];
1539 * TODO: Enable overdrive for navi10, that replies on smc/pptable
1542 if (smu->adev->asic_type == CHIP_NAVI10)
1546 if (table_context->overdrive_table)
1549 table_context->overdrive_table = kzalloc(table->size, GFP_KERNEL);
1551 if (!table_context->overdrive_table)
1554 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1555 table_context->overdrive_table, false);
1557 pr_err("Failed to export over drive table!\n");
1561 smu_set_default_od8_settings(smu);
1564 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1565 table_context->overdrive_table, true);
1567 pr_err("Failed to import over drive table!\n");
1574 static int smu_v11_0_update_od8_settings(struct smu_context *smu,
1578 struct smu_table_context *table_context = &smu->smu_table;
1581 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1582 table_context->overdrive_table, false);
1584 pr_err("Failed to export over drive table!\n");
1588 smu_update_specified_od8_value(smu, index, value);
1590 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1591 table_context->overdrive_table, true);
1593 pr_err("Failed to import over drive table!\n");
1600 static int smu_v11_0_get_current_rpm(struct smu_context *smu,
1601 uint32_t *current_rpm)
1605 ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
1608 pr_err("Attempt to get current RPM from SMC Failed!\n");
1612 smu_read_smc_arg(smu, current_rpm);
1618 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1620 if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1621 return AMD_FAN_CTRL_MANUAL;
1623 return AMD_FAN_CTRL_AUTO;
1627 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1631 if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1634 ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1636 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1637 __func__, (start ? "Start" : "Stop"));
1643 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1645 struct amdgpu_device *adev = smu->adev;
1647 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1648 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1649 CG_FDO_CTRL2, TMIN, 0));
1650 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1651 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1652 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1658 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1660 struct amdgpu_device *adev = smu->adev;
1669 if (smu_v11_0_smc_fan_control(smu, stop))
1671 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1672 CG_FDO_CTRL1, FMAX_DUTY100);
1676 tmp64 = (uint64_t)speed * duty100;
1678 duty = (uint32_t)tmp64;
1680 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1681 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1682 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1684 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1688 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1696 case AMD_FAN_CTRL_NONE:
1697 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1699 case AMD_FAN_CTRL_MANUAL:
1700 ret = smu_v11_0_smc_fan_control(smu, stop);
1702 case AMD_FAN_CTRL_AUTO:
1703 ret = smu_v11_0_smc_fan_control(smu, start);
1710 pr_err("[%s]Set fan control mode failed!", __func__);
1717 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1720 struct amdgpu_device *adev = smu->adev;
1722 uint32_t tach_period, crystal_clock_freq;
1728 mutex_lock(&(smu->mutex));
1729 ret = smu_v11_0_smc_fan_control(smu, stop);
1731 goto set_fan_speed_rpm_failed;
1733 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1734 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1735 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1736 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1737 CG_TACH_CTRL, TARGET_PERIOD,
1740 ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1742 set_fan_speed_rpm_failed:
1743 mutex_unlock(&(smu->mutex));
1747 #define XGMI_STATE_D0 1
1748 #define XGMI_STATE_D3 0
1750 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1754 mutex_lock(&(smu->mutex));
1755 ret = smu_send_smc_msg_with_param(smu,
1756 SMU_MSG_SetXgmiMode,
1757 pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1758 mutex_unlock(&(smu->mutex));
1762 static const struct smu_funcs smu_v11_0_funcs = {
1763 .init_microcode = smu_v11_0_init_microcode,
1764 .load_microcode = smu_v11_0_load_microcode,
1765 .check_fw_status = smu_v11_0_check_fw_status,
1766 .check_fw_version = smu_v11_0_check_fw_version,
1767 .send_smc_msg = smu_v11_0_send_msg,
1768 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1769 .read_smc_arg = smu_v11_0_read_arg,
1770 .setup_pptable = smu_v11_0_setup_pptable,
1771 .init_smc_tables = smu_v11_0_init_smc_tables,
1772 .fini_smc_tables = smu_v11_0_fini_smc_tables,
1773 .init_power = smu_v11_0_init_power,
1774 .fini_power = smu_v11_0_fini_power,
1775 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1776 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1777 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1778 .check_pptable = smu_v11_0_check_pptable,
1779 .parse_pptable = smu_v11_0_parse_pptable,
1780 .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1781 .write_pptable = smu_v11_0_write_pptable,
1782 .write_watermarks_table = smu_v11_0_write_watermarks_table,
1783 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1784 .set_tool_table_location = smu_v11_0_set_tool_table_location,
1785 .init_display = smu_v11_0_init_display,
1786 .set_allowed_mask = smu_v11_0_set_allowed_mask,
1787 .get_enabled_mask = smu_v11_0_get_enabled_mask,
1788 .system_features_control = smu_v11_0_system_features_control,
1789 .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1790 .notify_display_change = smu_v11_0_notify_display_change,
1791 .get_power_limit = smu_v11_0_get_power_limit,
1792 .set_power_limit = smu_v11_0_set_power_limit,
1793 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1794 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1795 .start_thermal_control = smu_v11_0_start_thermal_control,
1796 .read_sensor = smu_v11_0_read_sensor,
1797 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1798 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1799 .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1800 .get_sclk = smu_v11_0_dpm_get_sclk,
1801 .get_mclk = smu_v11_0_dpm_get_mclk,
1802 .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
1803 .update_od8_settings = smu_v11_0_update_od8_settings,
1804 .get_current_rpm = smu_v11_0_get_current_rpm,
1805 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1806 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1807 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1808 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1809 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1810 .gfx_off_control = smu_v11_0_gfx_off_control,
1813 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1815 struct amdgpu_device *adev = smu->adev;
1817 smu->funcs = &smu_v11_0_funcs;
1818 switch (adev->asic_type) {
1820 vega20_set_ppt_funcs(smu);
1823 navi10_set_ppt_funcs(smu);
1826 pr_warn("Unknown asic for smu11\n");