drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pp_debug.h"
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "atomfirmware.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "smu_v11_0.h"
  30 #include "soc15_common.h"
  31 #include "atom.h"
  32 #include "vega20_ppt.h"
  33 #include "navi10_ppt.h"
  34
  35 #include "asic_reg/thm/thm_11_0_2_offset.h"
  36 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  37 #include "asic_reg/mp/mp_11_0_offset.h"
  38 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  39 #include "asic_reg/nbio/nbio_7_4_offset.h"
  40 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  41 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  42
  43 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  44 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  45
  46 #define SMU11_VOLTAGE_SCALE 4
  47
  48 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  49                                               uint16_t msg)
  50 {
  51         struct amdgpu_device *adev = smu->adev;
  52         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  53         return 0;
  54 }
  55
  56 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  57 {
  58         struct amdgpu_device *adev = smu->adev;
  59
  60         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  61         return 0;
  62 }
  63
  64 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  65 {
  66         struct amdgpu_device *adev = smu->adev;
  67         uint32_t cur_value, i;
  68
  69         for (i = 0; i < adev->usec_timeout; i++) {
  70                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  71                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  72                         break;
  73                 udelay(1);
  74         }
  75
  76         /* timeout means wrong logic */
  77         if (i == adev->usec_timeout)
  78                 return -ETIME;
  79
  80         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  81 }
  82
  83 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  84 {
  85         struct amdgpu_device *adev = smu->adev;
  86         int ret = 0, index = 0;
  87
  88         index = smu_msg_get_index(smu, msg);
  89         if (index < 0)
  90                 return index;
  91
  92         smu_v11_0_wait_for_response(smu);
  93
  94         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
  95
  96         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
  97
  98         ret = smu_v11_0_wait_for_response(smu);
  99
 100         if (ret)
 101                 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 102                        ret);
 103
 104         return ret;
 105
 106 }
 107
 108 static int
 109 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 110                               uint32_t param)
 111 {
 112
 113         struct amdgpu_device *adev = smu->adev;
 114         int ret = 0, index = 0;
 115
 116         index = smu_msg_get_index(smu, msg);
 117         if (index < 0)
 118                 return index;
 119
 120         ret = smu_v11_0_wait_for_response(smu);
 121         if (ret)
 122                 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
 123                        index, ret, param);
 124
 125         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 126
 127         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 128
 129         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 130
 131         ret = smu_v11_0_wait_for_response(smu);
 132         if (ret)
 133                 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
 134                        index, ret, param);
 135
 136         return ret;
 137 }
 138
 139 static int smu_v11_0_init_microcode(struct smu_context *smu)
 140 {
 141         struct amdgpu_device *adev = smu->adev;
 142         const char *chip_name;
 143         char fw_name[30];
 144         int err = 0;
 145         const struct smc_firmware_header_v1_0 *hdr;
 146         const struct common_firmware_header *header;
 147         struct amdgpu_firmware_info *ucode = NULL;
 148
 149         switch (adev->asic_type) {
 150         case CHIP_VEGA20:
 151                 chip_name = "vega20";
 152                 break;
 153         case CHIP_NAVI10:
 154                 chip_name = "navi10";
 155                 break;
 156         default:
 157                 BUG();
 158         }
 159
 160         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 161
 162         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 163         if (err)
 164                 goto out;
 165         err = amdgpu_ucode_validate(adev->pm.fw);
 166         if (err)
 167                 goto out;
 168
 169         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 170         amdgpu_ucode_print_smc_hdr(&hdr->header);
 171         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 172
 173         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 174                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 175                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 176                 ucode->fw = adev->pm.fw;
 177                 header = (const struct common_firmware_header *)ucode->fw->data;
 178                 adev->firmware.fw_size +=
 179                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 180         }
 181
 182 out:
 183         if (err) {
 184                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 185                           fw_name);
 186                 release_firmware(adev->pm.fw);
 187                 adev->pm.fw = NULL;
 188         }
 189         return err;
 190 }
 191
 192 static int smu_v11_0_load_microcode(struct smu_context *smu)
 193 {
 194         struct amdgpu_device *adev = smu->adev;
 195         const uint32_t *src;
 196         const struct smc_firmware_header_v1_0 *hdr;
 197         uint32_t addr_start = MP1_SRAM;
 198         uint32_t i;
 199         uint32_t mp1_fw_flags;
 200
 201         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 202         src = (const uint32_t *)(adev->pm.fw->data +
 203                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 204
 205         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 206                 WREG32_PCIE(addr_start, src[i]);
 207                 addr_start += 4;
 208         }
 209
 210         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 211                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 212         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 213                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 214
 215         for (i = 0; i < adev->usec_timeout; i++) {
 216                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 217                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 218                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 219                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 220                         break;
 221                 udelay(1);
 222         }
 223
 224         if (i == adev->usec_timeout)
 225                 return -ETIME;
 226
 227         return 0;
 228 }
 229
 230 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 231 {
 232         struct amdgpu_device *adev = smu->adev;
 233         uint32_t mp1_fw_flags;
 234
 235         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 236                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 237
 238         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 239             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 240                 return 0;
 241
 242         return -EIO;
 243 }
 244
 245 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 246 {
 247         uint32_t if_version = 0xff, smu_version = 0xff;
 248         uint16_t smu_major;
 249         uint8_t smu_minor, smu_debug;
 250         int ret = 0;
 251
 252         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 253         if (ret)
 254                 return ret;
 255
 256         smu_major = (smu_version >> 16) & 0xffff;
 257         smu_minor = (smu_version >> 8) & 0xff;
 258         smu_debug = (smu_version >> 0) & 0xff;
 259
 260         pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x (%d.%d.%d)\n",
 261                 if_version, smu_version, smu_major, smu_minor, smu_debug);
 262
 263         if (if_version != smu->smc_if_version) {
 264                 pr_err("SMU driver if version not matched\n");
 265                 ret = -EINVAL;
 266         }
 267
 268         return ret;
 269 }
 270
 271 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 272 {
 273         struct amdgpu_device *adev = smu->adev;
 274         uint32_t ppt_offset_bytes;
 275         const struct smc_firmware_header_v2_0 *v2;
 276
 277         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 278
 279         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 280         *size = le32_to_cpu(v2->ppt_size_bytes);
 281         *table = (uint8_t *)v2 + ppt_offset_bytes;
 282
 283         return 0;
 284 }
 285
 286 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
 287 {
 288         struct amdgpu_device *adev = smu->adev;
 289         const struct smc_firmware_header_v2_1 *v2_1;
 290         struct smc_soft_pptable_entry *entries;
 291         uint32_t pptable_count = 0;
 292         int i = 0;
 293
 294         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 295         entries = (struct smc_soft_pptable_entry *)
 296                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 297         pptable_count = le32_to_cpu(v2_1->pptable_count);
 298         for (i = 0; i < pptable_count; i++) {
 299                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 300                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 301                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 302                         break;
 303                 }
 304         }
 305
 306         if (i == pptable_count)
 307                 return -EINVAL;
 308
 309         return 0;
 310 }
 311
 312 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 313 {
 314         struct amdgpu_device *adev = smu->adev;
 315         const struct smc_firmware_header_v1_0 *hdr;
 316         int ret, index;
 317         uint32_t size;
 318         uint8_t frev, crev;
 319         void *table;
 320         uint16_t version_major, version_minor;
 321
 322         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 323         version_major = le16_to_cpu(hdr->header.header_version_major);
 324         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 325         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 326                 switch (version_minor) {
 327                 case 0:
 328                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 329                         break;
 330                 case 1:
 331                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 332                                                          smu->smu_table.boot_values.pp_table_id);
 333                         break;
 334                 default:
 335                         ret = -EINVAL;
 336                         break;
 337                 }
 338                 if (ret)
 339                         return ret;
 340
 341         } else {
 342                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 343                                                     powerplayinfo);
 344
 345                 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
 346                                               (uint8_t **)&table);
 347                 if (ret)
 348                         return ret;
 349         }
 350
 351         if (!smu->smu_table.power_play_table)
 352                 smu->smu_table.power_play_table = table;
 353         if (!smu->smu_table.power_play_table_size)
 354                 smu->smu_table.power_play_table_size = size;
 355
 356         return 0;
 357 }
 358
 359 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 360 {
 361         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 362
 363         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 364                 return -EINVAL;
 365
 366         return smu_alloc_dpm_context(smu);
 367 }
 368
 369 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 370 {
 371         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 372
 373         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 374                 return -EINVAL;
 375
 376         kfree(smu_dpm->dpm_context);
 377         kfree(smu_dpm->golden_dpm_context);
 378         kfree(smu_dpm->dpm_current_power_state);
 379         kfree(smu_dpm->dpm_request_power_state);
 380         smu_dpm->dpm_context = NULL;
 381         smu_dpm->golden_dpm_context = NULL;
 382         smu_dpm->dpm_context_size = 0;
 383         smu_dpm->dpm_current_power_state = NULL;
 384         smu_dpm->dpm_request_power_state = NULL;
 385
 386         return 0;
 387 }
 388
 389 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 390 {
 391         struct smu_table_context *smu_table = &smu->smu_table;
 392         struct smu_table *tables = NULL;
 393         int ret = 0;
 394
 395         if (smu_table->tables || smu_table->table_count == 0)
 396                 return -EINVAL;
 397
 398         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 399                          GFP_KERNEL);
 400         if (!tables)
 401                 return -ENOMEM;
 402
 403         smu_table->tables = tables;
 404
 405         ret = smu_tables_init(smu, tables);
 406         if (ret)
 407                 return ret;
 408
 409         ret = smu_v11_0_init_dpm_context(smu);
 410         if (ret)
 411                 return ret;
 412
 413         return 0;
 414 }
 415
 416 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 417 {
 418         struct smu_table_context *smu_table = &smu->smu_table;
 419         int ret = 0;
 420
 421         if (!smu_table->tables || smu_table->table_count == 0)
 422                 return -EINVAL;
 423
 424         kfree(smu_table->tables);
 425         kfree(smu_table->metrics_table);
 426         smu_table->tables = NULL;
 427         smu_table->table_count = 0;
 428         smu_table->metrics_table = NULL;
 429         smu_table->metrics_time = 0;
 430
 431         ret = smu_v11_0_fini_dpm_context(smu);
 432         if (ret)
 433                 return ret;
 434         return 0;
 435 }
 436
 437 static int smu_v11_0_init_power(struct smu_context *smu)
 438 {
 439         struct smu_power_context *smu_power = &smu->smu_power;
 440
 441         if (!smu->pm_enabled)
 442                 return 0;
 443         if (smu_power->power_context || smu_power->power_context_size != 0)
 444                 return -EINVAL;
 445
 446         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 447                                            GFP_KERNEL);
 448         if (!smu_power->power_context)
 449                 return -ENOMEM;
 450         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 451
 452         return 0;
 453 }
 454
 455 static int smu_v11_0_fini_power(struct smu_context *smu)
 456 {
 457         struct smu_power_context *smu_power = &smu->smu_power;
 458
 459         if (!smu->pm_enabled)
 460                 return 0;
 461         if (!smu_power->power_context || smu_power->power_context_size == 0)
 462                 return -EINVAL;
 463
 464         kfree(smu_power->power_context);
 465         smu_power->power_context = NULL;
 466         smu_power->power_context_size = 0;
 467
 468         return 0;
 469 }
 470
 471 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 472 {
 473         int ret, index;
 474         uint16_t size;
 475         uint8_t frev, crev;
 476         struct atom_common_table_header *header;
 477         struct atom_firmware_info_v3_3 *v_3_3;
 478         struct atom_firmware_info_v3_1 *v_3_1;
 479
 480         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 481                                             firmwareinfo);
 482
 483         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 484                                       (uint8_t **)&header);
 485         if (ret)
 486                 return ret;
 487
 488         if (header->format_revision != 3) {
 489                 pr_err("unknown atom_firmware_info version! for smu11\n");
 490                 return -EINVAL;
 491         }
 492
 493         switch (header->content_revision) {
 494         case 0:
 495         case 1:
 496         case 2:
 497                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 498                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 499                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 500                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 501                 smu->smu_table.boot_values.socclk = 0;
 502                 smu->smu_table.boot_values.dcefclk = 0;
 503                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 504                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 505                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 506                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 507                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 508                 smu->smu_table.boot_values.pp_table_id = 0;
 509                 break;
 510         case 3:
 511         default:
 512                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 513                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 514                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 515                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 516                 smu->smu_table.boot_values.socclk = 0;
 517                 smu->smu_table.boot_values.dcefclk = 0;
 518                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 519                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 520                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 521                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 522                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 523                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 524         }
 525
 526         return 0;
 527 }
 528
 529 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 530 {
 531         int ret, index;
 532         struct amdgpu_device *adev = smu->adev;
 533         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 534         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 535
 536         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 537         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 538         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 539                                             getsmuclockinfo);
 540
 541         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 542                                         (uint32_t *)&input);
 543         if (ret)
 544                 return -EINVAL;
 545
 546         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 547         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 548
 549         memset(&input, 0, sizeof(input));
 550         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 551         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 552         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 553                                             getsmuclockinfo);
 554
 555         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 556                                         (uint32_t *)&input);
 557         if (ret)
 558                 return -EINVAL;
 559
 560         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 561         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 562
 563         memset(&input, 0, sizeof(input));
 564         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 565         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 566         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 567                                             getsmuclockinfo);
 568
 569         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 570                                         (uint32_t *)&input);
 571         if (ret)
 572                 return -EINVAL;
 573
 574         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 575         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 576
 577         memset(&input, 0, sizeof(input));
 578         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 579         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 580         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 581                                             getsmuclockinfo);
 582
 583         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 584                                         (uint32_t *)&input);
 585         if (ret)
 586                 return -EINVAL;
 587
 588         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 589         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 590
 591         memset(&input, 0, sizeof(input));
 592         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 593         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 594         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 595                                             getsmuclockinfo);
 596
 597         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 598                                         (uint32_t *)&input);
 599         if (ret)
 600                 return -EINVAL;
 601
 602         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 603         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 604
 605         return 0;
 606 }
 607
 608 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 609 {
 610         struct smu_table_context *smu_table = &smu->smu_table;
 611         struct smu_table *memory_pool = &smu_table->memory_pool;
 612         int ret = 0;
 613         uint64_t address;
 614         uint32_t address_low, address_high;
 615
 616         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 617                 return ret;
 618
 619         address = (uintptr_t)memory_pool->cpu_addr;
 620         address_high = (uint32_t)upper_32_bits(address);
 621         address_low  = (uint32_t)lower_32_bits(address);
 622
 623         ret = smu_send_smc_msg_with_param(smu,
 624                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 625                                           address_high);
 626         if (ret)
 627                 return ret;
 628         ret = smu_send_smc_msg_with_param(smu,
 629                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 630                                           address_low);
 631         if (ret)
 632                 return ret;
 633
 634         address = memory_pool->mc_address;
 635         address_high = (uint32_t)upper_32_bits(address);
 636         address_low  = (uint32_t)lower_32_bits(address);
 637
 638         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 639                                           address_high);
 640         if (ret)
 641                 return ret;
 642         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 643                                           address_low);
 644         if (ret)
 645                 return ret;
 646         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 647                                           (uint32_t)memory_pool->size);
 648         if (ret)
 649                 return ret;
 650
 651         return ret;
 652 }
 653
 654 static int smu_v11_0_check_pptable(struct smu_context *smu)
 655 {
 656         int ret;
 657
 658         ret = smu_check_powerplay_table(smu);
 659         return ret;
 660 }
 661
 662 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 663 {
 664         int ret;
 665
 666         struct smu_table_context *table_context = &smu->smu_table;
 667         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 668
 669         if (table_context->driver_pptable)
 670                 return -EINVAL;
 671
 672         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 673
 674         if (!table_context->driver_pptable)
 675                 return -ENOMEM;
 676
 677         ret = smu_store_powerplay_table(smu);
 678         if (ret)
 679                 return -EINVAL;
 680
 681         ret = smu_append_powerplay_table(smu);
 682
 683         return ret;
 684 }
 685
 686 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 687 {
 688         int ret;
 689
 690         ret = smu_set_default_dpm_table(smu);
 691
 692         return ret;
 693 }
 694
 695 static int smu_v11_0_write_pptable(struct smu_context *smu)
 696 {
 697         struct smu_table_context *table_context = &smu->smu_table;
 698         int ret = 0;
 699
 700         ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
 701                                table_context->driver_pptable, true);
 702
 703         return ret;
 704 }
 705
 706 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 707 {
 708         int ret = 0;
 709         struct smu_table_context *smu_table = &smu->smu_table;
 710         struct smu_table *table = NULL;
 711
 712         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
 713         if (!table)
 714                 return -EINVAL;
 715
 716         if (!table->cpu_addr)
 717                 return -EINVAL;
 718
 719         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
 720                                 true);
 721
 722         return ret;
 723 }
 724
 725 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 726 {
 727         int ret;
 728
 729         ret = smu_send_smc_msg_with_param(smu,
 730                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 731         if (ret)
 732                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 733
 734         return ret;
 735 }
 736
 737 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 738 {
 739         struct smu_table_context *table_context = &smu->smu_table;
 740
 741         if (!smu->pm_enabled)
 742                 return 0;
 743         if (!table_context)
 744                 return -EINVAL;
 745
 746         return smu_set_deep_sleep_dcefclk(smu,
 747                                           table_context->boot_values.dcefclk / 100);
 748 }
 749
 750 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 751 {
 752         int ret = 0;
 753         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 754
 755         if (tool_table->mc_address) {
 756                 ret = smu_send_smc_msg_with_param(smu,
 757                                 SMU_MSG_SetToolsDramAddrHigh,
 758                                 upper_32_bits(tool_table->mc_address));
 759                 if (!ret)
 760                         ret = smu_send_smc_msg_with_param(smu,
 761                                 SMU_MSG_SetToolsDramAddrLow,
 762                                 lower_32_bits(tool_table->mc_address));
 763         }
 764
 765         return ret;
 766 }
 767
 768 static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 769 {
 770         int ret = 0;
 771
 772         if (!smu->pm_enabled)
 773                 return ret;
 774         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 775         return ret;
 776 }
 777
 778 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 779 {
 780         uint32_t feature_low = 0, feature_high = 0;
 781         int ret = 0;
 782
 783         if (!smu->pm_enabled)
 784                 return ret;
 785         if (feature_id >= 0 && feature_id < 31)
 786                 feature_low = (1 << feature_id);
 787         else if (feature_id > 31 && feature_id < 63)
 788                 feature_high = (1 << feature_id);
 789         else
 790                 return -EINVAL;
 791
 792         if (enabled) {
 793                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 794                                                   feature_low);
 795                 if (ret)
 796                         return ret;
 797                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 798                                                   feature_high);
 799                 if (ret)
 800                         return ret;
 801
 802         } else {
 803                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 804                                                   feature_low);
 805                 if (ret)
 806                         return ret;
 807                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 808                                                   feature_high);
 809                 if (ret)
 810                         return ret;
 811
 812         }
 813
 814         return ret;
 815 }
 816
 817 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 818 {
 819         struct smu_feature *feature = &smu->smu_feature;
 820         int ret = 0;
 821         uint32_t feature_mask[2];
 822
 823         mutex_lock(&feature->mutex);
 824         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 825                 goto failed;
 826
 827         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 828
 829         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 830                                           feature_mask[1]);
 831         if (ret)
 832                 goto failed;
 833
 834         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 835                                           feature_mask[0]);
 836         if (ret)
 837                 goto failed;
 838
 839 failed:
 840         mutex_unlock(&feature->mutex);
 841         return ret;
 842 }
 843
 844 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 845                                       uint32_t *feature_mask, uint32_t num)
 846 {
 847         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 848         int ret = 0;
 849
 850         if (!feature_mask || num < 2)
 851                 return -EINVAL;
 852
 853         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 854         if (ret)
 855                 return ret;
 856         ret = smu_read_smc_arg(smu, &feature_mask_high);
 857         if (ret)
 858                 return ret;
 859
 860         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 861         if (ret)
 862                 return ret;
 863         ret = smu_read_smc_arg(smu, &feature_mask_low);
 864         if (ret)
 865                 return ret;
 866
 867         feature_mask[0] = feature_mask_low;
 868         feature_mask[1] = feature_mask_high;
 869
 870         return ret;
 871 }
 872
 873 static int smu_v11_0_system_features_control(struct smu_context *smu,
 874                                              bool en)
 875 {
 876         struct smu_feature *feature = &smu->smu_feature;
 877         uint32_t feature_mask[2];
 878         int ret = 0;
 879
 880         if (smu->pm_enabled) {
 881                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 882                                              SMU_MSG_DisableAllSmuFeatures));
 883                 if (ret)
 884                         return ret;
 885         }
 886
 887         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 888         if (ret)
 889                 return ret;
 890
 891         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 892                     feature->feature_num);
 893         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 894                     feature->feature_num);
 895
 896         return ret;
 897 }
 898
 899 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 900 {
 901         int ret = 0;
 902
 903         if (!smu->pm_enabled)
 904                 return ret;
 905         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 906             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 907                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 908
 909         return ret;
 910 }
 911
 912 static int
 913 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 914                                     enum smu_clk_type clock_select)
 915 {
 916         int ret = 0;
 917
 918         if (!smu->pm_enabled)
 919                 return ret;
 920         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 921                                           smu_clk_get_index(smu, clock_select) << 16);
 922         if (ret) {
 923                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 924                 return ret;
 925         }
 926
 927         ret = smu_read_smc_arg(smu, clock);
 928         if (ret)
 929                 return ret;
 930
 931         if (*clock != 0)
 932                 return 0;
 933
 934         /* if DC limit is zero, return AC limit */
 935         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 936                                           smu_clk_get_index(smu, clock_select) << 16);
 937         if (ret) {
 938                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 939                 return ret;
 940         }
 941
 942         ret = smu_read_smc_arg(smu, clock);
 943
 944         return ret;
 945 }
 946
 947 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 948 {
 949         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 950         int ret = 0;
 951
 952         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 953                                          GFP_KERNEL);
 954         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 955
 956         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 957         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 958         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 959         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 960         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 961         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 962
 963         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 964                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 965                                                           &(max_sustainable_clocks->uclock),
 966                                                           SMU_UCLK);
 967                 if (ret) {
 968                         pr_err("[%s] failed to get max UCLK from SMC!",
 969                                __func__);
 970                         return ret;
 971                 }
 972         }
 973
 974         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 975                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 976                                                           &(max_sustainable_clocks->soc_clock),
 977                                                           SMU_SOCCLK);
 978                 if (ret) {
 979                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 980                                __func__);
 981                         return ret;
 982                 }
 983         }
 984
 985         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 986                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 987                                                           &(max_sustainable_clocks->dcef_clock),
 988                                                           SMU_DCEFCLK);
 989                 if (ret) {
 990                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
 991                                __func__);
 992                         return ret;
 993                 }
 994
 995                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 996                                                           &(max_sustainable_clocks->display_clock),
 997                                                           SMU_DISPCLK);
 998                 if (ret) {
 999                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1000                                __func__);
1001                         return ret;
1002                 }
1003                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1004                                                           &(max_sustainable_clocks->phy_clock),
1005                                                           SMU_PHYCLK);
1006                 if (ret) {
1007                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1008                                __func__);
1009                         return ret;
1010                 }
1011                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1012                                                           &(max_sustainable_clocks->pixel_clock),
1013                                                           SMU_PIXCLK);
1014                 if (ret) {
1015                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1016                                __func__);
1017                         return ret;
1018                 }
1019         }
1020
1021         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1022                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1023
1024         return 0;
1025 }
1026
1027 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1028                                      uint32_t *limit,
1029                                      bool get_default)
1030 {
1031         int ret = 0;
1032
1033         if (get_default) {
1034                 mutex_lock(&smu->mutex);
1035                 *limit = smu->default_power_limit;
1036                 if (smu->od_enabled) {
1037                         *limit *= (100 + smu->smu_table.TDPODLimit);
1038                         *limit /= 100;
1039                 }
1040                 mutex_unlock(&smu->mutex);
1041         } else {
1042                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1043                         smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
1044                 if (ret) {
1045                         pr_err("[%s] get PPT limit failed!", __func__);
1046                         return ret;
1047                 }
1048                 smu_read_smc_arg(smu, limit);
1049                 smu->power_limit = *limit;
1050         }
1051
1052         return ret;
1053 }
1054
1055 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1056 {
1057         uint32_t max_power_limit;
1058         int ret = 0;
1059
1060         if (n == 0)
1061                 n = smu->default_power_limit;
1062
1063         max_power_limit = smu->default_power_limit;
1064
1065         if (smu->od_enabled) {
1066                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1067                 max_power_limit /= 100;
1068         }
1069
1070         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1071                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1072         if (ret) {
1073                 pr_err("[%s] Set power limit Failed!", __func__);
1074                 return ret;
1075         }
1076
1077         return ret;
1078 }
1079
1080 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1081                                           enum smu_clk_type clk_id,
1082                                           uint32_t *value)
1083 {
1084         int ret = 0;
1085         uint32_t freq;
1086
1087         if (clk_id >= SMU_CLK_COUNT || !value)
1088                 return -EINVAL;
1089
1090         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1091         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
1092                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1093         else {
1094                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1095                                                   (smu_clk_get_index(smu, clk_id) << 16));
1096                 if (ret)
1097                         return ret;
1098
1099                 ret = smu_read_smc_arg(smu, &freq);
1100                 if (ret)
1101                         return ret;
1102         }
1103
1104         freq *= 100;
1105         *value = freq;
1106
1107         return ret;
1108 }
1109
1110 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1111                                        struct smu_temperature_range *range)
1112 {
1113         struct amdgpu_device *adev = smu->adev;
1114         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
1115                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1116         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
1117                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1118         uint32_t val;
1119
1120         if (!range)
1121                 return -EINVAL;
1122
1123         if (low < range->min)
1124                 low = range->min;
1125         if (high > range->max)
1126                 high = range->max;
1127
1128         if (low > high)
1129                 return -EINVAL;
1130
1131         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1132         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1133         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1134         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1135         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1136         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
1137         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
1138         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1139
1140         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1141
1142         return 0;
1143 }
1144
1145 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1146 {
1147         struct amdgpu_device *adev = smu->adev;
1148         uint32_t val = 0;
1149
1150         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1151         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1152         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1153
1154         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1155
1156         return 0;
1157 }
1158
1159 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1160 {
1161         int ret = 0;
1162         struct smu_temperature_range range = {
1163                 TEMP_RANGE_MIN,
1164                 TEMP_RANGE_MAX,
1165                 TEMP_RANGE_MAX,
1166                 TEMP_RANGE_MIN,
1167                 TEMP_RANGE_MAX,
1168                 TEMP_RANGE_MAX,
1169                 TEMP_RANGE_MIN,
1170                 TEMP_RANGE_MAX,
1171                 TEMP_RANGE_MAX};
1172         struct amdgpu_device *adev = smu->adev;
1173
1174         if (!smu->pm_enabled)
1175                 return ret;
1176         ret = smu_get_thermal_temperature_range(smu, &range);
1177
1178         if (smu->smu_table.thermal_controller_type) {
1179                 ret = smu_v11_0_set_thermal_range(smu, &range);
1180                 if (ret)
1181                         return ret;
1182
1183                 ret = smu_v11_0_enable_thermal_alert(smu);
1184                 if (ret)
1185                         return ret;
1186
1187                 ret = smu_set_thermal_fan_table(smu);
1188                 if (ret)
1189                         return ret;
1190         }
1191
1192         adev->pm.dpm.thermal.min_temp = range.min;
1193         adev->pm.dpm.thermal.max_temp = range.max;
1194         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1195         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1196         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1197         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1198         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1199         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1200         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1201
1202         return ret;
1203 }
1204
1205 static uint16_t convert_to_vddc(uint8_t vid)
1206 {
1207         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1208 }
1209
1210 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1211 {
1212         struct amdgpu_device *adev = smu->adev;
1213         uint32_t vdd = 0, val_vid = 0;
1214
1215         if (!value)
1216                 return -EINVAL;
1217         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1218                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1219                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1220
1221         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1222
1223         *value = vdd;
1224
1225         return 0;
1226
1227 }
1228
1229 static int smu_v11_0_read_sensor(struct smu_context *smu,
1230                                  enum amd_pp_sensors sensor,
1231                                  void *data, uint32_t *size)
1232 {
1233         int ret = 0;
1234         switch (sensor) {
1235         case AMDGPU_PP_SENSOR_GFX_MCLK:
1236                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1237                 *size = 4;
1238                 break;
1239         case AMDGPU_PP_SENSOR_GFX_SCLK:
1240                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1241                 *size = 4;
1242                 break;
1243         case AMDGPU_PP_SENSOR_VDDGFX:
1244                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1245                 *size = 4;
1246                 break;
1247         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1248                 *(uint32_t *)data = 0;
1249                 *size = 4;
1250                 break;
1251         default:
1252                 ret = smu_common_read_sensor(smu, sensor, data, size);
1253                 break;
1254         }
1255
1256         /* try get sensor data by asic */
1257         if (ret)
1258                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1259
1260         if (ret)
1261                 *size = 0;
1262
1263         return ret;
1264 }
1265
1266 static int
1267 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1268                                         struct pp_display_clock_request
1269                                         *clock_req)
1270 {
1271         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1272         int ret = 0;
1273         enum smu_clk_type clk_select = 0;
1274         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1275
1276         if (!smu->pm_enabled)
1277                 return -EINVAL;
1278         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1279             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1280                 switch (clk_type) {
1281                 case amd_pp_dcef_clock:
1282                         clk_select = SMU_DCEFCLK;
1283                         break;
1284                 case amd_pp_disp_clock:
1285                         clk_select = SMU_DISPCLK;
1286                         break;
1287                 case amd_pp_pixel_clock:
1288                         clk_select = SMU_PIXCLK;
1289                         break;
1290                 case amd_pp_phy_clock:
1291                         clk_select = SMU_PHYCLK;
1292                         break;
1293                 case amd_pp_mem_clock:
1294                         clk_select = SMU_UCLK;
1295                         break;
1296                 default:
1297                         pr_info("[%s] Invalid Clock Type!", __func__);
1298                         ret = -EINVAL;
1299                         break;
1300                 }
1301
1302                 if (ret)
1303                         goto failed;
1304
1305                 mutex_lock(&smu->mutex);
1306                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1307                         (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1308                 mutex_unlock(&smu->mutex);
1309         }
1310
1311 failed:
1312         return ret;
1313 }
1314
1315 static int
1316 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1317                                           dm_pp_wm_sets_with_clock_ranges_soc15
1318                                           *clock_ranges)
1319 {
1320         int ret = 0;
1321         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1322         void *table = watermarks->cpu_addr;
1323
1324         if (!smu->disable_watermark &&
1325             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1326             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1327                 smu_set_watermarks_table(smu, table, clock_ranges);
1328                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1329                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1330         }
1331
1332         return ret;
1333 }
1334
1335 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1336 {
1337         int ret = 0;
1338         struct amdgpu_device *adev = smu->adev;
1339
1340         switch (adev->asic_type) {
1341         case CHIP_VEGA20:
1342                 break;
1343         case CHIP_NAVI10:
1344                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1345                         return 0;
1346                 mutex_lock(&smu->mutex);
1347                 if (enable)
1348                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1349                 else
1350                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1351                 mutex_unlock(&smu->mutex);
1352                 break;
1353         default:
1354                 break;
1355         }
1356
1357         return ret;
1358 }
1359
1360 static int smu_v11_0_get_current_rpm(struct smu_context *smu,
1361                                      uint32_t *current_rpm)
1362 {
1363         int ret;
1364
1365         ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
1366
1367         if (ret) {
1368                 pr_err("Attempt to get current RPM from SMC Failed!\n");
1369                 return ret;
1370         }
1371
1372         smu_read_smc_arg(smu, current_rpm);
1373
1374         return 0;
1375 }
1376
1377 static uint32_t
1378 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1379 {
1380         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1381                 return AMD_FAN_CTRL_MANUAL;
1382         else
1383                 return AMD_FAN_CTRL_AUTO;
1384 }
1385
1386 static int
1387 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1388 {
1389         int ret = 0;
1390
1391         if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1392                 return 0;
1393
1394         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1395         if (ret)
1396                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1397                        __func__, (start ? "Start" : "Stop"));
1398
1399         return ret;
1400 }
1401
1402 static int
1403 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1404 {
1405         struct amdgpu_device *adev = smu->adev;
1406
1407         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1408                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1409                                    CG_FDO_CTRL2, TMIN, 0));
1410         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1411                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1412                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1413
1414         return 0;
1415 }
1416
1417 static int
1418 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1419 {
1420         struct amdgpu_device *adev = smu->adev;
1421         uint32_t duty100;
1422         uint32_t duty;
1423         uint64_t tmp64;
1424         bool stop = 0;
1425
1426         if (speed > 100)
1427                 speed = 100;
1428
1429         if (smu_v11_0_smc_fan_control(smu, stop))
1430                 return -EINVAL;
1431         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1432                                 CG_FDO_CTRL1, FMAX_DUTY100);
1433         if (!duty100)
1434                 return -EINVAL;
1435
1436         tmp64 = (uint64_t)speed * duty100;
1437         do_div(tmp64, 100);
1438         duty = (uint32_t)tmp64;
1439
1440         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1441                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1442                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1443
1444         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1445 }
1446
1447 static int
1448 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1449                                uint32_t mode)
1450 {
1451         int ret = 0;
1452         bool start = 1;
1453         bool stop  = 0;
1454
1455         switch (mode) {
1456         case AMD_FAN_CTRL_NONE:
1457                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1458                 break;
1459         case AMD_FAN_CTRL_MANUAL:
1460                 ret = smu_v11_0_smc_fan_control(smu, stop);
1461                 break;
1462         case AMD_FAN_CTRL_AUTO:
1463                 ret = smu_v11_0_smc_fan_control(smu, start);
1464                 break;
1465         default:
1466                 break;
1467         }
1468
1469         if (ret) {
1470                 pr_err("[%s]Set fan control mode failed!", __func__);
1471                 return -EINVAL;
1472         }
1473
1474         return ret;
1475 }
1476
1477 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1478                                        uint32_t speed)
1479 {
1480         struct amdgpu_device *adev = smu->adev;
1481         int ret;
1482         uint32_t tach_period, crystal_clock_freq;
1483         bool stop = 0;
1484
1485         if (!speed)
1486                 return -EINVAL;
1487
1488         mutex_lock(&(smu->mutex));
1489         ret = smu_v11_0_smc_fan_control(smu, stop);
1490         if (ret)
1491                 goto set_fan_speed_rpm_failed;
1492
1493         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1494         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1495         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1496                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1497                                    CG_TACH_CTRL, TARGET_PERIOD,
1498                                    tach_period));
1499
1500         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1501
1502 set_fan_speed_rpm_failed:
1503         mutex_unlock(&(smu->mutex));
1504         return ret;
1505 }
1506
1507 #define XGMI_STATE_D0 1
1508 #define XGMI_STATE_D3 0
1509
1510 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1511                                      uint32_t pstate)
1512 {
1513         int ret = 0;
1514         mutex_lock(&(smu->mutex));
1515         ret = smu_send_smc_msg_with_param(smu,
1516                                           SMU_MSG_SetXgmiMode,
1517                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1518         mutex_unlock(&(smu->mutex));
1519         return ret;
1520 }
1521
1522 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1523 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1524
1525 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1526                                  struct amdgpu_irq_src *source,
1527                                  struct amdgpu_iv_entry *entry)
1528 {
1529         uint32_t client_id = entry->client_id;
1530         uint32_t src_id = entry->src_id;
1531
1532         if (client_id == SOC15_IH_CLIENTID_THM) {
1533                 switch (src_id) {
1534                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1535                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1536                                 PCI_BUS_NUM(adev->pdev->devfn),
1537                                 PCI_SLOT(adev->pdev->devfn),
1538                                 PCI_FUNC(adev->pdev->devfn));
1539                 break;
1540                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1541                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1542                                 PCI_BUS_NUM(adev->pdev->devfn),
1543                                 PCI_SLOT(adev->pdev->devfn),
1544                                 PCI_FUNC(adev->pdev->devfn));
1545                 break;
1546                 default:
1547                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1548                                 src_id,
1549                                 PCI_BUS_NUM(adev->pdev->devfn),
1550                                 PCI_SLOT(adev->pdev->devfn),
1551                                 PCI_FUNC(adev->pdev->devfn));
1552                 break;
1553
1554                 }
1555         }
1556
1557         return 0;
1558 }
1559
1560 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1561 {
1562         .process = smu_v11_0_irq_process,
1563 };
1564
1565 static int smu_v11_0_register_irq_handler(struct smu_context *smu)
1566 {
1567         struct amdgpu_device *adev = smu->adev;
1568         struct amdgpu_irq_src *irq_src = smu->irq_source;
1569         int ret = 0;
1570
1571         /* already register */
1572         if (irq_src)
1573                 return 0;
1574
1575         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1576         if (!irq_src)
1577                 return -ENOMEM;
1578         smu->irq_source = irq_src;
1579
1580         irq_src->funcs = &smu_v11_0_irq_funcs;
1581
1582         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1583                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1584                                 irq_src);
1585         if (ret)
1586                 return ret;
1587
1588         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1589                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1590                                 irq_src);
1591         if (ret)
1592                 return ret;
1593
1594         return ret;
1595 }
1596
1597 static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1598 {
1599         int ret = 0;
1600
1601         mutex_lock(&smu->mutex);
1602         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1603         mutex_unlock(&smu->mutex);
1604
1605         return ret;
1606 }
1607
1608 static const struct smu_funcs smu_v11_0_funcs = {
1609         .init_microcode = smu_v11_0_init_microcode,
1610         .load_microcode = smu_v11_0_load_microcode,
1611         .check_fw_status = smu_v11_0_check_fw_status,
1612         .check_fw_version = smu_v11_0_check_fw_version,
1613         .send_smc_msg = smu_v11_0_send_msg,
1614         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1615         .read_smc_arg = smu_v11_0_read_arg,
1616         .setup_pptable = smu_v11_0_setup_pptable,
1617         .init_smc_tables = smu_v11_0_init_smc_tables,
1618         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1619         .init_power = smu_v11_0_init_power,
1620         .fini_power = smu_v11_0_fini_power,
1621         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1622         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1623         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1624         .check_pptable = smu_v11_0_check_pptable,
1625         .parse_pptable = smu_v11_0_parse_pptable,
1626         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1627         .write_pptable = smu_v11_0_write_pptable,
1628         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1629         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1630         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1631         .init_display_count = smu_v11_0_init_display_count,
1632         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1633         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1634         .system_features_control = smu_v11_0_system_features_control,
1635         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1636         .notify_display_change = smu_v11_0_notify_display_change,
1637         .get_power_limit = smu_v11_0_get_power_limit,
1638         .set_power_limit = smu_v11_0_set_power_limit,
1639         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1640         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1641         .start_thermal_control = smu_v11_0_start_thermal_control,
1642         .read_sensor = smu_v11_0_read_sensor,
1643         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1644         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1645         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1646         .get_current_rpm = smu_v11_0_get_current_rpm,
1647         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1648         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1649         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1650         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1651         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1652         .gfx_off_control = smu_v11_0_gfx_off_control,
1653         .register_irq_handler = smu_v11_0_register_irq_handler,
1654         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1655 };
1656
1657 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1658 {
1659         struct amdgpu_device *adev = smu->adev;
1660
1661         smu->funcs = &smu_v11_0_funcs;
1662         switch (adev->asic_type) {
1663         case CHIP_VEGA20:
1664                 vega20_set_ppt_funcs(smu);
1665                 break;
1666         case CHIP_NAVI10:
1667                 navi10_set_ppt_funcs(smu);
1668                 break;
1669         default:
1670                 pr_warn("Unknown asic for smu11\n");
1671         }
1672 }