drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #define SMU_11_0_PARTIAL_PPTABLE
  28
  29 #include "pp_debug.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_smu.h"
  32 #include "smu_internal.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "smu_v11_0.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amd_pcie.h"
  40 #include "amdgpu_ras.h"
  41
  42 #include "asic_reg/thm/thm_11_0_2_offset.h"
  43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_11_0_offset.h"
  45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  46 #include "asic_reg/nbio/nbio_7_4_offset.h"
  47 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  48 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  49 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  50
  51 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  52 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  53 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  54 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  55 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  56
  57 #define SMU11_VOLTAGE_SCALE 4
  58
  59 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  60                                               uint16_t msg)
  61 {
  62         struct amdgpu_device *adev = smu->adev;
  63         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  64         return 0;
  65 }
  66
  67 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  68 {
  69         struct amdgpu_device *adev = smu->adev;
  70
  71         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  72         return 0;
  73 }
  74
  75 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  76 {
  77         struct amdgpu_device *adev = smu->adev;
  78         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  79
  80         for (i = 0; i < timeout; i++) {
  81                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  82                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  83                         return cur_value == 0x1 ? 0 : -EIO;
  84
  85                 udelay(1);
  86         }
  87
  88         /* timeout means wrong logic */
  89         return -ETIME;
  90 }
  91
  92 int
  93 smu_v11_0_send_msg_with_param(struct smu_context *smu,
  94                               enum smu_message_type msg,
  95                               uint32_t param)
  96 {
  97         struct amdgpu_device *adev = smu->adev;
  98         int ret = 0, index = 0;
  99
 100         index = smu_msg_get_index(smu, msg);
 101         if (index < 0)
 102                 return index;
 103
 104         ret = smu_v11_0_wait_for_response(smu);
 105         if (ret) {
 106                 pr_err("Msg issuing pre-check failed and "
 107                        "SMU may be not in the right state!\n");
 108                 return ret;
 109         }
 110
 111         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 112
 113         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 114
 115         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 116
 117         ret = smu_v11_0_wait_for_response(smu);
 118         if (ret)
 119                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 120                        smu_get_message_name(smu, msg), index, param, ret);
 121
 122         return ret;
 123 }
 124
 125 int smu_v11_0_init_microcode(struct smu_context *smu)
 126 {
 127         struct amdgpu_device *adev = smu->adev;
 128         const char *chip_name;
 129         char fw_name[30];
 130         int err = 0;
 131         const struct smc_firmware_header_v1_0 *hdr;
 132         const struct common_firmware_header *header;
 133         struct amdgpu_firmware_info *ucode = NULL;
 134
 135         switch (adev->asic_type) {
 136         case CHIP_VEGA20:
 137                 chip_name = "vega20";
 138                 break;
 139         case CHIP_ARCTURUS:
 140                 chip_name = "arcturus";
 141                 break;
 142         case CHIP_NAVI10:
 143                 chip_name = "navi10";
 144                 break;
 145         case CHIP_NAVI14:
 146                 chip_name = "navi14";
 147                 break;
 148         case CHIP_NAVI12:
 149                 chip_name = "navi12";
 150                 break;
 151         default:
 152                 BUG();
 153         }
 154
 155         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 156
 157         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 158         if (err)
 159                 goto out;
 160         err = amdgpu_ucode_validate(adev->pm.fw);
 161         if (err)
 162                 goto out;
 163
 164         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 165         amdgpu_ucode_print_smc_hdr(&hdr->header);
 166         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 167
 168         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 169                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 170                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 171                 ucode->fw = adev->pm.fw;
 172                 header = (const struct common_firmware_header *)ucode->fw->data;
 173                 adev->firmware.fw_size +=
 174                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 175         }
 176
 177 out:
 178         if (err) {
 179                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 180                           fw_name);
 181                 release_firmware(adev->pm.fw);
 182                 adev->pm.fw = NULL;
 183         }
 184         return err;
 185 }
 186
 187 int smu_v11_0_load_microcode(struct smu_context *smu)
 188 {
 189         struct amdgpu_device *adev = smu->adev;
 190         const uint32_t *src;
 191         const struct smc_firmware_header_v1_0 *hdr;
 192         uint32_t addr_start = MP1_SRAM;
 193         uint32_t i;
 194         uint32_t mp1_fw_flags;
 195
 196         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 197         src = (const uint32_t *)(adev->pm.fw->data +
 198                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 199
 200         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 201                 WREG32_PCIE(addr_start, src[i]);
 202                 addr_start += 4;
 203         }
 204
 205         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 206                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 207         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 208                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 209
 210         for (i = 0; i < adev->usec_timeout; i++) {
 211                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 212                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 213                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 214                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 215                         break;
 216                 udelay(1);
 217         }
 218
 219         if (i == adev->usec_timeout)
 220                 return -ETIME;
 221
 222         return 0;
 223 }
 224
 225 int smu_v11_0_check_fw_status(struct smu_context *smu)
 226 {
 227         struct amdgpu_device *adev = smu->adev;
 228         uint32_t mp1_fw_flags;
 229
 230         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 231                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 232
 233         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 234             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 235                 return 0;
 236
 237         return -EIO;
 238 }
 239
 240 int smu_v11_0_check_fw_version(struct smu_context *smu)
 241 {
 242         uint32_t if_version = 0xff, smu_version = 0xff;
 243         uint16_t smu_major;
 244         uint8_t smu_minor, smu_debug;
 245         int ret = 0;
 246
 247         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 248         if (ret)
 249                 return ret;
 250
 251         smu_major = (smu_version >> 16) & 0xffff;
 252         smu_minor = (smu_version >> 8) & 0xff;
 253         smu_debug = (smu_version >> 0) & 0xff;
 254
 255         switch (smu->adev->asic_type) {
 256         case CHIP_VEGA20:
 257                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
 258                 break;
 259         case CHIP_ARCTURUS:
 260                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 261                 break;
 262         case CHIP_NAVI10:
 263                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 264                 break;
 265         case CHIP_NAVI14:
 266                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 267                 break;
 268         default:
 269                 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
 270                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
 271                 break;
 272         }
 273
 274         /*
 275          * 1. if_version mismatch is not critical as our fw is designed
 276          * to be backward compatible.
 277          * 2. New fw usually brings some optimizations. But that's visible
 278          * only on the paired driver.
 279          * Considering above, we just leave user a warning message instead
 280          * of halt driver loading.
 281          */
 282         if (if_version != smu->smc_if_version) {
 283                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 284                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 285                         smu->smc_if_version, if_version,
 286                         smu_version, smu_major, smu_minor, smu_debug);
 287                 pr_warn("SMU driver if version not matched\n");
 288         }
 289
 290         return ret;
 291 }
 292
 293 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 294 {
 295         struct amdgpu_device *adev = smu->adev;
 296         uint32_t ppt_offset_bytes;
 297         const struct smc_firmware_header_v2_0 *v2;
 298
 299         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 300
 301         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 302         *size = le32_to_cpu(v2->ppt_size_bytes);
 303         *table = (uint8_t *)v2 + ppt_offset_bytes;
 304
 305         return 0;
 306 }
 307
 308 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 309                                       uint32_t *size, uint32_t pptable_id)
 310 {
 311         struct amdgpu_device *adev = smu->adev;
 312         const struct smc_firmware_header_v2_1 *v2_1;
 313         struct smc_soft_pptable_entry *entries;
 314         uint32_t pptable_count = 0;
 315         int i = 0;
 316
 317         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 318         entries = (struct smc_soft_pptable_entry *)
 319                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 320         pptable_count = le32_to_cpu(v2_1->pptable_count);
 321         for (i = 0; i < pptable_count; i++) {
 322                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 323                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 324                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 325                         break;
 326                 }
 327         }
 328
 329         if (i == pptable_count)
 330                 return -EINVAL;
 331
 332         return 0;
 333 }
 334
 335 int smu_v11_0_setup_pptable(struct smu_context *smu)
 336 {
 337         struct amdgpu_device *adev = smu->adev;
 338         const struct smc_firmware_header_v1_0 *hdr;
 339         int ret, index;
 340         uint32_t size = 0;
 341         uint16_t atom_table_size;
 342         uint8_t frev, crev;
 343         void *table;
 344         uint16_t version_major, version_minor;
 345
 346         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 347         version_major = le16_to_cpu(hdr->header.header_version_major);
 348         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 349         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 350                 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 351                 switch (version_minor) {
 352                 case 0:
 353                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 354                         break;
 355                 case 1:
 356                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 357                                                          smu->smu_table.boot_values.pp_table_id);
 358                         break;
 359                 default:
 360                         ret = -EINVAL;
 361                         break;
 362                 }
 363                 if (ret)
 364                         return ret;
 365
 366         } else {
 367                 pr_info("use vbios provided pptable\n");
 368                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 369                                                     powerplayinfo);
 370
 371                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 372                                               (uint8_t **)&table);
 373                 if (ret)
 374                         return ret;
 375                 size = atom_table_size;
 376         }
 377
 378         if (!smu->smu_table.power_play_table)
 379                 smu->smu_table.power_play_table = table;
 380         if (!smu->smu_table.power_play_table_size)
 381                 smu->smu_table.power_play_table_size = size;
 382
 383         return 0;
 384 }
 385
 386 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 387 {
 388         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 389
 390         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 391                 return -EINVAL;
 392
 393         return smu_alloc_dpm_context(smu);
 394 }
 395
 396 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 397 {
 398         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 399
 400         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 401                 return -EINVAL;
 402
 403         kfree(smu_dpm->dpm_context);
 404         kfree(smu_dpm->golden_dpm_context);
 405         kfree(smu_dpm->dpm_current_power_state);
 406         kfree(smu_dpm->dpm_request_power_state);
 407         smu_dpm->dpm_context = NULL;
 408         smu_dpm->golden_dpm_context = NULL;
 409         smu_dpm->dpm_context_size = 0;
 410         smu_dpm->dpm_current_power_state = NULL;
 411         smu_dpm->dpm_request_power_state = NULL;
 412
 413         return 0;
 414 }
 415
 416 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 417 {
 418         struct smu_table_context *smu_table = &smu->smu_table;
 419         struct smu_table *tables = NULL;
 420         int ret = 0;
 421
 422         if (smu_table->tables)
 423                 return -EINVAL;
 424
 425         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 426                          GFP_KERNEL);
 427         if (!tables)
 428                 return -ENOMEM;
 429
 430         smu_table->tables = tables;
 431
 432         ret = smu_tables_init(smu, tables);
 433         if (ret)
 434                 return ret;
 435
 436         ret = smu_v11_0_init_dpm_context(smu);
 437         if (ret)
 438                 return ret;
 439
 440         return 0;
 441 }
 442
 443 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 444 {
 445         struct smu_table_context *smu_table = &smu->smu_table;
 446         int ret = 0;
 447
 448         if (!smu_table->tables)
 449                 return -EINVAL;
 450
 451         kfree(smu_table->tables);
 452         kfree(smu_table->metrics_table);
 453         kfree(smu_table->watermarks_table);
 454         smu_table->tables = NULL;
 455         smu_table->metrics_table = NULL;
 456         smu_table->watermarks_table = NULL;
 457         smu_table->metrics_time = 0;
 458
 459         ret = smu_v11_0_fini_dpm_context(smu);
 460         if (ret)
 461                 return ret;
 462         return 0;
 463 }
 464
 465 int smu_v11_0_init_power(struct smu_context *smu)
 466 {
 467         struct smu_power_context *smu_power = &smu->smu_power;
 468
 469         if (!smu->pm_enabled)
 470                 return 0;
 471         if (smu_power->power_context || smu_power->power_context_size != 0)
 472                 return -EINVAL;
 473
 474         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 475                                            GFP_KERNEL);
 476         if (!smu_power->power_context)
 477                 return -ENOMEM;
 478         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 479
 480         return 0;
 481 }
 482
 483 int smu_v11_0_fini_power(struct smu_context *smu)
 484 {
 485         struct smu_power_context *smu_power = &smu->smu_power;
 486
 487         if (!smu->pm_enabled)
 488                 return 0;
 489         if (!smu_power->power_context || smu_power->power_context_size == 0)
 490                 return -EINVAL;
 491
 492         kfree(smu_power->power_context);
 493         smu_power->power_context = NULL;
 494         smu_power->power_context_size = 0;
 495
 496         return 0;
 497 }
 498
 499 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 500 {
 501         int ret, index;
 502         uint16_t size;
 503         uint8_t frev, crev;
 504         struct atom_common_table_header *header;
 505         struct atom_firmware_info_v3_3 *v_3_3;
 506         struct atom_firmware_info_v3_1 *v_3_1;
 507
 508         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 509                                             firmwareinfo);
 510
 511         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 512                                       (uint8_t **)&header);
 513         if (ret)
 514                 return ret;
 515
 516         if (header->format_revision != 3) {
 517                 pr_err("unknown atom_firmware_info version! for smu11\n");
 518                 return -EINVAL;
 519         }
 520
 521         switch (header->content_revision) {
 522         case 0:
 523         case 1:
 524         case 2:
 525                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 526                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 527                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 528                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 529                 smu->smu_table.boot_values.socclk = 0;
 530                 smu->smu_table.boot_values.dcefclk = 0;
 531                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 532                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 533                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 534                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 535                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 536                 smu->smu_table.boot_values.pp_table_id = 0;
 537                 break;
 538         case 3:
 539         default:
 540                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 541                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 542                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 543                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 544                 smu->smu_table.boot_values.socclk = 0;
 545                 smu->smu_table.boot_values.dcefclk = 0;
 546                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 547                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 548                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 549                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 550                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 551                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 552         }
 553
 554         smu->smu_table.boot_values.format_revision = header->format_revision;
 555         smu->smu_table.boot_values.content_revision = header->content_revision;
 556
 557         return 0;
 558 }
 559
 560 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 561 {
 562         int ret, index;
 563         struct amdgpu_device *adev = smu->adev;
 564         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 565         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 566
 567         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 568         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 569         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 570                                             getsmuclockinfo);
 571
 572         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 573                                         (uint32_t *)&input);
 574         if (ret)
 575                 return -EINVAL;
 576
 577         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 578         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 579
 580         memset(&input, 0, sizeof(input));
 581         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 582         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 583         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 584                                             getsmuclockinfo);
 585
 586         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 587                                         (uint32_t *)&input);
 588         if (ret)
 589                 return -EINVAL;
 590
 591         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 592         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 593
 594         memset(&input, 0, sizeof(input));
 595         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 596         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 597         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 598                                             getsmuclockinfo);
 599
 600         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 601                                         (uint32_t *)&input);
 602         if (ret)
 603                 return -EINVAL;
 604
 605         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 606         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 607
 608         memset(&input, 0, sizeof(input));
 609         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 610         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 611         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 612                                             getsmuclockinfo);
 613
 614         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 615                                         (uint32_t *)&input);
 616         if (ret)
 617                 return -EINVAL;
 618
 619         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 620         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 621
 622         memset(&input, 0, sizeof(input));
 623         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 624         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 625         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 626                                             getsmuclockinfo);
 627
 628         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 629                                         (uint32_t *)&input);
 630         if (ret)
 631                 return -EINVAL;
 632
 633         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 634         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 635
 636         if ((smu->smu_table.boot_values.format_revision == 3) &&
 637             (smu->smu_table.boot_values.content_revision >= 2)) {
 638                 memset(&input, 0, sizeof(input));
 639                 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
 640                 input.syspll_id = SMU11_SYSPLL1_2_ID;
 641                 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 642                 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 643                                                     getsmuclockinfo);
 644
 645                 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 646                                                 (uint32_t *)&input);
 647                 if (ret)
 648                         return -EINVAL;
 649
 650                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 651                 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 652         }
 653
 654         return 0;
 655 }
 656
 657 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 658 {
 659         struct smu_table_context *smu_table = &smu->smu_table;
 660         struct smu_table *memory_pool = &smu_table->memory_pool;
 661         int ret = 0;
 662         uint64_t address;
 663         uint32_t address_low, address_high;
 664
 665         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 666                 return ret;
 667
 668         address = (uintptr_t)memory_pool->cpu_addr;
 669         address_high = (uint32_t)upper_32_bits(address);
 670         address_low  = (uint32_t)lower_32_bits(address);
 671
 672         ret = smu_send_smc_msg_with_param(smu,
 673                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 674                                           address_high);
 675         if (ret)
 676                 return ret;
 677         ret = smu_send_smc_msg_with_param(smu,
 678                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 679                                           address_low);
 680         if (ret)
 681                 return ret;
 682
 683         address = memory_pool->mc_address;
 684         address_high = (uint32_t)upper_32_bits(address);
 685         address_low  = (uint32_t)lower_32_bits(address);
 686
 687         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 688                                           address_high);
 689         if (ret)
 690                 return ret;
 691         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 692                                           address_low);
 693         if (ret)
 694                 return ret;
 695         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 696                                           (uint32_t)memory_pool->size);
 697         if (ret)
 698                 return ret;
 699
 700         return ret;
 701 }
 702
 703 int smu_v11_0_check_pptable(struct smu_context *smu)
 704 {
 705         int ret;
 706
 707         ret = smu_check_powerplay_table(smu);
 708         return ret;
 709 }
 710
 711 int smu_v11_0_parse_pptable(struct smu_context *smu)
 712 {
 713         int ret;
 714
 715         struct smu_table_context *table_context = &smu->smu_table;
 716         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 717
 718         if (table_context->driver_pptable)
 719                 return -EINVAL;
 720
 721         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 722
 723         if (!table_context->driver_pptable)
 724                 return -ENOMEM;
 725
 726         ret = smu_store_powerplay_table(smu);
 727         if (ret)
 728                 return -EINVAL;
 729
 730         ret = smu_append_powerplay_table(smu);
 731
 732         return ret;
 733 }
 734
 735 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 736 {
 737         int ret;
 738
 739         ret = smu_set_default_dpm_table(smu);
 740
 741         return ret;
 742 }
 743
 744 int smu_v11_0_write_pptable(struct smu_context *smu)
 745 {
 746         struct smu_table_context *table_context = &smu->smu_table;
 747         int ret = 0;
 748
 749         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 750                                table_context->driver_pptable, true);
 751
 752         return ret;
 753 }
 754
 755 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 756 {
 757         int ret;
 758
 759         ret = smu_send_smc_msg_with_param(smu,
 760                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 761         if (ret)
 762                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 763
 764         return ret;
 765 }
 766
 767 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 768 {
 769         struct smu_table_context *table_context = &smu->smu_table;
 770
 771         if (!smu->pm_enabled)
 772                 return 0;
 773         if (!table_context)
 774                 return -EINVAL;
 775
 776         return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
 777 }
 778
 779 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 780 {
 781         int ret = 0;
 782         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 783
 784         if (tool_table->mc_address) {
 785                 ret = smu_send_smc_msg_with_param(smu,
 786                                 SMU_MSG_SetToolsDramAddrHigh,
 787                                 upper_32_bits(tool_table->mc_address));
 788                 if (!ret)
 789                         ret = smu_send_smc_msg_with_param(smu,
 790                                 SMU_MSG_SetToolsDramAddrLow,
 791                                 lower_32_bits(tool_table->mc_address));
 792         }
 793
 794         return ret;
 795 }
 796
 797 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 798 {
 799         int ret = 0;
 800
 801         if (!smu->pm_enabled)
 802                 return ret;
 803
 804         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 805         return ret;
 806 }
 807
 808
 809 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 810 {
 811         struct smu_feature *feature = &smu->smu_feature;
 812         int ret = 0;
 813         uint32_t feature_mask[2];
 814
 815         mutex_lock(&feature->mutex);
 816         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 817                 goto failed;
 818
 819         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 820
 821         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 822                                           feature_mask[1]);
 823         if (ret)
 824                 goto failed;
 825
 826         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 827                                           feature_mask[0]);
 828         if (ret)
 829                 goto failed;
 830
 831 failed:
 832         mutex_unlock(&feature->mutex);
 833         return ret;
 834 }
 835
 836 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 837                                       uint32_t *feature_mask, uint32_t num)
 838 {
 839         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 840         struct smu_feature *feature = &smu->smu_feature;
 841         int ret = 0;
 842
 843         if (!feature_mask || num < 2)
 844                 return -EINVAL;
 845
 846         if (bitmap_empty(feature->enabled, feature->feature_num)) {
 847                 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 848                 if (ret)
 849                         return ret;
 850                 ret = smu_read_smc_arg(smu, &feature_mask_high);
 851                 if (ret)
 852                         return ret;
 853
 854                 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 855                 if (ret)
 856                         return ret;
 857                 ret = smu_read_smc_arg(smu, &feature_mask_low);
 858                 if (ret)
 859                         return ret;
 860
 861                 feature_mask[0] = feature_mask_low;
 862                 feature_mask[1] = feature_mask_high;
 863         } else {
 864                 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
 865                              feature->feature_num);
 866         }
 867
 868         return ret;
 869 }
 870
 871 int smu_v11_0_system_features_control(struct smu_context *smu,
 872                                              bool en)
 873 {
 874         struct smu_feature *feature = &smu->smu_feature;
 875         uint32_t feature_mask[2];
 876         int ret = 0;
 877
 878         ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 879                                      SMU_MSG_DisableAllSmuFeatures));
 880         if (ret)
 881                 return ret;
 882
 883         if (en) {
 884                 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 885                 if (ret)
 886                         return ret;
 887
 888                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 889                             feature->feature_num);
 890                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 891                             feature->feature_num);
 892         } else {
 893                 bitmap_zero(feature->enabled, feature->feature_num);
 894                 bitmap_zero(feature->supported, feature->feature_num);
 895         }
 896
 897         return ret;
 898 }
 899
 900 int smu_v11_0_notify_display_change(struct smu_context *smu)
 901 {
 902         int ret = 0;
 903
 904         if (!smu->pm_enabled)
 905                 return ret;
 906         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 907             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 908                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 909
 910         return ret;
 911 }
 912
 913 static int
 914 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 915                                     enum smu_clk_type clock_select)
 916 {
 917         int ret = 0;
 918         int clk_id;
 919
 920         if (!smu->pm_enabled)
 921                 return ret;
 922
 923         if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 924             (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
 925                 return 0;
 926
 927         clk_id = smu_clk_get_index(smu, clock_select);
 928         if (clk_id < 0)
 929                 return -EINVAL;
 930
 931         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 932                                           clk_id << 16);
 933         if (ret) {
 934                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 935                 return ret;
 936         }
 937
 938         ret = smu_read_smc_arg(smu, clock);
 939         if (ret)
 940                 return ret;
 941
 942         if (*clock != 0)
 943                 return 0;
 944
 945         /* if DC limit is zero, return AC limit */
 946         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 947                                           clk_id << 16);
 948         if (ret) {
 949                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 950                 return ret;
 951         }
 952
 953         ret = smu_read_smc_arg(smu, clock);
 954
 955         return ret;
 956 }
 957
 958 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 959 {
 960         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 961         int ret = 0;
 962
 963         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 964                                          GFP_KERNEL);
 965         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 966
 967         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 968         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 969         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 970         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 971         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 972         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 973
 974         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 975                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 976                                                           &(max_sustainable_clocks->uclock),
 977                                                           SMU_UCLK);
 978                 if (ret) {
 979                         pr_err("[%s] failed to get max UCLK from SMC!",
 980                                __func__);
 981                         return ret;
 982                 }
 983         }
 984
 985         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 986                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 987                                                           &(max_sustainable_clocks->soc_clock),
 988                                                           SMU_SOCCLK);
 989                 if (ret) {
 990                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 991                                __func__);
 992                         return ret;
 993                 }
 994         }
 995
 996         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 997                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 998                                                           &(max_sustainable_clocks->dcef_clock),
 999                                                           SMU_DCEFCLK);
1000                 if (ret) {
1001                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1002                                __func__);
1003                         return ret;
1004                 }
1005
1006                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1007                                                           &(max_sustainable_clocks->display_clock),
1008                                                           SMU_DISPCLK);
1009                 if (ret) {
1010                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1011                                __func__);
1012                         return ret;
1013                 }
1014                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1015                                                           &(max_sustainable_clocks->phy_clock),
1016                                                           SMU_PHYCLK);
1017                 if (ret) {
1018                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1019                                __func__);
1020                         return ret;
1021                 }
1022                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1023                                                           &(max_sustainable_clocks->pixel_clock),
1024                                                           SMU_PIXCLK);
1025                 if (ret) {
1026                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1027                                __func__);
1028                         return ret;
1029                 }
1030         }
1031
1032         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1033                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1034
1035         return 0;
1036 }
1037
1038 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1039         uint32_t od_limit, max_power_limit;
1040         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1041         struct smu_table_context *table_context = &smu->smu_table;
1042         powerplay_table = table_context->power_play_table;
1043
1044         max_power_limit = smu_get_pptable_power_limit(smu);
1045
1046         if (!max_power_limit) {
1047                 // If we couldn't get the table limit, fall back on first-read value
1048                 if (!smu->default_power_limit)
1049                         smu->default_power_limit = smu->power_limit;
1050                 max_power_limit = smu->default_power_limit;
1051         }
1052
1053         if (smu->od_enabled) {
1054                 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1055
1056                 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1057
1058                 max_power_limit *= (100 + od_limit);
1059                 max_power_limit /= 100;
1060         }
1061
1062         return max_power_limit;
1063 }
1064
1065 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1066 {
1067         int ret = 0;
1068         uint32_t max_power_limit;
1069
1070         max_power_limit = smu_v11_0_get_max_power_limit(smu);
1071
1072         if (n > max_power_limit) {
1073                 pr_err("New power limit (%d) is over the max allowed %d\n",
1074                                 n,
1075                                 max_power_limit);
1076                 return -EINVAL;
1077         }
1078
1079         if (n == 0)
1080                 n = smu->default_power_limit;
1081
1082         if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1083                 pr_err("Setting new power limit is not supported!\n");
1084                 return -EOPNOTSUPP;
1085         }
1086
1087         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1088         if (ret) {
1089                 pr_err("[%s] Set power limit Failed!\n", __func__);
1090                 return ret;
1091         }
1092         smu->power_limit = n;
1093
1094         return 0;
1095 }
1096
1097 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1098                                           enum smu_clk_type clk_id,
1099                                           uint32_t *value)
1100 {
1101         int ret = 0;
1102         uint32_t freq = 0;
1103         int asic_clk_id;
1104
1105         if (clk_id >= SMU_CLK_COUNT || !value)
1106                 return -EINVAL;
1107
1108         asic_clk_id = smu_clk_get_index(smu, clk_id);
1109         if (asic_clk_id < 0)
1110                 return -EINVAL;
1111
1112         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1113         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1114                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1115         else {
1116                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1117                                                   (asic_clk_id << 16));
1118                 if (ret)
1119                         return ret;
1120
1121                 ret = smu_read_smc_arg(smu, &freq);
1122                 if (ret)
1123                         return ret;
1124         }
1125
1126         freq *= 100;
1127         *value = freq;
1128
1129         return ret;
1130 }
1131
1132 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1133                                        struct smu_temperature_range range)
1134 {
1135         struct amdgpu_device *adev = smu->adev;
1136         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1137         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1138         uint32_t val;
1139
1140         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1141                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1142         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1143                         range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1144
1145         if (low > high)
1146                 return -EINVAL;
1147
1148         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1149         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1150         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1151         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1152         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1153         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1154         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1155         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1156
1157         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1158
1159         return 0;
1160 }
1161
1162 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1163 {
1164         struct amdgpu_device *adev = smu->adev;
1165         uint32_t val = 0;
1166
1167         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1168         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1169         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1170
1171         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1172
1173         return 0;
1174 }
1175
1176 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1177 {
1178         int ret = 0;
1179         struct smu_temperature_range range;
1180         struct amdgpu_device *adev = smu->adev;
1181
1182         if (!smu->pm_enabled)
1183                 return ret;
1184
1185         memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1186
1187         ret = smu_get_thermal_temperature_range(smu, &range);
1188         if (ret)
1189                 return ret;
1190
1191         if (smu->smu_table.thermal_controller_type) {
1192                 ret = smu_v11_0_set_thermal_range(smu, range);
1193                 if (ret)
1194                         return ret;
1195
1196                 ret = smu_v11_0_enable_thermal_alert(smu);
1197                 if (ret)
1198                         return ret;
1199
1200                 ret = smu_set_thermal_fan_table(smu);
1201                 if (ret)
1202                         return ret;
1203         }
1204
1205         adev->pm.dpm.thermal.min_temp = range.min;
1206         adev->pm.dpm.thermal.max_temp = range.max;
1207         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1208         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1209         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1210         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1211         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1212         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1213         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1214
1215         return ret;
1216 }
1217
1218 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1219 {
1220         struct amdgpu_device *adev = smu->adev;
1221
1222         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1223
1224         return 0;
1225 }
1226
1227 static uint16_t convert_to_vddc(uint8_t vid)
1228 {
1229         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1230 }
1231
1232 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1233 {
1234         struct amdgpu_device *adev = smu->adev;
1235         uint32_t vdd = 0, val_vid = 0;
1236
1237         if (!value)
1238                 return -EINVAL;
1239         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1240                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1241                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1242
1243         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1244
1245         *value = vdd;
1246
1247         return 0;
1248
1249 }
1250
1251 int smu_v11_0_read_sensor(struct smu_context *smu,
1252                                  enum amd_pp_sensors sensor,
1253                                  void *data, uint32_t *size)
1254 {
1255         int ret = 0;
1256
1257         if(!data || !size)
1258                 return -EINVAL;
1259
1260         switch (sensor) {
1261         case AMDGPU_PP_SENSOR_GFX_MCLK:
1262                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1263                 *size = 4;
1264                 break;
1265         case AMDGPU_PP_SENSOR_GFX_SCLK:
1266                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1267                 *size = 4;
1268                 break;
1269         case AMDGPU_PP_SENSOR_VDDGFX:
1270                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1271                 *size = 4;
1272                 break;
1273         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1274                 *(uint32_t *)data = 0;
1275                 *size = 4;
1276                 break;
1277         default:
1278                 ret = smu_common_read_sensor(smu, sensor, data, size);
1279                 break;
1280         }
1281
1282         if (ret)
1283                 *size = 0;
1284
1285         return ret;
1286 }
1287
1288 int
1289 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1290                                         struct pp_display_clock_request
1291                                         *clock_req)
1292 {
1293         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1294         int ret = 0;
1295         enum smu_clk_type clk_select = 0;
1296         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1297
1298         if (!smu->pm_enabled)
1299                 return -EINVAL;
1300
1301         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1302                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1303                 switch (clk_type) {
1304                 case amd_pp_dcef_clock:
1305                         clk_select = SMU_DCEFCLK;
1306                         break;
1307                 case amd_pp_disp_clock:
1308                         clk_select = SMU_DISPCLK;
1309                         break;
1310                 case amd_pp_pixel_clock:
1311                         clk_select = SMU_PIXCLK;
1312                         break;
1313                 case amd_pp_phy_clock:
1314                         clk_select = SMU_PHYCLK;
1315                         break;
1316                 case amd_pp_mem_clock:
1317                         clk_select = SMU_UCLK;
1318                         break;
1319                 default:
1320                         pr_info("[%s] Invalid Clock Type!", __func__);
1321                         ret = -EINVAL;
1322                         break;
1323                 }
1324
1325                 if (ret)
1326                         goto failed;
1327
1328                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1329                         return 0;
1330
1331                 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1332
1333                 if(clk_select == SMU_UCLK)
1334                         smu->hard_min_uclk_req_from_dal = clk_freq;
1335         }
1336
1337 failed:
1338         return ret;
1339 }
1340
1341 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1342 {
1343         int ret = 0;
1344         struct amdgpu_device *adev = smu->adev;
1345
1346         switch (adev->asic_type) {
1347         case CHIP_VEGA20:
1348                 break;
1349         case CHIP_NAVI10:
1350         case CHIP_NAVI14:
1351         case CHIP_NAVI12:
1352                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1353                         return 0;
1354                 if (enable)
1355                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1356                 else
1357                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1358                 break;
1359         default:
1360                 break;
1361         }
1362
1363         return ret;
1364 }
1365
1366 uint32_t
1367 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1368 {
1369         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1370                 return AMD_FAN_CTRL_MANUAL;
1371         else
1372                 return AMD_FAN_CTRL_AUTO;
1373 }
1374
1375 static int
1376 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1377 {
1378         int ret = 0;
1379
1380         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1381                 return 0;
1382
1383         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1384         if (ret)
1385                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1386                        __func__, (auto_fan_control ? "Start" : "Stop"));
1387
1388         return ret;
1389 }
1390
1391 static int
1392 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1393 {
1394         struct amdgpu_device *adev = smu->adev;
1395
1396         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1397                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1398                                    CG_FDO_CTRL2, TMIN, 0));
1399         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1400                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1401                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1402
1403         return 0;
1404 }
1405
1406 int
1407 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1408 {
1409         struct amdgpu_device *adev = smu->adev;
1410         uint32_t duty100, duty;
1411         uint64_t tmp64;
1412
1413         if (speed > 100)
1414                 speed = 100;
1415
1416         if (smu_v11_0_auto_fan_control(smu, 0))
1417                 return -EINVAL;
1418
1419         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1420                                 CG_FDO_CTRL1, FMAX_DUTY100);
1421         if (!duty100)
1422                 return -EINVAL;
1423
1424         tmp64 = (uint64_t)speed * duty100;
1425         do_div(tmp64, 100);
1426         duty = (uint32_t)tmp64;
1427
1428         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1429                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1430                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1431
1432         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1433 }
1434
1435 int
1436 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1437                                uint32_t mode)
1438 {
1439         int ret = 0;
1440
1441         switch (mode) {
1442         case AMD_FAN_CTRL_NONE:
1443                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1444                 break;
1445         case AMD_FAN_CTRL_MANUAL:
1446                 ret = smu_v11_0_auto_fan_control(smu, 0);
1447                 break;
1448         case AMD_FAN_CTRL_AUTO:
1449                 ret = smu_v11_0_auto_fan_control(smu, 1);
1450                 break;
1451         default:
1452                 break;
1453         }
1454
1455         if (ret) {
1456                 pr_err("[%s]Set fan control mode failed!", __func__);
1457                 return -EINVAL;
1458         }
1459
1460         return ret;
1461 }
1462
1463 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1464                                        uint32_t speed)
1465 {
1466         struct amdgpu_device *adev = smu->adev;
1467         int ret;
1468         uint32_t tach_period, crystal_clock_freq;
1469
1470         if (!speed)
1471                 return -EINVAL;
1472
1473         ret = smu_v11_0_auto_fan_control(smu, 0);
1474         if (ret)
1475                 return ret;
1476
1477         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1478         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1479         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1480                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1481                                    CG_TACH_CTRL, TARGET_PERIOD,
1482                                    tach_period));
1483
1484         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1485
1486         return ret;
1487 }
1488
1489 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1490                                      uint32_t pstate)
1491 {
1492         int ret = 0;
1493         ret = smu_send_smc_msg_with_param(smu,
1494                                           SMU_MSG_SetXgmiMode,
1495                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
1496         return ret;
1497 }
1498
1499 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1500 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1501
1502 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1503                                  struct amdgpu_irq_src *source,
1504                                  struct amdgpu_iv_entry *entry)
1505 {
1506         uint32_t client_id = entry->client_id;
1507         uint32_t src_id = entry->src_id;
1508
1509         if (client_id == SOC15_IH_CLIENTID_THM) {
1510                 switch (src_id) {
1511                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1512                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1513                                 PCI_BUS_NUM(adev->pdev->devfn),
1514                                 PCI_SLOT(adev->pdev->devfn),
1515                                 PCI_FUNC(adev->pdev->devfn));
1516                 break;
1517                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1518                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1519                                 PCI_BUS_NUM(adev->pdev->devfn),
1520                                 PCI_SLOT(adev->pdev->devfn),
1521                                 PCI_FUNC(adev->pdev->devfn));
1522                 break;
1523                 default:
1524                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1525                                 src_id,
1526                                 PCI_BUS_NUM(adev->pdev->devfn),
1527                                 PCI_SLOT(adev->pdev->devfn),
1528                                 PCI_FUNC(adev->pdev->devfn));
1529                 break;
1530
1531                 }
1532         }
1533
1534         return 0;
1535 }
1536
1537 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1538 {
1539         .process = smu_v11_0_irq_process,
1540 };
1541
1542 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1543 {
1544         struct amdgpu_device *adev = smu->adev;
1545         struct amdgpu_irq_src *irq_src = smu->irq_source;
1546         int ret = 0;
1547
1548         /* already register */
1549         if (irq_src)
1550                 return 0;
1551
1552         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1553         if (!irq_src)
1554                 return -ENOMEM;
1555         smu->irq_source = irq_src;
1556
1557         irq_src->funcs = &smu_v11_0_irq_funcs;
1558
1559         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1560                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1561                                 irq_src);
1562         if (ret)
1563                 return ret;
1564
1565         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1566                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1567                                 irq_src);
1568         if (ret)
1569                 return ret;
1570
1571         return ret;
1572 }
1573
1574 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1575                 struct pp_smu_nv_clock_table *max_clocks)
1576 {
1577         struct smu_table_context *table_context = &smu->smu_table;
1578         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1579
1580         if (!max_clocks || !table_context->max_sustainable_clocks)
1581                 return -EINVAL;
1582
1583         sustainable_clocks = table_context->max_sustainable_clocks;
1584
1585         max_clocks->dcfClockInKhz =
1586                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1587         max_clocks->displayClockInKhz =
1588                         (unsigned int) sustainable_clocks->display_clock * 1000;
1589         max_clocks->phyClockInKhz =
1590                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1591         max_clocks->pixelClockInKhz =
1592                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1593         max_clocks->uClockInKhz =
1594                         (unsigned int) sustainable_clocks->uclock * 1000;
1595         max_clocks->socClockInKhz =
1596                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1597         max_clocks->dscClockInKhz = 0;
1598         max_clocks->dppClockInKhz = 0;
1599         max_clocks->fabricClockInKhz = 0;
1600
1601         return 0;
1602 }
1603
1604 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1605 {
1606         int ret = 0;
1607
1608         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1609
1610         return ret;
1611 }
1612
1613 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1614 {
1615         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1616 }
1617
1618 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1619 {
1620         struct amdgpu_device *adev = smu->adev;
1621         struct smu_baco_context *smu_baco = &smu->smu_baco;
1622         uint32_t val;
1623         bool baco_support;
1624
1625         mutex_lock(&smu_baco->mutex);
1626         baco_support = smu_baco->platform_support;
1627         mutex_unlock(&smu_baco->mutex);
1628
1629         if (!baco_support)
1630                 return false;
1631
1632         /* Arcturus does not support this bit mask */
1633         if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1634            !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1635                 return false;
1636
1637         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1638         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1639                 return true;
1640
1641         return false;
1642 }
1643
1644 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1645 {
1646         struct smu_baco_context *smu_baco = &smu->smu_baco;
1647         enum smu_baco_state baco_state;
1648
1649         mutex_lock(&smu_baco->mutex);
1650         baco_state = smu_baco->state;
1651         mutex_unlock(&smu_baco->mutex);
1652
1653         return baco_state;
1654 }
1655
1656 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1657 {
1658
1659         struct smu_baco_context *smu_baco = &smu->smu_baco;
1660         struct amdgpu_device *adev = smu->adev;
1661         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1662         uint32_t bif_doorbell_intr_cntl;
1663         uint32_t data;
1664         int ret = 0;
1665
1666         if (smu_v11_0_baco_get_state(smu) == state)
1667                 return 0;
1668
1669         mutex_lock(&smu_baco->mutex);
1670
1671         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
1672
1673         if (state == SMU_BACO_STATE_ENTER) {
1674                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1675                                                 BIF_DOORBELL_INT_CNTL,
1676                                                 DOORBELL_INTERRUPT_DISABLE, 1);
1677                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1678
1679                 if (!ras || !ras->supported) {
1680                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1681                         data |= 0x80000000;
1682                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1683
1684                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0);
1685                 } else {
1686                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1);
1687                 }
1688         } else {
1689                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1690                 if (ret)
1691                         goto out;
1692
1693                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1694                                                 BIF_DOORBELL_INT_CNTL,
1695                                                 DOORBELL_INTERRUPT_DISABLE, 0);
1696                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1697
1698                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1699                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1700                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1701         }
1702         if (ret)
1703                 goto out;
1704
1705         smu_baco->state = state;
1706 out:
1707         mutex_unlock(&smu_baco->mutex);
1708         return ret;
1709 }
1710
1711 int smu_v11_0_baco_enter(struct smu_context *smu)
1712 {
1713         struct amdgpu_device *adev = smu->adev;
1714         int ret = 0;
1715
1716         /* Arcturus does not need this audio workaround */
1717         if (adev->asic_type != CHIP_ARCTURUS) {
1718                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1719                 if (ret)
1720                         return ret;
1721         }
1722
1723         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1724         if (ret)
1725                 return ret;
1726
1727         msleep(10);
1728
1729         return ret;
1730 }
1731
1732 int smu_v11_0_baco_exit(struct smu_context *smu)
1733 {
1734         int ret = 0;
1735
1736         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1737         if (ret)
1738                 return ret;
1739
1740         return ret;
1741 }
1742
1743 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1744                                                  uint32_t *min, uint32_t *max)
1745 {
1746         int ret = 0, clk_id = 0;
1747         uint32_t param = 0;
1748
1749         clk_id = smu_clk_get_index(smu, clk_type);
1750         if (clk_id < 0) {
1751                 ret = -EINVAL;
1752                 goto failed;
1753         }
1754         param = (clk_id & 0xffff) << 16;
1755
1756         if (max) {
1757                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
1758                 if (ret)
1759                         goto failed;
1760                 ret = smu_read_smc_arg(smu, max);
1761                 if (ret)
1762                         goto failed;
1763         }
1764
1765         if (min) {
1766                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
1767                 if (ret)
1768                         goto failed;
1769                 ret = smu_read_smc_arg(smu, min);
1770                 if (ret)
1771                         goto failed;
1772         }
1773
1774 failed:
1775         return ret;
1776 }
1777
1778 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1779                             uint32_t min, uint32_t max)
1780 {
1781         int ret = 0, clk_id = 0;
1782         uint32_t param;
1783
1784         clk_id = smu_clk_get_index(smu, clk_type);
1785         if (clk_id < 0)
1786                 return clk_id;
1787
1788         if (max > 0) {
1789                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1790                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1791                                                   param);
1792                 if (ret)
1793                         return ret;
1794         }
1795
1796         if (min > 0) {
1797                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1798                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1799                                                   param);
1800                 if (ret)
1801                         return ret;
1802         }
1803
1804         return ret;
1805 }
1806
1807 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1808 {
1809         struct amdgpu_device *adev = smu->adev;
1810         uint32_t pcie_gen = 0, pcie_width = 0;
1811         int ret;
1812
1813         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1814                 pcie_gen = 3;
1815         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1816                 pcie_gen = 2;
1817         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1818                 pcie_gen = 1;
1819         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1820                 pcie_gen = 0;
1821
1822         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1823          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1824          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1825          */
1826         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1827                 pcie_width = 6;
1828         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1829                 pcie_width = 5;
1830         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1831                 pcie_width = 4;
1832         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1833                 pcie_width = 3;
1834         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1835                 pcie_width = 2;
1836         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1837                 pcie_width = 1;
1838
1839         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1840
1841         if (ret)
1842                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1843
1844         return ret;
1845
1846 }
1847
1848 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1849 {
1850         struct smu_table_context *table_context = &smu->smu_table;
1851         int ret = 0;
1852
1853         if (initialize) {
1854                 if (table_context->overdrive_table) {
1855                         return -EINVAL;
1856                 }
1857                 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1858                 if (!table_context->overdrive_table) {
1859                         return -ENOMEM;
1860                 }
1861                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1862                 if (ret) {
1863                         pr_err("Failed to export overdrive table!\n");
1864                         return ret;
1865                 }
1866         }
1867         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1868         if (ret) {
1869                 pr_err("Failed to import overdrive table!\n");
1870                 return ret;
1871         }
1872         return ret;
1873 }
1874
1875 int smu_v11_0_set_performance_level(struct smu_context *smu,
1876                                     enum amd_dpm_forced_level level)
1877 {
1878         int ret = 0;
1879         uint32_t sclk_mask, mclk_mask, soc_mask;
1880
1881         switch (level) {
1882         case AMD_DPM_FORCED_LEVEL_HIGH:
1883                 ret = smu_force_dpm_limit_value(smu, true);
1884                 break;
1885         case AMD_DPM_FORCED_LEVEL_LOW:
1886                 ret = smu_force_dpm_limit_value(smu, false);
1887                 break;
1888         case AMD_DPM_FORCED_LEVEL_AUTO:
1889         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1890                 ret = smu_unforce_dpm_levels(smu);
1891                 break;
1892         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1893         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1894         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1895                 ret = smu_get_profiling_clk_mask(smu, level,
1896                                                  &sclk_mask,
1897                                                  &mclk_mask,
1898                                                  &soc_mask);
1899                 if (ret)
1900                         return ret;
1901                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1902                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1903                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1904                 break;
1905         case AMD_DPM_FORCED_LEVEL_MANUAL:
1906         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1907         default:
1908                 break;
1909         }
1910         return ret;
1911 }
1912