2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
29 #include "amdgpu_smu.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "smu_v11_0.h"
33 #include "soc15_common.h"
35 #include "vega20_ppt.h"
36 #include "arcturus_ppt.h"
37 #include "navi10_ppt.h"
39 #include "asic_reg/thm/thm_11_0_2_offset.h"
40 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
41 #include "asic_reg/mp/mp_11_0_offset.h"
42 #include "asic_reg/mp/mp_11_0_sh_mask.h"
43 #include "asic_reg/nbio/nbio_7_4_offset.h"
44 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
45 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
46 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
49 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
50 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
51 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
53 #define SMU11_VOLTAGE_SCALE 4
55 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
58 struct amdgpu_device *adev = smu->adev;
59 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
63 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
65 struct amdgpu_device *adev = smu->adev;
67 *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
71 static int smu_v11_0_wait_for_response(struct smu_context *smu)
73 struct amdgpu_device *adev = smu->adev;
74 uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
76 for (i = 0; i < timeout; i++) {
77 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
78 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
83 /* timeout means wrong logic */
87 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
90 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
92 struct amdgpu_device *adev = smu->adev;
93 int ret = 0, index = 0;
95 index = smu_msg_get_index(smu, msg);
99 smu_v11_0_wait_for_response(smu);
101 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
103 smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
105 ret = smu_v11_0_wait_for_response(smu);
108 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
116 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
120 struct amdgpu_device *adev = smu->adev;
121 int ret = 0, index = 0;
123 index = smu_msg_get_index(smu, msg);
127 ret = smu_v11_0_wait_for_response(smu);
129 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
132 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
134 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
136 smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
138 ret = smu_v11_0_wait_for_response(smu);
140 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
146 static int smu_v11_0_init_microcode(struct smu_context *smu)
148 struct amdgpu_device *adev = smu->adev;
149 const char *chip_name;
152 const struct smc_firmware_header_v1_0 *hdr;
153 const struct common_firmware_header *header;
154 struct amdgpu_firmware_info *ucode = NULL;
156 switch (adev->asic_type) {
158 chip_name = "vega20";
161 chip_name = "arcturus";
164 chip_name = "navi10";
167 chip_name = "navi14";
173 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
175 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
178 err = amdgpu_ucode_validate(adev->pm.fw);
182 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
183 amdgpu_ucode_print_smc_hdr(&hdr->header);
184 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
186 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
187 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
188 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
189 ucode->fw = adev->pm.fw;
190 header = (const struct common_firmware_header *)ucode->fw->data;
191 adev->firmware.fw_size +=
192 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
197 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
199 release_firmware(adev->pm.fw);
205 static int smu_v11_0_load_microcode(struct smu_context *smu)
207 struct amdgpu_device *adev = smu->adev;
209 const struct smc_firmware_header_v1_0 *hdr;
210 uint32_t addr_start = MP1_SRAM;
212 uint32_t mp1_fw_flags;
214 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
215 src = (const uint32_t *)(adev->pm.fw->data +
216 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
218 for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
219 WREG32_PCIE(addr_start, src[i]);
223 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
224 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
225 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
226 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
228 for (i = 0; i < adev->usec_timeout; i++) {
229 mp1_fw_flags = RREG32_PCIE(MP1_Public |
230 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
231 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
232 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
237 if (i == adev->usec_timeout)
243 static int smu_v11_0_check_fw_status(struct smu_context *smu)
245 struct amdgpu_device *adev = smu->adev;
246 uint32_t mp1_fw_flags;
248 mp1_fw_flags = RREG32_PCIE(MP1_Public |
249 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
251 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
252 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
258 static int smu_v11_0_check_fw_version(struct smu_context *smu)
260 uint32_t if_version = 0xff, smu_version = 0xff;
262 uint8_t smu_minor, smu_debug;
265 ret = smu_get_smc_version(smu, &if_version, &smu_version);
269 smu_major = (smu_version >> 16) & 0xffff;
270 smu_minor = (smu_version >> 8) & 0xff;
271 smu_debug = (smu_version >> 0) & 0xff;
274 * 1. if_version mismatch is not critical as our fw is designed
275 * to be backward compatible.
276 * 2. New fw usually brings some optimizations. But that's visible
277 * only on the paired driver.
278 * Considering above, we just leave user a warning message instead
279 * of halt driver loading.
281 if (if_version != smu->smc_if_version) {
282 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
283 "smu fw version = 0x%08x (%d.%d.%d)\n",
284 smu->smc_if_version, if_version,
285 smu_version, smu_major, smu_minor, smu_debug);
286 pr_warn("SMU driver if version not matched\n");
292 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
294 struct amdgpu_device *adev = smu->adev;
295 uint32_t ppt_offset_bytes;
296 const struct smc_firmware_header_v2_0 *v2;
298 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
300 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
301 *size = le32_to_cpu(v2->ppt_size_bytes);
302 *table = (uint8_t *)v2 + ppt_offset_bytes;
307 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
308 uint32_t *size, uint32_t pptable_id)
310 struct amdgpu_device *adev = smu->adev;
311 const struct smc_firmware_header_v2_1 *v2_1;
312 struct smc_soft_pptable_entry *entries;
313 uint32_t pptable_count = 0;
316 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
317 entries = (struct smc_soft_pptable_entry *)
318 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
319 pptable_count = le32_to_cpu(v2_1->pptable_count);
320 for (i = 0; i < pptable_count; i++) {
321 if (le32_to_cpu(entries[i].id) == pptable_id) {
322 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
323 *size = le32_to_cpu(entries[i].ppt_size_bytes);
328 if (i == pptable_count)
334 static int smu_v11_0_setup_pptable(struct smu_context *smu)
336 struct amdgpu_device *adev = smu->adev;
337 const struct smc_firmware_header_v1_0 *hdr;
342 uint16_t version_major, version_minor;
344 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
345 version_major = le16_to_cpu(hdr->header.header_version_major);
346 version_minor = le16_to_cpu(hdr->header.header_version_minor);
347 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
348 switch (version_minor) {
350 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
353 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
354 smu->smu_table.boot_values.pp_table_id);
364 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
367 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
373 if (!smu->smu_table.power_play_table)
374 smu->smu_table.power_play_table = table;
375 if (!smu->smu_table.power_play_table_size)
376 smu->smu_table.power_play_table_size = size;
381 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
383 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
385 if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
388 return smu_alloc_dpm_context(smu);
391 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
393 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
395 if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
398 kfree(smu_dpm->dpm_context);
399 kfree(smu_dpm->golden_dpm_context);
400 kfree(smu_dpm->dpm_current_power_state);
401 kfree(smu_dpm->dpm_request_power_state);
402 smu_dpm->dpm_context = NULL;
403 smu_dpm->golden_dpm_context = NULL;
404 smu_dpm->dpm_context_size = 0;
405 smu_dpm->dpm_current_power_state = NULL;
406 smu_dpm->dpm_request_power_state = NULL;
411 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
413 struct smu_table_context *smu_table = &smu->smu_table;
414 struct smu_table *tables = NULL;
417 if (smu_table->tables || smu_table->table_count == 0)
420 tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
425 smu_table->tables = tables;
427 ret = smu_tables_init(smu, tables);
431 ret = smu_v11_0_init_dpm_context(smu);
438 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
440 struct smu_table_context *smu_table = &smu->smu_table;
443 if (!smu_table->tables || smu_table->table_count == 0)
446 kfree(smu_table->tables);
447 kfree(smu_table->metrics_table);
448 smu_table->tables = NULL;
449 smu_table->table_count = 0;
450 smu_table->metrics_table = NULL;
451 smu_table->metrics_time = 0;
453 ret = smu_v11_0_fini_dpm_context(smu);
459 static int smu_v11_0_init_power(struct smu_context *smu)
461 struct smu_power_context *smu_power = &smu->smu_power;
463 if (!smu->pm_enabled)
465 if (smu_power->power_context || smu_power->power_context_size != 0)
468 smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
470 if (!smu_power->power_context)
472 smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
477 static int smu_v11_0_fini_power(struct smu_context *smu)
479 struct smu_power_context *smu_power = &smu->smu_power;
481 if (!smu->pm_enabled)
483 if (!smu_power->power_context || smu_power->power_context_size == 0)
486 kfree(smu_power->power_context);
487 smu_power->power_context = NULL;
488 smu_power->power_context_size = 0;
493 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
498 struct atom_common_table_header *header;
499 struct atom_firmware_info_v3_3 *v_3_3;
500 struct atom_firmware_info_v3_1 *v_3_1;
502 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
505 ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
506 (uint8_t **)&header);
510 if (header->format_revision != 3) {
511 pr_err("unknown atom_firmware_info version! for smu11\n");
515 switch (header->content_revision) {
519 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
520 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
521 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
522 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
523 smu->smu_table.boot_values.socclk = 0;
524 smu->smu_table.boot_values.dcefclk = 0;
525 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
526 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
527 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
528 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
529 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
530 smu->smu_table.boot_values.pp_table_id = 0;
534 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
535 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
536 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
537 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
538 smu->smu_table.boot_values.socclk = 0;
539 smu->smu_table.boot_values.dcefclk = 0;
540 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
541 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
542 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
543 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
544 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
545 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
551 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
554 struct amdgpu_device *adev = smu->adev;
555 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
556 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
558 input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
559 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
560 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
563 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
568 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
569 smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
571 memset(&input, 0, sizeof(input));
572 input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
573 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
574 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
577 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
582 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
583 smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
585 memset(&input, 0, sizeof(input));
586 input.clk_id = SMU11_SYSPLL0_ECLK_ID;
587 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
588 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
591 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
596 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
597 smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
599 memset(&input, 0, sizeof(input));
600 input.clk_id = SMU11_SYSPLL0_VCLK_ID;
601 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
602 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
605 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
610 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
611 smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
613 memset(&input, 0, sizeof(input));
614 input.clk_id = SMU11_SYSPLL0_DCLK_ID;
615 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
616 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
619 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
624 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
625 smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
630 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
632 struct smu_table_context *smu_table = &smu->smu_table;
633 struct smu_table *memory_pool = &smu_table->memory_pool;
636 uint32_t address_low, address_high;
638 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
641 address = (uintptr_t)memory_pool->cpu_addr;
642 address_high = (uint32_t)upper_32_bits(address);
643 address_low = (uint32_t)lower_32_bits(address);
645 ret = smu_send_smc_msg_with_param(smu,
646 SMU_MSG_SetSystemVirtualDramAddrHigh,
650 ret = smu_send_smc_msg_with_param(smu,
651 SMU_MSG_SetSystemVirtualDramAddrLow,
656 address = memory_pool->mc_address;
657 address_high = (uint32_t)upper_32_bits(address);
658 address_low = (uint32_t)lower_32_bits(address);
660 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
664 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
668 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
669 (uint32_t)memory_pool->size);
676 static int smu_v11_0_check_pptable(struct smu_context *smu)
680 ret = smu_check_powerplay_table(smu);
684 static int smu_v11_0_parse_pptable(struct smu_context *smu)
688 struct smu_table_context *table_context = &smu->smu_table;
689 struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
691 if (table_context->driver_pptable)
694 table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
696 if (!table_context->driver_pptable)
699 ret = smu_store_powerplay_table(smu);
703 ret = smu_append_powerplay_table(smu);
708 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
712 ret = smu_set_default_dpm_table(smu);
717 static int smu_v11_0_write_pptable(struct smu_context *smu)
719 struct smu_table_context *table_context = &smu->smu_table;
722 ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
723 table_context->driver_pptable, true);
728 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
731 struct smu_table_context *smu_table = &smu->smu_table;
732 struct smu_table *table = NULL;
734 table = &smu_table->tables[SMU_TABLE_WATERMARKS];
738 if (!table->cpu_addr)
741 ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
747 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
751 ret = smu_send_smc_msg_with_param(smu,
752 SMU_MSG_SetMinDeepSleepDcefclk, clk);
754 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
759 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
761 struct smu_table_context *table_context = &smu->smu_table;
763 if (!smu->pm_enabled)
768 return smu_set_deep_sleep_dcefclk(smu,
769 table_context->boot_values.dcefclk / 100);
772 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
775 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
777 if (tool_table->mc_address) {
778 ret = smu_send_smc_msg_with_param(smu,
779 SMU_MSG_SetToolsDramAddrHigh,
780 upper_32_bits(tool_table->mc_address));
782 ret = smu_send_smc_msg_with_param(smu,
783 SMU_MSG_SetToolsDramAddrLow,
784 lower_32_bits(tool_table->mc_address));
790 static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
794 if (!smu->pm_enabled)
797 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
801 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
803 uint32_t feature_low = 0, feature_high = 0;
806 if (!smu->pm_enabled)
808 if (feature_id >= 0 && feature_id < 31)
809 feature_low = (1 << feature_id);
810 else if (feature_id > 31 && feature_id < 63)
811 feature_high = (1 << feature_id);
816 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
820 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
826 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
830 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
840 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
842 struct smu_feature *feature = &smu->smu_feature;
844 uint32_t feature_mask[2];
846 mutex_lock(&feature->mutex);
847 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
850 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
852 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
857 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
863 mutex_unlock(&feature->mutex);
867 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
868 uint32_t *feature_mask, uint32_t num)
870 uint32_t feature_mask_high = 0, feature_mask_low = 0;
873 if (!feature_mask || num < 2)
876 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
879 ret = smu_read_smc_arg(smu, &feature_mask_high);
883 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
886 ret = smu_read_smc_arg(smu, &feature_mask_low);
890 feature_mask[0] = feature_mask_low;
891 feature_mask[1] = feature_mask_high;
896 static int smu_v11_0_system_features_control(struct smu_context *smu,
899 struct smu_feature *feature = &smu->smu_feature;
900 uint32_t feature_mask[2];
903 if (smu->pm_enabled) {
904 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
905 SMU_MSG_DisableAllSmuFeatures));
910 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
914 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
915 feature->feature_num);
916 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
917 feature->feature_num);
922 static int smu_v11_0_notify_display_change(struct smu_context *smu)
926 if (!smu->pm_enabled)
928 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
929 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
930 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
936 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
937 enum smu_clk_type clock_select)
942 if (!smu->pm_enabled)
945 clk_id = smu_clk_get_index(smu, clock_select);
949 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
952 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
956 ret = smu_read_smc_arg(smu, clock);
963 /* if DC limit is zero, return AC limit */
964 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
967 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
971 ret = smu_read_smc_arg(smu, clock);
976 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
978 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
981 max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
983 smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
985 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
986 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
987 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
988 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
989 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
990 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
992 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
993 ret = smu_v11_0_get_max_sustainable_clock(smu,
994 &(max_sustainable_clocks->uclock),
997 pr_err("[%s] failed to get max UCLK from SMC!",
1003 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1004 ret = smu_v11_0_get_max_sustainable_clock(smu,
1005 &(max_sustainable_clocks->soc_clock),
1008 pr_err("[%s] failed to get max SOCCLK from SMC!",
1014 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1015 ret = smu_v11_0_get_max_sustainable_clock(smu,
1016 &(max_sustainable_clocks->dcef_clock),
1019 pr_err("[%s] failed to get max DCEFCLK from SMC!",
1024 ret = smu_v11_0_get_max_sustainable_clock(smu,
1025 &(max_sustainable_clocks->display_clock),
1028 pr_err("[%s] failed to get max DISPCLK from SMC!",
1032 ret = smu_v11_0_get_max_sustainable_clock(smu,
1033 &(max_sustainable_clocks->phy_clock),
1036 pr_err("[%s] failed to get max PHYCLK from SMC!",
1040 ret = smu_v11_0_get_max_sustainable_clock(smu,
1041 &(max_sustainable_clocks->pixel_clock),
1044 pr_err("[%s] failed to get max PIXCLK from SMC!",
1050 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1051 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1056 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1063 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1068 mutex_lock(&smu->mutex);
1069 *limit = smu->default_power_limit;
1070 if (smu->od_enabled) {
1071 *limit *= (100 + smu->smu_table.TDPODLimit);
1074 mutex_unlock(&smu->mutex);
1076 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1079 pr_err("[%s] get PPT limit failed!", __func__);
1082 smu_read_smc_arg(smu, limit);
1083 smu->power_limit = *limit;
1089 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1091 uint32_t max_power_limit;
1095 n = smu->default_power_limit;
1097 max_power_limit = smu->default_power_limit;
1099 if (smu->od_enabled) {
1100 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1101 max_power_limit /= 100;
1104 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1105 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1107 pr_err("[%s] Set power limit Failed!", __func__);
1114 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1115 enum smu_clk_type clk_id,
1122 if (clk_id >= SMU_CLK_COUNT || !value)
1125 asic_clk_id = smu_clk_get_index(smu, clk_id);
1126 if (asic_clk_id < 0)
1129 /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1130 if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1131 ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1133 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1134 (asic_clk_id << 16));
1138 ret = smu_read_smc_arg(smu, &freq);
1149 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1150 struct smu_temperature_range *range)
1152 struct amdgpu_device *adev = smu->adev;
1153 int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
1154 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1155 int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
1156 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1162 if (low < range->min)
1164 if (high > range->max)
1170 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1171 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1172 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1173 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1174 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1175 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
1176 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
1177 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1179 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1184 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1186 struct amdgpu_device *adev = smu->adev;
1189 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1190 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1191 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1193 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1198 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1201 struct smu_temperature_range range = {
1211 struct amdgpu_device *adev = smu->adev;
1213 if (!smu->pm_enabled)
1215 ret = smu_get_thermal_temperature_range(smu, &range);
1217 if (smu->smu_table.thermal_controller_type) {
1218 ret = smu_v11_0_set_thermal_range(smu, &range);
1222 ret = smu_v11_0_enable_thermal_alert(smu);
1226 ret = smu_set_thermal_fan_table(smu);
1231 adev->pm.dpm.thermal.min_temp = range.min;
1232 adev->pm.dpm.thermal.max_temp = range.max;
1233 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1234 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1235 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1236 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1237 adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1238 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1239 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1244 static uint16_t convert_to_vddc(uint8_t vid)
1246 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1249 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1251 struct amdgpu_device *adev = smu->adev;
1252 uint32_t vdd = 0, val_vid = 0;
1256 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1257 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1258 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1260 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1268 static int smu_v11_0_read_sensor(struct smu_context *smu,
1269 enum amd_pp_sensors sensor,
1270 void *data, uint32_t *size)
1274 case AMDGPU_PP_SENSOR_GFX_MCLK:
1275 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1278 case AMDGPU_PP_SENSOR_GFX_SCLK:
1279 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1282 case AMDGPU_PP_SENSOR_VDDGFX:
1283 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1286 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1287 *(uint32_t *)data = 0;
1291 ret = smu_common_read_sensor(smu, sensor, data, size);
1295 /* try get sensor data by asic */
1297 ret = smu_asic_read_sensor(smu, sensor, data, size);
1306 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1307 struct pp_display_clock_request
1310 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1312 enum smu_clk_type clk_select = 0;
1313 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1316 if (!smu->pm_enabled)
1319 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1320 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1322 case amd_pp_dcef_clock:
1323 clk_select = SMU_DCEFCLK;
1325 case amd_pp_disp_clock:
1326 clk_select = SMU_DISPCLK;
1328 case amd_pp_pixel_clock:
1329 clk_select = SMU_PIXCLK;
1331 case amd_pp_phy_clock:
1332 clk_select = SMU_PHYCLK;
1334 case amd_pp_mem_clock:
1335 clk_select = SMU_UCLK;
1338 pr_info("[%s] Invalid Clock Type!", __func__);
1346 clk_id = smu_clk_get_index(smu, clk_select);
1352 mutex_lock(&smu->mutex);
1353 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1354 (clk_id << 16) | clk_freq);
1355 mutex_unlock(&smu->mutex);
1363 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1364 dm_pp_wm_sets_with_clock_ranges_soc15
1368 struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1369 void *table = watermarks->cpu_addr;
1371 if (!smu->disable_watermark &&
1372 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1373 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1374 smu_set_watermarks_table(smu, table, clock_ranges);
1375 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1376 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1382 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1385 struct amdgpu_device *adev = smu->adev;
1387 switch (adev->asic_type) {
1392 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1394 mutex_lock(&smu->mutex);
1396 ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1398 ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1399 mutex_unlock(&smu->mutex);
1409 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1411 if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1412 return AMD_FAN_CTRL_MANUAL;
1414 return AMD_FAN_CTRL_AUTO;
1418 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1422 if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1425 ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1427 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1428 __func__, (start ? "Start" : "Stop"));
1434 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1436 struct amdgpu_device *adev = smu->adev;
1438 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1439 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1440 CG_FDO_CTRL2, TMIN, 0));
1441 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1442 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1443 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1449 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1451 struct amdgpu_device *adev = smu->adev;
1460 if (smu_v11_0_smc_fan_control(smu, stop))
1462 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1463 CG_FDO_CTRL1, FMAX_DUTY100);
1467 tmp64 = (uint64_t)speed * duty100;
1469 duty = (uint32_t)tmp64;
1471 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1472 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1473 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1475 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1479 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1487 case AMD_FAN_CTRL_NONE:
1488 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1490 case AMD_FAN_CTRL_MANUAL:
1491 ret = smu_v11_0_smc_fan_control(smu, stop);
1493 case AMD_FAN_CTRL_AUTO:
1494 ret = smu_v11_0_smc_fan_control(smu, start);
1501 pr_err("[%s]Set fan control mode failed!", __func__);
1508 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1511 struct amdgpu_device *adev = smu->adev;
1513 uint32_t tach_period, crystal_clock_freq;
1519 mutex_lock(&(smu->mutex));
1520 ret = smu_v11_0_smc_fan_control(smu, stop);
1522 goto set_fan_speed_rpm_failed;
1524 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1525 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1526 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1527 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1528 CG_TACH_CTRL, TARGET_PERIOD,
1531 ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1533 set_fan_speed_rpm_failed:
1534 mutex_unlock(&(smu->mutex));
1538 #define XGMI_STATE_D0 1
1539 #define XGMI_STATE_D3 0
1541 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1545 mutex_lock(&(smu->mutex));
1546 ret = smu_send_smc_msg_with_param(smu,
1547 SMU_MSG_SetXgmiMode,
1548 pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1549 mutex_unlock(&(smu->mutex));
1553 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1554 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1556 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1557 struct amdgpu_irq_src *source,
1558 struct amdgpu_iv_entry *entry)
1560 uint32_t client_id = entry->client_id;
1561 uint32_t src_id = entry->src_id;
1563 if (client_id == SOC15_IH_CLIENTID_THM) {
1565 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1566 pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1567 PCI_BUS_NUM(adev->pdev->devfn),
1568 PCI_SLOT(adev->pdev->devfn),
1569 PCI_FUNC(adev->pdev->devfn));
1571 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1572 pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1573 PCI_BUS_NUM(adev->pdev->devfn),
1574 PCI_SLOT(adev->pdev->devfn),
1575 PCI_FUNC(adev->pdev->devfn));
1578 pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1580 PCI_BUS_NUM(adev->pdev->devfn),
1581 PCI_SLOT(adev->pdev->devfn),
1582 PCI_FUNC(adev->pdev->devfn));
1591 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1593 .process = smu_v11_0_irq_process,
1596 static int smu_v11_0_register_irq_handler(struct smu_context *smu)
1598 struct amdgpu_device *adev = smu->adev;
1599 struct amdgpu_irq_src *irq_src = smu->irq_source;
1602 /* already register */
1606 irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1609 smu->irq_source = irq_src;
1611 irq_src->funcs = &smu_v11_0_irq_funcs;
1613 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1614 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1619 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1620 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1628 static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1629 struct pp_smu_nv_clock_table *max_clocks)
1631 struct smu_table_context *table_context = &smu->smu_table;
1632 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1634 if (!max_clocks || !table_context->max_sustainable_clocks)
1637 sustainable_clocks = table_context->max_sustainable_clocks;
1639 max_clocks->dcfClockInKhz =
1640 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1641 max_clocks->displayClockInKhz =
1642 (unsigned int) sustainable_clocks->display_clock * 1000;
1643 max_clocks->phyClockInKhz =
1644 (unsigned int) sustainable_clocks->phy_clock * 1000;
1645 max_clocks->pixelClockInKhz =
1646 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1647 max_clocks->uClockInKhz =
1648 (unsigned int) sustainable_clocks->uclock * 1000;
1649 max_clocks->socClockInKhz =
1650 (unsigned int) sustainable_clocks->soc_clock * 1000;
1651 max_clocks->dscClockInKhz = 0;
1652 max_clocks->dppClockInKhz = 0;
1653 max_clocks->fabricClockInKhz = 0;
1658 static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1662 mutex_lock(&smu->mutex);
1663 ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1664 mutex_unlock(&smu->mutex);
1669 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1671 return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1674 static bool smu_v11_0_baco_is_support(struct smu_context *smu)
1676 struct amdgpu_device *adev = smu->adev;
1677 struct smu_baco_context *smu_baco = &smu->smu_baco;
1681 mutex_lock(&smu_baco->mutex);
1682 baco_support = smu_baco->platform_support;
1683 mutex_unlock(&smu_baco->mutex);
1688 if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1691 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1692 if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1698 static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1700 struct smu_baco_context *smu_baco = &smu->smu_baco;
1701 enum smu_baco_state baco_state = SMU_BACO_STATE_EXIT;
1703 mutex_lock(&smu_baco->mutex);
1704 baco_state = smu_baco->state;
1705 mutex_unlock(&smu_baco->mutex);
1710 static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1713 struct smu_baco_context *smu_baco = &smu->smu_baco;
1716 if (smu_v11_0_baco_get_state(smu) == state)
1719 mutex_lock(&smu_baco->mutex);
1721 if (state == SMU_BACO_STATE_ENTER)
1722 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
1724 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1728 smu_baco->state = state;
1730 mutex_unlock(&smu_baco->mutex);
1734 static int smu_v11_0_baco_reset(struct smu_context *smu)
1738 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1742 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1748 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1755 static const struct smu_funcs smu_v11_0_funcs = {
1756 .init_microcode = smu_v11_0_init_microcode,
1757 .load_microcode = smu_v11_0_load_microcode,
1758 .check_fw_status = smu_v11_0_check_fw_status,
1759 .check_fw_version = smu_v11_0_check_fw_version,
1760 .send_smc_msg = smu_v11_0_send_msg,
1761 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1762 .read_smc_arg = smu_v11_0_read_arg,
1763 .setup_pptable = smu_v11_0_setup_pptable,
1764 .init_smc_tables = smu_v11_0_init_smc_tables,
1765 .fini_smc_tables = smu_v11_0_fini_smc_tables,
1766 .init_power = smu_v11_0_init_power,
1767 .fini_power = smu_v11_0_fini_power,
1768 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1769 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1770 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1771 .check_pptable = smu_v11_0_check_pptable,
1772 .parse_pptable = smu_v11_0_parse_pptable,
1773 .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1774 .write_pptable = smu_v11_0_write_pptable,
1775 .write_watermarks_table = smu_v11_0_write_watermarks_table,
1776 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1777 .set_tool_table_location = smu_v11_0_set_tool_table_location,
1778 .init_display_count = smu_v11_0_init_display_count,
1779 .set_allowed_mask = smu_v11_0_set_allowed_mask,
1780 .get_enabled_mask = smu_v11_0_get_enabled_mask,
1781 .system_features_control = smu_v11_0_system_features_control,
1782 .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1783 .notify_display_change = smu_v11_0_notify_display_change,
1784 .get_power_limit = smu_v11_0_get_power_limit,
1785 .set_power_limit = smu_v11_0_set_power_limit,
1786 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1787 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1788 .start_thermal_control = smu_v11_0_start_thermal_control,
1789 .read_sensor = smu_v11_0_read_sensor,
1790 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1791 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1792 .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1793 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1794 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1795 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1796 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1797 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1798 .gfx_off_control = smu_v11_0_gfx_off_control,
1799 .register_irq_handler = smu_v11_0_register_irq_handler,
1800 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1801 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1802 .baco_is_support = smu_v11_0_baco_is_support,
1803 .baco_get_state = smu_v11_0_baco_get_state,
1804 .baco_set_state = smu_v11_0_baco_set_state,
1805 .baco_reset = smu_v11_0_baco_reset,
1808 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1810 struct amdgpu_device *adev = smu->adev;
1812 smu->funcs = &smu_v11_0_funcs;
1813 switch (adev->asic_type) {
1815 vega20_set_ppt_funcs(smu);
1818 arcturus_set_ppt_funcs(smu);
1822 navi10_set_ppt_funcs(smu);
1825 pr_warn("Unknown asic for smu11\n");