drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #include "pp_debug.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "vega20_ppt.h"
  36 #include "arcturus_ppt.h"
  37 #include "navi10_ppt.h"
  38
  39 #include "asic_reg/thm/thm_11_0_2_offset.h"
  40 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  41 #include "asic_reg/mp/mp_11_0_offset.h"
  42 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  43 #include "asic_reg/nbio/nbio_7_4_offset.h"
  44 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  45 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  46 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  47
  48 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  49 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  50 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  51 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  52
  53 #define SMU11_VOLTAGE_SCALE 4
  54
  55 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  56                                               uint16_t msg)
  57 {
  58         struct amdgpu_device *adev = smu->adev;
  59         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  60         return 0;
  61 }
  62
  63 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  64 {
  65         struct amdgpu_device *adev = smu->adev;
  66
  67         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  68         return 0;
  69 }
  70
  71 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  72 {
  73         struct amdgpu_device *adev = smu->adev;
  74         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  75
  76         for (i = 0; i < timeout; i++) {
  77                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  78                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  79                         break;
  80                 udelay(1);
  81         }
  82
  83         /* timeout means wrong logic */
  84         if (i == timeout)
  85                 return -ETIME;
  86
  87         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  88 }
  89
  90 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  91 {
  92         struct amdgpu_device *adev = smu->adev;
  93         int ret = 0, index = 0;
  94
  95         index = smu_msg_get_index(smu, msg);
  96         if (index < 0)
  97                 return index;
  98
  99         smu_v11_0_wait_for_response(smu);
 100
 101         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 102
 103         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 104
 105         ret = smu_v11_0_wait_for_response(smu);
 106
 107         if (ret)
 108                 pr_err("failed send message: %10s (%d) response %#x\n",
 109                        smu_get_message_name(smu, msg), index, ret);
 110
 111         return ret;
 112
 113 }
 114
 115 static int
 116 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 117                               uint32_t param)
 118 {
 119
 120         struct amdgpu_device *adev = smu->adev;
 121         int ret = 0, index = 0;
 122
 123         index = smu_msg_get_index(smu, msg);
 124         if (index < 0)
 125                 return index;
 126
 127         ret = smu_v11_0_wait_for_response(smu);
 128         if (ret)
 129                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 130                        smu_get_message_name(smu, msg), index, param, ret);
 131
 132         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 133
 134         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 135
 136         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 137
 138         ret = smu_v11_0_wait_for_response(smu);
 139         if (ret)
 140                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 141                        smu_get_message_name(smu, msg), index, param, ret);
 142
 143         return ret;
 144 }
 145
 146 static int smu_v11_0_init_microcode(struct smu_context *smu)
 147 {
 148         struct amdgpu_device *adev = smu->adev;
 149         const char *chip_name;
 150         char fw_name[30];
 151         int err = 0;
 152         const struct smc_firmware_header_v1_0 *hdr;
 153         const struct common_firmware_header *header;
 154         struct amdgpu_firmware_info *ucode = NULL;
 155
 156         switch (adev->asic_type) {
 157         case CHIP_VEGA20:
 158                 chip_name = "vega20";
 159                 break;
 160         case CHIP_ARCTURUS:
 161                 chip_name = "arcturus";
 162                 break;
 163         case CHIP_NAVI10:
 164                 chip_name = "navi10";
 165                 break;
 166         case CHIP_NAVI14:
 167                 chip_name = "navi14";
 168                 break;
 169         default:
 170                 BUG();
 171         }
 172
 173         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 174
 175         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 176         if (err)
 177                 goto out;
 178         err = amdgpu_ucode_validate(adev->pm.fw);
 179         if (err)
 180                 goto out;
 181
 182         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 183         amdgpu_ucode_print_smc_hdr(&hdr->header);
 184         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 185
 186         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 187                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 188                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 189                 ucode->fw = adev->pm.fw;
 190                 header = (const struct common_firmware_header *)ucode->fw->data;
 191                 adev->firmware.fw_size +=
 192                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 193         }
 194
 195 out:
 196         if (err) {
 197                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 198                           fw_name);
 199                 release_firmware(adev->pm.fw);
 200                 adev->pm.fw = NULL;
 201         }
 202         return err;
 203 }
 204
 205 static int smu_v11_0_load_microcode(struct smu_context *smu)
 206 {
 207         struct amdgpu_device *adev = smu->adev;
 208         const uint32_t *src;
 209         const struct smc_firmware_header_v1_0 *hdr;
 210         uint32_t addr_start = MP1_SRAM;
 211         uint32_t i;
 212         uint32_t mp1_fw_flags;
 213
 214         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 215         src = (const uint32_t *)(adev->pm.fw->data +
 216                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 217
 218         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 219                 WREG32_PCIE(addr_start, src[i]);
 220                 addr_start += 4;
 221         }
 222
 223         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 224                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 225         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 226                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 227
 228         for (i = 0; i < adev->usec_timeout; i++) {
 229                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 230                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 231                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 232                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 233                         break;
 234                 udelay(1);
 235         }
 236
 237         if (i == adev->usec_timeout)
 238                 return -ETIME;
 239
 240         return 0;
 241 }
 242
 243 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 244 {
 245         struct amdgpu_device *adev = smu->adev;
 246         uint32_t mp1_fw_flags;
 247
 248         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 249                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 250
 251         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 252             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 253                 return 0;
 254
 255         return -EIO;
 256 }
 257
 258 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 259 {
 260         uint32_t if_version = 0xff, smu_version = 0xff;
 261         uint16_t smu_major;
 262         uint8_t smu_minor, smu_debug;
 263         int ret = 0;
 264
 265         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 266         if (ret)
 267                 return ret;
 268
 269         smu_major = (smu_version >> 16) & 0xffff;
 270         smu_minor = (smu_version >> 8) & 0xff;
 271         smu_debug = (smu_version >> 0) & 0xff;
 272
 273         /*
 274          * 1. if_version mismatch is not critical as our fw is designed
 275          * to be backward compatible.
 276          * 2. New fw usually brings some optimizations. But that's visible
 277          * only on the paired driver.
 278          * Considering above, we just leave user a warning message instead
 279          * of halt driver loading.
 280          */
 281         if (if_version != smu->smc_if_version) {
 282                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 283                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 284                         smu->smc_if_version, if_version,
 285                         smu_version, smu_major, smu_minor, smu_debug);
 286                 pr_warn("SMU driver if version not matched\n");
 287         }
 288
 289         return ret;
 290 }
 291
 292 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 293 {
 294         struct amdgpu_device *adev = smu->adev;
 295         uint32_t ppt_offset_bytes;
 296         const struct smc_firmware_header_v2_0 *v2;
 297
 298         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 299
 300         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 301         *size = le32_to_cpu(v2->ppt_size_bytes);
 302         *table = (uint8_t *)v2 + ppt_offset_bytes;
 303
 304         return 0;
 305 }
 306
 307 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 308                                       uint32_t *size, uint32_t pptable_id)
 309 {
 310         struct amdgpu_device *adev = smu->adev;
 311         const struct smc_firmware_header_v2_1 *v2_1;
 312         struct smc_soft_pptable_entry *entries;
 313         uint32_t pptable_count = 0;
 314         int i = 0;
 315
 316         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 317         entries = (struct smc_soft_pptable_entry *)
 318                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 319         pptable_count = le32_to_cpu(v2_1->pptable_count);
 320         for (i = 0; i < pptable_count; i++) {
 321                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 322                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 323                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 324                         break;
 325                 }
 326         }
 327
 328         if (i == pptable_count)
 329                 return -EINVAL;
 330
 331         return 0;
 332 }
 333
 334 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 335 {
 336         struct amdgpu_device *adev = smu->adev;
 337         const struct smc_firmware_header_v1_0 *hdr;
 338         int ret, index;
 339         uint32_t size;
 340         uint8_t frev, crev;
 341         void *table;
 342         uint16_t version_major, version_minor;
 343
 344         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 345         version_major = le16_to_cpu(hdr->header.header_version_major);
 346         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 347         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 348                 switch (version_minor) {
 349                 case 0:
 350                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 351                         break;
 352                 case 1:
 353                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 354                                                          smu->smu_table.boot_values.pp_table_id);
 355                         break;
 356                 default:
 357                         ret = -EINVAL;
 358                         break;
 359                 }
 360                 if (ret)
 361                         return ret;
 362
 363         } else {
 364                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 365                                                     powerplayinfo);
 366
 367                 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
 368                                               (uint8_t **)&table);
 369                 if (ret)
 370                         return ret;
 371         }
 372
 373         if (!smu->smu_table.power_play_table)
 374                 smu->smu_table.power_play_table = table;
 375         if (!smu->smu_table.power_play_table_size)
 376                 smu->smu_table.power_play_table_size = size;
 377
 378         return 0;
 379 }
 380
 381 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 382 {
 383         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 384
 385         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 386                 return -EINVAL;
 387
 388         return smu_alloc_dpm_context(smu);
 389 }
 390
 391 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 392 {
 393         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 394
 395         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 396                 return -EINVAL;
 397
 398         kfree(smu_dpm->dpm_context);
 399         kfree(smu_dpm->golden_dpm_context);
 400         kfree(smu_dpm->dpm_current_power_state);
 401         kfree(smu_dpm->dpm_request_power_state);
 402         smu_dpm->dpm_context = NULL;
 403         smu_dpm->golden_dpm_context = NULL;
 404         smu_dpm->dpm_context_size = 0;
 405         smu_dpm->dpm_current_power_state = NULL;
 406         smu_dpm->dpm_request_power_state = NULL;
 407
 408         return 0;
 409 }
 410
 411 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 412 {
 413         struct smu_table_context *smu_table = &smu->smu_table;
 414         struct smu_table *tables = NULL;
 415         int ret = 0;
 416
 417         if (smu_table->tables || smu_table->table_count == 0)
 418                 return -EINVAL;
 419
 420         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 421                          GFP_KERNEL);
 422         if (!tables)
 423                 return -ENOMEM;
 424
 425         smu_table->tables = tables;
 426
 427         ret = smu_tables_init(smu, tables);
 428         if (ret)
 429                 return ret;
 430
 431         ret = smu_v11_0_init_dpm_context(smu);
 432         if (ret)
 433                 return ret;
 434
 435         return 0;
 436 }
 437
 438 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 439 {
 440         struct smu_table_context *smu_table = &smu->smu_table;
 441         int ret = 0;
 442
 443         if (!smu_table->tables || smu_table->table_count == 0)
 444                 return -EINVAL;
 445
 446         kfree(smu_table->tables);
 447         kfree(smu_table->metrics_table);
 448         smu_table->tables = NULL;
 449         smu_table->table_count = 0;
 450         smu_table->metrics_table = NULL;
 451         smu_table->metrics_time = 0;
 452
 453         ret = smu_v11_0_fini_dpm_context(smu);
 454         if (ret)
 455                 return ret;
 456         return 0;
 457 }
 458
 459 static int smu_v11_0_init_power(struct smu_context *smu)
 460 {
 461         struct smu_power_context *smu_power = &smu->smu_power;
 462
 463         if (!smu->pm_enabled)
 464                 return 0;
 465         if (smu_power->power_context || smu_power->power_context_size != 0)
 466                 return -EINVAL;
 467
 468         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 469                                            GFP_KERNEL);
 470         if (!smu_power->power_context)
 471                 return -ENOMEM;
 472         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 473
 474         return 0;
 475 }
 476
 477 static int smu_v11_0_fini_power(struct smu_context *smu)
 478 {
 479         struct smu_power_context *smu_power = &smu->smu_power;
 480
 481         if (!smu->pm_enabled)
 482                 return 0;
 483         if (!smu_power->power_context || smu_power->power_context_size == 0)
 484                 return -EINVAL;
 485
 486         kfree(smu_power->power_context);
 487         smu_power->power_context = NULL;
 488         smu_power->power_context_size = 0;
 489
 490         return 0;
 491 }
 492
 493 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 494 {
 495         int ret, index;
 496         uint16_t size;
 497         uint8_t frev, crev;
 498         struct atom_common_table_header *header;
 499         struct atom_firmware_info_v3_3 *v_3_3;
 500         struct atom_firmware_info_v3_1 *v_3_1;
 501
 502         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 503                                             firmwareinfo);
 504
 505         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 506                                       (uint8_t **)&header);
 507         if (ret)
 508                 return ret;
 509
 510         if (header->format_revision != 3) {
 511                 pr_err("unknown atom_firmware_info version! for smu11\n");
 512                 return -EINVAL;
 513         }
 514
 515         switch (header->content_revision) {
 516         case 0:
 517         case 1:
 518         case 2:
 519                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 520                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 521                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 522                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 523                 smu->smu_table.boot_values.socclk = 0;
 524                 smu->smu_table.boot_values.dcefclk = 0;
 525                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 526                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 527                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 528                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 529                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 530                 smu->smu_table.boot_values.pp_table_id = 0;
 531                 break;
 532         case 3:
 533         default:
 534                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 535                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 536                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 537                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 538                 smu->smu_table.boot_values.socclk = 0;
 539                 smu->smu_table.boot_values.dcefclk = 0;
 540                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 541                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 542                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 543                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 544                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 545                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 546         }
 547
 548         return 0;
 549 }
 550
 551 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 552 {
 553         int ret, index;
 554         struct amdgpu_device *adev = smu->adev;
 555         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 556         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 557
 558         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 559         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 560         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 561                                             getsmuclockinfo);
 562
 563         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 564                                         (uint32_t *)&input);
 565         if (ret)
 566                 return -EINVAL;
 567
 568         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 569         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 570
 571         memset(&input, 0, sizeof(input));
 572         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 573         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 574         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 575                                             getsmuclockinfo);
 576
 577         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 578                                         (uint32_t *)&input);
 579         if (ret)
 580                 return -EINVAL;
 581
 582         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 583         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 584
 585         memset(&input, 0, sizeof(input));
 586         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 587         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 588         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 589                                             getsmuclockinfo);
 590
 591         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 592                                         (uint32_t *)&input);
 593         if (ret)
 594                 return -EINVAL;
 595
 596         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 597         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 598
 599         memset(&input, 0, sizeof(input));
 600         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 601         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 602         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 603                                             getsmuclockinfo);
 604
 605         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 606                                         (uint32_t *)&input);
 607         if (ret)
 608                 return -EINVAL;
 609
 610         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 611         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 612
 613         memset(&input, 0, sizeof(input));
 614         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 615         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 616         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 617                                             getsmuclockinfo);
 618
 619         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 620                                         (uint32_t *)&input);
 621         if (ret)
 622                 return -EINVAL;
 623
 624         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 625         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 626
 627         return 0;
 628 }
 629
 630 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 631 {
 632         struct smu_table_context *smu_table = &smu->smu_table;
 633         struct smu_table *memory_pool = &smu_table->memory_pool;
 634         int ret = 0;
 635         uint64_t address;
 636         uint32_t address_low, address_high;
 637
 638         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 639                 return ret;
 640
 641         address = (uintptr_t)memory_pool->cpu_addr;
 642         address_high = (uint32_t)upper_32_bits(address);
 643         address_low  = (uint32_t)lower_32_bits(address);
 644
 645         ret = smu_send_smc_msg_with_param(smu,
 646                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 647                                           address_high);
 648         if (ret)
 649                 return ret;
 650         ret = smu_send_smc_msg_with_param(smu,
 651                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 652                                           address_low);
 653         if (ret)
 654                 return ret;
 655
 656         address = memory_pool->mc_address;
 657         address_high = (uint32_t)upper_32_bits(address);
 658         address_low  = (uint32_t)lower_32_bits(address);
 659
 660         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 661                                           address_high);
 662         if (ret)
 663                 return ret;
 664         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 665                                           address_low);
 666         if (ret)
 667                 return ret;
 668         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 669                                           (uint32_t)memory_pool->size);
 670         if (ret)
 671                 return ret;
 672
 673         return ret;
 674 }
 675
 676 static int smu_v11_0_check_pptable(struct smu_context *smu)
 677 {
 678         int ret;
 679
 680         ret = smu_check_powerplay_table(smu);
 681         return ret;
 682 }
 683
 684 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 685 {
 686         int ret;
 687
 688         struct smu_table_context *table_context = &smu->smu_table;
 689         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 690
 691         if (table_context->driver_pptable)
 692                 return -EINVAL;
 693
 694         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 695
 696         if (!table_context->driver_pptable)
 697                 return -ENOMEM;
 698
 699         ret = smu_store_powerplay_table(smu);
 700         if (ret)
 701                 return -EINVAL;
 702
 703         ret = smu_append_powerplay_table(smu);
 704
 705         return ret;
 706 }
 707
 708 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 709 {
 710         int ret;
 711
 712         ret = smu_set_default_dpm_table(smu);
 713
 714         return ret;
 715 }
 716
 717 static int smu_v11_0_write_pptable(struct smu_context *smu)
 718 {
 719         struct smu_table_context *table_context = &smu->smu_table;
 720         int ret = 0;
 721
 722         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 723                                table_context->driver_pptable, true);
 724
 725         return ret;
 726 }
 727
 728 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 729 {
 730         int ret = 0;
 731         struct smu_table_context *smu_table = &smu->smu_table;
 732         struct smu_table *table = NULL;
 733
 734         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
 735         if (!table)
 736                 return -EINVAL;
 737
 738         if (!table->cpu_addr)
 739                 return -EINVAL;
 740
 741         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
 742                                 true);
 743
 744         return ret;
 745 }
 746
 747 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 748 {
 749         int ret;
 750
 751         ret = smu_send_smc_msg_with_param(smu,
 752                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 753         if (ret)
 754                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 755
 756         return ret;
 757 }
 758
 759 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 760 {
 761         struct smu_table_context *table_context = &smu->smu_table;
 762
 763         if (!smu->pm_enabled)
 764                 return 0;
 765         if (!table_context)
 766                 return -EINVAL;
 767
 768         return smu_set_deep_sleep_dcefclk(smu,
 769                                           table_context->boot_values.dcefclk / 100);
 770 }
 771
 772 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 773 {
 774         int ret = 0;
 775         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 776
 777         if (tool_table->mc_address) {
 778                 ret = smu_send_smc_msg_with_param(smu,
 779                                 SMU_MSG_SetToolsDramAddrHigh,
 780                                 upper_32_bits(tool_table->mc_address));
 781                 if (!ret)
 782                         ret = smu_send_smc_msg_with_param(smu,
 783                                 SMU_MSG_SetToolsDramAddrLow,
 784                                 lower_32_bits(tool_table->mc_address));
 785         }
 786
 787         return ret;
 788 }
 789
 790 static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 791 {
 792         int ret = 0;
 793
 794         if (!smu->pm_enabled)
 795                 return ret;
 796
 797         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 798         return ret;
 799 }
 800
 801 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 802 {
 803         uint32_t feature_low = 0, feature_high = 0;
 804         int ret = 0;
 805
 806         if (!smu->pm_enabled)
 807                 return ret;
 808         if (feature_id >= 0 && feature_id < 31)
 809                 feature_low = (1 << feature_id);
 810         else if (feature_id > 31 && feature_id < 63)
 811                 feature_high = (1 << feature_id);
 812         else
 813                 return -EINVAL;
 814
 815         if (enabled) {
 816                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 817                                                   feature_low);
 818                 if (ret)
 819                         return ret;
 820                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 821                                                   feature_high);
 822                 if (ret)
 823                         return ret;
 824
 825         } else {
 826                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 827                                                   feature_low);
 828                 if (ret)
 829                         return ret;
 830                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 831                                                   feature_high);
 832                 if (ret)
 833                         return ret;
 834
 835         }
 836
 837         return ret;
 838 }
 839
 840 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 841 {
 842         struct smu_feature *feature = &smu->smu_feature;
 843         int ret = 0;
 844         uint32_t feature_mask[2];
 845
 846         mutex_lock(&feature->mutex);
 847         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 848                 goto failed;
 849
 850         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 851
 852         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 853                                           feature_mask[1]);
 854         if (ret)
 855                 goto failed;
 856
 857         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 858                                           feature_mask[0]);
 859         if (ret)
 860                 goto failed;
 861
 862 failed:
 863         mutex_unlock(&feature->mutex);
 864         return ret;
 865 }
 866
 867 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 868                                       uint32_t *feature_mask, uint32_t num)
 869 {
 870         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 871         int ret = 0;
 872
 873         if (!feature_mask || num < 2)
 874                 return -EINVAL;
 875
 876         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 877         if (ret)
 878                 return ret;
 879         ret = smu_read_smc_arg(smu, &feature_mask_high);
 880         if (ret)
 881                 return ret;
 882
 883         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 884         if (ret)
 885                 return ret;
 886         ret = smu_read_smc_arg(smu, &feature_mask_low);
 887         if (ret)
 888                 return ret;
 889
 890         feature_mask[0] = feature_mask_low;
 891         feature_mask[1] = feature_mask_high;
 892
 893         return ret;
 894 }
 895
 896 static int smu_v11_0_system_features_control(struct smu_context *smu,
 897                                              bool en)
 898 {
 899         struct smu_feature *feature = &smu->smu_feature;
 900         uint32_t feature_mask[2];
 901         int ret = 0;
 902
 903         if (smu->pm_enabled) {
 904                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 905                                              SMU_MSG_DisableAllSmuFeatures));
 906                 if (ret)
 907                         return ret;
 908         }
 909
 910         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 911         if (ret)
 912                 return ret;
 913
 914         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 915                     feature->feature_num);
 916         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 917                     feature->feature_num);
 918
 919         return ret;
 920 }
 921
 922 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 923 {
 924         int ret = 0;
 925
 926         if (!smu->pm_enabled)
 927                 return ret;
 928         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 929             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 930                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 931
 932         return ret;
 933 }
 934
 935 static int
 936 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 937                                     enum smu_clk_type clock_select)
 938 {
 939         int ret = 0;
 940         int clk_id;
 941
 942         if (!smu->pm_enabled)
 943                 return ret;
 944
 945         clk_id = smu_clk_get_index(smu, clock_select);
 946         if (clk_id < 0)
 947                 return -EINVAL;
 948
 949         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 950                                           clk_id << 16);
 951         if (ret) {
 952                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 953                 return ret;
 954         }
 955
 956         ret = smu_read_smc_arg(smu, clock);
 957         if (ret)
 958                 return ret;
 959
 960         if (*clock != 0)
 961                 return 0;
 962
 963         /* if DC limit is zero, return AC limit */
 964         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 965                                           clk_id << 16);
 966         if (ret) {
 967                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 968                 return ret;
 969         }
 970
 971         ret = smu_read_smc_arg(smu, clock);
 972
 973         return ret;
 974 }
 975
 976 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 977 {
 978         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 979         int ret = 0;
 980
 981         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 982                                          GFP_KERNEL);
 983         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 984
 985         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 986         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 987         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 988         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 989         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 990         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 991
 992         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 993                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 994                                                           &(max_sustainable_clocks->uclock),
 995                                                           SMU_UCLK);
 996                 if (ret) {
 997                         pr_err("[%s] failed to get max UCLK from SMC!",
 998                                __func__);
 999                         return ret;
1000                 }
1001         }
1002
1003         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1004                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1005                                                           &(max_sustainable_clocks->soc_clock),
1006                                                           SMU_SOCCLK);
1007                 if (ret) {
1008                         pr_err("[%s] failed to get max SOCCLK from SMC!",
1009                                __func__);
1010                         return ret;
1011                 }
1012         }
1013
1014         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1015                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1016                                                           &(max_sustainable_clocks->dcef_clock),
1017                                                           SMU_DCEFCLK);
1018                 if (ret) {
1019                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1020                                __func__);
1021                         return ret;
1022                 }
1023
1024                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1025                                                           &(max_sustainable_clocks->display_clock),
1026                                                           SMU_DISPCLK);
1027                 if (ret) {
1028                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1029                                __func__);
1030                         return ret;
1031                 }
1032                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1033                                                           &(max_sustainable_clocks->phy_clock),
1034                                                           SMU_PHYCLK);
1035                 if (ret) {
1036                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1037                                __func__);
1038                         return ret;
1039                 }
1040                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1041                                                           &(max_sustainable_clocks->pixel_clock),
1042                                                           SMU_PIXCLK);
1043                 if (ret) {
1044                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1045                                __func__);
1046                         return ret;
1047                 }
1048         }
1049
1050         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1051                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1052
1053         return 0;
1054 }
1055
1056 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1057                                      uint32_t *limit,
1058                                      bool get_default)
1059 {
1060         int ret = 0;
1061         int power_src;
1062
1063         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1064         if (power_src < 0)
1065                 return -EINVAL;
1066
1067         if (get_default) {
1068                 mutex_lock(&smu->mutex);
1069                 *limit = smu->default_power_limit;
1070                 if (smu->od_enabled) {
1071                         *limit *= (100 + smu->smu_table.TDPODLimit);
1072                         *limit /= 100;
1073                 }
1074                 mutex_unlock(&smu->mutex);
1075         } else {
1076                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1077                         power_src << 16);
1078                 if (ret) {
1079                         pr_err("[%s] get PPT limit failed!", __func__);
1080                         return ret;
1081                 }
1082                 smu_read_smc_arg(smu, limit);
1083                 smu->power_limit = *limit;
1084         }
1085
1086         return ret;
1087 }
1088
1089 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1090 {
1091         uint32_t max_power_limit;
1092         int ret = 0;
1093
1094         if (n == 0)
1095                 n = smu->default_power_limit;
1096
1097         max_power_limit = smu->default_power_limit;
1098
1099         if (smu->od_enabled) {
1100                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1101                 max_power_limit /= 100;
1102         }
1103         if (n > max_power_limit)
1104                 return -EINVAL;
1105
1106         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1107                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1108         if (ret) {
1109                 pr_err("[%s] Set power limit Failed!", __func__);
1110                 return ret;
1111         }
1112
1113         return ret;
1114 }
1115
1116 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1117                                           enum smu_clk_type clk_id,
1118                                           uint32_t *value)
1119 {
1120         int ret = 0;
1121         uint32_t freq = 0;
1122         int asic_clk_id;
1123
1124         if (clk_id >= SMU_CLK_COUNT || !value)
1125                 return -EINVAL;
1126
1127         asic_clk_id = smu_clk_get_index(smu, clk_id);
1128         if (asic_clk_id < 0)
1129                 return -EINVAL;
1130
1131         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1132         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1133                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1134         else {
1135                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1136                                                   (asic_clk_id << 16));
1137                 if (ret)
1138                         return ret;
1139
1140                 ret = smu_read_smc_arg(smu, &freq);
1141                 if (ret)
1142                         return ret;
1143         }
1144
1145         freq *= 100;
1146         *value = freq;
1147
1148         return ret;
1149 }
1150
1151 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1152                                        struct smu_temperature_range *range)
1153 {
1154         struct amdgpu_device *adev = smu->adev;
1155         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1156         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1157         uint32_t val;
1158
1159         if (!range)
1160                 return -EINVAL;
1161
1162         if (low < range->min)
1163                 low = range->min;
1164         if (high > range->max)
1165                 high = range->max;
1166
1167         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
1168         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
1169
1170         if (low > high)
1171                 return -EINVAL;
1172
1173         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1174         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1175         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1176         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1177         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1178         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1179         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1180         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1181
1182         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1183
1184         return 0;
1185 }
1186
1187 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1188 {
1189         struct amdgpu_device *adev = smu->adev;
1190         uint32_t val = 0;
1191
1192         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1193         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1194         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1195
1196         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1197
1198         return 0;
1199 }
1200
1201 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1202 {
1203         int ret = 0;
1204         struct smu_temperature_range range = {
1205                 TEMP_RANGE_MIN,
1206                 TEMP_RANGE_MAX,
1207                 TEMP_RANGE_MAX,
1208                 TEMP_RANGE_MIN,
1209                 TEMP_RANGE_MAX,
1210                 TEMP_RANGE_MAX,
1211                 TEMP_RANGE_MIN,
1212                 TEMP_RANGE_MAX,
1213                 TEMP_RANGE_MAX};
1214         struct amdgpu_device *adev = smu->adev;
1215
1216         if (!smu->pm_enabled)
1217                 return ret;
1218
1219         ret = smu_get_thermal_temperature_range(smu, &range);
1220         if (ret)
1221                 return ret;
1222
1223         if (smu->smu_table.thermal_controller_type) {
1224                 ret = smu_v11_0_set_thermal_range(smu, &range);
1225                 if (ret)
1226                         return ret;
1227
1228                 ret = smu_v11_0_enable_thermal_alert(smu);
1229                 if (ret)
1230                         return ret;
1231
1232                 ret = smu_set_thermal_fan_table(smu);
1233                 if (ret)
1234                         return ret;
1235         }
1236
1237         adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1238         adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1239         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1240         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1241         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1242         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1243         adev->pm.dpm.thermal.min_mem_temp = range.mem_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1244         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1245         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1246         adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1247         adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1248
1249         return ret;
1250 }
1251
1252 static uint16_t convert_to_vddc(uint8_t vid)
1253 {
1254         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1255 }
1256
1257 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1258 {
1259         struct amdgpu_device *adev = smu->adev;
1260         uint32_t vdd = 0, val_vid = 0;
1261
1262         if (!value)
1263                 return -EINVAL;
1264         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1265                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1266                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1267
1268         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1269
1270         *value = vdd;
1271
1272         return 0;
1273
1274 }
1275
1276 static int smu_v11_0_read_sensor(struct smu_context *smu,
1277                                  enum amd_pp_sensors sensor,
1278                                  void *data, uint32_t *size)
1279 {
1280         int ret = 0;
1281         switch (sensor) {
1282         case AMDGPU_PP_SENSOR_GFX_MCLK:
1283                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1284                 *size = 4;
1285                 break;
1286         case AMDGPU_PP_SENSOR_GFX_SCLK:
1287                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1288                 *size = 4;
1289                 break;
1290         case AMDGPU_PP_SENSOR_VDDGFX:
1291                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1292                 *size = 4;
1293                 break;
1294         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1295                 *(uint32_t *)data = 0;
1296                 *size = 4;
1297                 break;
1298         default:
1299                 ret = smu_common_read_sensor(smu, sensor, data, size);
1300                 break;
1301         }
1302
1303         /* try get sensor data by asic */
1304         if (ret)
1305                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1306
1307         if (ret)
1308                 *size = 0;
1309
1310         return ret;
1311 }
1312
1313 static int
1314 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1315                                         struct pp_display_clock_request
1316                                         *clock_req)
1317 {
1318         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1319         int ret = 0;
1320         enum smu_clk_type clk_select = 0;
1321         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1322         int clk_id;
1323
1324         if (!smu->pm_enabled)
1325                 return -EINVAL;
1326
1327         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1328                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1329                 switch (clk_type) {
1330                 case amd_pp_dcef_clock:
1331                         clk_select = SMU_DCEFCLK;
1332                         break;
1333                 case amd_pp_disp_clock:
1334                         clk_select = SMU_DISPCLK;
1335                         break;
1336                 case amd_pp_pixel_clock:
1337                         clk_select = SMU_PIXCLK;
1338                         break;
1339                 case amd_pp_phy_clock:
1340                         clk_select = SMU_PHYCLK;
1341                         break;
1342                 case amd_pp_mem_clock:
1343                         clk_select = SMU_UCLK;
1344                         break;
1345                 default:
1346                         pr_info("[%s] Invalid Clock Type!", __func__);
1347                         ret = -EINVAL;
1348                         break;
1349                 }
1350
1351                 if (ret)
1352                         goto failed;
1353
1354                 clk_id = smu_clk_get_index(smu, clk_select);
1355                 if (clk_id < 0) {
1356                         ret = -EINVAL;
1357                         goto failed;
1358                 }
1359
1360                 mutex_lock(&smu->mutex);
1361                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1362                         (clk_id << 16) | clk_freq);
1363                 mutex_unlock(&smu->mutex);
1364         }
1365
1366 failed:
1367         return ret;
1368 }
1369
1370 static int
1371 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1372                                           dm_pp_wm_sets_with_clock_ranges_soc15
1373                                           *clock_ranges)
1374 {
1375         int ret = 0;
1376         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1377         void *table = watermarks->cpu_addr;
1378
1379         if (!smu->disable_watermark &&
1380             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1381             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1382                 smu_set_watermarks_table(smu, table, clock_ranges);
1383                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1384                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1385         }
1386
1387         return ret;
1388 }
1389
1390 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1391 {
1392         int ret = 0;
1393         struct amdgpu_device *adev = smu->adev;
1394
1395         switch (adev->asic_type) {
1396         case CHIP_VEGA20:
1397                 break;
1398         case CHIP_NAVI10:
1399         case CHIP_NAVI14:
1400                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1401                         return 0;
1402                 mutex_lock(&smu->mutex);
1403                 if (enable)
1404                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1405                 else
1406                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1407                 mutex_unlock(&smu->mutex);
1408                 break;
1409         default:
1410                 break;
1411         }
1412
1413         return ret;
1414 }
1415
1416 static uint32_t
1417 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1418 {
1419         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1420                 return AMD_FAN_CTRL_MANUAL;
1421         else
1422                 return AMD_FAN_CTRL_AUTO;
1423 }
1424
1425 static int
1426 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1427 {
1428         int ret = 0;
1429
1430         if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1431                 return 0;
1432
1433         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1434         if (ret)
1435                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1436                        __func__, (auto_fan_control ? "Start" : "Stop"));
1437
1438         return ret;
1439 }
1440
1441 static int
1442 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1443 {
1444         struct amdgpu_device *adev = smu->adev;
1445
1446         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1447                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1448                                    CG_FDO_CTRL2, TMIN, 0));
1449         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1450                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1451                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1452
1453         return 0;
1454 }
1455
1456 static int
1457 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1458 {
1459         struct amdgpu_device *adev = smu->adev;
1460         uint32_t duty100, duty;
1461         uint64_t tmp64;
1462
1463         if (speed > 100)
1464                 speed = 100;
1465
1466         if (smu_v11_0_auto_fan_control(smu, 0))
1467                 return -EINVAL;
1468
1469         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1470                                 CG_FDO_CTRL1, FMAX_DUTY100);
1471         if (!duty100)
1472                 return -EINVAL;
1473
1474         tmp64 = (uint64_t)speed * duty100;
1475         do_div(tmp64, 100);
1476         duty = (uint32_t)tmp64;
1477
1478         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1479                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1480                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1481
1482         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1483 }
1484
1485 static int
1486 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1487                                uint32_t mode)
1488 {
1489         int ret = 0;
1490
1491         switch (mode) {
1492         case AMD_FAN_CTRL_NONE:
1493                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1494                 break;
1495         case AMD_FAN_CTRL_MANUAL:
1496                 ret = smu_v11_0_auto_fan_control(smu, 0);
1497                 break;
1498         case AMD_FAN_CTRL_AUTO:
1499                 ret = smu_v11_0_auto_fan_control(smu, 1);
1500                 break;
1501         default:
1502                 break;
1503         }
1504
1505         if (ret) {
1506                 pr_err("[%s]Set fan control mode failed!", __func__);
1507                 return -EINVAL;
1508         }
1509
1510         return ret;
1511 }
1512
1513 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1514                                        uint32_t speed)
1515 {
1516         struct amdgpu_device *adev = smu->adev;
1517         int ret;
1518         uint32_t tach_period, crystal_clock_freq;
1519
1520         if (!speed)
1521                 return -EINVAL;
1522
1523         mutex_lock(&(smu->mutex));
1524         ret = smu_v11_0_auto_fan_control(smu, 0);
1525         if (ret)
1526                 goto set_fan_speed_rpm_failed;
1527
1528         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1529         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1530         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1531                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1532                                    CG_TACH_CTRL, TARGET_PERIOD,
1533                                    tach_period));
1534
1535         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1536
1537 set_fan_speed_rpm_failed:
1538         mutex_unlock(&(smu->mutex));
1539         return ret;
1540 }
1541
1542 #define XGMI_STATE_D0 1
1543 #define XGMI_STATE_D3 0
1544
1545 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1546                                      uint32_t pstate)
1547 {
1548         int ret = 0;
1549         mutex_lock(&(smu->mutex));
1550         ret = smu_send_smc_msg_with_param(smu,
1551                                           SMU_MSG_SetXgmiMode,
1552                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1553         mutex_unlock(&(smu->mutex));
1554         return ret;
1555 }
1556
1557 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1558 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1559
1560 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1561                                  struct amdgpu_irq_src *source,
1562                                  struct amdgpu_iv_entry *entry)
1563 {
1564         uint32_t client_id = entry->client_id;
1565         uint32_t src_id = entry->src_id;
1566
1567         if (client_id == SOC15_IH_CLIENTID_THM) {
1568                 switch (src_id) {
1569                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1570                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1571                                 PCI_BUS_NUM(adev->pdev->devfn),
1572                                 PCI_SLOT(adev->pdev->devfn),
1573                                 PCI_FUNC(adev->pdev->devfn));
1574                 break;
1575                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1576                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1577                                 PCI_BUS_NUM(adev->pdev->devfn),
1578                                 PCI_SLOT(adev->pdev->devfn),
1579                                 PCI_FUNC(adev->pdev->devfn));
1580                 break;
1581                 default:
1582                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1583                                 src_id,
1584                                 PCI_BUS_NUM(adev->pdev->devfn),
1585                                 PCI_SLOT(adev->pdev->devfn),
1586                                 PCI_FUNC(adev->pdev->devfn));
1587                 break;
1588
1589                 }
1590         }
1591
1592         return 0;
1593 }
1594
1595 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1596 {
1597         .process = smu_v11_0_irq_process,
1598 };
1599
1600 static int smu_v11_0_register_irq_handler(struct smu_context *smu)
1601 {
1602         struct amdgpu_device *adev = smu->adev;
1603         struct amdgpu_irq_src *irq_src = smu->irq_source;
1604         int ret = 0;
1605
1606         /* already register */
1607         if (irq_src)
1608                 return 0;
1609
1610         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1611         if (!irq_src)
1612                 return -ENOMEM;
1613         smu->irq_source = irq_src;
1614
1615         irq_src->funcs = &smu_v11_0_irq_funcs;
1616
1617         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1618                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1619                                 irq_src);
1620         if (ret)
1621                 return ret;
1622
1623         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1624                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1625                                 irq_src);
1626         if (ret)
1627                 return ret;
1628
1629         return ret;
1630 }
1631
1632 static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1633                 struct pp_smu_nv_clock_table *max_clocks)
1634 {
1635         struct smu_table_context *table_context = &smu->smu_table;
1636         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1637
1638         if (!max_clocks || !table_context->max_sustainable_clocks)
1639                 return -EINVAL;
1640
1641         sustainable_clocks = table_context->max_sustainable_clocks;
1642
1643         max_clocks->dcfClockInKhz =
1644                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1645         max_clocks->displayClockInKhz =
1646                         (unsigned int) sustainable_clocks->display_clock * 1000;
1647         max_clocks->phyClockInKhz =
1648                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1649         max_clocks->pixelClockInKhz =
1650                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1651         max_clocks->uClockInKhz =
1652                         (unsigned int) sustainable_clocks->uclock * 1000;
1653         max_clocks->socClockInKhz =
1654                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1655         max_clocks->dscClockInKhz = 0;
1656         max_clocks->dppClockInKhz = 0;
1657         max_clocks->fabricClockInKhz = 0;
1658
1659         return 0;
1660 }
1661
1662 static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1663 {
1664         int ret = 0;
1665
1666         mutex_lock(&smu->mutex);
1667         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1668         mutex_unlock(&smu->mutex);
1669
1670         return ret;
1671 }
1672
1673 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1674 {
1675         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1676 }
1677
1678 static bool smu_v11_0_baco_is_support(struct smu_context *smu)
1679 {
1680         struct amdgpu_device *adev = smu->adev;
1681         struct smu_baco_context *smu_baco = &smu->smu_baco;
1682         uint32_t val;
1683         bool baco_support;
1684
1685         mutex_lock(&smu_baco->mutex);
1686         baco_support = smu_baco->platform_support;
1687         mutex_unlock(&smu_baco->mutex);
1688
1689         if (!baco_support)
1690                 return false;
1691
1692         if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1693                 return false;
1694
1695         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1696         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1697                 return true;
1698
1699         return false;
1700 }
1701
1702 static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1703 {
1704         struct smu_baco_context *smu_baco = &smu->smu_baco;
1705         enum smu_baco_state baco_state = SMU_BACO_STATE_EXIT;
1706
1707         mutex_lock(&smu_baco->mutex);
1708         baco_state = smu_baco->state;
1709         mutex_unlock(&smu_baco->mutex);
1710
1711         return baco_state;
1712 }
1713
1714 static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1715 {
1716
1717         struct smu_baco_context *smu_baco = &smu->smu_baco;
1718         int ret = 0;
1719
1720         if (smu_v11_0_baco_get_state(smu) == state)
1721                 return 0;
1722
1723         mutex_lock(&smu_baco->mutex);
1724
1725         if (state == SMU_BACO_STATE_ENTER)
1726                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
1727         else
1728                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1729         if (ret)
1730                 goto out;
1731
1732         smu_baco->state = state;
1733 out:
1734         mutex_unlock(&smu_baco->mutex);
1735         return ret;
1736 }
1737
1738 static int smu_v11_0_baco_reset(struct smu_context *smu)
1739 {
1740         int ret = 0;
1741
1742         ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1743         if (ret)
1744                 return ret;
1745
1746         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1747         if (ret)
1748                 return ret;
1749
1750         msleep(10);
1751
1752         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1753         if (ret)
1754                 return ret;
1755
1756         return ret;
1757 }
1758
1759 static const struct smu_funcs smu_v11_0_funcs = {
1760         .init_microcode = smu_v11_0_init_microcode,
1761         .load_microcode = smu_v11_0_load_microcode,
1762         .check_fw_status = smu_v11_0_check_fw_status,
1763         .check_fw_version = smu_v11_0_check_fw_version,
1764         .send_smc_msg = smu_v11_0_send_msg,
1765         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1766         .read_smc_arg = smu_v11_0_read_arg,
1767         .setup_pptable = smu_v11_0_setup_pptable,
1768         .init_smc_tables = smu_v11_0_init_smc_tables,
1769         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1770         .init_power = smu_v11_0_init_power,
1771         .fini_power = smu_v11_0_fini_power,
1772         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1773         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1774         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1775         .check_pptable = smu_v11_0_check_pptable,
1776         .parse_pptable = smu_v11_0_parse_pptable,
1777         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1778         .write_pptable = smu_v11_0_write_pptable,
1779         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1780         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1781         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1782         .init_display_count = smu_v11_0_init_display_count,
1783         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1784         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1785         .system_features_control = smu_v11_0_system_features_control,
1786         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1787         .notify_display_change = smu_v11_0_notify_display_change,
1788         .get_power_limit = smu_v11_0_get_power_limit,
1789         .set_power_limit = smu_v11_0_set_power_limit,
1790         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1791         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1792         .start_thermal_control = smu_v11_0_start_thermal_control,
1793         .read_sensor = smu_v11_0_read_sensor,
1794         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1795         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1796         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1797         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1798         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1799         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1800         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1801         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1802         .gfx_off_control = smu_v11_0_gfx_off_control,
1803         .register_irq_handler = smu_v11_0_register_irq_handler,
1804         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1805         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1806         .baco_is_support = smu_v11_0_baco_is_support,
1807         .baco_get_state = smu_v11_0_baco_get_state,
1808         .baco_set_state = smu_v11_0_baco_set_state,
1809         .baco_reset = smu_v11_0_baco_reset,
1810 };
1811
1812 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1813 {
1814         struct amdgpu_device *adev = smu->adev;
1815
1816         smu->funcs = &smu_v11_0_funcs;
1817         switch (adev->asic_type) {
1818         case CHIP_VEGA20:
1819                 vega20_set_ppt_funcs(smu);
1820                 break;
1821         case CHIP_ARCTURUS:
1822                 arcturus_set_ppt_funcs(smu);
1823                 break;
1824         case CHIP_NAVI10:
1825         case CHIP_NAVI14:
1826                 navi10_set_ppt_funcs(smu);
1827                 break;
1828         default:
1829                 pr_warn("Unknown asic for smu11\n");
1830         }
1831 }