drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #include "pp_debug.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "smu_v11_0.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "vega20_ppt.h"
  37 #include "arcturus_ppt.h"
  38 #include "navi10_ppt.h"
  39 #include "amd_pcie.h"
  40
  41 #include "asic_reg/thm/thm_11_0_2_offset.h"
  42 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  43 #include "asic_reg/mp/mp_11_0_offset.h"
  44 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  45 #include "asic_reg/nbio/nbio_7_4_offset.h"
  46 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  48 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  49
  50 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  51 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  52 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  53 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  54 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  55
  56 #define SMU11_VOLTAGE_SCALE 4
  57
  58 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  59                                               uint16_t msg)
  60 {
  61         struct amdgpu_device *adev = smu->adev;
  62         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  63         return 0;
  64 }
  65
  66 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  67 {
  68         struct amdgpu_device *adev = smu->adev;
  69
  70         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  71         return 0;
  72 }
  73
  74 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  75 {
  76         struct amdgpu_device *adev = smu->adev;
  77         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  78
  79         for (i = 0; i < timeout; i++) {
  80                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  81                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  82                         break;
  83                 udelay(1);
  84         }
  85
  86         /* timeout means wrong logic */
  87         if (i == timeout)
  88                 return -ETIME;
  89
  90         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  91 }
  92
  93 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  94 {
  95         struct amdgpu_device *adev = smu->adev;
  96         int ret = 0, index = 0;
  97
  98         index = smu_msg_get_index(smu, msg);
  99         if (index < 0)
 100                 return index;
 101
 102         smu_v11_0_wait_for_response(smu);
 103
 104         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 105
 106         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 107
 108         ret = smu_v11_0_wait_for_response(smu);
 109
 110         if (ret)
 111                 pr_err("failed send message: %10s (%d) response %#x\n",
 112                        smu_get_message_name(smu, msg), index, ret);
 113
 114         return ret;
 115
 116 }
 117
 118 static int
 119 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 120                               uint32_t param)
 121 {
 122
 123         struct amdgpu_device *adev = smu->adev;
 124         int ret = 0, index = 0;
 125
 126         index = smu_msg_get_index(smu, msg);
 127         if (index < 0)
 128                 return index;
 129
 130         ret = smu_v11_0_wait_for_response(smu);
 131         if (ret)
 132                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 133                        smu_get_message_name(smu, msg), index, param, ret);
 134
 135         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 136
 137         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 138
 139         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 140
 141         ret = smu_v11_0_wait_for_response(smu);
 142         if (ret)
 143                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 144                        smu_get_message_name(smu, msg), index, param, ret);
 145
 146         return ret;
 147 }
 148
 149 static int smu_v11_0_init_microcode(struct smu_context *smu)
 150 {
 151         struct amdgpu_device *adev = smu->adev;
 152         const char *chip_name;
 153         char fw_name[30];
 154         int err = 0;
 155         const struct smc_firmware_header_v1_0 *hdr;
 156         const struct common_firmware_header *header;
 157         struct amdgpu_firmware_info *ucode = NULL;
 158
 159         switch (adev->asic_type) {
 160         case CHIP_VEGA20:
 161                 chip_name = "vega20";
 162                 break;
 163         case CHIP_ARCTURUS:
 164                 chip_name = "arcturus";
 165                 break;
 166         case CHIP_NAVI10:
 167                 chip_name = "navi10";
 168                 break;
 169         case CHIP_NAVI14:
 170                 chip_name = "navi14";
 171                 break;
 172         case CHIP_NAVI12:
 173                 chip_name = "navi12";
 174                 break;
 175         default:
 176                 BUG();
 177         }
 178
 179         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 180
 181         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 182         if (err)
 183                 goto out;
 184         err = amdgpu_ucode_validate(adev->pm.fw);
 185         if (err)
 186                 goto out;
 187
 188         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 189         amdgpu_ucode_print_smc_hdr(&hdr->header);
 190         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 191
 192         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 193                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 194                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 195                 ucode->fw = adev->pm.fw;
 196                 header = (const struct common_firmware_header *)ucode->fw->data;
 197                 adev->firmware.fw_size +=
 198                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 199         }
 200
 201 out:
 202         if (err) {
 203                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 204                           fw_name);
 205                 release_firmware(adev->pm.fw);
 206                 adev->pm.fw = NULL;
 207         }
 208         return err;
 209 }
 210
 211 static int smu_v11_0_load_microcode(struct smu_context *smu)
 212 {
 213         struct amdgpu_device *adev = smu->adev;
 214         const uint32_t *src;
 215         const struct smc_firmware_header_v1_0 *hdr;
 216         uint32_t addr_start = MP1_SRAM;
 217         uint32_t i;
 218         uint32_t mp1_fw_flags;
 219
 220         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 221         src = (const uint32_t *)(adev->pm.fw->data +
 222                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 223
 224         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 225                 WREG32_PCIE(addr_start, src[i]);
 226                 addr_start += 4;
 227         }
 228
 229         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 230                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 231         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 232                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 233
 234         for (i = 0; i < adev->usec_timeout; i++) {
 235                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 236                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 237                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 238                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 239                         break;
 240                 udelay(1);
 241         }
 242
 243         if (i == adev->usec_timeout)
 244                 return -ETIME;
 245
 246         return 0;
 247 }
 248
 249 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 250 {
 251         struct amdgpu_device *adev = smu->adev;
 252         uint32_t mp1_fw_flags;
 253
 254         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 255                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 256
 257         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 258             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 259                 return 0;
 260
 261         return -EIO;
 262 }
 263
 264 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 265 {
 266         uint32_t if_version = 0xff, smu_version = 0xff;
 267         uint16_t smu_major;
 268         uint8_t smu_minor, smu_debug;
 269         int ret = 0;
 270
 271         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 272         if (ret)
 273                 return ret;
 274
 275         smu_major = (smu_version >> 16) & 0xffff;
 276         smu_minor = (smu_version >> 8) & 0xff;
 277         smu_debug = (smu_version >> 0) & 0xff;
 278
 279         switch (smu->adev->asic_type) {
 280         case CHIP_VEGA20:
 281                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
 282                 break;
 283         case CHIP_ARCTURUS:
 284                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 285                 break;
 286         case CHIP_NAVI10:
 287                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 288                 break;
 289         case CHIP_NAVI14:
 290                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 291                 break;
 292         default:
 293                 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
 294                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
 295                 break;
 296         }
 297
 298         /*
 299          * 1. if_version mismatch is not critical as our fw is designed
 300          * to be backward compatible.
 301          * 2. New fw usually brings some optimizations. But that's visible
 302          * only on the paired driver.
 303          * Considering above, we just leave user a warning message instead
 304          * of halt driver loading.
 305          */
 306         if (if_version != smu->smc_if_version) {
 307                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 308                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 309                         smu->smc_if_version, if_version,
 310                         smu_version, smu_major, smu_minor, smu_debug);
 311                 pr_warn("SMU driver if version not matched\n");
 312         }
 313
 314         return ret;
 315 }
 316
 317 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 318 {
 319         struct amdgpu_device *adev = smu->adev;
 320         uint32_t ppt_offset_bytes;
 321         const struct smc_firmware_header_v2_0 *v2;
 322
 323         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 324
 325         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 326         *size = le32_to_cpu(v2->ppt_size_bytes);
 327         *table = (uint8_t *)v2 + ppt_offset_bytes;
 328
 329         return 0;
 330 }
 331
 332 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 333                                       uint32_t *size, uint32_t pptable_id)
 334 {
 335         struct amdgpu_device *adev = smu->adev;
 336         const struct smc_firmware_header_v2_1 *v2_1;
 337         struct smc_soft_pptable_entry *entries;
 338         uint32_t pptable_count = 0;
 339         int i = 0;
 340
 341         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 342         entries = (struct smc_soft_pptable_entry *)
 343                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 344         pptable_count = le32_to_cpu(v2_1->pptable_count);
 345         for (i = 0; i < pptable_count; i++) {
 346                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 347                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 348                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 349                         break;
 350                 }
 351         }
 352
 353         if (i == pptable_count)
 354                 return -EINVAL;
 355
 356         return 0;
 357 }
 358
 359 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 360 {
 361         struct amdgpu_device *adev = smu->adev;
 362         const struct smc_firmware_header_v1_0 *hdr;
 363         int ret, index;
 364         uint32_t size = 0;
 365         uint16_t atom_table_size;
 366         uint8_t frev, crev;
 367         void *table;
 368         uint16_t version_major, version_minor;
 369
 370         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 371         version_major = le16_to_cpu(hdr->header.header_version_major);
 372         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 373         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 374                 switch (version_minor) {
 375                 case 0:
 376                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 377                         break;
 378                 case 1:
 379                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 380                                                          smu->smu_table.boot_values.pp_table_id);
 381                         break;
 382                 default:
 383                         ret = -EINVAL;
 384                         break;
 385                 }
 386                 if (ret)
 387                         return ret;
 388
 389         } else {
 390                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 391                                                     powerplayinfo);
 392
 393                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 394                                               (uint8_t **)&table);
 395                 if (ret)
 396                         return ret;
 397                 size = atom_table_size;
 398         }
 399
 400         if (!smu->smu_table.power_play_table)
 401                 smu->smu_table.power_play_table = table;
 402         if (!smu->smu_table.power_play_table_size)
 403                 smu->smu_table.power_play_table_size = size;
 404
 405         return 0;
 406 }
 407
 408 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 409 {
 410         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 411
 412         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 413                 return -EINVAL;
 414
 415         return smu_alloc_dpm_context(smu);
 416 }
 417
 418 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 419 {
 420         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 421
 422         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 423                 return -EINVAL;
 424
 425         kfree(smu_dpm->dpm_context);
 426         kfree(smu_dpm->golden_dpm_context);
 427         kfree(smu_dpm->dpm_current_power_state);
 428         kfree(smu_dpm->dpm_request_power_state);
 429         smu_dpm->dpm_context = NULL;
 430         smu_dpm->golden_dpm_context = NULL;
 431         smu_dpm->dpm_context_size = 0;
 432         smu_dpm->dpm_current_power_state = NULL;
 433         smu_dpm->dpm_request_power_state = NULL;
 434
 435         return 0;
 436 }
 437
 438 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 439 {
 440         struct smu_table_context *smu_table = &smu->smu_table;
 441         struct smu_table *tables = NULL;
 442         int ret = 0;
 443
 444         if (smu_table->tables)
 445                 return -EINVAL;
 446
 447         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 448                          GFP_KERNEL);
 449         if (!tables)
 450                 return -ENOMEM;
 451
 452         smu_table->tables = tables;
 453
 454         ret = smu_tables_init(smu, tables);
 455         if (ret)
 456                 return ret;
 457
 458         ret = smu_v11_0_init_dpm_context(smu);
 459         if (ret)
 460                 return ret;
 461
 462         return 0;
 463 }
 464
 465 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 466 {
 467         struct smu_table_context *smu_table = &smu->smu_table;
 468         int ret = 0;
 469
 470         if (!smu_table->tables)
 471                 return -EINVAL;
 472
 473         kfree(smu_table->tables);
 474         kfree(smu_table->metrics_table);
 475         smu_table->tables = NULL;
 476         smu_table->metrics_table = NULL;
 477         smu_table->metrics_time = 0;
 478
 479         ret = smu_v11_0_fini_dpm_context(smu);
 480         if (ret)
 481                 return ret;
 482         return 0;
 483 }
 484
 485 static int smu_v11_0_init_power(struct smu_context *smu)
 486 {
 487         struct smu_power_context *smu_power = &smu->smu_power;
 488
 489         if (!smu->pm_enabled)
 490                 return 0;
 491         if (smu_power->power_context || smu_power->power_context_size != 0)
 492                 return -EINVAL;
 493
 494         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 495                                            GFP_KERNEL);
 496         if (!smu_power->power_context)
 497                 return -ENOMEM;
 498         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 499
 500         return 0;
 501 }
 502
 503 static int smu_v11_0_fini_power(struct smu_context *smu)
 504 {
 505         struct smu_power_context *smu_power = &smu->smu_power;
 506
 507         if (!smu->pm_enabled)
 508                 return 0;
 509         if (!smu_power->power_context || smu_power->power_context_size == 0)
 510                 return -EINVAL;
 511
 512         kfree(smu_power->power_context);
 513         smu_power->power_context = NULL;
 514         smu_power->power_context_size = 0;
 515
 516         return 0;
 517 }
 518
 519 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 520 {
 521         int ret, index;
 522         uint16_t size;
 523         uint8_t frev, crev;
 524         struct atom_common_table_header *header;
 525         struct atom_firmware_info_v3_3 *v_3_3;
 526         struct atom_firmware_info_v3_1 *v_3_1;
 527
 528         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 529                                             firmwareinfo);
 530
 531         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 532                                       (uint8_t **)&header);
 533         if (ret)
 534                 return ret;
 535
 536         if (header->format_revision != 3) {
 537                 pr_err("unknown atom_firmware_info version! for smu11\n");
 538                 return -EINVAL;
 539         }
 540
 541         switch (header->content_revision) {
 542         case 0:
 543         case 1:
 544         case 2:
 545                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 546                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 547                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 548                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 549                 smu->smu_table.boot_values.socclk = 0;
 550                 smu->smu_table.boot_values.dcefclk = 0;
 551                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 552                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 553                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 554                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 555                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 556                 smu->smu_table.boot_values.pp_table_id = 0;
 557                 break;
 558         case 3:
 559         default:
 560                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 561                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 562                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 563                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 564                 smu->smu_table.boot_values.socclk = 0;
 565                 smu->smu_table.boot_values.dcefclk = 0;
 566                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 567                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 568                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 569                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 570                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 571                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 572         }
 573
 574         smu->smu_table.boot_values.format_revision = header->format_revision;
 575         smu->smu_table.boot_values.content_revision = header->content_revision;
 576
 577         return 0;
 578 }
 579
 580 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 581 {
 582         int ret, index;
 583         struct amdgpu_device *adev = smu->adev;
 584         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 585         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 586
 587         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 588         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 589         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 590                                             getsmuclockinfo);
 591
 592         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 593                                         (uint32_t *)&input);
 594         if (ret)
 595                 return -EINVAL;
 596
 597         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 598         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 599
 600         memset(&input, 0, sizeof(input));
 601         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 602         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 603         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 604                                             getsmuclockinfo);
 605
 606         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 607                                         (uint32_t *)&input);
 608         if (ret)
 609                 return -EINVAL;
 610
 611         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 612         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 613
 614         memset(&input, 0, sizeof(input));
 615         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 616         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 617         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 618                                             getsmuclockinfo);
 619
 620         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 621                                         (uint32_t *)&input);
 622         if (ret)
 623                 return -EINVAL;
 624
 625         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 626         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 627
 628         memset(&input, 0, sizeof(input));
 629         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 630         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 631         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 632                                             getsmuclockinfo);
 633
 634         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 635                                         (uint32_t *)&input);
 636         if (ret)
 637                 return -EINVAL;
 638
 639         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 640         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 641
 642         memset(&input, 0, sizeof(input));
 643         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 644         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 645         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 646                                             getsmuclockinfo);
 647
 648         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 649                                         (uint32_t *)&input);
 650         if (ret)
 651                 return -EINVAL;
 652
 653         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 654         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 655
 656         if ((smu->smu_table.boot_values.format_revision == 3) &&
 657             (smu->smu_table.boot_values.content_revision >= 2)) {
 658                 memset(&input, 0, sizeof(input));
 659                 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
 660                 input.syspll_id = SMU11_SYSPLL1_2_ID;
 661                 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 662                 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 663                                                     getsmuclockinfo);
 664
 665                 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 666                                                 (uint32_t *)&input);
 667                 if (ret)
 668                         return -EINVAL;
 669
 670                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 671                 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 672         }
 673
 674         return 0;
 675 }
 676
 677 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 678 {
 679         struct smu_table_context *smu_table = &smu->smu_table;
 680         struct smu_table *memory_pool = &smu_table->memory_pool;
 681         int ret = 0;
 682         uint64_t address;
 683         uint32_t address_low, address_high;
 684
 685         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 686                 return ret;
 687
 688         address = (uintptr_t)memory_pool->cpu_addr;
 689         address_high = (uint32_t)upper_32_bits(address);
 690         address_low  = (uint32_t)lower_32_bits(address);
 691
 692         ret = smu_send_smc_msg_with_param(smu,
 693                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 694                                           address_high);
 695         if (ret)
 696                 return ret;
 697         ret = smu_send_smc_msg_with_param(smu,
 698                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 699                                           address_low);
 700         if (ret)
 701                 return ret;
 702
 703         address = memory_pool->mc_address;
 704         address_high = (uint32_t)upper_32_bits(address);
 705         address_low  = (uint32_t)lower_32_bits(address);
 706
 707         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 708                                           address_high);
 709         if (ret)
 710                 return ret;
 711         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 712                                           address_low);
 713         if (ret)
 714                 return ret;
 715         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 716                                           (uint32_t)memory_pool->size);
 717         if (ret)
 718                 return ret;
 719
 720         return ret;
 721 }
 722
 723 static int smu_v11_0_check_pptable(struct smu_context *smu)
 724 {
 725         int ret;
 726
 727         ret = smu_check_powerplay_table(smu);
 728         return ret;
 729 }
 730
 731 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 732 {
 733         int ret;
 734
 735         struct smu_table_context *table_context = &smu->smu_table;
 736         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 737
 738         if (table_context->driver_pptable)
 739                 return -EINVAL;
 740
 741         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 742
 743         if (!table_context->driver_pptable)
 744                 return -ENOMEM;
 745
 746         ret = smu_store_powerplay_table(smu);
 747         if (ret)
 748                 return -EINVAL;
 749
 750         ret = smu_append_powerplay_table(smu);
 751
 752         return ret;
 753 }
 754
 755 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 756 {
 757         int ret;
 758
 759         ret = smu_set_default_dpm_table(smu);
 760
 761         return ret;
 762 }
 763
 764 static int smu_v11_0_write_pptable(struct smu_context *smu)
 765 {
 766         struct smu_table_context *table_context = &smu->smu_table;
 767         int ret = 0;
 768
 769         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 770                                table_context->driver_pptable, true);
 771
 772         return ret;
 773 }
 774
 775 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 776 {
 777         int ret;
 778
 779         ret = smu_send_smc_msg_with_param(smu,
 780                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 781         if (ret)
 782                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 783
 784         return ret;
 785 }
 786
 787 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 788 {
 789         struct smu_table_context *table_context = &smu->smu_table;
 790
 791         if (!smu->pm_enabled)
 792                 return 0;
 793         if (!table_context)
 794                 return -EINVAL;
 795
 796         if (smu->funcs->set_deep_sleep_dcefclk)
 797                 return smu->funcs->set_deep_sleep_dcefclk(smu,
 798                                 table_context->boot_values.dcefclk / 100);
 799
 800         return 0;
 801 }
 802
 803 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 804 {
 805         int ret = 0;
 806         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 807
 808         if (tool_table->mc_address) {
 809                 ret = smu_send_smc_msg_with_param(smu,
 810                                 SMU_MSG_SetToolsDramAddrHigh,
 811                                 upper_32_bits(tool_table->mc_address));
 812                 if (!ret)
 813                         ret = smu_send_smc_msg_with_param(smu,
 814                                 SMU_MSG_SetToolsDramAddrLow,
 815                                 lower_32_bits(tool_table->mc_address));
 816         }
 817
 818         return ret;
 819 }
 820
 821 static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 822 {
 823         int ret = 0;
 824
 825         if (!smu->pm_enabled)
 826                 return ret;
 827
 828         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 829         return ret;
 830 }
 831
 832
 833 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 834 {
 835         struct smu_feature *feature = &smu->smu_feature;
 836         int ret = 0;
 837         uint32_t feature_mask[2];
 838
 839         mutex_lock(&feature->mutex);
 840         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 841                 goto failed;
 842
 843         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 844
 845         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 846                                           feature_mask[1]);
 847         if (ret)
 848                 goto failed;
 849
 850         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 851                                           feature_mask[0]);
 852         if (ret)
 853                 goto failed;
 854
 855 failed:
 856         mutex_unlock(&feature->mutex);
 857         return ret;
 858 }
 859
 860 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 861                                       uint32_t *feature_mask, uint32_t num)
 862 {
 863         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 864         int ret = 0;
 865
 866         if (!feature_mask || num < 2)
 867                 return -EINVAL;
 868
 869         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 870         if (ret)
 871                 return ret;
 872         ret = smu_read_smc_arg(smu, &feature_mask_high);
 873         if (ret)
 874                 return ret;
 875
 876         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 877         if (ret)
 878                 return ret;
 879         ret = smu_read_smc_arg(smu, &feature_mask_low);
 880         if (ret)
 881                 return ret;
 882
 883         feature_mask[0] = feature_mask_low;
 884         feature_mask[1] = feature_mask_high;
 885
 886         return ret;
 887 }
 888
 889 static int smu_v11_0_system_features_control(struct smu_context *smu,
 890                                              bool en)
 891 {
 892         struct smu_feature *feature = &smu->smu_feature;
 893         uint32_t feature_mask[2];
 894         int ret = 0;
 895
 896         if (smu->pm_enabled) {
 897                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 898                                              SMU_MSG_DisableAllSmuFeatures));
 899                 if (ret)
 900                         return ret;
 901         }
 902
 903         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 904         if (ret)
 905                 return ret;
 906
 907         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 908                     feature->feature_num);
 909         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 910                     feature->feature_num);
 911
 912         return ret;
 913 }
 914
 915 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 916 {
 917         int ret = 0;
 918
 919         if (!smu->pm_enabled)
 920                 return ret;
 921         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 922             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 923                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 924
 925         return ret;
 926 }
 927
 928 static int
 929 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 930                                     enum smu_clk_type clock_select)
 931 {
 932         int ret = 0;
 933         int clk_id;
 934
 935         if (!smu->pm_enabled)
 936                 return ret;
 937
 938         if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 939             (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
 940                 return 0;
 941
 942         clk_id = smu_clk_get_index(smu, clock_select);
 943         if (clk_id < 0)
 944                 return -EINVAL;
 945
 946         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 947                                           clk_id << 16);
 948         if (ret) {
 949                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 950                 return ret;
 951         }
 952
 953         ret = smu_read_smc_arg(smu, clock);
 954         if (ret)
 955                 return ret;
 956
 957         if (*clock != 0)
 958                 return 0;
 959
 960         /* if DC limit is zero, return AC limit */
 961         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 962                                           clk_id << 16);
 963         if (ret) {
 964                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 965                 return ret;
 966         }
 967
 968         ret = smu_read_smc_arg(smu, clock);
 969
 970         return ret;
 971 }
 972
 973 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 974 {
 975         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 976         int ret = 0;
 977
 978         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 979                                          GFP_KERNEL);
 980         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 981
 982         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 983         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 984         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 985         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 986         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 987         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 988
 989         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 990                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 991                                                           &(max_sustainable_clocks->uclock),
 992                                                           SMU_UCLK);
 993                 if (ret) {
 994                         pr_err("[%s] failed to get max UCLK from SMC!",
 995                                __func__);
 996                         return ret;
 997                 }
 998         }
 999
1000         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1001                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1002                                                           &(max_sustainable_clocks->soc_clock),
1003                                                           SMU_SOCCLK);
1004                 if (ret) {
1005                         pr_err("[%s] failed to get max SOCCLK from SMC!",
1006                                __func__);
1007                         return ret;
1008                 }
1009         }
1010
1011         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1012                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1013                                                           &(max_sustainable_clocks->dcef_clock),
1014                                                           SMU_DCEFCLK);
1015                 if (ret) {
1016                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1017                                __func__);
1018                         return ret;
1019                 }
1020
1021                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1022                                                           &(max_sustainable_clocks->display_clock),
1023                                                           SMU_DISPCLK);
1024                 if (ret) {
1025                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1026                                __func__);
1027                         return ret;
1028                 }
1029                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1030                                                           &(max_sustainable_clocks->phy_clock),
1031                                                           SMU_PHYCLK);
1032                 if (ret) {
1033                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1034                                __func__);
1035                         return ret;
1036                 }
1037                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1038                                                           &(max_sustainable_clocks->pixel_clock),
1039                                                           SMU_PIXCLK);
1040                 if (ret) {
1041                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1042                                __func__);
1043                         return ret;
1044                 }
1045         }
1046
1047         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1048                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1049
1050         return 0;
1051 }
1052
1053 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1054 {
1055         int ret = 0;
1056
1057         if (n > smu->default_power_limit) {
1058                 pr_err("New power limit is over the max allowed %d\n",
1059                                 smu->default_power_limit);
1060                 return -EINVAL;
1061         }
1062
1063         if (n == 0)
1064                 n = smu->default_power_limit;
1065
1066         if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1067                 pr_err("Setting new power limit is not supported!\n");
1068                 return -EOPNOTSUPP;
1069         }
1070
1071         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1072         if (ret) {
1073                 pr_err("[%s] Set power limit Failed!\n", __func__);
1074                 return ret;
1075         }
1076         smu->power_limit = n;
1077
1078         return 0;
1079 }
1080
1081 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1082                                           enum smu_clk_type clk_id,
1083                                           uint32_t *value)
1084 {
1085         int ret = 0;
1086         uint32_t freq = 0;
1087         int asic_clk_id;
1088
1089         if (clk_id >= SMU_CLK_COUNT || !value)
1090                 return -EINVAL;
1091
1092         asic_clk_id = smu_clk_get_index(smu, clk_id);
1093         if (asic_clk_id < 0)
1094                 return -EINVAL;
1095
1096         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1097         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1098                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1099         else {
1100                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1101                                                   (asic_clk_id << 16));
1102                 if (ret)
1103                         return ret;
1104
1105                 ret = smu_read_smc_arg(smu, &freq);
1106                 if (ret)
1107                         return ret;
1108         }
1109
1110         freq *= 100;
1111         *value = freq;
1112
1113         return ret;
1114 }
1115
1116 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1117                                        struct smu_temperature_range range)
1118 {
1119         struct amdgpu_device *adev = smu->adev;
1120         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1121         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1122         uint32_t val;
1123
1124         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1125                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1126         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1127                         range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1128
1129         if (low > high)
1130                 return -EINVAL;
1131
1132         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1133         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1134         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1135         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1136         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1137         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1138         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1139         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1140
1141         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1142
1143         return 0;
1144 }
1145
1146 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1147 {
1148         struct amdgpu_device *adev = smu->adev;
1149         uint32_t val = 0;
1150
1151         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1152         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1153         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1154
1155         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1156
1157         return 0;
1158 }
1159
1160 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1161 {
1162         int ret = 0;
1163         struct smu_temperature_range range;
1164         struct amdgpu_device *adev = smu->adev;
1165
1166         if (!smu->pm_enabled)
1167                 return ret;
1168
1169         memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1170
1171         ret = smu_get_thermal_temperature_range(smu, &range);
1172         if (ret)
1173                 return ret;
1174
1175         if (smu->smu_table.thermal_controller_type) {
1176                 ret = smu_v11_0_set_thermal_range(smu, range);
1177                 if (ret)
1178                         return ret;
1179
1180                 ret = smu_v11_0_enable_thermal_alert(smu);
1181                 if (ret)
1182                         return ret;
1183
1184                 ret = smu_set_thermal_fan_table(smu);
1185                 if (ret)
1186                         return ret;
1187         }
1188
1189         adev->pm.dpm.thermal.min_temp = range.min;
1190         adev->pm.dpm.thermal.max_temp = range.max;
1191         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1192         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1193         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1194         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1195         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1196         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1197         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1198
1199         return ret;
1200 }
1201
1202 static int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1203 {
1204         struct amdgpu_device *adev = smu->adev;
1205
1206         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1207
1208         return 0;
1209 }
1210
1211 static uint16_t convert_to_vddc(uint8_t vid)
1212 {
1213         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1214 }
1215
1216 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1217 {
1218         struct amdgpu_device *adev = smu->adev;
1219         uint32_t vdd = 0, val_vid = 0;
1220
1221         if (!value)
1222                 return -EINVAL;
1223         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1224                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1225                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1226
1227         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1228
1229         *value = vdd;
1230
1231         return 0;
1232
1233 }
1234
1235 static int smu_v11_0_read_sensor(struct smu_context *smu,
1236                                  enum amd_pp_sensors sensor,
1237                                  void *data, uint32_t *size)
1238 {
1239         int ret = 0;
1240
1241         if(!data || !size)
1242                 return -EINVAL;
1243
1244         switch (sensor) {
1245         case AMDGPU_PP_SENSOR_GFX_MCLK:
1246                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1247                 *size = 4;
1248                 break;
1249         case AMDGPU_PP_SENSOR_GFX_SCLK:
1250                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1251                 *size = 4;
1252                 break;
1253         case AMDGPU_PP_SENSOR_VDDGFX:
1254                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1255                 *size = 4;
1256                 break;
1257         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1258                 *(uint32_t *)data = 0;
1259                 *size = 4;
1260                 break;
1261         default:
1262                 ret = smu_common_read_sensor(smu, sensor, data, size);
1263                 break;
1264         }
1265
1266         if (ret)
1267                 *size = 0;
1268
1269         return ret;
1270 }
1271
1272 static int
1273 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1274                                         struct pp_display_clock_request
1275                                         *clock_req)
1276 {
1277         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1278         int ret = 0;
1279         enum smu_clk_type clk_select = 0;
1280         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1281
1282         if (!smu->pm_enabled)
1283                 return -EINVAL;
1284
1285         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1286                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1287                 switch (clk_type) {
1288                 case amd_pp_dcef_clock:
1289                         clk_select = SMU_DCEFCLK;
1290                         break;
1291                 case amd_pp_disp_clock:
1292                         clk_select = SMU_DISPCLK;
1293                         break;
1294                 case amd_pp_pixel_clock:
1295                         clk_select = SMU_PIXCLK;
1296                         break;
1297                 case amd_pp_phy_clock:
1298                         clk_select = SMU_PHYCLK;
1299                         break;
1300                 case amd_pp_mem_clock:
1301                         clk_select = SMU_UCLK;
1302                         break;
1303                 default:
1304                         pr_info("[%s] Invalid Clock Type!", __func__);
1305                         ret = -EINVAL;
1306                         break;
1307                 }
1308
1309                 if (ret)
1310                         goto failed;
1311
1312                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1313                         return 0;
1314
1315                 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1316
1317                 if(clk_select == SMU_UCLK)
1318                         smu->hard_min_uclk_req_from_dal = clk_freq;
1319         }
1320
1321 failed:
1322         return ret;
1323 }
1324
1325 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1326 {
1327         int ret = 0;
1328         struct amdgpu_device *adev = smu->adev;
1329
1330         switch (adev->asic_type) {
1331         case CHIP_VEGA20:
1332                 break;
1333         case CHIP_NAVI10:
1334         case CHIP_NAVI14:
1335         case CHIP_NAVI12:
1336                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1337                         return 0;
1338                 if (enable)
1339                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1340                 else
1341                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1342                 break;
1343         default:
1344                 break;
1345         }
1346
1347         return ret;
1348 }
1349
1350 static uint32_t
1351 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1352 {
1353         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1354                 return AMD_FAN_CTRL_MANUAL;
1355         else
1356                 return AMD_FAN_CTRL_AUTO;
1357 }
1358
1359 static int
1360 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1361 {
1362         int ret = 0;
1363
1364         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1365                 return 0;
1366
1367         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1368         if (ret)
1369                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1370                        __func__, (auto_fan_control ? "Start" : "Stop"));
1371
1372         return ret;
1373 }
1374
1375 static int
1376 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1377 {
1378         struct amdgpu_device *adev = smu->adev;
1379
1380         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1381                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1382                                    CG_FDO_CTRL2, TMIN, 0));
1383         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1384                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1385                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1386
1387         return 0;
1388 }
1389
1390 static int
1391 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1392 {
1393         struct amdgpu_device *adev = smu->adev;
1394         uint32_t duty100, duty;
1395         uint64_t tmp64;
1396
1397         if (speed > 100)
1398                 speed = 100;
1399
1400         if (smu_v11_0_auto_fan_control(smu, 0))
1401                 return -EINVAL;
1402
1403         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1404                                 CG_FDO_CTRL1, FMAX_DUTY100);
1405         if (!duty100)
1406                 return -EINVAL;
1407
1408         tmp64 = (uint64_t)speed * duty100;
1409         do_div(tmp64, 100);
1410         duty = (uint32_t)tmp64;
1411
1412         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1413                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1414                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1415
1416         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1417 }
1418
1419 static int
1420 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1421                                uint32_t mode)
1422 {
1423         int ret = 0;
1424
1425         switch (mode) {
1426         case AMD_FAN_CTRL_NONE:
1427                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1428                 break;
1429         case AMD_FAN_CTRL_MANUAL:
1430                 ret = smu_v11_0_auto_fan_control(smu, 0);
1431                 break;
1432         case AMD_FAN_CTRL_AUTO:
1433                 ret = smu_v11_0_auto_fan_control(smu, 1);
1434                 break;
1435         default:
1436                 break;
1437         }
1438
1439         if (ret) {
1440                 pr_err("[%s]Set fan control mode failed!", __func__);
1441                 return -EINVAL;
1442         }
1443
1444         return ret;
1445 }
1446
1447 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1448                                        uint32_t speed)
1449 {
1450         struct amdgpu_device *adev = smu->adev;
1451         int ret;
1452         uint32_t tach_period, crystal_clock_freq;
1453
1454         if (!speed)
1455                 return -EINVAL;
1456
1457         ret = smu_v11_0_auto_fan_control(smu, 0);
1458         if (ret)
1459                 return ret;
1460
1461         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1462         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1463         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1464                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1465                                    CG_TACH_CTRL, TARGET_PERIOD,
1466                                    tach_period));
1467
1468         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1469
1470         return ret;
1471 }
1472
1473 #define XGMI_STATE_D0 1
1474 #define XGMI_STATE_D3 0
1475
1476 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1477                                      uint32_t pstate)
1478 {
1479         int ret = 0;
1480         ret = smu_send_smc_msg_with_param(smu,
1481                                           SMU_MSG_SetXgmiMode,
1482                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1483         return ret;
1484 }
1485
1486 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1487 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1488
1489 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1490                                  struct amdgpu_irq_src *source,
1491                                  struct amdgpu_iv_entry *entry)
1492 {
1493         uint32_t client_id = entry->client_id;
1494         uint32_t src_id = entry->src_id;
1495
1496         if (client_id == SOC15_IH_CLIENTID_THM) {
1497                 switch (src_id) {
1498                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1499                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1500                                 PCI_BUS_NUM(adev->pdev->devfn),
1501                                 PCI_SLOT(adev->pdev->devfn),
1502                                 PCI_FUNC(adev->pdev->devfn));
1503                 break;
1504                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1505                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1506                                 PCI_BUS_NUM(adev->pdev->devfn),
1507                                 PCI_SLOT(adev->pdev->devfn),
1508                                 PCI_FUNC(adev->pdev->devfn));
1509                 break;
1510                 default:
1511                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1512                                 src_id,
1513                                 PCI_BUS_NUM(adev->pdev->devfn),
1514                                 PCI_SLOT(adev->pdev->devfn),
1515                                 PCI_FUNC(adev->pdev->devfn));
1516                 break;
1517
1518                 }
1519         }
1520
1521         return 0;
1522 }
1523
1524 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1525 {
1526         .process = smu_v11_0_irq_process,
1527 };
1528
1529 static int smu_v11_0_register_irq_handler(struct smu_context *smu)
1530 {
1531         struct amdgpu_device *adev = smu->adev;
1532         struct amdgpu_irq_src *irq_src = smu->irq_source;
1533         int ret = 0;
1534
1535         /* already register */
1536         if (irq_src)
1537                 return 0;
1538
1539         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1540         if (!irq_src)
1541                 return -ENOMEM;
1542         smu->irq_source = irq_src;
1543
1544         irq_src->funcs = &smu_v11_0_irq_funcs;
1545
1546         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1547                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1548                                 irq_src);
1549         if (ret)
1550                 return ret;
1551
1552         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1553                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1554                                 irq_src);
1555         if (ret)
1556                 return ret;
1557
1558         return ret;
1559 }
1560
1561 static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1562                 struct pp_smu_nv_clock_table *max_clocks)
1563 {
1564         struct smu_table_context *table_context = &smu->smu_table;
1565         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1566
1567         if (!max_clocks || !table_context->max_sustainable_clocks)
1568                 return -EINVAL;
1569
1570         sustainable_clocks = table_context->max_sustainable_clocks;
1571
1572         max_clocks->dcfClockInKhz =
1573                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1574         max_clocks->displayClockInKhz =
1575                         (unsigned int) sustainable_clocks->display_clock * 1000;
1576         max_clocks->phyClockInKhz =
1577                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1578         max_clocks->pixelClockInKhz =
1579                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1580         max_clocks->uClockInKhz =
1581                         (unsigned int) sustainable_clocks->uclock * 1000;
1582         max_clocks->socClockInKhz =
1583                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1584         max_clocks->dscClockInKhz = 0;
1585         max_clocks->dppClockInKhz = 0;
1586         max_clocks->fabricClockInKhz = 0;
1587
1588         return 0;
1589 }
1590
1591 static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1592 {
1593         int ret = 0;
1594
1595         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1596
1597         return ret;
1598 }
1599
1600 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1601 {
1602         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1603 }
1604
1605 static bool smu_v11_0_baco_is_support(struct smu_context *smu)
1606 {
1607         struct amdgpu_device *adev = smu->adev;
1608         struct smu_baco_context *smu_baco = &smu->smu_baco;
1609         uint32_t val;
1610         bool baco_support;
1611
1612         mutex_lock(&smu_baco->mutex);
1613         baco_support = smu_baco->platform_support;
1614         mutex_unlock(&smu_baco->mutex);
1615
1616         if (!baco_support)
1617                 return false;
1618
1619         if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1620                 return false;
1621
1622         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1623         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1624                 return true;
1625
1626         return false;
1627 }
1628
1629 static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1630 {
1631         struct smu_baco_context *smu_baco = &smu->smu_baco;
1632         enum smu_baco_state baco_state;
1633
1634         mutex_lock(&smu_baco->mutex);
1635         baco_state = smu_baco->state;
1636         mutex_unlock(&smu_baco->mutex);
1637
1638         return baco_state;
1639 }
1640
1641 static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1642 {
1643
1644         struct smu_baco_context *smu_baco = &smu->smu_baco;
1645         int ret = 0;
1646
1647         if (smu_v11_0_baco_get_state(smu) == state)
1648                 return 0;
1649
1650         mutex_lock(&smu_baco->mutex);
1651
1652         if (state == SMU_BACO_STATE_ENTER)
1653                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
1654         else
1655                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1656         if (ret)
1657                 goto out;
1658
1659         smu_baco->state = state;
1660 out:
1661         mutex_unlock(&smu_baco->mutex);
1662         return ret;
1663 }
1664
1665 static int smu_v11_0_baco_reset(struct smu_context *smu)
1666 {
1667         int ret = 0;
1668
1669         ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1670         if (ret)
1671                 return ret;
1672
1673         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1674         if (ret)
1675                 return ret;
1676
1677         msleep(10);
1678
1679         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1680         if (ret)
1681                 return ret;
1682
1683         return ret;
1684 }
1685
1686 static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1687                                                  uint32_t *min, uint32_t *max)
1688 {
1689         int ret = 0, clk_id = 0;
1690         uint32_t param = 0;
1691
1692         clk_id = smu_clk_get_index(smu, clk_type);
1693         if (clk_id < 0) {
1694                 ret = -EINVAL;
1695                 goto failed;
1696         }
1697         param = (clk_id & 0xffff) << 16;
1698
1699         if (max) {
1700                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
1701                 if (ret)
1702                         goto failed;
1703                 ret = smu_read_smc_arg(smu, max);
1704                 if (ret)
1705                         goto failed;
1706         }
1707
1708         if (min) {
1709                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
1710                 if (ret)
1711                         goto failed;
1712                 ret = smu_read_smc_arg(smu, min);
1713                 if (ret)
1714                         goto failed;
1715         }
1716
1717 failed:
1718         return ret;
1719 }
1720
1721 static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1722                             uint32_t min, uint32_t max)
1723 {
1724         int ret = 0, clk_id = 0;
1725         uint32_t param;
1726
1727         clk_id = smu_clk_get_index(smu, clk_type);
1728         if (clk_id < 0)
1729                 return clk_id;
1730
1731         if (max > 0) {
1732                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1733                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1734                                                   param);
1735                 if (ret)
1736                         return ret;
1737         }
1738
1739         if (min > 0) {
1740                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1741                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1742                                                   param);
1743                 if (ret)
1744                         return ret;
1745         }
1746
1747         return ret;
1748 }
1749
1750 static int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1751 {
1752         struct amdgpu_device *adev = smu->adev;
1753         uint32_t pcie_gen = 0, pcie_width = 0;
1754         int ret;
1755
1756         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1757                 pcie_gen = 3;
1758         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1759                 pcie_gen = 2;
1760         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1761                 pcie_gen = 1;
1762         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1763                 pcie_gen = 0;
1764
1765         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1766          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1767          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1768          */
1769         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1770                 pcie_width = 6;
1771         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1772                 pcie_width = 5;
1773         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1774                 pcie_width = 4;
1775         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1776                 pcie_width = 3;
1777         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1778                 pcie_width = 2;
1779         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1780                 pcie_width = 1;
1781
1782         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1783
1784         if (ret)
1785                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1786
1787         return ret;
1788
1789 }
1790
1791
1792 static const struct smu_funcs smu_v11_0_funcs = {
1793         .init_microcode = smu_v11_0_init_microcode,
1794         .load_microcode = smu_v11_0_load_microcode,
1795         .check_fw_status = smu_v11_0_check_fw_status,
1796         .check_fw_version = smu_v11_0_check_fw_version,
1797         .send_smc_msg = smu_v11_0_send_msg,
1798         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1799         .read_smc_arg = smu_v11_0_read_arg,
1800         .setup_pptable = smu_v11_0_setup_pptable,
1801         .init_smc_tables = smu_v11_0_init_smc_tables,
1802         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1803         .init_power = smu_v11_0_init_power,
1804         .fini_power = smu_v11_0_fini_power,
1805         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1806         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1807         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1808         .check_pptable = smu_v11_0_check_pptable,
1809         .parse_pptable = smu_v11_0_parse_pptable,
1810         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
1811         .write_pptable = smu_v11_0_write_pptable,
1812         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1813         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1814         .init_display_count = smu_v11_0_init_display_count,
1815         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1816         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1817         .system_features_control = smu_v11_0_system_features_control,
1818         .notify_display_change = smu_v11_0_notify_display_change,
1819         .set_power_limit = smu_v11_0_set_power_limit,
1820         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1821         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1822         .start_thermal_control = smu_v11_0_start_thermal_control,
1823         .stop_thermal_control = smu_v11_0_stop_thermal_control,
1824         .read_sensor = smu_v11_0_read_sensor,
1825         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1826         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1827         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1828         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1829         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1830         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1831         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1832         .gfx_off_control = smu_v11_0_gfx_off_control,
1833         .register_irq_handler = smu_v11_0_register_irq_handler,
1834         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1835         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1836         .baco_is_support = smu_v11_0_baco_is_support,
1837         .baco_get_state = smu_v11_0_baco_get_state,
1838         .baco_set_state = smu_v11_0_baco_set_state,
1839         .baco_reset = smu_v11_0_baco_reset,
1840         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
1841         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
1842         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
1843 };
1844
1845 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1846 {
1847         struct amdgpu_device *adev = smu->adev;
1848
1849         smu->funcs = &smu_v11_0_funcs;
1850         switch (adev->asic_type) {
1851         case CHIP_VEGA20:
1852                 vega20_set_ppt_funcs(smu);
1853                 break;
1854         case CHIP_ARCTURUS:
1855                 arcturus_set_ppt_funcs(smu);
1856                 break;
1857         case CHIP_NAVI10:
1858         case CHIP_NAVI14:
1859         case CHIP_NAVI12:
1860                 navi10_set_ppt_funcs(smu);
1861                 break;
1862         default:
1863                 pr_warn("Unknown asic for smu11\n");
1864         }
1865 }