drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pp_debug.h"
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "atomfirmware.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "smu_v11_0.h"
  30 #include "soc15_common.h"
  31 #include "atom.h"
  32 #include "vega20_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "pp_thermal.h"
  35
  36 #include "asic_reg/thm/thm_11_0_2_offset.h"
  37 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  38 #include "asic_reg/mp/mp_11_0_offset.h"
  39 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  40 #include "asic_reg/nbio/nbio_7_4_offset.h"
  41 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  42 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  43
  44 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  45 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  46
  47 #define SMU11_THERMAL_MINIMUM_ALERT_TEMP      0
  48 #define SMU11_THERMAL_MAXIMUM_ALERT_TEMP      255
  49
  50 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
  51 #define SMU11_VOLTAGE_SCALE 4
  52
  53 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  54                                               uint16_t msg)
  55 {
  56         struct amdgpu_device *adev = smu->adev;
  57         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  58         return 0;
  59 }
  60
  61 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  62 {
  63         struct amdgpu_device *adev = smu->adev;
  64
  65         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  66         return 0;
  67 }
  68
  69 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  70 {
  71         struct amdgpu_device *adev = smu->adev;
  72         uint32_t cur_value, i;
  73
  74         for (i = 0; i < adev->usec_timeout; i++) {
  75                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  76                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  77                         break;
  78                 udelay(1);
  79         }
  80
  81         /* timeout means wrong logic */
  82         if (i == adev->usec_timeout)
  83                 return -ETIME;
  84
  85         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  86 }
  87
  88 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  89 {
  90         struct amdgpu_device *adev = smu->adev;
  91         int ret = 0, index = 0;
  92
  93         index = smu_msg_get_index(smu, msg);
  94         if (index < 0)
  95                 return index;
  96
  97         smu_v11_0_wait_for_response(smu);
  98
  99         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 100
 101         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 102
 103         ret = smu_v11_0_wait_for_response(smu);
 104
 105         if (ret)
 106                 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 107                        ret);
 108
 109         return ret;
 110
 111 }
 112
 113 static int
 114 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 115                               uint32_t param)
 116 {
 117
 118         struct amdgpu_device *adev = smu->adev;
 119         int ret = 0, index = 0;
 120
 121         index = smu_msg_get_index(smu, msg);
 122         if (index < 0)
 123                 return index;
 124
 125         ret = smu_v11_0_wait_for_response(smu);
 126         if (ret)
 127                 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
 128                        index, ret, param);
 129
 130         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 131
 132         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 133
 134         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 135
 136         ret = smu_v11_0_wait_for_response(smu);
 137         if (ret)
 138                 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
 139                        index, ret, param);
 140
 141         return ret;
 142 }
 143
 144 static int smu_v11_0_init_microcode(struct smu_context *smu)
 145 {
 146         struct amdgpu_device *adev = smu->adev;
 147         const char *chip_name;
 148         char fw_name[30];
 149         int err = 0;
 150         const struct smc_firmware_header_v1_0 *hdr;
 151         const struct common_firmware_header *header;
 152         struct amdgpu_firmware_info *ucode = NULL;
 153
 154         switch (adev->asic_type) {
 155         case CHIP_VEGA20:
 156                 chip_name = "vega20";
 157                 break;
 158         case CHIP_NAVI10:
 159                 chip_name = "navi10";
 160                 break;
 161         default:
 162                 BUG();
 163         }
 164
 165         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 166
 167         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 168         if (err)
 169                 goto out;
 170         err = amdgpu_ucode_validate(adev->pm.fw);
 171         if (err)
 172                 goto out;
 173
 174         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 175         amdgpu_ucode_print_smc_hdr(&hdr->header);
 176         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 177
 178         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 179                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 180                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 181                 ucode->fw = adev->pm.fw;
 182                 header = (const struct common_firmware_header *)ucode->fw->data;
 183                 adev->firmware.fw_size +=
 184                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 185         }
 186
 187 out:
 188         if (err) {
 189                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 190                           fw_name);
 191                 release_firmware(adev->pm.fw);
 192                 adev->pm.fw = NULL;
 193         }
 194         return err;
 195 }
 196
 197 static int smu_v11_0_load_microcode(struct smu_context *smu)
 198 {
 199         struct amdgpu_device *adev = smu->adev;
 200         const uint32_t *src;
 201         const struct smc_firmware_header_v1_0 *hdr;
 202         uint32_t addr_start = MP1_SRAM;
 203         uint32_t i;
 204         uint32_t mp1_fw_flags;
 205
 206         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 207         src = (const uint32_t *)(adev->pm.fw->data +
 208                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 209
 210         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 211                 WREG32_PCIE(addr_start, src[i]);
 212                 addr_start += 4;
 213         }
 214
 215         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 216                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 217         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 218                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 219
 220         for (i = 0; i < adev->usec_timeout; i++) {
 221                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 222                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 223                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 224                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 225                         break;
 226                 udelay(1);
 227         }
 228
 229         if (i == adev->usec_timeout)
 230                 return -ETIME;
 231
 232         return 0;
 233 }
 234
 235 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 236 {
 237         struct amdgpu_device *adev = smu->adev;
 238         uint32_t mp1_fw_flags;
 239
 240         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 241                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 242
 243         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 244             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 245                 return 0;
 246
 247         return -EIO;
 248 }
 249
 250 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 251 {
 252         uint32_t if_version = 0xff, smu_version = 0xff;
 253         uint16_t smu_major;
 254         uint8_t smu_minor, smu_debug;
 255         int ret = 0;
 256
 257         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 258         if (ret)
 259                 return ret;
 260
 261         smu_major = (smu_version >> 16) & 0xffff;
 262         smu_minor = (smu_version >> 8) & 0xff;
 263         smu_debug = (smu_version >> 0) & 0xff;
 264
 265         pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x (%d.%d.%d)\n",
 266                 if_version, smu_version, smu_major, smu_minor, smu_debug);
 267
 268         if (if_version != smu->smc_if_version) {
 269                 pr_err("SMU driver if version not matched\n");
 270                 ret = -EINVAL;
 271         }
 272
 273         return ret;
 274 }
 275
 276 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 277 {
 278         struct amdgpu_device *adev = smu->adev;
 279         uint32_t ppt_offset_bytes;
 280         const struct smc_firmware_header_v2_0 *v2;
 281
 282         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 283
 284         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 285         *size = le32_to_cpu(v2->ppt_size_bytes);
 286         *table = (uint8_t *)v2 + ppt_offset_bytes;
 287
 288         return 0;
 289 }
 290
 291 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
 292 {
 293         struct amdgpu_device *adev = smu->adev;
 294         const struct smc_firmware_header_v2_1 *v2_1;
 295         struct smc_soft_pptable_entry *entries;
 296         uint32_t pptable_count = 0;
 297         int i = 0;
 298
 299         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 300         entries = (struct smc_soft_pptable_entry *)
 301                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 302         pptable_count = le32_to_cpu(v2_1->pptable_count);
 303         for (i = 0; i < pptable_count; i++) {
 304                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 305                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 306                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 307                         break;
 308                 }
 309         }
 310
 311         if (i == pptable_count)
 312                 return -EINVAL;
 313
 314         return 0;
 315 }
 316
 317 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 318 {
 319         struct amdgpu_device *adev = smu->adev;
 320         const struct smc_firmware_header_v1_0 *hdr;
 321         int ret, index;
 322         uint32_t size;
 323         uint8_t frev, crev;
 324         void *table;
 325         uint16_t version_major, version_minor;
 326
 327         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 328         version_major = le16_to_cpu(hdr->header.header_version_major);
 329         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 330         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 331                 switch (version_minor) {
 332                 case 0:
 333                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 334                         break;
 335                 case 1:
 336                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 337                                                          smu->smu_table.boot_values.pp_table_id);
 338                         break;
 339                 default:
 340                         ret = -EINVAL;
 341                         break;
 342                 }
 343                 if (ret)
 344                         return ret;
 345
 346         } else {
 347                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 348                                                     powerplayinfo);
 349
 350                 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
 351                                               (uint8_t **)&table);
 352                 if (ret)
 353                         return ret;
 354         }
 355
 356         if (!smu->smu_table.power_play_table)
 357                 smu->smu_table.power_play_table = table;
 358         if (!smu->smu_table.power_play_table_size)
 359                 smu->smu_table.power_play_table_size = size;
 360
 361         return 0;
 362 }
 363
 364 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 365 {
 366         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 367
 368         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 369                 return -EINVAL;
 370
 371         return smu_alloc_dpm_context(smu);
 372 }
 373
 374 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 375 {
 376         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 377
 378         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 379                 return -EINVAL;
 380
 381         kfree(smu_dpm->dpm_context);
 382         kfree(smu_dpm->golden_dpm_context);
 383         kfree(smu_dpm->dpm_current_power_state);
 384         kfree(smu_dpm->dpm_request_power_state);
 385         smu_dpm->dpm_context = NULL;
 386         smu_dpm->golden_dpm_context = NULL;
 387         smu_dpm->dpm_context_size = 0;
 388         smu_dpm->dpm_current_power_state = NULL;
 389         smu_dpm->dpm_request_power_state = NULL;
 390
 391         return 0;
 392 }
 393
 394 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 395 {
 396         struct smu_table_context *smu_table = &smu->smu_table;
 397         struct smu_table *tables = NULL;
 398         int ret = 0;
 399
 400         if (smu_table->tables || smu_table->table_count == 0)
 401                 return -EINVAL;
 402
 403         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 404                          GFP_KERNEL);
 405         if (!tables)
 406                 return -ENOMEM;
 407
 408         smu_table->tables = tables;
 409
 410         smu_tables_init(smu, tables);
 411
 412         ret = smu_v11_0_init_dpm_context(smu);
 413         if (ret)
 414                 return ret;
 415
 416         return 0;
 417 }
 418
 419 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 420 {
 421         struct smu_table_context *smu_table = &smu->smu_table;
 422         int ret = 0;
 423
 424         if (!smu_table->tables || smu_table->table_count == 0)
 425                 return -EINVAL;
 426
 427         kfree(smu_table->tables);
 428         smu_table->tables = NULL;
 429         smu_table->table_count = 0;
 430
 431         ret = smu_v11_0_fini_dpm_context(smu);
 432         if (ret)
 433                 return ret;
 434         return 0;
 435 }
 436
 437 static int smu_v11_0_init_power(struct smu_context *smu)
 438 {
 439         struct smu_power_context *smu_power = &smu->smu_power;
 440
 441         if (!smu->pm_enabled)
 442                 return 0;
 443         if (smu_power->power_context || smu_power->power_context_size != 0)
 444                 return -EINVAL;
 445
 446         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 447                                            GFP_KERNEL);
 448         if (!smu_power->power_context)
 449                 return -ENOMEM;
 450         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 451
 452         smu->metrics_time = 0;
 453         smu->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 454         if (!smu->metrics_table) {
 455                 kfree(smu_power->power_context);
 456                 return -ENOMEM;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int smu_v11_0_fini_power(struct smu_context *smu)
 463 {
 464         struct smu_power_context *smu_power = &smu->smu_power;
 465
 466         if (!smu->pm_enabled)
 467                 return 0;
 468         if (!smu_power->power_context || smu_power->power_context_size == 0)
 469                 return -EINVAL;
 470
 471         kfree(smu->metrics_table);
 472         kfree(smu_power->power_context);
 473         smu->metrics_table = NULL;
 474         smu_power->power_context = NULL;
 475         smu_power->power_context_size = 0;
 476
 477         return 0;
 478 }
 479
 480 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 481 {
 482         int ret, index;
 483         uint16_t size;
 484         uint8_t frev, crev;
 485         struct atom_common_table_header *header;
 486         struct atom_firmware_info_v3_3 *v_3_3;
 487         struct atom_firmware_info_v3_1 *v_3_1;
 488
 489         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 490                                             firmwareinfo);
 491
 492         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 493                                       (uint8_t **)&header);
 494         if (ret)
 495                 return ret;
 496
 497         if (header->format_revision != 3) {
 498                 pr_err("unknown atom_firmware_info version! for smu11\n");
 499                 return -EINVAL;
 500         }
 501
 502         switch (header->content_revision) {
 503         case 0:
 504         case 1:
 505         case 2:
 506                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 507                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 508                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 509                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 510                 smu->smu_table.boot_values.socclk = 0;
 511                 smu->smu_table.boot_values.dcefclk = 0;
 512                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 513                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 514                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 515                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 516                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 517                 smu->smu_table.boot_values.pp_table_id = 0;
 518                 break;
 519         case 3:
 520         default:
 521                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 522                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 523                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 524                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 525                 smu->smu_table.boot_values.socclk = 0;
 526                 smu->smu_table.boot_values.dcefclk = 0;
 527                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 528                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 529                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 530                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 531                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 532                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 539 {
 540         int ret, index;
 541         struct amdgpu_device *adev = smu->adev;
 542         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 543         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 544
 545         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 546         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 547         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 548                                             getsmuclockinfo);
 549
 550         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 551                                         (uint32_t *)&input);
 552         if (ret)
 553                 return -EINVAL;
 554
 555         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 556         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 557
 558         memset(&input, 0, sizeof(input));
 559         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 560         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 561         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 562                                             getsmuclockinfo);
 563
 564         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 565                                         (uint32_t *)&input);
 566         if (ret)
 567                 return -EINVAL;
 568
 569         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 570         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 571
 572         memset(&input, 0, sizeof(input));
 573         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 574         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 575         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 576                                             getsmuclockinfo);
 577
 578         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 579                                         (uint32_t *)&input);
 580         if (ret)
 581                 return -EINVAL;
 582
 583         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 584         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 585
 586         memset(&input, 0, sizeof(input));
 587         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 588         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 589         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 590                                             getsmuclockinfo);
 591
 592         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 593                                         (uint32_t *)&input);
 594         if (ret)
 595                 return -EINVAL;
 596
 597         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 598         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 599
 600         memset(&input, 0, sizeof(input));
 601         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 602         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 603         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 604                                             getsmuclockinfo);
 605
 606         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 607                                         (uint32_t *)&input);
 608         if (ret)
 609                 return -EINVAL;
 610
 611         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 612         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 613
 614         return 0;
 615 }
 616
 617 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 618 {
 619         struct smu_table_context *smu_table = &smu->smu_table;
 620         struct smu_table *memory_pool = &smu_table->memory_pool;
 621         int ret = 0;
 622         uint64_t address;
 623         uint32_t address_low, address_high;
 624
 625         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 626                 return ret;
 627
 628         address = (uintptr_t)memory_pool->cpu_addr;
 629         address_high = (uint32_t)upper_32_bits(address);
 630         address_low  = (uint32_t)lower_32_bits(address);
 631
 632         ret = smu_send_smc_msg_with_param(smu,
 633                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 634                                           address_high);
 635         if (ret)
 636                 return ret;
 637         ret = smu_send_smc_msg_with_param(smu,
 638                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 639                                           address_low);
 640         if (ret)
 641                 return ret;
 642
 643         address = memory_pool->mc_address;
 644         address_high = (uint32_t)upper_32_bits(address);
 645         address_low  = (uint32_t)lower_32_bits(address);
 646
 647         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 648                                           address_high);
 649         if (ret)
 650                 return ret;
 651         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 652                                           address_low);
 653         if (ret)
 654                 return ret;
 655         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 656                                           (uint32_t)memory_pool->size);
 657         if (ret)
 658                 return ret;
 659
 660         return ret;
 661 }
 662
 663 static int smu_v11_0_check_pptable(struct smu_context *smu)
 664 {
 665         int ret;
 666
 667         ret = smu_check_powerplay_table(smu);
 668         return ret;
 669 }
 670
 671 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 672 {
 673         int ret;
 674
 675         struct smu_table_context *table_context = &smu->smu_table;
 676         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 677
 678         if (table_context->driver_pptable)
 679                 return -EINVAL;
 680
 681         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 682
 683         if (!table_context->driver_pptable)
 684                 return -ENOMEM;
 685
 686         ret = smu_store_powerplay_table(smu);
 687         if (ret)
 688                 return -EINVAL;
 689
 690         ret = smu_append_powerplay_table(smu);
 691
 692         return ret;
 693 }
 694
 695 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 696 {
 697         int ret;
 698
 699         ret = smu_set_default_dpm_table(smu);
 700
 701         return ret;
 702 }
 703
 704 static int smu_v11_0_write_pptable(struct smu_context *smu)
 705 {
 706         struct smu_table_context *table_context = &smu->smu_table;
 707         int ret = 0;
 708
 709         ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
 710                                table_context->driver_pptable, true);
 711
 712         return ret;
 713 }
 714
 715 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 716 {
 717         int ret = 0;
 718         struct smu_table_context *smu_table = &smu->smu_table;
 719         struct smu_table *table = NULL;
 720
 721         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
 722         if (!table)
 723                 return -EINVAL;
 724
 725         if (!table->cpu_addr)
 726                 return -EINVAL;
 727
 728         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
 729                                 true);
 730
 731         return ret;
 732 }
 733
 734 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 735 {
 736         int ret;
 737
 738         ret = smu_send_smc_msg_with_param(smu,
 739                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 740         if (ret)
 741                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 742
 743         return ret;
 744 }
 745
 746 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 747 {
 748         struct smu_table_context *table_context = &smu->smu_table;
 749
 750         if (!smu->pm_enabled)
 751                 return 0;
 752         if (!table_context)
 753                 return -EINVAL;
 754
 755         return smu_set_deep_sleep_dcefclk(smu,
 756                                           table_context->boot_values.dcefclk / 100);
 757 }
 758
 759 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 760 {
 761         int ret = 0;
 762         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 763
 764         if (tool_table->mc_address) {
 765                 ret = smu_send_smc_msg_with_param(smu,
 766                                 SMU_MSG_SetToolsDramAddrHigh,
 767                                 upper_32_bits(tool_table->mc_address));
 768                 if (!ret)
 769                         ret = smu_send_smc_msg_with_param(smu,
 770                                 SMU_MSG_SetToolsDramAddrLow,
 771                                 lower_32_bits(tool_table->mc_address));
 772         }
 773
 774         return ret;
 775 }
 776
 777 static int smu_v11_0_init_display(struct smu_context *smu)
 778 {
 779         int ret = 0;
 780
 781         if (!smu->pm_enabled)
 782                 return ret;
 783         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 784         return ret;
 785 }
 786
 787 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 788 {
 789         uint32_t feature_low = 0, feature_high = 0;
 790         int ret = 0;
 791
 792         if (!smu->pm_enabled)
 793                 return ret;
 794         if (feature_id >= 0 && feature_id < 31)
 795                 feature_low = (1 << feature_id);
 796         else if (feature_id > 31 && feature_id < 63)
 797                 feature_high = (1 << feature_id);
 798         else
 799                 return -EINVAL;
 800
 801         if (enabled) {
 802                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 803                                                   feature_low);
 804                 if (ret)
 805                         return ret;
 806                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 807                                                   feature_high);
 808                 if (ret)
 809                         return ret;
 810
 811         } else {
 812                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 813                                                   feature_low);
 814                 if (ret)
 815                         return ret;
 816                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 817                                                   feature_high);
 818                 if (ret)
 819                         return ret;
 820
 821         }
 822
 823         return ret;
 824 }
 825
 826 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 827 {
 828         struct smu_feature *feature = &smu->smu_feature;
 829         int ret = 0;
 830         uint32_t feature_mask[2];
 831
 832         mutex_lock(&feature->mutex);
 833         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 834                 goto failed;
 835
 836         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 837
 838         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 839                                           feature_mask[1]);
 840         if (ret)
 841                 goto failed;
 842
 843         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 844                                           feature_mask[0]);
 845         if (ret)
 846                 goto failed;
 847
 848 failed:
 849         mutex_unlock(&feature->mutex);
 850         return ret;
 851 }
 852
 853 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 854                                       uint32_t *feature_mask, uint32_t num)
 855 {
 856         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 857         int ret = 0;
 858
 859         if (!feature_mask || num < 2)
 860                 return -EINVAL;
 861
 862         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 863         if (ret)
 864                 return ret;
 865         ret = smu_read_smc_arg(smu, &feature_mask_high);
 866         if (ret)
 867                 return ret;
 868
 869         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 870         if (ret)
 871                 return ret;
 872         ret = smu_read_smc_arg(smu, &feature_mask_low);
 873         if (ret)
 874                 return ret;
 875
 876         feature_mask[0] = feature_mask_low;
 877         feature_mask[1] = feature_mask_high;
 878
 879         return ret;
 880 }
 881
 882 static int smu_v11_0_system_features_control(struct smu_context *smu,
 883                                              bool en)
 884 {
 885         struct smu_feature *feature = &smu->smu_feature;
 886         uint32_t feature_mask[2];
 887         int ret = 0;
 888
 889         if (smu->pm_enabled) {
 890                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 891                                              SMU_MSG_DisableAllSmuFeatures));
 892                 if (ret)
 893                         return ret;
 894         }
 895
 896         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 897         if (ret)
 898                 return ret;
 899
 900         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 901                     feature->feature_num);
 902         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 903                     feature->feature_num);
 904
 905         return ret;
 906 }
 907
 908 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 909 {
 910         int ret = 0;
 911
 912         if (!smu->pm_enabled)
 913                 return ret;
 914         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 915             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 916                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 917
 918         return ret;
 919 }
 920
 921 static int
 922 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 923                                     enum smu_clk_type clock_select)
 924 {
 925         int ret = 0;
 926
 927         if (!smu->pm_enabled)
 928                 return ret;
 929         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 930                                           smu_clk_get_index(smu, clock_select) << 16);
 931         if (ret) {
 932                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 933                 return ret;
 934         }
 935
 936         ret = smu_read_smc_arg(smu, clock);
 937         if (ret)
 938                 return ret;
 939
 940         if (*clock != 0)
 941                 return 0;
 942
 943         /* if DC limit is zero, return AC limit */
 944         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 945                                           smu_clk_get_index(smu, clock_select) << 16);
 946         if (ret) {
 947                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 948                 return ret;
 949         }
 950
 951         ret = smu_read_smc_arg(smu, clock);
 952
 953         return ret;
 954 }
 955
 956 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 957 {
 958         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 959         int ret = 0;
 960
 961         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 962                                          GFP_KERNEL);
 963         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 964
 965         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 966         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 967         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 968         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 969         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 970         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 971
 972         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 973                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 974                                                           &(max_sustainable_clocks->uclock),
 975                                                           SMU_UCLK);
 976                 if (ret) {
 977                         pr_err("[%s] failed to get max UCLK from SMC!",
 978                                __func__);
 979                         return ret;
 980                 }
 981         }
 982
 983         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 984                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 985                                                           &(max_sustainable_clocks->soc_clock),
 986                                                           SMU_SOCCLK);
 987                 if (ret) {
 988                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 989                                __func__);
 990                         return ret;
 991                 }
 992         }
 993
 994         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 995                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 996                                                           &(max_sustainable_clocks->dcef_clock),
 997                                                           SMU_DCEFCLK);
 998                 if (ret) {
 999                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1000                                __func__);
1001                         return ret;
1002                 }
1003
1004                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1005                                                           &(max_sustainable_clocks->display_clock),
1006                                                           SMU_DISPCLK);
1007                 if (ret) {
1008                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1009                                __func__);
1010                         return ret;
1011                 }
1012                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1013                                                           &(max_sustainable_clocks->phy_clock),
1014                                                           SMU_PHYCLK);
1015                 if (ret) {
1016                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1017                                __func__);
1018                         return ret;
1019                 }
1020                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1021                                                           &(max_sustainable_clocks->pixel_clock),
1022                                                           SMU_PIXCLK);
1023                 if (ret) {
1024                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1025                                __func__);
1026                         return ret;
1027                 }
1028         }
1029
1030         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1031                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1032
1033         return 0;
1034 }
1035
1036 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1037                                      uint32_t *limit,
1038                                      bool get_default)
1039 {
1040         int ret = 0;
1041
1042         if (get_default) {
1043                 mutex_lock(&smu->mutex);
1044                 *limit = smu->default_power_limit;
1045                 if (smu->od_enabled) {
1046                         *limit *= (100 + smu->smu_table.TDPODLimit);
1047                         *limit /= 100;
1048                 }
1049                 mutex_unlock(&smu->mutex);
1050         } else {
1051                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1052                         smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
1053                 if (ret) {
1054                         pr_err("[%s] get PPT limit failed!", __func__);
1055                         return ret;
1056                 }
1057                 smu_read_smc_arg(smu, limit);
1058                 smu->power_limit = *limit;
1059         }
1060
1061         return ret;
1062 }
1063
1064 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1065 {
1066         uint32_t max_power_limit;
1067         int ret = 0;
1068
1069         if (n == 0)
1070                 n = smu->default_power_limit;
1071
1072         max_power_limit = smu->default_power_limit;
1073
1074         if (smu->od_enabled) {
1075                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1076                 max_power_limit /= 100;
1077         }
1078
1079         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1080                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1081         if (ret) {
1082                 pr_err("[%s] Set power limit Failed!", __func__);
1083                 return ret;
1084         }
1085
1086         return ret;
1087 }
1088
1089 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1090                                           enum smu_clk_type clk_id,
1091                                           uint32_t *value)
1092 {
1093         int ret = 0;
1094         uint32_t freq;
1095
1096         if (clk_id >= SMU_CLK_COUNT || !value)
1097                 return -EINVAL;
1098
1099         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1100         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
1101                 return smu_get_current_clk_freq_by_table(smu, clk_id, value);
1102
1103         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1104                                           (smu_clk_get_index(smu, clk_id) << 16));
1105         if (ret)
1106                 return ret;
1107
1108         ret = smu_read_smc_arg(smu, &freq);
1109         if (ret)
1110                 return ret;
1111
1112         freq *= 100;
1113         *value = freq;
1114
1115         return ret;
1116 }
1117
1118 static int smu_v11_0_get_thermal_range(struct smu_context *smu,
1119                                 struct PP_TemperatureRange *range)
1120 {
1121         PPTable_t *pptable = smu->smu_table.driver_pptable;
1122         memcpy(range, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
1123
1124         range->max = pptable->TedgeLimit *
1125                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1126         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1127                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1128         range->hotspot_crit_max = pptable->ThotspotLimit *
1129                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1130         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1131                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1132         range->mem_crit_max = pptable->ThbmLimit *
1133                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1134         range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
1135                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1136
1137         return 0;
1138 }
1139
1140 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1141                         struct PP_TemperatureRange *range)
1142 {
1143         struct amdgpu_device *adev = smu->adev;
1144         int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
1145                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1146         int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
1147                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1148         uint32_t val;
1149
1150         if (low < range->min)
1151                 low = range->min;
1152         if (high > range->max)
1153                 high = range->max;
1154
1155         if (low > high)
1156                 return -EINVAL;
1157
1158         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1159         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1160         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1161         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1162         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1163         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1164
1165         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1166
1167         return 0;
1168 }
1169
1170 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1171 {
1172         struct amdgpu_device *adev = smu->adev;
1173         uint32_t val = 0;
1174
1175         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1176         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1177         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1178
1179         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1180
1181         return 0;
1182 }
1183
1184 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1185 {
1186         int ret = 0;
1187         struct PP_TemperatureRange range = {
1188                 TEMP_RANGE_MIN,
1189                 TEMP_RANGE_MAX,
1190                 TEMP_RANGE_MAX,
1191                 TEMP_RANGE_MIN,
1192                 TEMP_RANGE_MAX,
1193                 TEMP_RANGE_MAX,
1194                 TEMP_RANGE_MIN,
1195                 TEMP_RANGE_MAX,
1196                 TEMP_RANGE_MAX};
1197         struct amdgpu_device *adev = smu->adev;
1198
1199         if (!smu->pm_enabled)
1200                 return ret;
1201         smu_v11_0_get_thermal_range(smu, &range);
1202
1203         if (smu->smu_table.thermal_controller_type) {
1204                 ret = smu_v11_0_set_thermal_range(smu, &range);
1205                 if (ret)
1206                         return ret;
1207
1208                 ret = smu_v11_0_enable_thermal_alert(smu);
1209                 if (ret)
1210                         return ret;
1211                 ret = smu_set_thermal_fan_table(smu);
1212                 if (ret)
1213                         return ret;
1214         }
1215
1216         adev->pm.dpm.thermal.min_temp = range.min;
1217         adev->pm.dpm.thermal.max_temp = range.max;
1218         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1219         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1220         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1221         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1222         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1223         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1224         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1225
1226         return ret;
1227 }
1228
1229 static int smu_v11_0_get_metrics_table(struct smu_context *smu,
1230                 SmuMetrics_t *metrics_table)
1231 {
1232         int ret = 0;
1233
1234         if (!smu->metrics_time || time_after(jiffies, smu->metrics_time + HZ / 1000)) {
1235                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
1236                                 (void *)metrics_table, false);
1237                 if (ret) {
1238                         pr_info("Failed to export SMU metrics table!\n");
1239                         return ret;
1240                 }
1241                 memcpy(smu->metrics_table, metrics_table, sizeof(SmuMetrics_t));
1242                 smu->metrics_time = jiffies;
1243         } else
1244                 memcpy(metrics_table, smu->metrics_table, sizeof(SmuMetrics_t));
1245
1246         return ret;
1247 }
1248
1249 static int smu_v11_0_thermal_get_temperature(struct smu_context *smu,
1250                                              enum amd_pp_sensors sensor,
1251                                              uint32_t *value)
1252 {
1253         struct amdgpu_device *adev = smu->adev;
1254         SmuMetrics_t metrics;
1255         uint32_t temp = 0;
1256         int ret = 0;
1257
1258         if (!value)
1259                 return -EINVAL;
1260
1261         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1262         if (ret)
1263                 return ret;
1264
1265         switch (sensor) {
1266         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1267                 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
1268                 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
1269                                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
1270
1271                 temp = temp & 0x1ff;
1272                 temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
1273
1274                 *value = temp;
1275                 break;
1276         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1277                 *value = metrics.TemperatureEdge *
1278                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1279                 break;
1280         case AMDGPU_PP_SENSOR_MEM_TEMP:
1281                 *value = metrics.TemperatureHBM *
1282                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1283                 break;
1284         default:
1285                 pr_err("Invalid sensor for retrieving temp\n");
1286                 return -EINVAL;
1287         }
1288
1289         return 0;
1290 }
1291
1292 static uint16_t convert_to_vddc(uint8_t vid)
1293 {
1294         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1295 }
1296
1297 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1298 {
1299         struct amdgpu_device *adev = smu->adev;
1300         uint32_t vdd = 0, val_vid = 0;
1301
1302         if (!value)
1303                 return -EINVAL;
1304         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1305                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1306                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1307
1308         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1309
1310         *value = vdd;
1311
1312         return 0;
1313
1314 }
1315
1316 static int smu_v11_0_read_sensor(struct smu_context *smu,
1317                                  enum amd_pp_sensors sensor,
1318                                  void *data, uint32_t *size)
1319 {
1320         int ret = 0;
1321         switch (sensor) {
1322         case AMDGPU_PP_SENSOR_GPU_LOAD:
1323         case AMDGPU_PP_SENSOR_MEM_LOAD:
1324                 ret = smu_get_current_activity_percent(smu,
1325                                                        sensor,
1326                                                        (uint32_t *)data);
1327                 *size = 4;
1328                 break;
1329         case AMDGPU_PP_SENSOR_GFX_MCLK:
1330                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1331                 *size = 4;
1332                 break;
1333         case AMDGPU_PP_SENSOR_GFX_SCLK:
1334                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1335                 *size = 4;
1336                 break;
1337         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1338         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1339         case AMDGPU_PP_SENSOR_MEM_TEMP:
1340                 ret = smu_v11_0_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1341                 *size = 4;
1342                 break;
1343         case AMDGPU_PP_SENSOR_GPU_POWER:
1344                 ret = smu_get_gpu_power(smu, (uint32_t *)data);
1345                 *size = 4;
1346                 break;
1347         case AMDGPU_PP_SENSOR_VDDGFX:
1348                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1349                 *size = 4;
1350                 break;
1351         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1352                 *(uint32_t *)data = 0;
1353                 *size = 4;
1354                 break;
1355         default:
1356                 ret = smu_common_read_sensor(smu, sensor, data, size);
1357                 break;
1358         }
1359
1360         /* try get sensor data by asic */
1361         if (ret)
1362                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1363
1364         if (ret)
1365                 *size = 0;
1366
1367         return ret;
1368 }
1369
1370 static int
1371 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1372                                         struct pp_display_clock_request
1373                                         *clock_req)
1374 {
1375         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1376         int ret = 0;
1377         enum smu_clk_type clk_select = 0;
1378         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1379
1380         if (!smu->pm_enabled)
1381                 return -EINVAL;
1382         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1383                 switch (clk_type) {
1384                 case amd_pp_dcef_clock:
1385                         clk_select = SMU_DCEFCLK;
1386                         break;
1387                 case amd_pp_disp_clock:
1388                         clk_select = SMU_DISPCLK;
1389                         break;
1390                 case amd_pp_pixel_clock:
1391                         clk_select = SMU_PIXCLK;
1392                         break;
1393                 case amd_pp_phy_clock:
1394                         clk_select = SMU_PHYCLK;
1395                         break;
1396                 default:
1397                         pr_info("[%s] Invalid Clock Type!", __func__);
1398                         ret = -EINVAL;
1399                         break;
1400                 }
1401
1402                 if (ret)
1403                         goto failed;
1404
1405                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1406                         (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1407         }
1408
1409 failed:
1410         return ret;
1411 }
1412
1413 static int
1414 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1415                                           dm_pp_wm_sets_with_clock_ranges_soc15
1416                                           *clock_ranges)
1417 {
1418         int ret = 0;
1419         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1420         void *table = watermarks->cpu_addr;
1421
1422         if (!smu->disable_watermark &&
1423             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1424             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1425                 smu_set_watermarks_table(smu, table, clock_ranges);
1426                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1427                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1428         }
1429
1430         return ret;
1431 }
1432
1433 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1434 {
1435         int ret = 0;
1436         struct amdgpu_device *adev = smu->adev;
1437
1438         switch (adev->asic_type) {
1439         case CHIP_VEGA20:
1440                 break;
1441         case CHIP_NAVI10:
1442                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1443                         return 0;
1444                 mutex_lock(&smu->mutex);
1445                 if (enable)
1446                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1447                 else
1448                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1449                 mutex_unlock(&smu->mutex);
1450                 break;
1451         default:
1452                 break;
1453         }
1454
1455         return ret;
1456 }
1457
1458
1459 static int smu_v11_0_get_clock_ranges(struct smu_context *smu,
1460                                       uint32_t *clock,
1461                                       enum smu_clk_type clock_select,
1462                                       bool max)
1463 {
1464         int ret;
1465         *clock = 0;
1466         if (max) {
1467                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
1468                                 smu_clk_get_index(smu, clock_select) << 16);
1469                 if (ret) {
1470                         pr_err("[GetClockRanges] Failed to get max clock from SMC!\n");
1471                         return ret;
1472                 }
1473                 smu_read_smc_arg(smu, clock);
1474         } else {
1475                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq,
1476                                 smu_clk_get_index(smu, clock_select) << 16);
1477                 if (ret) {
1478                         pr_err("[GetClockRanges] Failed to get min clock from SMC!\n");
1479                         return ret;
1480                 }
1481                 smu_read_smc_arg(smu, clock);
1482         }
1483
1484         return 0;
1485 }
1486
1487 static uint32_t smu_v11_0_dpm_get_sclk(struct smu_context *smu, bool low)
1488 {
1489         uint32_t gfx_clk;
1490         int ret;
1491
1492         if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1493                 pr_err("[GetSclks]: gfxclk dpm not enabled!\n");
1494                 return -EPERM;
1495         }
1496
1497         if (low) {
1498                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, false);
1499                 if (ret) {
1500                         pr_err("[GetSclks]: fail to get min SMU_GFXCLK\n");
1501                         return ret;
1502                 }
1503         } else {
1504                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, true);
1505                 if (ret) {
1506                         pr_err("[GetSclks]: fail to get max SMU_GFXCLK\n");
1507                         return ret;
1508                 }
1509         }
1510
1511         return (gfx_clk * 100);
1512 }
1513
1514 static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low)
1515 {
1516         uint32_t mem_clk;
1517         int ret;
1518
1519         if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1520                 pr_err("[GetMclks]: memclk dpm not enabled!\n");
1521                 return -EPERM;
1522         }
1523
1524         if (low) {
1525                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_UCLK, false);
1526                 if (ret) {
1527                         pr_err("[GetMclks]: fail to get min SMU_UCLK\n");
1528                         return ret;
1529                 }
1530         } else {
1531                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_GFXCLK, true);
1532                 if (ret) {
1533                         pr_err("[GetMclks]: fail to get max SMU_UCLK\n");
1534                         return ret;
1535                 }
1536         }
1537
1538         return (mem_clk * 100);
1539 }
1540
1541 static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
1542                                               bool initialize)
1543 {
1544         struct smu_table_context *table_context = &smu->smu_table;
1545         struct smu_table *table = &table_context->tables[SMU_TABLE_OVERDRIVE];
1546         int ret;
1547
1548         /**
1549          * TODO: Enable overdrive for navi10, that replies on smc/pptable
1550          * support.
1551          */
1552         if (smu->adev->asic_type == CHIP_NAVI10)
1553                 return 0;
1554
1555         if (initialize) {
1556                 if (table_context->overdrive_table)
1557                         return -EINVAL;
1558
1559                 table_context->overdrive_table = kzalloc(table->size, GFP_KERNEL);
1560
1561                 if (!table_context->overdrive_table)
1562                         return -ENOMEM;
1563
1564                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1565                                        table_context->overdrive_table, false);
1566                 if (ret) {
1567                         pr_err("Failed to export over drive table!\n");
1568                         return ret;
1569                 }
1570
1571                 smu_set_default_od8_settings(smu);
1572         }
1573
1574         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1575                                table_context->overdrive_table, true);
1576         if (ret) {
1577                 pr_err("Failed to import over drive table!\n");
1578                 return ret;
1579         }
1580
1581         return 0;
1582 }
1583
1584 static int smu_v11_0_update_od8_settings(struct smu_context *smu,
1585                                         uint32_t index,
1586                                         uint32_t value)
1587 {
1588         struct smu_table_context *table_context = &smu->smu_table;
1589         int ret;
1590
1591         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1592                                table_context->overdrive_table, false);
1593         if (ret) {
1594                 pr_err("Failed to export over drive table!\n");
1595                 return ret;
1596         }
1597
1598         smu_update_specified_od8_value(smu, index, value);
1599
1600         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1601                                table_context->overdrive_table, true);
1602         if (ret) {
1603                 pr_err("Failed to import over drive table!\n");
1604                 return ret;
1605         }
1606
1607         return 0;
1608 }
1609
1610 static int smu_v11_0_get_current_rpm(struct smu_context *smu,
1611                                      uint32_t *current_rpm)
1612 {
1613         int ret;
1614
1615         ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
1616
1617         if (ret) {
1618                 pr_err("Attempt to get current RPM from SMC Failed!\n");
1619                 return ret;
1620         }
1621
1622         smu_read_smc_arg(smu, current_rpm);
1623
1624         return 0;
1625 }
1626
1627 static uint32_t
1628 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1629 {
1630         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1631                 return AMD_FAN_CTRL_MANUAL;
1632         else
1633                 return AMD_FAN_CTRL_AUTO;
1634 }
1635
1636 static int
1637 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1638 {
1639         int ret = 0;
1640
1641         if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1642                 return 0;
1643
1644         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1645         if (ret)
1646                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1647                        __func__, (start ? "Start" : "Stop"));
1648
1649         return ret;
1650 }
1651
1652 static int
1653 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1654 {
1655         struct amdgpu_device *adev = smu->adev;
1656
1657         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1658                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1659                                    CG_FDO_CTRL2, TMIN, 0));
1660         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1661                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1662                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1663
1664         return 0;
1665 }
1666
1667 static int
1668 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1669 {
1670         struct amdgpu_device *adev = smu->adev;
1671         uint32_t duty100;
1672         uint32_t duty;
1673         uint64_t tmp64;
1674         bool stop = 0;
1675
1676         if (speed > 100)
1677                 speed = 100;
1678
1679         if (smu_v11_0_smc_fan_control(smu, stop))
1680                 return -EINVAL;
1681         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1682                                 CG_FDO_CTRL1, FMAX_DUTY100);
1683         if (!duty100)
1684                 return -EINVAL;
1685
1686         tmp64 = (uint64_t)speed * duty100;
1687         do_div(tmp64, 100);
1688         duty = (uint32_t)tmp64;
1689
1690         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1691                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1692                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1693
1694         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1695 }
1696
1697 static int
1698 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1699                                uint32_t mode)
1700 {
1701         int ret = 0;
1702         bool start = 1;
1703         bool stop  = 0;
1704
1705         switch (mode) {
1706         case AMD_FAN_CTRL_NONE:
1707                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1708                 break;
1709         case AMD_FAN_CTRL_MANUAL:
1710                 ret = smu_v11_0_smc_fan_control(smu, stop);
1711                 break;
1712         case AMD_FAN_CTRL_AUTO:
1713                 ret = smu_v11_0_smc_fan_control(smu, start);
1714                 break;
1715         default:
1716                 break;
1717         }
1718
1719         if (ret) {
1720                 pr_err("[%s]Set fan control mode failed!", __func__);
1721                 return -EINVAL;
1722         }
1723
1724         return ret;
1725 }
1726
1727 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1728                                        uint32_t speed)
1729 {
1730         struct amdgpu_device *adev = smu->adev;
1731         int ret;
1732         uint32_t tach_period, crystal_clock_freq;
1733         bool stop = 0;
1734
1735         if (!speed)
1736                 return -EINVAL;
1737
1738         mutex_lock(&(smu->mutex));
1739         ret = smu_v11_0_smc_fan_control(smu, stop);
1740         if (ret)
1741                 goto set_fan_speed_rpm_failed;
1742
1743         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1744         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1745         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1746                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1747                                    CG_TACH_CTRL, TARGET_PERIOD,
1748                                    tach_period));
1749
1750         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1751
1752 set_fan_speed_rpm_failed:
1753         mutex_unlock(&(smu->mutex));
1754         return ret;
1755 }
1756
1757 #define XGMI_STATE_D0 1
1758 #define XGMI_STATE_D3 0
1759
1760 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1761                                      uint32_t pstate)
1762 {
1763         int ret = 0;
1764         mutex_lock(&(smu->mutex));
1765         ret = smu_send_smc_msg_with_param(smu,
1766                                           SMU_MSG_SetXgmiMode,
1767                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1768         mutex_unlock(&(smu->mutex));
1769         return ret;
1770 }
1771
1772 static const struct smu_funcs smu_v11_0_funcs = {
1773         .init_microcode = smu_v11_0_init_microcode,
1774         .load_microcode = smu_v11_0_load_microcode,
1775         .check_fw_status = smu_v11_0_check_fw_status,
1776         .check_fw_version = smu_v11_0_check_fw_version,
1777         .send_smc_msg = smu_v11_0_send_msg,
1778         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1779         .read_smc_arg = smu_v11_0_read_arg,
1780         .setup_pptable = smu_v11_0_setup_pptable,
1781         .init_smc_tables = smu_v11_0_init_smc_tables,
1782         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1783         .init_power = smu_v11_0_init_power,
1784         .fini_power = smu_v11_0_fini_power,
1785         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1786         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1787         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1788         .check_pptable = smu_v11_0_check_pptable,
1789         .parse_pptable = smu_v11_0_parse_pptable,
1790         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1791         .write_pptable = smu_v11_0_write_pptable,
1792         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1793         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1794         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1795         .init_display = smu_v11_0_init_display,
1796         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1797         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1798         .system_features_control = smu_v11_0_system_features_control,
1799         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1800         .notify_display_change = smu_v11_0_notify_display_change,
1801         .get_power_limit = smu_v11_0_get_power_limit,
1802         .set_power_limit = smu_v11_0_set_power_limit,
1803         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1804         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1805         .start_thermal_control = smu_v11_0_start_thermal_control,
1806         .read_sensor = smu_v11_0_read_sensor,
1807         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1808         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1809         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1810         .get_sclk = smu_v11_0_dpm_get_sclk,
1811         .get_mclk = smu_v11_0_dpm_get_mclk,
1812         .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
1813         .update_od8_settings = smu_v11_0_update_od8_settings,
1814         .get_current_rpm = smu_v11_0_get_current_rpm,
1815         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1816         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1817         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1818         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1819         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1820         .gfx_off_control = smu_v11_0_gfx_off_control,
1821 };
1822
1823 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1824 {
1825         struct amdgpu_device *adev = smu->adev;
1826
1827         smu->funcs = &smu_v11_0_funcs;
1828         switch (adev->asic_type) {
1829         case CHIP_VEGA20:
1830                 vega20_set_ppt_funcs(smu);
1831                 break;
1832         case CHIP_NAVI10:
1833                 navi10_set_ppt_funcs(smu);
1834                 break;
1835         default:
1836                 pr_warn("Unknown asic for smu11\n");
1837         }
1838 }