2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
26 #include "amdgpu_smu.h"
27 #include "atomfirmware.h"
28 #include "amdgpu_atomfirmware.h"
29 #include "smu_v11_0.h"
30 #include "soc15_common.h"
32 #include "vega20_ppt.h"
33 #include "navi10_ppt.h"
34 #include "pp_thermal.h"
36 #include "asic_reg/thm/thm_11_0_2_offset.h"
37 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
38 #include "asic_reg/mp/mp_11_0_offset.h"
39 #include "asic_reg/mp/mp_11_0_sh_mask.h"
40 #include "asic_reg/nbio/nbio_7_4_offset.h"
41 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
42 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
44 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
45 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
47 #define SMU11_THERMAL_MINIMUM_ALERT_TEMP 0
48 #define SMU11_THERMAL_MAXIMUM_ALERT_TEMP 255
50 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
51 #define SMU11_VOLTAGE_SCALE 4
53 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
56 struct amdgpu_device *adev = smu->adev;
57 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
61 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
63 struct amdgpu_device *adev = smu->adev;
65 *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
69 static int smu_v11_0_wait_for_response(struct smu_context *smu)
71 struct amdgpu_device *adev = smu->adev;
72 uint32_t cur_value, i;
74 for (i = 0; i < adev->usec_timeout; i++) {
75 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
76 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
81 /* timeout means wrong logic */
82 if (i == adev->usec_timeout)
85 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
88 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
90 struct amdgpu_device *adev = smu->adev;
91 int ret = 0, index = 0;
93 index = smu_msg_get_index(smu, msg);
97 smu_v11_0_wait_for_response(smu);
99 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
101 smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
103 ret = smu_v11_0_wait_for_response(smu);
106 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
114 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
118 struct amdgpu_device *adev = smu->adev;
119 int ret = 0, index = 0;
121 index = smu_msg_get_index(smu, msg);
125 ret = smu_v11_0_wait_for_response(smu);
127 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
130 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
132 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
134 smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
136 ret = smu_v11_0_wait_for_response(smu);
138 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
144 static int smu_v11_0_init_microcode(struct smu_context *smu)
146 struct amdgpu_device *adev = smu->adev;
147 const char *chip_name;
150 const struct smc_firmware_header_v1_0 *hdr;
151 const struct common_firmware_header *header;
152 struct amdgpu_firmware_info *ucode = NULL;
154 switch (adev->asic_type) {
156 chip_name = "vega20";
159 chip_name = "navi10";
165 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
167 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
170 err = amdgpu_ucode_validate(adev->pm.fw);
174 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
175 amdgpu_ucode_print_smc_hdr(&hdr->header);
176 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
178 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
179 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
180 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
181 ucode->fw = adev->pm.fw;
182 header = (const struct common_firmware_header *)ucode->fw->data;
183 adev->firmware.fw_size +=
184 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
189 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
191 release_firmware(adev->pm.fw);
197 static int smu_v11_0_load_microcode(struct smu_context *smu)
199 struct amdgpu_device *adev = smu->adev;
201 const struct smc_firmware_header_v1_0 *hdr;
202 uint32_t addr_start = MP1_SRAM;
204 uint32_t mp1_fw_flags;
206 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
207 src = (const uint32_t *)(adev->pm.fw->data +
208 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
210 for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
211 WREG32_PCIE(addr_start, src[i]);
215 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
216 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
217 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
218 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
220 for (i = 0; i < adev->usec_timeout; i++) {
221 mp1_fw_flags = RREG32_PCIE(MP1_Public |
222 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
223 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
224 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
229 if (i == adev->usec_timeout)
235 static int smu_v11_0_check_fw_status(struct smu_context *smu)
237 struct amdgpu_device *adev = smu->adev;
238 uint32_t mp1_fw_flags;
240 mp1_fw_flags = RREG32_PCIE(MP1_Public |
241 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
243 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
244 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
250 static int smu_v11_0_check_fw_version(struct smu_context *smu)
252 uint32_t if_version = 0xff, smu_version = 0xff;
254 uint8_t smu_minor, smu_debug;
257 ret = smu_get_smc_version(smu, &if_version, &smu_version);
261 smu_major = (smu_version >> 16) & 0xffff;
262 smu_minor = (smu_version >> 8) & 0xff;
263 smu_debug = (smu_version >> 0) & 0xff;
265 pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x (%d.%d.%d)\n",
266 if_version, smu_version, smu_major, smu_minor, smu_debug);
268 if (if_version != smu->smc_if_version) {
269 pr_err("SMU driver if version not matched\n");
276 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
278 struct amdgpu_device *adev = smu->adev;
279 uint32_t ppt_offset_bytes;
280 const struct smc_firmware_header_v2_0 *v2;
282 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
284 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
285 *size = le32_to_cpu(v2->ppt_size_bytes);
286 *table = (uint8_t *)v2 + ppt_offset_bytes;
291 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
293 struct amdgpu_device *adev = smu->adev;
294 const struct smc_firmware_header_v2_1 *v2_1;
295 struct smc_soft_pptable_entry *entries;
296 uint32_t pptable_count = 0;
299 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
300 entries = (struct smc_soft_pptable_entry *)
301 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
302 pptable_count = le32_to_cpu(v2_1->pptable_count);
303 for (i = 0; i < pptable_count; i++) {
304 if (le32_to_cpu(entries[i].id) == pptable_id) {
305 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
306 *size = le32_to_cpu(entries[i].ppt_size_bytes);
311 if (i == pptable_count)
317 static int smu_v11_0_setup_pptable(struct smu_context *smu)
319 struct amdgpu_device *adev = smu->adev;
320 const struct smc_firmware_header_v1_0 *hdr;
325 uint16_t version_major, version_minor;
327 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
328 version_major = le16_to_cpu(hdr->header.header_version_major);
329 version_minor = le16_to_cpu(hdr->header.header_version_minor);
331 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
332 switch (version_minor) {
334 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
337 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
338 smu->smu_table.boot_values.pp_table_id);
348 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
351 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
357 if (!smu->smu_table.power_play_table)
358 smu->smu_table.power_play_table = table;
359 if (!smu->smu_table.power_play_table_size)
360 smu->smu_table.power_play_table_size = size;
365 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
367 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
369 if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
372 return smu_alloc_dpm_context(smu);
375 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
377 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
379 if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
382 kfree(smu_dpm->dpm_context);
383 kfree(smu_dpm->golden_dpm_context);
384 kfree(smu_dpm->dpm_current_power_state);
385 kfree(smu_dpm->dpm_request_power_state);
386 smu_dpm->dpm_context = NULL;
387 smu_dpm->golden_dpm_context = NULL;
388 smu_dpm->dpm_context_size = 0;
389 smu_dpm->dpm_current_power_state = NULL;
390 smu_dpm->dpm_request_power_state = NULL;
395 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
397 struct smu_table_context *smu_table = &smu->smu_table;
398 struct smu_table *tables = NULL;
401 if (smu_table->tables || smu_table->table_count == 0)
404 tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
409 smu_table->tables = tables;
411 smu_tables_init(smu, tables);
413 ret = smu_v11_0_init_dpm_context(smu);
420 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
422 struct smu_table_context *smu_table = &smu->smu_table;
425 if (!smu_table->tables || smu_table->table_count == 0)
428 kfree(smu_table->tables);
429 smu_table->tables = NULL;
430 smu_table->table_count = 0;
432 ret = smu_v11_0_fini_dpm_context(smu);
438 static int smu_v11_0_init_power(struct smu_context *smu)
440 struct smu_power_context *smu_power = &smu->smu_power;
442 if (!smu->pm_enabled)
444 if (smu_power->power_context || smu_power->power_context_size != 0)
447 smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
449 if (!smu_power->power_context)
451 smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
453 smu->metrics_time = 0;
454 smu->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
455 if (!smu->metrics_table) {
456 kfree(smu_power->power_context);
463 static int smu_v11_0_fini_power(struct smu_context *smu)
465 struct smu_power_context *smu_power = &smu->smu_power;
467 if (!smu->pm_enabled)
469 if (!smu_power->power_context || smu_power->power_context_size == 0)
472 kfree(smu->metrics_table);
473 kfree(smu_power->power_context);
474 smu->metrics_table = NULL;
475 smu_power->power_context = NULL;
476 smu_power->power_context_size = 0;
481 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
486 struct atom_common_table_header *header;
487 struct atom_firmware_info_v3_3 *v_3_3;
488 struct atom_firmware_info_v3_1 *v_3_1;
490 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
493 ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
494 (uint8_t **)&header);
498 if (header->format_revision != 3) {
499 pr_err("unknown atom_firmware_info version! for smu11\n");
503 switch (header->content_revision) {
507 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
508 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
509 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
510 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
511 smu->smu_table.boot_values.socclk = 0;
512 smu->smu_table.boot_values.dcefclk = 0;
513 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
514 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
515 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
516 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
517 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
518 smu->smu_table.boot_values.pp_table_id = 0;
522 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
523 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
524 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
525 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
526 smu->smu_table.boot_values.socclk = 0;
527 smu->smu_table.boot_values.dcefclk = 0;
528 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
529 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
530 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
531 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
532 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
533 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
539 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
542 struct amdgpu_device *adev = smu->adev;
543 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
544 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
546 input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
547 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
548 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
551 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
556 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
557 smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
559 memset(&input, 0, sizeof(input));
560 input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
561 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
562 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
565 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
570 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
571 smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
573 memset(&input, 0, sizeof(input));
574 input.clk_id = SMU11_SYSPLL0_ECLK_ID;
575 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
576 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
579 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
584 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
585 smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
587 memset(&input, 0, sizeof(input));
588 input.clk_id = SMU11_SYSPLL0_VCLK_ID;
589 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
590 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
593 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
598 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
599 smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
601 memset(&input, 0, sizeof(input));
602 input.clk_id = SMU11_SYSPLL0_DCLK_ID;
603 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
604 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
607 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
612 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
613 smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
618 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
620 struct smu_table_context *smu_table = &smu->smu_table;
621 struct smu_table *memory_pool = &smu_table->memory_pool;
624 uint32_t address_low, address_high;
626 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
629 address = (uintptr_t)memory_pool->cpu_addr;
630 address_high = (uint32_t)upper_32_bits(address);
631 address_low = (uint32_t)lower_32_bits(address);
633 ret = smu_send_smc_msg_with_param(smu,
634 SMU_MSG_SetSystemVirtualDramAddrHigh,
638 ret = smu_send_smc_msg_with_param(smu,
639 SMU_MSG_SetSystemVirtualDramAddrLow,
644 address = memory_pool->mc_address;
645 address_high = (uint32_t)upper_32_bits(address);
646 address_low = (uint32_t)lower_32_bits(address);
648 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
652 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
656 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
657 (uint32_t)memory_pool->size);
664 static int smu_v11_0_check_pptable(struct smu_context *smu)
668 ret = smu_check_powerplay_table(smu);
672 static int smu_v11_0_parse_pptable(struct smu_context *smu)
676 struct smu_table_context *table_context = &smu->smu_table;
677 struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
679 if (table_context->driver_pptable)
682 table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
684 if (!table_context->driver_pptable)
687 ret = smu_store_powerplay_table(smu);
691 ret = smu_append_powerplay_table(smu);
696 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
700 ret = smu_set_default_dpm_table(smu);
705 static int smu_v11_0_write_pptable(struct smu_context *smu)
707 struct smu_table_context *table_context = &smu->smu_table;
710 ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
711 table_context->driver_pptable, true);
716 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
718 return smu_update_table(smu, SMU_TABLE_WATERMARKS,
719 smu->smu_table.tables[SMU_TABLE_WATERMARKS].cpu_addr,
723 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
727 ret = smu_send_smc_msg_with_param(smu,
728 SMU_MSG_SetMinDeepSleepDcefclk, clk);
730 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
735 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
737 struct smu_table_context *table_context = &smu->smu_table;
739 if (!smu->pm_enabled)
744 return smu_set_deep_sleep_dcefclk(smu,
745 table_context->boot_values.dcefclk / 100);
748 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
751 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
753 if (tool_table->mc_address) {
754 ret = smu_send_smc_msg_with_param(smu,
755 SMU_MSG_SetToolsDramAddrHigh,
756 upper_32_bits(tool_table->mc_address));
758 ret = smu_send_smc_msg_with_param(smu,
759 SMU_MSG_SetToolsDramAddrLow,
760 lower_32_bits(tool_table->mc_address));
766 static int smu_v11_0_init_display(struct smu_context *smu)
770 if (!smu->pm_enabled)
772 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
776 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
778 uint32_t feature_low = 0, feature_high = 0;
781 if (!smu->pm_enabled)
783 if (feature_id >= 0 && feature_id < 31)
784 feature_low = (1 << feature_id);
785 else if (feature_id > 31 && feature_id < 63)
786 feature_high = (1 << feature_id);
791 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
795 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
801 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
805 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
815 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
817 struct smu_feature *feature = &smu->smu_feature;
819 uint32_t feature_mask[2];
821 mutex_lock(&feature->mutex);
822 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
825 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
827 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
832 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
838 mutex_unlock(&feature->mutex);
842 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
843 uint32_t *feature_mask, uint32_t num)
845 uint32_t feature_mask_high = 0, feature_mask_low = 0;
848 if (!feature_mask || num < 2)
851 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
854 ret = smu_read_smc_arg(smu, &feature_mask_high);
858 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
861 ret = smu_read_smc_arg(smu, &feature_mask_low);
865 feature_mask[0] = feature_mask_low;
866 feature_mask[1] = feature_mask_high;
871 static int smu_v11_0_system_features_control(struct smu_context *smu,
874 struct smu_feature *feature = &smu->smu_feature;
875 uint32_t feature_mask[2];
878 if (smu->pm_enabled) {
879 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
880 SMU_MSG_DisableAllSmuFeatures));
885 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
889 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
890 feature->feature_num);
891 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
892 feature->feature_num);
897 static int smu_v11_0_notify_display_change(struct smu_context *smu)
901 if (!smu->pm_enabled)
903 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
904 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
910 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
911 enum smu_clk_type clock_select)
915 if (!smu->pm_enabled)
917 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
918 smu_clk_get_index(smu, clock_select) << 16);
920 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
924 ret = smu_read_smc_arg(smu, clock);
931 /* if DC limit is zero, return AC limit */
932 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
933 smu_clk_get_index(smu, clock_select) << 16);
935 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
939 ret = smu_read_smc_arg(smu, clock);
944 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
946 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
949 max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
951 smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
953 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
954 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
955 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
956 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
957 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
958 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
960 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
961 ret = smu_v11_0_get_max_sustainable_clock(smu,
962 &(max_sustainable_clocks->uclock),
965 pr_err("[%s] failed to get max UCLK from SMC!",
971 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
972 ret = smu_v11_0_get_max_sustainable_clock(smu,
973 &(max_sustainable_clocks->soc_clock),
976 pr_err("[%s] failed to get max SOCCLK from SMC!",
982 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
983 ret = smu_v11_0_get_max_sustainable_clock(smu,
984 &(max_sustainable_clocks->dcef_clock),
987 pr_err("[%s] failed to get max DCEFCLK from SMC!",
992 ret = smu_v11_0_get_max_sustainable_clock(smu,
993 &(max_sustainable_clocks->display_clock),
996 pr_err("[%s] failed to get max DISPCLK from SMC!",
1000 ret = smu_v11_0_get_max_sustainable_clock(smu,
1001 &(max_sustainable_clocks->phy_clock),
1004 pr_err("[%s] failed to get max PHYCLK from SMC!",
1008 ret = smu_v11_0_get_max_sustainable_clock(smu,
1009 &(max_sustainable_clocks->pixel_clock),
1012 pr_err("[%s] failed to get max PIXCLK from SMC!",
1018 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1019 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1024 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1031 mutex_lock(&smu->mutex);
1032 *limit = smu->default_power_limit;
1033 if (smu->od_enabled) {
1034 *limit *= (100 + smu->smu_table.TDPODLimit);
1037 mutex_unlock(&smu->mutex);
1039 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1040 smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
1042 pr_err("[%s] get PPT limit failed!", __func__);
1045 smu_read_smc_arg(smu, limit);
1046 smu->power_limit = *limit;
1052 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1054 uint32_t max_power_limit;
1058 n = smu->default_power_limit;
1060 max_power_limit = smu->default_power_limit;
1062 if (smu->od_enabled) {
1063 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1064 max_power_limit /= 100;
1067 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1068 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1070 pr_err("[%s] Set power limit Failed!", __func__);
1077 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1078 enum smu_clk_type clk_id,
1084 if (clk_id >= SMU_CLK_COUNT || !value)
1087 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1088 (smu_clk_get_index(smu, clk_id) << 16));
1092 ret = smu_read_smc_arg(smu, &freq);
1102 static int smu_v11_0_get_thermal_range(struct smu_context *smu,
1103 struct PP_TemperatureRange *range)
1105 PPTable_t *pptable = smu->smu_table.driver_pptable;
1106 memcpy(range, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
1108 range->max = pptable->TedgeLimit *
1109 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1110 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1111 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1112 range->hotspot_crit_max = pptable->ThotspotLimit *
1113 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1114 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1115 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1116 range->mem_crit_max = pptable->ThbmLimit *
1117 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1118 range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
1119 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1124 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1125 struct PP_TemperatureRange *range)
1127 struct amdgpu_device *adev = smu->adev;
1128 int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
1129 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1130 int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
1131 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1134 if (low < range->min)
1136 if (high > range->max)
1142 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1143 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1144 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1145 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1146 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1147 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1149 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1154 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1156 struct amdgpu_device *adev = smu->adev;
1159 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1160 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1161 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1163 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1168 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1171 struct PP_TemperatureRange range = {
1181 struct amdgpu_device *adev = smu->adev;
1183 if (!smu->pm_enabled)
1185 smu_v11_0_get_thermal_range(smu, &range);
1187 if (smu->smu_table.thermal_controller_type) {
1188 ret = smu_v11_0_set_thermal_range(smu, &range);
1192 ret = smu_v11_0_enable_thermal_alert(smu);
1195 ret = smu_set_thermal_fan_table(smu);
1200 adev->pm.dpm.thermal.min_temp = range.min;
1201 adev->pm.dpm.thermal.max_temp = range.max;
1202 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1203 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1204 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1205 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1206 adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1207 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1208 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1213 static int smu_v11_0_get_metrics_table(struct smu_context *smu,
1214 SmuMetrics_t *metrics_table)
1218 if (!smu->metrics_time || time_after(jiffies, smu->metrics_time + HZ / 1000)) {
1219 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
1220 (void *)metrics_table, false);
1222 pr_info("Failed to export SMU metrics table!\n");
1225 memcpy(smu->metrics_table, metrics_table, sizeof(SmuMetrics_t));
1226 smu->metrics_time = jiffies;
1228 memcpy(metrics_table, smu->metrics_table, sizeof(SmuMetrics_t));
1233 static int smu_v11_0_thermal_get_temperature(struct smu_context *smu,
1234 enum amd_pp_sensors sensor,
1237 struct amdgpu_device *adev = smu->adev;
1238 SmuMetrics_t metrics;
1245 ret = smu_v11_0_get_metrics_table(smu, &metrics);
1250 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1251 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
1252 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
1253 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
1255 temp = temp & 0x1ff;
1256 temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
1260 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1261 *value = metrics.TemperatureEdge *
1262 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1264 case AMDGPU_PP_SENSOR_MEM_TEMP:
1265 *value = metrics.TemperatureHBM *
1266 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1269 pr_err("Invalid sensor for retrieving temp\n");
1276 static uint16_t convert_to_vddc(uint8_t vid)
1278 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1281 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1283 struct amdgpu_device *adev = smu->adev;
1284 uint32_t vdd = 0, val_vid = 0;
1288 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1289 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1290 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1292 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1300 static int smu_v11_0_read_sensor(struct smu_context *smu,
1301 enum amd_pp_sensors sensor,
1302 void *data, uint32_t *size)
1306 case AMDGPU_PP_SENSOR_GPU_LOAD:
1307 case AMDGPU_PP_SENSOR_MEM_LOAD:
1308 ret = smu_get_current_activity_percent(smu,
1313 case AMDGPU_PP_SENSOR_GFX_MCLK:
1314 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1317 case AMDGPU_PP_SENSOR_GFX_SCLK:
1318 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1321 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1322 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1323 case AMDGPU_PP_SENSOR_MEM_TEMP:
1324 ret = smu_v11_0_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1327 case AMDGPU_PP_SENSOR_GPU_POWER:
1328 ret = smu_get_gpu_power(smu, (uint32_t *)data);
1331 case AMDGPU_PP_SENSOR_VDDGFX:
1332 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1335 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1336 *(uint32_t *)data = 0;
1340 ret = smu_common_read_sensor(smu, sensor, data, size);
1344 /* try get sensor data by asic */
1346 ret = smu_asic_read_sensor(smu, sensor, data, size);
1355 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1356 struct pp_display_clock_request
1359 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1361 enum smu_clk_type clk_select = 0;
1362 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1364 if (!smu->pm_enabled)
1366 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1368 case amd_pp_dcef_clock:
1369 clk_select = SMU_DCEFCLK;
1371 case amd_pp_disp_clock:
1372 clk_select = SMU_DISPCLK;
1374 case amd_pp_pixel_clock:
1375 clk_select = SMU_PIXCLK;
1377 case amd_pp_phy_clock:
1378 clk_select = SMU_PHYCLK;
1381 pr_info("[%s] Invalid Clock Type!", __func__);
1389 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1390 (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1398 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1399 dm_pp_wm_sets_with_clock_ranges_soc15
1403 struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1404 void *table = watermarks->cpu_addr;
1406 if (!smu->disable_watermark &&
1407 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1408 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1409 smu_set_watermarks_table(smu, table, clock_ranges);
1410 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1411 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1417 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1420 struct amdgpu_device *adev = smu->adev;
1422 switch (adev->asic_type) {
1426 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1428 mutex_lock(&smu->mutex);
1430 ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1432 ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1433 mutex_unlock(&smu->mutex);
1443 static int smu_v11_0_get_clock_ranges(struct smu_context *smu,
1445 enum smu_clk_type clock_select,
1451 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
1452 smu_clk_get_index(smu, clock_select) << 16);
1454 pr_err("[GetClockRanges] Failed to get max clock from SMC!\n");
1457 smu_read_smc_arg(smu, clock);
1459 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq,
1460 smu_clk_get_index(smu, clock_select) << 16);
1462 pr_err("[GetClockRanges] Failed to get min clock from SMC!\n");
1465 smu_read_smc_arg(smu, clock);
1471 static uint32_t smu_v11_0_dpm_get_sclk(struct smu_context *smu, bool low)
1476 if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1477 pr_err("[GetSclks]: gfxclk dpm not enabled!\n");
1482 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, false);
1484 pr_err("[GetSclks]: fail to get min SMU_GFXCLK\n");
1488 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, true);
1490 pr_err("[GetSclks]: fail to get max SMU_GFXCLK\n");
1495 return (gfx_clk * 100);
1498 static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low)
1503 if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1504 pr_err("[GetMclks]: memclk dpm not enabled!\n");
1509 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_UCLK, false);
1511 pr_err("[GetMclks]: fail to get min SMU_UCLK\n");
1515 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_GFXCLK, true);
1517 pr_err("[GetMclks]: fail to get max SMU_UCLK\n");
1522 return (mem_clk * 100);
1525 static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
1528 struct smu_table_context *table_context = &smu->smu_table;
1529 struct smu_table *table = &table_context->tables[SMU_TABLE_OVERDRIVE];
1533 * TODO: Enable overdrive for navi10, that replies on smc/pptable
1536 if (smu->adev->asic_type == CHIP_NAVI10)
1540 if (table_context->overdrive_table)
1543 table_context->overdrive_table = kzalloc(table->size, GFP_KERNEL);
1545 if (!table_context->overdrive_table)
1548 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1549 table_context->overdrive_table, false);
1551 pr_err("Failed to export over drive table!\n");
1555 smu_set_default_od8_settings(smu);
1558 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1559 table_context->overdrive_table, true);
1561 pr_err("Failed to import over drive table!\n");
1568 static int smu_v11_0_update_od8_settings(struct smu_context *smu,
1572 struct smu_table_context *table_context = &smu->smu_table;
1575 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1576 table_context->overdrive_table, false);
1578 pr_err("Failed to export over drive table!\n");
1582 smu_update_specified_od8_value(smu, index, value);
1584 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1585 table_context->overdrive_table, true);
1587 pr_err("Failed to import over drive table!\n");
1594 static int smu_v11_0_get_current_rpm(struct smu_context *smu,
1595 uint32_t *current_rpm)
1599 ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
1602 pr_err("Attempt to get current RPM from SMC Failed!\n");
1606 smu_read_smc_arg(smu, current_rpm);
1612 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1614 if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1615 return AMD_FAN_CTRL_MANUAL;
1617 return AMD_FAN_CTRL_AUTO;
1621 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1625 if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1628 ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1630 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1631 __func__, (start ? "Start" : "Stop"));
1637 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1639 struct amdgpu_device *adev = smu->adev;
1641 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1642 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1643 CG_FDO_CTRL2, TMIN, 0));
1644 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1645 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1646 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1652 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1654 struct amdgpu_device *adev = smu->adev;
1663 if (smu_v11_0_smc_fan_control(smu, stop))
1665 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1666 CG_FDO_CTRL1, FMAX_DUTY100);
1670 tmp64 = (uint64_t)speed * duty100;
1672 duty = (uint32_t)tmp64;
1674 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1675 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1676 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1678 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1682 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1690 case AMD_FAN_CTRL_NONE:
1691 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1693 case AMD_FAN_CTRL_MANUAL:
1694 ret = smu_v11_0_smc_fan_control(smu, stop);
1696 case AMD_FAN_CTRL_AUTO:
1697 ret = smu_v11_0_smc_fan_control(smu, start);
1704 pr_err("[%s]Set fan control mode failed!", __func__);
1711 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1714 struct amdgpu_device *adev = smu->adev;
1716 uint32_t tach_period, crystal_clock_freq;
1722 mutex_lock(&(smu->mutex));
1723 ret = smu_v11_0_smc_fan_control(smu, stop);
1725 goto set_fan_speed_rpm_failed;
1727 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1728 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1729 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1730 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1731 CG_TACH_CTRL, TARGET_PERIOD,
1734 ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1736 set_fan_speed_rpm_failed:
1737 mutex_unlock(&(smu->mutex));
1741 #define XGMI_STATE_D0 1
1742 #define XGMI_STATE_D3 0
1744 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1748 mutex_lock(&(smu->mutex));
1749 ret = smu_send_smc_msg_with_param(smu,
1750 SMU_MSG_SetXgmiMode,
1751 pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1752 mutex_unlock(&(smu->mutex));
1756 static const struct smu_funcs smu_v11_0_funcs = {
1757 .init_microcode = smu_v11_0_init_microcode,
1758 .load_microcode = smu_v11_0_load_microcode,
1759 .check_fw_status = smu_v11_0_check_fw_status,
1760 .check_fw_version = smu_v11_0_check_fw_version,
1761 .send_smc_msg = smu_v11_0_send_msg,
1762 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1763 .read_smc_arg = smu_v11_0_read_arg,
1764 .setup_pptable = smu_v11_0_setup_pptable,
1765 .init_smc_tables = smu_v11_0_init_smc_tables,
1766 .fini_smc_tables = smu_v11_0_fini_smc_tables,
1767 .init_power = smu_v11_0_init_power,
1768 .fini_power = smu_v11_0_fini_power,
1769 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1770 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1771 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1772 .check_pptable = smu_v11_0_check_pptable,
1773 .parse_pptable = smu_v11_0_parse_pptable,
1774 .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1775 .write_pptable = smu_v11_0_write_pptable,
1776 .write_watermarks_table = smu_v11_0_write_watermarks_table,
1777 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1778 .set_tool_table_location = smu_v11_0_set_tool_table_location,
1779 .init_display = smu_v11_0_init_display,
1780 .set_allowed_mask = smu_v11_0_set_allowed_mask,
1781 .get_enabled_mask = smu_v11_0_get_enabled_mask,
1782 .system_features_control = smu_v11_0_system_features_control,
1783 .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1784 .notify_display_change = smu_v11_0_notify_display_change,
1785 .get_power_limit = smu_v11_0_get_power_limit,
1786 .set_power_limit = smu_v11_0_set_power_limit,
1787 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1788 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1789 .start_thermal_control = smu_v11_0_start_thermal_control,
1790 .read_sensor = smu_v11_0_read_sensor,
1791 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1792 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1793 .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1794 .get_sclk = smu_v11_0_dpm_get_sclk,
1795 .get_mclk = smu_v11_0_dpm_get_mclk,
1796 .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
1797 .update_od8_settings = smu_v11_0_update_od8_settings,
1798 .get_current_rpm = smu_v11_0_get_current_rpm,
1799 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1800 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1801 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1802 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1803 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1804 .gfx_off_control = smu_v11_0_gfx_off_control,
1807 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1809 struct amdgpu_device *adev = smu->adev;
1811 smu->funcs = &smu_v11_0_funcs;
1812 switch (adev->asic_type) {
1814 vega20_set_ppt_funcs(smu);
1817 navi10_set_ppt_funcs(smu);
1820 pr_warn("Unknown asic for smu11\n");