drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pp_debug.h"
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "atomfirmware.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "smu_v11_0.h"
  30 #include "smu_11_0_driver_if.h"
  31 #include "soc15_common.h"
  32 #include "atom.h"
  33 #include "vega20_ppt.h"
  34 #include "navi10_ppt.h"
  35 #include "pp_thermal.h"
  36
  37 #include "asic_reg/thm/thm_11_0_2_offset.h"
  38 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  39 #include "asic_reg/mp/mp_11_0_offset.h"
  40 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  41 #include "asic_reg/nbio/nbio_7_4_offset.h"
  42 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  43 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  44
  45 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  47
  48 #define SMU11_THERMAL_MINIMUM_ALERT_TEMP      0
  49 #define SMU11_THERMAL_MAXIMUM_ALERT_TEMP      255
  50
  51 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
  52 #define SMU11_VOLTAGE_SCALE 4
  53
  54 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  55                                               uint16_t msg)
  56 {
  57         struct amdgpu_device *adev = smu->adev;
  58         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  59         return 0;
  60 }
  61
  62 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  63 {
  64         struct amdgpu_device *adev = smu->adev;
  65
  66         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  67         return 0;
  68 }
  69
  70 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  71 {
  72         struct amdgpu_device *adev = smu->adev;
  73         uint32_t cur_value, i;
  74
  75         for (i = 0; i < adev->usec_timeout; i++) {
  76                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  77                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  78                         break;
  79                 udelay(1);
  80         }
  81
  82         /* timeout means wrong logic */
  83         if (i == adev->usec_timeout)
  84                 return -ETIME;
  85
  86         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  87 }
  88
  89 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  90 {
  91         struct amdgpu_device *adev = smu->adev;
  92         int ret = 0, index = 0;
  93
  94         index = smu_msg_get_index(smu, msg);
  95         if (index < 0)
  96                 return index;
  97
  98         smu_v11_0_wait_for_response(smu);
  99
 100         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 101
 102         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 103
 104         ret = smu_v11_0_wait_for_response(smu);
 105
 106         if (ret)
 107                 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 108                        ret);
 109
 110         return ret;
 111
 112 }
 113
 114 static int
 115 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 116                               uint32_t param)
 117 {
 118
 119         struct amdgpu_device *adev = smu->adev;
 120         int ret = 0, index = 0;
 121
 122         index = smu_msg_get_index(smu, msg);
 123         if (index < 0)
 124                 return index;
 125
 126         ret = smu_v11_0_wait_for_response(smu);
 127         if (ret)
 128                 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
 129                        index, ret, param);
 130
 131         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 132
 133         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 134
 135         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 136
 137         ret = smu_v11_0_wait_for_response(smu);
 138         if (ret)
 139                 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
 140                        index, ret, param);
 141
 142         return ret;
 143 }
 144
 145 static int smu_v11_0_init_microcode(struct smu_context *smu)
 146 {
 147         struct amdgpu_device *adev = smu->adev;
 148         const char *chip_name;
 149         char fw_name[30];
 150         int err = 0;
 151         const struct smc_firmware_header_v1_0 *hdr;
 152         const struct common_firmware_header *header;
 153         struct amdgpu_firmware_info *ucode = NULL;
 154
 155         switch (adev->asic_type) {
 156         case CHIP_VEGA20:
 157                 chip_name = "vega20";
 158                 break;
 159         case CHIP_NAVI10:
 160                 chip_name = "navi10";
 161                 break;
 162         default:
 163                 BUG();
 164         }
 165
 166         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 167
 168         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 169         if (err)
 170                 goto out;
 171         err = amdgpu_ucode_validate(adev->pm.fw);
 172         if (err)
 173                 goto out;
 174
 175         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 176         amdgpu_ucode_print_smc_hdr(&hdr->header);
 177         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 178
 179         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 180                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 181                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 182                 ucode->fw = adev->pm.fw;
 183                 header = (const struct common_firmware_header *)ucode->fw->data;
 184                 adev->firmware.fw_size +=
 185                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 186         }
 187
 188 out:
 189         if (err) {
 190                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 191                           fw_name);
 192                 release_firmware(adev->pm.fw);
 193                 adev->pm.fw = NULL;
 194         }
 195         return err;
 196 }
 197
 198 static int smu_v11_0_load_microcode(struct smu_context *smu)
 199 {
 200         struct amdgpu_device *adev = smu->adev;
 201         const uint32_t *src;
 202         const struct smc_firmware_header_v1_0 *hdr;
 203         uint32_t addr_start = MP1_SRAM;
 204         uint32_t i;
 205         uint32_t mp1_fw_flags;
 206
 207         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 208         src = (const uint32_t *)(adev->pm.fw->data +
 209                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 210
 211         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 212                 WREG32_PCIE(addr_start, src[i]);
 213                 addr_start += 4;
 214         }
 215
 216         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 217                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 218         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 219                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 220
 221         for (i = 0; i < adev->usec_timeout; i++) {
 222                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 223                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 224                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 225                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 226                         break;
 227                 udelay(1);
 228         }
 229
 230         if (i == adev->usec_timeout)
 231                 return -ETIME;
 232
 233         return 0;
 234 }
 235
 236 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 237 {
 238         struct amdgpu_device *adev = smu->adev;
 239         uint32_t mp1_fw_flags;
 240
 241         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 242                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 243
 244         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 245             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 246                 return 0;
 247
 248         return -EIO;
 249 }
 250
 251 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 252 {
 253         uint32_t if_version = 0xff, smu_version = 0xff;
 254         uint16_t smu_major;
 255         uint8_t smu_minor, smu_debug;
 256         int ret = 0;
 257
 258         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 259         if (ret)
 260                 return ret;
 261
 262         smu_major = (smu_version >> 16) & 0xffff;
 263         smu_minor = (smu_version >> 8) & 0xff;
 264         smu_debug = (smu_version >> 0) & 0xff;
 265
 266         pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x (%d.%d.%d)\n",
 267                 if_version, smu_version, smu_major, smu_minor, smu_debug);
 268
 269         if (if_version != smu->smc_if_version) {
 270                 pr_err("SMU driver if version not matched\n");
 271                 ret = -EINVAL;
 272         }
 273
 274         return ret;
 275 }
 276
 277 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 278 {
 279         struct amdgpu_device *adev = smu->adev;
 280         uint32_t ppt_offset_bytes;
 281         const struct smc_firmware_header_v2_0 *v2;
 282
 283         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 284
 285         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 286         *size = le32_to_cpu(v2->ppt_size_bytes);
 287         *table = (uint8_t *)v2 + ppt_offset_bytes;
 288
 289         return 0;
 290 }
 291
 292 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
 293 {
 294         struct amdgpu_device *adev = smu->adev;
 295         const struct smc_firmware_header_v2_1 *v2_1;
 296         struct smc_soft_pptable_entry *entries;
 297         uint32_t pptable_count = 0;
 298         int i = 0;
 299
 300         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 301         entries = (struct smc_soft_pptable_entry *)
 302                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 303         pptable_count = le32_to_cpu(v2_1->pptable_count);
 304         for (i = 0; i < pptable_count; i++) {
 305                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 306                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 307                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 308                         break;
 309                 }
 310         }
 311
 312         if (i == pptable_count)
 313                 return -EINVAL;
 314
 315         return 0;
 316 }
 317
 318 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 319 {
 320         struct amdgpu_device *adev = smu->adev;
 321         const struct smc_firmware_header_v1_0 *hdr;
 322         int ret, index;
 323         uint32_t size;
 324         uint8_t frev, crev;
 325         void *table;
 326         uint16_t version_major, version_minor;
 327
 328         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 329         version_major = le16_to_cpu(hdr->header.header_version_major);
 330         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 331
 332         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 333                 switch (version_minor) {
 334                 case 0:
 335                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 336                         break;
 337                 case 1:
 338                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 339                                                          smu->smu_table.boot_values.pp_table_id);
 340                         break;
 341                 default:
 342                         ret = -EINVAL;
 343                         break;
 344                 }
 345                 if (ret)
 346                         return ret;
 347
 348         } else {
 349                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 350                                                     powerplayinfo);
 351
 352                 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
 353                                               (uint8_t **)&table);
 354                 if (ret)
 355                         return ret;
 356         }
 357
 358         if (!smu->smu_table.power_play_table)
 359                 smu->smu_table.power_play_table = table;
 360         if (!smu->smu_table.power_play_table_size)
 361                 smu->smu_table.power_play_table_size = size;
 362
 363         return 0;
 364 }
 365
 366 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 367 {
 368         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 369
 370         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 371                 return -EINVAL;
 372
 373         return smu_alloc_dpm_context(smu);
 374 }
 375
 376 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 377 {
 378         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 379
 380         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 381                 return -EINVAL;
 382
 383         kfree(smu_dpm->dpm_context);
 384         kfree(smu_dpm->golden_dpm_context);
 385         kfree(smu_dpm->dpm_current_power_state);
 386         kfree(smu_dpm->dpm_request_power_state);
 387         smu_dpm->dpm_context = NULL;
 388         smu_dpm->golden_dpm_context = NULL;
 389         smu_dpm->dpm_context_size = 0;
 390         smu_dpm->dpm_current_power_state = NULL;
 391         smu_dpm->dpm_request_power_state = NULL;
 392
 393         return 0;
 394 }
 395
 396 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 397 {
 398         struct smu_table_context *smu_table = &smu->smu_table;
 399         struct smu_table *tables = NULL;
 400         int ret = 0;
 401
 402         if (smu_table->tables || smu_table->table_count == 0)
 403                 return -EINVAL;
 404
 405         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 406                          GFP_KERNEL);
 407         if (!tables)
 408                 return -ENOMEM;
 409
 410         smu_table->tables = tables;
 411
 412         smu_tables_init(smu, tables);
 413
 414         ret = smu_v11_0_init_dpm_context(smu);
 415         if (ret)
 416                 return ret;
 417
 418         return 0;
 419 }
 420
 421 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 422 {
 423         struct smu_table_context *smu_table = &smu->smu_table;
 424         int ret = 0;
 425
 426         if (!smu_table->tables || smu_table->table_count == 0)
 427                 return -EINVAL;
 428
 429         kfree(smu_table->tables);
 430         smu_table->tables = NULL;
 431         smu_table->table_count = 0;
 432
 433         ret = smu_v11_0_fini_dpm_context(smu);
 434         if (ret)
 435                 return ret;
 436         return 0;
 437 }
 438
 439 static int smu_v11_0_init_power(struct smu_context *smu)
 440 {
 441         struct smu_power_context *smu_power = &smu->smu_power;
 442
 443         if (!smu->pm_enabled)
 444                 return 0;
 445         if (smu_power->power_context || smu_power->power_context_size != 0)
 446                 return -EINVAL;
 447
 448         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 449                                            GFP_KERNEL);
 450         if (!smu_power->power_context)
 451                 return -ENOMEM;
 452         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 453
 454         smu->metrics_time = 0;
 455         smu->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 456         if (!smu->metrics_table) {
 457                 kfree(smu_power->power_context);
 458                 return -ENOMEM;
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int smu_v11_0_fini_power(struct smu_context *smu)
 465 {
 466         struct smu_power_context *smu_power = &smu->smu_power;
 467
 468         if (!smu->pm_enabled)
 469                 return 0;
 470         if (!smu_power->power_context || smu_power->power_context_size == 0)
 471                 return -EINVAL;
 472
 473         kfree(smu->metrics_table);
 474         kfree(smu_power->power_context);
 475         smu->metrics_table = NULL;
 476         smu_power->power_context = NULL;
 477         smu_power->power_context_size = 0;
 478
 479         return 0;
 480 }
 481
 482 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 483 {
 484         int ret, index;
 485         uint16_t size;
 486         uint8_t frev, crev;
 487         struct atom_common_table_header *header;
 488         struct atom_firmware_info_v3_3 *v_3_3;
 489         struct atom_firmware_info_v3_1 *v_3_1;
 490
 491         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 492                                             firmwareinfo);
 493
 494         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 495                                       (uint8_t **)&header);
 496         if (ret)
 497                 return ret;
 498
 499         if (header->format_revision != 3) {
 500                 pr_err("unknown atom_firmware_info version! for smu11\n");
 501                 return -EINVAL;
 502         }
 503
 504         switch (header->content_revision) {
 505         case 0:
 506         case 1:
 507         case 2:
 508                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 509                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 510                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 511                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 512                 smu->smu_table.boot_values.socclk = 0;
 513                 smu->smu_table.boot_values.dcefclk = 0;
 514                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 515                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 516                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 517                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 518                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 519                 smu->smu_table.boot_values.pp_table_id = 0;
 520                 break;
 521         case 3:
 522         default:
 523                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 524                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 525                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 526                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 527                 smu->smu_table.boot_values.socclk = 0;
 528                 smu->smu_table.boot_values.dcefclk = 0;
 529                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 530                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 531                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 532                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 533                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 534                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 535         }
 536
 537         return 0;
 538 }
 539
 540 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 541 {
 542         int ret, index;
 543         struct amdgpu_device *adev = smu->adev;
 544         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 545         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 546
 547         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 548         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 549         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 550                                             getsmuclockinfo);
 551
 552         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 553                                         (uint32_t *)&input);
 554         if (ret)
 555                 return -EINVAL;
 556
 557         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 558         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 559
 560         memset(&input, 0, sizeof(input));
 561         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 562         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 563         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 564                                             getsmuclockinfo);
 565
 566         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 567                                         (uint32_t *)&input);
 568         if (ret)
 569                 return -EINVAL;
 570
 571         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 572         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 573
 574         memset(&input, 0, sizeof(input));
 575         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 576         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 577         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 578                                             getsmuclockinfo);
 579
 580         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 581                                         (uint32_t *)&input);
 582         if (ret)
 583                 return -EINVAL;
 584
 585         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 586         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 587
 588         memset(&input, 0, sizeof(input));
 589         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 590         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 591         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 592                                             getsmuclockinfo);
 593
 594         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 595                                         (uint32_t *)&input);
 596         if (ret)
 597                 return -EINVAL;
 598
 599         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 600         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 601
 602         memset(&input, 0, sizeof(input));
 603         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 604         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 605         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 606                                             getsmuclockinfo);
 607
 608         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 609                                         (uint32_t *)&input);
 610         if (ret)
 611                 return -EINVAL;
 612
 613         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 614         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 615
 616         return 0;
 617 }
 618
 619 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 620 {
 621         struct smu_table_context *smu_table = &smu->smu_table;
 622         struct smu_table *memory_pool = &smu_table->memory_pool;
 623         int ret = 0;
 624         uint64_t address;
 625         uint32_t address_low, address_high;
 626
 627         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 628                 return ret;
 629
 630         address = (uintptr_t)memory_pool->cpu_addr;
 631         address_high = (uint32_t)upper_32_bits(address);
 632         address_low  = (uint32_t)lower_32_bits(address);
 633
 634         ret = smu_send_smc_msg_with_param(smu,
 635                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 636                                           address_high);
 637         if (ret)
 638                 return ret;
 639         ret = smu_send_smc_msg_with_param(smu,
 640                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 641                                           address_low);
 642         if (ret)
 643                 return ret;
 644
 645         address = memory_pool->mc_address;
 646         address_high = (uint32_t)upper_32_bits(address);
 647         address_low  = (uint32_t)lower_32_bits(address);
 648
 649         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 650                                           address_high);
 651         if (ret)
 652                 return ret;
 653         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 654                                           address_low);
 655         if (ret)
 656                 return ret;
 657         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 658                                           (uint32_t)memory_pool->size);
 659         if (ret)
 660                 return ret;
 661
 662         return ret;
 663 }
 664
 665 static int smu_v11_0_check_pptable(struct smu_context *smu)
 666 {
 667         int ret;
 668
 669         ret = smu_check_powerplay_table(smu);
 670         return ret;
 671 }
 672
 673 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 674 {
 675         int ret;
 676
 677         struct smu_table_context *table_context = &smu->smu_table;
 678
 679         if (table_context->driver_pptable)
 680                 return -EINVAL;
 681
 682         table_context->driver_pptable = kzalloc(sizeof(PPTable_t), GFP_KERNEL);
 683
 684         if (!table_context->driver_pptable)
 685                 return -ENOMEM;
 686
 687         ret = smu_store_powerplay_table(smu);
 688         if (ret)
 689                 return -EINVAL;
 690
 691         ret = smu_append_powerplay_table(smu);
 692
 693         return ret;
 694 }
 695
 696 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 697 {
 698         int ret;
 699
 700         ret = smu_set_default_dpm_table(smu);
 701
 702         return ret;
 703 }
 704
 705 static int smu_v11_0_write_pptable(struct smu_context *smu)
 706 {
 707         struct smu_table_context *table_context = &smu->smu_table;
 708         int ret = 0;
 709
 710         ret = smu_update_table(smu, TABLE_PPTABLE, table_context->driver_pptable, true);
 711
 712         return ret;
 713 }
 714
 715 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 716 {
 717         return smu_update_table(smu, TABLE_WATERMARKS,
 718                                 smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr, true);
 719 }
 720
 721 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 722 {
 723         int ret;
 724
 725         ret = smu_send_smc_msg_with_param(smu,
 726                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 727         if (ret)
 728                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 729
 730         return ret;
 731 }
 732
 733 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 734 {
 735         struct smu_table_context *table_context = &smu->smu_table;
 736
 737         if (!smu->pm_enabled)
 738                 return 0;
 739         if (!table_context)
 740                 return -EINVAL;
 741
 742         return smu_set_deep_sleep_dcefclk(smu,
 743                                           table_context->boot_values.dcefclk / 100);
 744 }
 745
 746 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 747 {
 748         int ret = 0;
 749         struct smu_table *tool_table = &smu->smu_table.tables[TABLE_PMSTATUSLOG];
 750
 751         if (tool_table->mc_address) {
 752                 ret = smu_send_smc_msg_with_param(smu,
 753                                 SMU_MSG_SetToolsDramAddrHigh,
 754                                 upper_32_bits(tool_table->mc_address));
 755                 if (!ret)
 756                         ret = smu_send_smc_msg_with_param(smu,
 757                                 SMU_MSG_SetToolsDramAddrLow,
 758                                 lower_32_bits(tool_table->mc_address));
 759         }
 760
 761         return ret;
 762 }
 763
 764 static int smu_v11_0_init_display(struct smu_context *smu)
 765 {
 766         int ret = 0;
 767
 768         if (!smu->pm_enabled)
 769                 return ret;
 770         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 771         return ret;
 772 }
 773
 774 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 775 {
 776         uint32_t feature_low = 0, feature_high = 0;
 777         int ret = 0;
 778
 779         if (!smu->pm_enabled)
 780                 return ret;
 781         if (feature_id >= 0 && feature_id < 31)
 782                 feature_low = (1 << feature_id);
 783         else if (feature_id > 31 && feature_id < 63)
 784                 feature_high = (1 << feature_id);
 785         else
 786                 return -EINVAL;
 787
 788         if (enabled) {
 789                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 790                                                   feature_low);
 791                 if (ret)
 792                         return ret;
 793                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 794                                                   feature_high);
 795                 if (ret)
 796                         return ret;
 797
 798         } else {
 799                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 800                                                   feature_low);
 801                 if (ret)
 802                         return ret;
 803                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 804                                                   feature_high);
 805                 if (ret)
 806                         return ret;
 807
 808         }
 809
 810         return ret;
 811 }
 812
 813 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 814 {
 815         struct smu_feature *feature = &smu->smu_feature;
 816         int ret = 0;
 817         uint32_t feature_mask[2];
 818
 819         mutex_lock(&feature->mutex);
 820         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 821                 goto failed;
 822
 823         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 824
 825         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 826                                           feature_mask[1]);
 827         if (ret)
 828                 goto failed;
 829
 830         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 831                                           feature_mask[0]);
 832         if (ret)
 833                 goto failed;
 834
 835 failed:
 836         mutex_unlock(&feature->mutex);
 837         return ret;
 838 }
 839
 840 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 841                                       uint32_t *feature_mask, uint32_t num)
 842 {
 843         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 844         int ret = 0;
 845
 846         if (!feature_mask || num < 2)
 847                 return -EINVAL;
 848
 849         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 850         if (ret)
 851                 return ret;
 852         ret = smu_read_smc_arg(smu, &feature_mask_high);
 853         if (ret)
 854                 return ret;
 855
 856         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 857         if (ret)
 858                 return ret;
 859         ret = smu_read_smc_arg(smu, &feature_mask_low);
 860         if (ret)
 861                 return ret;
 862
 863         feature_mask[0] = feature_mask_low;
 864         feature_mask[1] = feature_mask_high;
 865
 866         return ret;
 867 }
 868
 869 static int smu_v11_0_system_features_control(struct smu_context *smu,
 870                                              bool en)
 871 {
 872         struct smu_feature *feature = &smu->smu_feature;
 873         uint32_t feature_mask[2];
 874         int ret = 0;
 875
 876         if (smu->pm_enabled) {
 877                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 878                                              SMU_MSG_DisableAllSmuFeatures));
 879                 if (ret)
 880                         return ret;
 881         }
 882
 883         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 884         if (ret)
 885                 return ret;
 886
 887         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 888                     feature->feature_num);
 889         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 890                     feature->feature_num);
 891
 892         return ret;
 893 }
 894
 895 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 896 {
 897         int ret = 0;
 898
 899         if (!smu->pm_enabled)
 900                 return ret;
 901         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 902             ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 903
 904         return ret;
 905 }
 906
 907 static int
 908 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 909                                     enum smu_clk_type clock_select)
 910 {
 911         int ret = 0;
 912
 913         if (!smu->pm_enabled)
 914                 return ret;
 915         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 916                                           smu_clk_get_index(smu, clock_select) << 16);
 917         if (ret) {
 918                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 919                 return ret;
 920         }
 921
 922         ret = smu_read_smc_arg(smu, clock);
 923         if (ret)
 924                 return ret;
 925
 926         if (*clock != 0)
 927                 return 0;
 928
 929         /* if DC limit is zero, return AC limit */
 930         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 931                                           smu_clk_get_index(smu, clock_select) << 16);
 932         if (ret) {
 933                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 934                 return ret;
 935         }
 936
 937         ret = smu_read_smc_arg(smu, clock);
 938
 939         return ret;
 940 }
 941
 942 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 943 {
 944         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 945         int ret = 0;
 946
 947         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 948                                          GFP_KERNEL);
 949         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 950
 951         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 952         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 953         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 954         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 955         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 956         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 957
 958         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 959                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 960                                                           &(max_sustainable_clocks->uclock),
 961                                                           SMU_UCLK);
 962                 if (ret) {
 963                         pr_err("[%s] failed to get max UCLK from SMC!",
 964                                __func__);
 965                         return ret;
 966                 }
 967         }
 968
 969         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 970                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 971                                                           &(max_sustainable_clocks->soc_clock),
 972                                                           SMU_SOCCLK);
 973                 if (ret) {
 974                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 975                                __func__);
 976                         return ret;
 977                 }
 978         }
 979
 980         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 981                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 982                                                           &(max_sustainable_clocks->dcef_clock),
 983                                                           SMU_DCEFCLK);
 984                 if (ret) {
 985                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
 986                                __func__);
 987                         return ret;
 988                 }
 989
 990                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 991                                                           &(max_sustainable_clocks->display_clock),
 992                                                           SMU_DISPCLK);
 993                 if (ret) {
 994                         pr_err("[%s] failed to get max DISPCLK from SMC!",
 995                                __func__);
 996                         return ret;
 997                 }
 998                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 999                                                           &(max_sustainable_clocks->phy_clock),
1000                                                           SMU_PHYCLK);
1001                 if (ret) {
1002                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1003                                __func__);
1004                         return ret;
1005                 }
1006                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1007                                                           &(max_sustainable_clocks->pixel_clock),
1008                                                           SMU_PIXCLK);
1009                 if (ret) {
1010                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1011                                __func__);
1012                         return ret;
1013                 }
1014         }
1015
1016         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1017                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1018
1019         return 0;
1020 }
1021
1022 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1023                                      uint32_t *limit,
1024                                      bool get_default)
1025 {
1026         int ret = 0;
1027
1028         if (get_default) {
1029                 mutex_lock(&smu->mutex);
1030                 *limit = smu->default_power_limit;
1031                 if (smu->od_enabled) {
1032                         *limit *= (100 + smu->smu_table.TDPODLimit);
1033                         *limit /= 100;
1034                 }
1035                 mutex_unlock(&smu->mutex);
1036         } else {
1037                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1038                                                   POWER_SOURCE_AC << 16);
1039                 if (ret) {
1040                         pr_err("[%s] get PPT limit failed!", __func__);
1041                         return ret;
1042                 }
1043                 smu_read_smc_arg(smu, limit);
1044                 smu->power_limit = *limit;
1045         }
1046
1047         return ret;
1048 }
1049
1050 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1051 {
1052         uint32_t max_power_limit;
1053         int ret = 0;
1054
1055         if (n == 0)
1056                 n = smu->default_power_limit;
1057
1058         max_power_limit = smu->default_power_limit;
1059
1060         if (smu->od_enabled) {
1061                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1062                 max_power_limit /= 100;
1063         }
1064
1065         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1066                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1067         if (ret) {
1068                 pr_err("[%s] Set power limit Failed!", __func__);
1069                 return ret;
1070         }
1071
1072         return ret;
1073 }
1074
1075 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1076                                           enum smu_clk_type clk_id,
1077                                           uint32_t *value)
1078 {
1079         int ret = 0;
1080         uint32_t freq;
1081
1082         if (clk_id >= SMU_CLK_COUNT || !value)
1083                 return -EINVAL;
1084
1085         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1086                                           (smu_clk_get_index(smu, clk_id) << 16));
1087         if (ret)
1088                 return ret;
1089
1090         ret = smu_read_smc_arg(smu, &freq);
1091         if (ret)
1092                 return ret;
1093
1094         freq *= 100;
1095         *value = freq;
1096
1097         return ret;
1098 }
1099
1100 static int smu_v11_0_get_thermal_range(struct smu_context *smu,
1101                                 struct PP_TemperatureRange *range)
1102 {
1103         PPTable_t *pptable = smu->smu_table.driver_pptable;
1104         memcpy(range, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
1105
1106         range->max = pptable->TedgeLimit *
1107                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1108         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1109                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1110         range->hotspot_crit_max = pptable->ThotspotLimit *
1111                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1112         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1113                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1114         range->mem_crit_max = pptable->ThbmLimit *
1115                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1116         range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
1117                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1118
1119         return 0;
1120 }
1121
1122 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1123                         struct PP_TemperatureRange *range)
1124 {
1125         struct amdgpu_device *adev = smu->adev;
1126         int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
1127                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1128         int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
1129                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1130         uint32_t val;
1131
1132         if (low < range->min)
1133                 low = range->min;
1134         if (high > range->max)
1135                 high = range->max;
1136
1137         if (low > high)
1138                 return -EINVAL;
1139
1140         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1141         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1142         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1143         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1144         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1145         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1146
1147         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1148
1149         return 0;
1150 }
1151
1152 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1153 {
1154         struct amdgpu_device *adev = smu->adev;
1155         uint32_t val = 0;
1156
1157         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1158         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1159         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1160
1161         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1162
1163         return 0;
1164 }
1165
1166 static int smu_v11_0_set_thermal_fan_table(struct smu_context *smu)
1167 {
1168         int ret;
1169         struct smu_table_context *table_context = &smu->smu_table;
1170         PPTable_t *pptable = table_context->driver_pptable;
1171
1172         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
1173                         (uint32_t)pptable->FanTargetTemperature);
1174
1175         return ret;
1176 }
1177
1178 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1179 {
1180         int ret = 0;
1181         struct PP_TemperatureRange range = {
1182                 TEMP_RANGE_MIN,
1183                 TEMP_RANGE_MAX,
1184                 TEMP_RANGE_MAX,
1185                 TEMP_RANGE_MIN,
1186                 TEMP_RANGE_MAX,
1187                 TEMP_RANGE_MAX,
1188                 TEMP_RANGE_MIN,
1189                 TEMP_RANGE_MAX,
1190                 TEMP_RANGE_MAX};
1191         struct amdgpu_device *adev = smu->adev;
1192
1193         if (!smu->pm_enabled)
1194                 return ret;
1195         smu_v11_0_get_thermal_range(smu, &range);
1196
1197         if (smu->smu_table.thermal_controller_type) {
1198                 ret = smu_v11_0_set_thermal_range(smu, &range);
1199                 if (ret)
1200                         return ret;
1201
1202                 ret = smu_v11_0_enable_thermal_alert(smu);
1203                 if (ret)
1204                         return ret;
1205                 ret = smu_v11_0_set_thermal_fan_table(smu);
1206                 if (ret)
1207                         return ret;
1208         }
1209
1210         adev->pm.dpm.thermal.min_temp = range.min;
1211         adev->pm.dpm.thermal.max_temp = range.max;
1212         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1213         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1214         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1215         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1216         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1217         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1218         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1219
1220         return ret;
1221 }
1222
1223 static int smu_v11_0_get_metrics_table(struct smu_context *smu,
1224                 SmuMetrics_t *metrics_table)
1225 {
1226         int ret = 0;
1227
1228         if (!smu->metrics_time || time_after(jiffies, smu->metrics_time + HZ / 1000)) {
1229                 ret = smu_update_table(smu, TABLE_SMU_METRICS,
1230                                 (void *)metrics_table, false);
1231                 if (ret) {
1232                         pr_info("Failed to export SMU metrics table!\n");
1233                         return ret;
1234                 }
1235                 memcpy(smu->metrics_table, metrics_table, sizeof(SmuMetrics_t));
1236                 smu->metrics_time = jiffies;
1237         } else
1238                 memcpy(metrics_table, smu->metrics_table, sizeof(SmuMetrics_t));
1239
1240         return ret;
1241 }
1242
1243 static int smu_v11_0_get_current_activity_percent(struct smu_context *smu,
1244                                                   enum amd_pp_sensors sensor,
1245                                                   uint32_t *value)
1246 {
1247         int ret = 0;
1248         SmuMetrics_t metrics;
1249
1250         if (!value)
1251                 return -EINVAL;
1252
1253         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1254         if (ret)
1255                 return ret;
1256
1257         switch (sensor) {
1258         case AMDGPU_PP_SENSOR_GPU_LOAD:
1259                 *value = metrics.AverageGfxActivity;
1260                 break;
1261         case AMDGPU_PP_SENSOR_MEM_LOAD:
1262                 *value = metrics.AverageUclkActivity;
1263                 break;
1264         default:
1265                 pr_err("Invalid sensor for retrieving clock activity\n");
1266                 return -EINVAL;
1267         }
1268
1269         return 0;
1270 }
1271
1272 static int smu_v11_0_thermal_get_temperature(struct smu_context *smu,
1273                                              enum amd_pp_sensors sensor,
1274                                              uint32_t *value)
1275 {
1276         struct amdgpu_device *adev = smu->adev;
1277         SmuMetrics_t metrics;
1278         uint32_t temp = 0;
1279         int ret = 0;
1280
1281         if (!value)
1282                 return -EINVAL;
1283
1284         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1285         if (ret)
1286                 return ret;
1287
1288         switch (sensor) {
1289         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1290                 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
1291                 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
1292                                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
1293
1294                 temp = temp & 0x1ff;
1295                 temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
1296
1297                 *value = temp;
1298                 break;
1299         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1300                 *value = metrics.TemperatureEdge *
1301                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1302                 break;
1303         case AMDGPU_PP_SENSOR_MEM_TEMP:
1304                 *value = metrics.TemperatureHBM *
1305                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1306                 break;
1307         default:
1308                 pr_err("Invalid sensor for retrieving temp\n");
1309                 return -EINVAL;
1310         }
1311
1312         return 0;
1313 }
1314
1315 static int smu_v11_0_get_gpu_power(struct smu_context *smu, uint32_t *value)
1316 {
1317         int ret = 0;
1318         SmuMetrics_t metrics;
1319
1320         if (!value)
1321                 return -EINVAL;
1322
1323         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1324         if (ret)
1325                 return ret;
1326
1327         *value = metrics.CurrSocketPower << 8;
1328
1329         return 0;
1330 }
1331
1332 static uint16_t convert_to_vddc(uint8_t vid)
1333 {
1334         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1335 }
1336
1337 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1338 {
1339         struct amdgpu_device *adev = smu->adev;
1340         uint32_t vdd = 0, val_vid = 0;
1341
1342         if (!value)
1343                 return -EINVAL;
1344         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1345                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1346                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1347
1348         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1349
1350         *value = vdd;
1351
1352         return 0;
1353
1354 }
1355
1356 static int smu_v11_0_read_sensor(struct smu_context *smu,
1357                                  enum amd_pp_sensors sensor,
1358                                  void *data, uint32_t *size)
1359 {
1360         struct smu_table_context *table_context = &smu->smu_table;
1361         PPTable_t *pptable = table_context->driver_pptable;
1362         int ret = 0;
1363         switch (sensor) {
1364         case AMDGPU_PP_SENSOR_GPU_LOAD:
1365         case AMDGPU_PP_SENSOR_MEM_LOAD:
1366                 ret = smu_v11_0_get_current_activity_percent(smu,
1367                                                              sensor,
1368                                                              (uint32_t *)data);
1369                 *size = 4;
1370                 break;
1371         case AMDGPU_PP_SENSOR_GFX_MCLK:
1372                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1373                 *size = 4;
1374                 break;
1375         case AMDGPU_PP_SENSOR_GFX_SCLK:
1376                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1377                 *size = 4;
1378                 break;
1379         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1380         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1381         case AMDGPU_PP_SENSOR_MEM_TEMP:
1382                 ret = smu_v11_0_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1383                 *size = 4;
1384                 break;
1385         case AMDGPU_PP_SENSOR_GPU_POWER:
1386                 ret = smu_v11_0_get_gpu_power(smu, (uint32_t *)data);
1387                 *size = 4;
1388                 break;
1389         case AMDGPU_PP_SENSOR_VDDGFX:
1390                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1391                 *size = 4;
1392                 break;
1393         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1394                 *(uint32_t *)data = 0;
1395                 *size = 4;
1396                 break;
1397         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1398                 *(uint32_t *)data = pptable->FanMaximumRpm;
1399                 *size = 4;
1400                 break;
1401         default:
1402                 ret = smu_common_read_sensor(smu, sensor, data, size);
1403                 break;
1404         }
1405
1406         /* try get sensor data by asic */
1407         if (ret)
1408                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1409
1410         if (ret)
1411                 *size = 0;
1412
1413         return ret;
1414 }
1415
1416 static int
1417 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1418                                         struct pp_display_clock_request
1419                                         *clock_req)
1420 {
1421         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1422         int ret = 0;
1423         enum smu_clk_type clk_select = 0;
1424         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1425
1426         if (!smu->pm_enabled)
1427                 return -EINVAL;
1428         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1429                 switch (clk_type) {
1430                 case amd_pp_dcef_clock:
1431                         clk_select = SMU_DCEFCLK;
1432                         break;
1433                 case amd_pp_disp_clock:
1434                         clk_select = SMU_DISPCLK;
1435                         break;
1436                 case amd_pp_pixel_clock:
1437                         clk_select = SMU_PIXCLK;
1438                         break;
1439                 case amd_pp_phy_clock:
1440                         clk_select = SMU_PHYCLK;
1441                         break;
1442                 default:
1443                         pr_info("[%s] Invalid Clock Type!", __func__);
1444                         ret = -EINVAL;
1445                         break;
1446                 }
1447
1448                 if (ret)
1449                         goto failed;
1450
1451                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1452                         (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1453         }
1454
1455 failed:
1456         return ret;
1457 }
1458
1459 static int smu_v11_0_set_watermarks_table(struct smu_context *smu,
1460                                           Watermarks_t *table, struct
1461                                           dm_pp_wm_sets_with_clock_ranges_soc15
1462                                           *clock_ranges)
1463 {
1464         int i;
1465
1466         if (!table || !clock_ranges)
1467                 return -EINVAL;
1468
1469         if (clock_ranges->num_wm_dmif_sets > 4 ||
1470             clock_ranges->num_wm_mcif_sets > 4)
1471                 return -EINVAL;
1472
1473         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1474                 table->WatermarkRow[1][i].MinClock =
1475                         cpu_to_le16((uint16_t)
1476                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1477                         1000));
1478                 table->WatermarkRow[1][i].MaxClock =
1479                         cpu_to_le16((uint16_t)
1480                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1481                         1000));
1482                 table->WatermarkRow[1][i].MinUclk =
1483                         cpu_to_le16((uint16_t)
1484                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1485                         1000));
1486                 table->WatermarkRow[1][i].MaxUclk =
1487                         cpu_to_le16((uint16_t)
1488                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1489                         1000));
1490                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1491                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1492         }
1493
1494         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1495                 table->WatermarkRow[0][i].MinClock =
1496                         cpu_to_le16((uint16_t)
1497                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1498                         1000));
1499                 table->WatermarkRow[0][i].MaxClock =
1500                         cpu_to_le16((uint16_t)
1501                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1502                         1000));
1503                 table->WatermarkRow[0][i].MinUclk =
1504                         cpu_to_le16((uint16_t)
1505                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1506                         1000));
1507                 table->WatermarkRow[0][i].MaxUclk =
1508                         cpu_to_le16((uint16_t)
1509                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1510                         1000));
1511                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1512                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1513         }
1514
1515         return 0;
1516 }
1517
1518 static int
1519 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1520                                           dm_pp_wm_sets_with_clock_ranges_soc15
1521                                           *clock_ranges)
1522 {
1523         int ret = 0;
1524         struct smu_table *watermarks = &smu->smu_table.tables[TABLE_WATERMARKS];
1525         Watermarks_t *table = watermarks->cpu_addr;
1526
1527         if (!smu->disable_watermark &&
1528             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1529             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1530                 smu_v11_0_set_watermarks_table(smu, table, clock_ranges);
1531                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1532                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1533         }
1534
1535         return ret;
1536 }
1537
1538 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1539 {
1540         int ret = 0;
1541         struct amdgpu_device *adev = smu->adev;
1542
1543         switch (adev->asic_type) {
1544         case CHIP_VEGA20:
1545                 break;
1546         case CHIP_NAVI10:
1547                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1548                         return 0;
1549                 mutex_lock(&smu->mutex);
1550                 if (enable)
1551                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1552                 else
1553                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1554                 mutex_unlock(&smu->mutex);
1555                 break;
1556         default:
1557                 break;
1558         }
1559
1560         return ret;
1561 }
1562
1563
1564 static int smu_v11_0_get_clock_ranges(struct smu_context *smu,
1565                                       uint32_t *clock,
1566                                       enum smu_clk_type clock_select,
1567                                       bool max)
1568 {
1569         int ret;
1570         *clock = 0;
1571         if (max) {
1572                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
1573                                 smu_clk_get_index(smu, clock_select) << 16);
1574                 if (ret) {
1575                         pr_err("[GetClockRanges] Failed to get max clock from SMC!\n");
1576                         return ret;
1577                 }
1578                 smu_read_smc_arg(smu, clock);
1579         } else {
1580                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq,
1581                                 smu_clk_get_index(smu, clock_select) << 16);
1582                 if (ret) {
1583                         pr_err("[GetClockRanges] Failed to get min clock from SMC!\n");
1584                         return ret;
1585                 }
1586                 smu_read_smc_arg(smu, clock);
1587         }
1588
1589         return 0;
1590 }
1591
1592 static uint32_t smu_v11_0_dpm_get_sclk(struct smu_context *smu, bool low)
1593 {
1594         uint32_t gfx_clk;
1595         int ret;
1596
1597         if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1598                 pr_err("[GetSclks]: gfxclk dpm not enabled!\n");
1599                 return -EPERM;
1600         }
1601
1602         if (low) {
1603                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, false);
1604                 if (ret) {
1605                         pr_err("[GetSclks]: fail to get min SMU_GFXCLK\n");
1606                         return ret;
1607                 }
1608         } else {
1609                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, true);
1610                 if (ret) {
1611                         pr_err("[GetSclks]: fail to get max SMU_GFXCLK\n");
1612                         return ret;
1613                 }
1614         }
1615
1616         return (gfx_clk * 100);
1617 }
1618
1619 static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low)
1620 {
1621         uint32_t mem_clk;
1622         int ret;
1623
1624         if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1625                 pr_err("[GetMclks]: memclk dpm not enabled!\n");
1626                 return -EPERM;
1627         }
1628
1629         if (low) {
1630                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_UCLK, false);
1631                 if (ret) {
1632                         pr_err("[GetMclks]: fail to get min SMU_UCLK\n");
1633                         return ret;
1634                 }
1635         } else {
1636                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_GFXCLK, true);
1637                 if (ret) {
1638                         pr_err("[GetMclks]: fail to get max SMU_UCLK\n");
1639                         return ret;
1640                 }
1641         }
1642
1643         return (mem_clk * 100);
1644 }
1645
1646 static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
1647                                               bool initialize)
1648 {
1649         struct smu_table_context *table_context = &smu->smu_table;
1650         int ret;
1651
1652         /**
1653          * TODO: Enable overdrive for navi10, that replies on smc/pptable
1654          * support.
1655          */
1656         if (smu->adev->asic_type == CHIP_NAVI10)
1657                 return 0;
1658
1659         if (initialize) {
1660                 if (table_context->overdrive_table)
1661                         return -EINVAL;
1662
1663                 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1664
1665                 if (!table_context->overdrive_table)
1666                         return -ENOMEM;
1667
1668                 ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
1669                 if (ret) {
1670                         pr_err("Failed to export over drive table!\n");
1671                         return ret;
1672                 }
1673
1674                 smu_set_default_od8_settings(smu);
1675         }
1676
1677         ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
1678         if (ret) {
1679                 pr_err("Failed to import over drive table!\n");
1680                 return ret;
1681         }
1682
1683         return 0;
1684 }
1685
1686 static int smu_v11_0_update_od8_settings(struct smu_context *smu,
1687                                         uint32_t index,
1688                                         uint32_t value)
1689 {
1690         struct smu_table_context *table_context = &smu->smu_table;
1691         int ret;
1692
1693         ret = smu_update_table(smu, TABLE_OVERDRIVE,
1694                                table_context->overdrive_table, false);
1695         if (ret) {
1696                 pr_err("Failed to export over drive table!\n");
1697                 return ret;
1698         }
1699
1700         smu_update_specified_od8_value(smu, index, value);
1701
1702         ret = smu_update_table(smu, TABLE_OVERDRIVE,
1703                                table_context->overdrive_table, true);
1704         if (ret) {
1705                 pr_err("Failed to import over drive table!\n");
1706                 return ret;
1707         }
1708
1709         return 0;
1710 }
1711
1712 static int smu_v11_0_get_current_rpm(struct smu_context *smu,
1713                                      uint32_t *current_rpm)
1714 {
1715         int ret;
1716
1717         ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
1718
1719         if (ret) {
1720                 pr_err("Attempt to get current RPM from SMC Failed!\n");
1721                 return ret;
1722         }
1723
1724         smu_read_smc_arg(smu, current_rpm);
1725
1726         return 0;
1727 }
1728
1729 static uint32_t
1730 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1731 {
1732         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1733                 return AMD_FAN_CTRL_MANUAL;
1734         else
1735                 return AMD_FAN_CTRL_AUTO;
1736 }
1737
1738 static int
1739 smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
1740                                            uint32_t *speed)
1741 {
1742         int ret = 0;
1743         uint32_t percent = 0;
1744         uint32_t current_rpm;
1745         PPTable_t *pptable = smu->smu_table.driver_pptable;
1746
1747         ret = smu_v11_0_get_current_rpm(smu, &current_rpm);
1748         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1749         *speed = percent > 100 ? 100 : percent;
1750
1751         return ret;
1752 }
1753
1754 static int
1755 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1756 {
1757         int ret = 0;
1758
1759         if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1760                 return 0;
1761
1762         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1763         if (ret)
1764                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1765                        __func__, (start ? "Start" : "Stop"));
1766
1767         return ret;
1768 }
1769
1770 static int
1771 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1772 {
1773         struct amdgpu_device *adev = smu->adev;
1774
1775         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1776                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1777                                    CG_FDO_CTRL2, TMIN, 0));
1778         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1779                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1780                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1781
1782         return 0;
1783 }
1784
1785 static int
1786 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1787 {
1788         struct amdgpu_device *adev = smu->adev;
1789         uint32_t duty100;
1790         uint32_t duty;
1791         uint64_t tmp64;
1792         bool stop = 0;
1793
1794         if (speed > 100)
1795                 speed = 100;
1796
1797         if (smu_v11_0_smc_fan_control(smu, stop))
1798                 return -EINVAL;
1799         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1800                                 CG_FDO_CTRL1, FMAX_DUTY100);
1801         if (!duty100)
1802                 return -EINVAL;
1803
1804         tmp64 = (uint64_t)speed * duty100;
1805         do_div(tmp64, 100);
1806         duty = (uint32_t)tmp64;
1807
1808         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1809                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1810                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1811
1812         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1813 }
1814
1815 static int
1816 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1817                                uint32_t mode)
1818 {
1819         int ret = 0;
1820         bool start = 1;
1821         bool stop  = 0;
1822
1823         switch (mode) {
1824         case AMD_FAN_CTRL_NONE:
1825                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1826                 break;
1827         case AMD_FAN_CTRL_MANUAL:
1828                 ret = smu_v11_0_smc_fan_control(smu, stop);
1829                 break;
1830         case AMD_FAN_CTRL_AUTO:
1831                 ret = smu_v11_0_smc_fan_control(smu, start);
1832                 break;
1833         default:
1834                 break;
1835         }
1836
1837         if (ret) {
1838                 pr_err("[%s]Set fan control mode failed!", __func__);
1839                 return -EINVAL;
1840         }
1841
1842         return ret;
1843 }
1844
1845 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1846                                        uint32_t speed)
1847 {
1848         struct amdgpu_device *adev = smu->adev;
1849         int ret;
1850         uint32_t tach_period, crystal_clock_freq;
1851         bool stop = 0;
1852
1853         if (!speed)
1854                 return -EINVAL;
1855
1856         mutex_lock(&(smu->mutex));
1857         ret = smu_v11_0_smc_fan_control(smu, stop);
1858         if (ret)
1859                 goto set_fan_speed_rpm_failed;
1860
1861         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1862         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1863         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1864                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1865                                    CG_TACH_CTRL, TARGET_PERIOD,
1866                                    tach_period));
1867
1868         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1869
1870 set_fan_speed_rpm_failed:
1871         mutex_unlock(&(smu->mutex));
1872         return ret;
1873 }
1874
1875 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1876                                      uint32_t pstate)
1877 {
1878         int ret = 0;
1879         mutex_lock(&(smu->mutex));
1880         ret = smu_send_smc_msg_with_param(smu,
1881                                           SMU_MSG_SetXgmiMode,
1882                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1883         mutex_unlock(&(smu->mutex));
1884         return ret;
1885 }
1886
1887 static const struct smu_funcs smu_v11_0_funcs = {
1888         .init_microcode = smu_v11_0_init_microcode,
1889         .load_microcode = smu_v11_0_load_microcode,
1890         .check_fw_status = smu_v11_0_check_fw_status,
1891         .check_fw_version = smu_v11_0_check_fw_version,
1892         .send_smc_msg = smu_v11_0_send_msg,
1893         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1894         .read_smc_arg = smu_v11_0_read_arg,
1895         .setup_pptable = smu_v11_0_setup_pptable,
1896         .init_smc_tables = smu_v11_0_init_smc_tables,
1897         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1898         .init_power = smu_v11_0_init_power,
1899         .fini_power = smu_v11_0_fini_power,
1900         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1901         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1902         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1903         .check_pptable = smu_v11_0_check_pptable,
1904         .parse_pptable = smu_v11_0_parse_pptable,
1905         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1906         .write_pptable = smu_v11_0_write_pptable,
1907         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1908         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1909         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1910         .init_display = smu_v11_0_init_display,
1911         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1912         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1913         .system_features_control = smu_v11_0_system_features_control,
1914         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1915         .notify_display_change = smu_v11_0_notify_display_change,
1916         .get_power_limit = smu_v11_0_get_power_limit,
1917         .set_power_limit = smu_v11_0_set_power_limit,
1918         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1919         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1920         .start_thermal_control = smu_v11_0_start_thermal_control,
1921         .read_sensor = smu_v11_0_read_sensor,
1922         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1923         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1924         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1925         .get_sclk = smu_v11_0_dpm_get_sclk,
1926         .get_mclk = smu_v11_0_dpm_get_mclk,
1927         .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
1928         .update_od8_settings = smu_v11_0_update_od8_settings,
1929         .get_current_rpm = smu_v11_0_get_current_rpm,
1930         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1931         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1932         .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
1933         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1934         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1935         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1936         .gfx_off_control = smu_v11_0_gfx_off_control,
1937 };
1938
1939 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1940 {
1941         struct amdgpu_device *adev = smu->adev;
1942
1943         smu->funcs = &smu_v11_0_funcs;
1944         switch (adev->asic_type) {
1945         case CHIP_VEGA20:
1946                 vega20_set_ppt_funcs(smu);
1947                 break;
1948         case CHIP_NAVI10:
1949                 navi10_set_ppt_funcs(smu);
1950                 break;
1951         default:
1952                 pr_warn("Unknown asic for smu11\n");
1953         }
1954 }