drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pp_debug.h"
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "atomfirmware.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "smu_v11_0.h"
  30 #include "smu_11_0_driver_if.h"
  31 #include "soc15_common.h"
  32 #include "atom.h"
  33 #include "vega20_ppt.h"
  34 #include "navi10_ppt.h"
  35 #include "pp_thermal.h"
  36
  37 #include "asic_reg/thm/thm_11_0_2_offset.h"
  38 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  39 #include "asic_reg/mp/mp_11_0_offset.h"
  40 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  41 #include "asic_reg/nbio/nbio_7_4_offset.h"
  42 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  43 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  44
  45 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  47
  48 #define SMU11_THERMAL_MINIMUM_ALERT_TEMP      0
  49 #define SMU11_THERMAL_MAXIMUM_ALERT_TEMP      255
  50
  51 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
  52 #define SMU11_VOLTAGE_SCALE 4
  53
  54 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  55                                               uint16_t msg)
  56 {
  57         struct amdgpu_device *adev = smu->adev;
  58         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  59         return 0;
  60 }
  61
  62 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  63 {
  64         struct amdgpu_device *adev = smu->adev;
  65
  66         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  67         return 0;
  68 }
  69
  70 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  71 {
  72         struct amdgpu_device *adev = smu->adev;
  73         uint32_t cur_value, i;
  74
  75         for (i = 0; i < adev->usec_timeout; i++) {
  76                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  77                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  78                         break;
  79                 udelay(1);
  80         }
  81
  82         /* timeout means wrong logic */
  83         if (i == adev->usec_timeout)
  84                 return -ETIME;
  85
  86         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  87 }
  88
  89 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  90 {
  91         struct amdgpu_device *adev = smu->adev;
  92         int ret = 0, index = 0;
  93
  94         index = smu_msg_get_index(smu, msg);
  95         if (index < 0)
  96                 return index;
  97
  98         smu_v11_0_wait_for_response(smu);
  99
 100         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 101
 102         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 103
 104         ret = smu_v11_0_wait_for_response(smu);
 105
 106         if (ret)
 107                 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 108                        ret);
 109
 110         return ret;
 111
 112 }
 113
 114 static int
 115 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 116                               uint32_t param)
 117 {
 118
 119         struct amdgpu_device *adev = smu->adev;
 120         int ret = 0, index = 0;
 121
 122         index = smu_msg_get_index(smu, msg);
 123         if (index < 0)
 124                 return index;
 125
 126         ret = smu_v11_0_wait_for_response(smu);
 127         if (ret)
 128                 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
 129                        index, ret, param);
 130
 131         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 132
 133         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 134
 135         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 136
 137         ret = smu_v11_0_wait_for_response(smu);
 138         if (ret)
 139                 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
 140                        index, ret, param);
 141
 142         return ret;
 143 }
 144
 145 static int smu_v11_0_init_microcode(struct smu_context *smu)
 146 {
 147         struct amdgpu_device *adev = smu->adev;
 148         const char *chip_name;
 149         char fw_name[30];
 150         int err = 0;
 151         const struct smc_firmware_header_v1_0 *hdr;
 152         const struct common_firmware_header *header;
 153         struct amdgpu_firmware_info *ucode = NULL;
 154
 155         switch (adev->asic_type) {
 156         case CHIP_VEGA20:
 157                 chip_name = "vega20";
 158                 break;
 159         case CHIP_NAVI10:
 160                 chip_name = "navi10";
 161                 break;
 162         default:
 163                 BUG();
 164         }
 165
 166         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 167
 168         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 169         if (err)
 170                 goto out;
 171         err = amdgpu_ucode_validate(adev->pm.fw);
 172         if (err)
 173                 goto out;
 174
 175         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 176         amdgpu_ucode_print_smc_hdr(&hdr->header);
 177         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 178
 179         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 180                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 181                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 182                 ucode->fw = adev->pm.fw;
 183                 header = (const struct common_firmware_header *)ucode->fw->data;
 184                 adev->firmware.fw_size +=
 185                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 186         }
 187
 188 out:
 189         if (err) {
 190                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 191                           fw_name);
 192                 release_firmware(adev->pm.fw);
 193                 adev->pm.fw = NULL;
 194         }
 195         return err;
 196 }
 197
 198 static int smu_v11_0_load_microcode(struct smu_context *smu)
 199 {
 200         struct amdgpu_device *adev = smu->adev;
 201         const uint32_t *src;
 202         const struct smc_firmware_header_v1_0 *hdr;
 203         uint32_t addr_start = MP1_SRAM;
 204         uint32_t i;
 205         uint32_t mp1_fw_flags;
 206
 207         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 208         src = (const uint32_t *)(adev->pm.fw->data +
 209                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 210
 211         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 212                 WREG32_PCIE(addr_start, src[i]);
 213                 addr_start += 4;
 214         }
 215
 216         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 217                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 218         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 219                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 220
 221         for (i = 0; i < adev->usec_timeout; i++) {
 222                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 223                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 224                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 225                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 226                         break;
 227                 udelay(1);
 228         }
 229
 230         if (i == adev->usec_timeout)
 231                 return -ETIME;
 232
 233         return 0;
 234 }
 235
 236 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 237 {
 238         struct amdgpu_device *adev = smu->adev;
 239         uint32_t mp1_fw_flags;
 240
 241         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 242                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 243
 244         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 245             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 246                 return 0;
 247
 248         return -EIO;
 249 }
 250
 251 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 252 {
 253         uint32_t if_version = 0xff, smu_version = 0xff;
 254         uint16_t smu_major;
 255         uint8_t smu_minor, smu_debug;
 256         int ret = 0;
 257
 258         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 259         if (ret)
 260                 return ret;
 261
 262         smu_major = (smu_version >> 16) & 0xffff;
 263         smu_minor = (smu_version >> 8) & 0xff;
 264         smu_debug = (smu_version >> 0) & 0xff;
 265
 266         pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x (%d.%d.%d)\n",
 267                 if_version, smu_version, smu_major, smu_minor, smu_debug);
 268
 269         if (if_version != smu->smc_if_version) {
 270                 pr_err("SMU driver if version not matched\n");
 271                 ret = -EINVAL;
 272         }
 273
 274         return ret;
 275 }
 276
 277 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 278 {
 279         struct amdgpu_device *adev = smu->adev;
 280         uint32_t ppt_offset_bytes;
 281         const struct smc_firmware_header_v2_0 *v2;
 282
 283         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 284
 285         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 286         *size = le32_to_cpu(v2->ppt_size_bytes);
 287         *table = (uint8_t *)v2 + ppt_offset_bytes;
 288
 289         return 0;
 290 }
 291
 292 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
 293 {
 294         struct amdgpu_device *adev = smu->adev;
 295         const struct smc_firmware_header_v2_1 *v2_1;
 296         struct smc_soft_pptable_entry *entries;
 297         uint32_t pptable_count = 0;
 298         int i = 0;
 299
 300         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 301         entries = (struct smc_soft_pptable_entry *)
 302                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 303         pptable_count = le32_to_cpu(v2_1->pptable_count);
 304         for (i = 0; i < pptable_count; i++) {
 305                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 306                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 307                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 308                         break;
 309                 }
 310         }
 311
 312         if (i == pptable_count)
 313                 return -EINVAL;
 314
 315         return 0;
 316 }
 317
 318 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 319 {
 320         struct amdgpu_device *adev = smu->adev;
 321         const struct smc_firmware_header_v1_0 *hdr;
 322         int ret, index;
 323         uint32_t size;
 324         uint8_t frev, crev;
 325         void *table;
 326         uint16_t version_major, version_minor;
 327
 328         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 329         version_major = le16_to_cpu(hdr->header.header_version_major);
 330         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 331
 332         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 333                 switch (version_minor) {
 334                 case 0:
 335                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 336                         break;
 337                 case 1:
 338                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 339                                                          smu->smu_table.boot_values.pp_table_id);
 340                         break;
 341                 default:
 342                         ret = -EINVAL;
 343                         break;
 344                 }
 345                 if (ret)
 346                         return ret;
 347
 348         } else {
 349                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 350                                                     powerplayinfo);
 351
 352                 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
 353                                               (uint8_t **)&table);
 354                 if (ret)
 355                         return ret;
 356         }
 357
 358         if (!smu->smu_table.power_play_table)
 359                 smu->smu_table.power_play_table = table;
 360         if (!smu->smu_table.power_play_table_size)
 361                 smu->smu_table.power_play_table_size = size;
 362
 363         return 0;
 364 }
 365
 366 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 367 {
 368         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 369
 370         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 371                 return -EINVAL;
 372
 373         return smu_alloc_dpm_context(smu);
 374 }
 375
 376 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 377 {
 378         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 379
 380         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 381                 return -EINVAL;
 382
 383         kfree(smu_dpm->dpm_context);
 384         kfree(smu_dpm->golden_dpm_context);
 385         kfree(smu_dpm->dpm_current_power_state);
 386         kfree(smu_dpm->dpm_request_power_state);
 387         smu_dpm->dpm_context = NULL;
 388         smu_dpm->golden_dpm_context = NULL;
 389         smu_dpm->dpm_context_size = 0;
 390         smu_dpm->dpm_current_power_state = NULL;
 391         smu_dpm->dpm_request_power_state = NULL;
 392
 393         return 0;
 394 }
 395
 396 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 397 {
 398         struct smu_table_context *smu_table = &smu->smu_table;
 399         struct smu_table *tables = NULL;
 400         int ret = 0;
 401
 402         if (smu_table->tables || smu_table->table_count == 0)
 403                 return -EINVAL;
 404
 405         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 406                          GFP_KERNEL);
 407         if (!tables)
 408                 return -ENOMEM;
 409
 410         smu_table->tables = tables;
 411
 412         smu_tables_init(smu, tables);
 413
 414         ret = smu_v11_0_init_dpm_context(smu);
 415         if (ret)
 416                 return ret;
 417
 418         return 0;
 419 }
 420
 421 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 422 {
 423         struct smu_table_context *smu_table = &smu->smu_table;
 424         int ret = 0;
 425
 426         if (!smu_table->tables || smu_table->table_count == 0)
 427                 return -EINVAL;
 428
 429         kfree(smu_table->tables);
 430         smu_table->tables = NULL;
 431         smu_table->table_count = 0;
 432
 433         ret = smu_v11_0_fini_dpm_context(smu);
 434         if (ret)
 435                 return ret;
 436         return 0;
 437 }
 438
 439 static int smu_v11_0_init_power(struct smu_context *smu)
 440 {
 441         struct smu_power_context *smu_power = &smu->smu_power;
 442
 443         if (!smu->pm_enabled)
 444                 return 0;
 445         if (smu_power->power_context || smu_power->power_context_size != 0)
 446                 return -EINVAL;
 447
 448         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 449                                            GFP_KERNEL);
 450         if (!smu_power->power_context)
 451                 return -ENOMEM;
 452         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 453
 454         smu->metrics_time = 0;
 455         smu->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 456         if (!smu->metrics_table) {
 457                 kfree(smu_power->power_context);
 458                 return -ENOMEM;
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int smu_v11_0_fini_power(struct smu_context *smu)
 465 {
 466         struct smu_power_context *smu_power = &smu->smu_power;
 467
 468         if (!smu->pm_enabled)
 469                 return 0;
 470         if (!smu_power->power_context || smu_power->power_context_size == 0)
 471                 return -EINVAL;
 472
 473         kfree(smu->metrics_table);
 474         kfree(smu_power->power_context);
 475         smu->metrics_table = NULL;
 476         smu_power->power_context = NULL;
 477         smu_power->power_context_size = 0;
 478
 479         return 0;
 480 }
 481
 482 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 483 {
 484         int ret, index;
 485         uint16_t size;
 486         uint8_t frev, crev;
 487         struct atom_common_table_header *header;
 488         struct atom_firmware_info_v3_3 *v_3_3;
 489         struct atom_firmware_info_v3_1 *v_3_1;
 490
 491         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 492                                             firmwareinfo);
 493
 494         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 495                                       (uint8_t **)&header);
 496         if (ret)
 497                 return ret;
 498
 499         if (header->format_revision != 3) {
 500                 pr_err("unknown atom_firmware_info version! for smu11\n");
 501                 return -EINVAL;
 502         }
 503
 504         switch (header->content_revision) {
 505         case 0:
 506         case 1:
 507         case 2:
 508                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 509                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 510                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 511                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 512                 smu->smu_table.boot_values.socclk = 0;
 513                 smu->smu_table.boot_values.dcefclk = 0;
 514                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 515                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 516                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 517                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 518                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 519                 smu->smu_table.boot_values.pp_table_id = 0;
 520                 break;
 521         case 3:
 522         default:
 523                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 524                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 525                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 526                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 527                 smu->smu_table.boot_values.socclk = 0;
 528                 smu->smu_table.boot_values.dcefclk = 0;
 529                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 530                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 531                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 532                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 533                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 534                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 535         }
 536
 537         return 0;
 538 }
 539
 540 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 541 {
 542         int ret, index;
 543         struct amdgpu_device *adev = smu->adev;
 544         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 545         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 546
 547         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 548         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 549         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 550                                             getsmuclockinfo);
 551
 552         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 553                                         (uint32_t *)&input);
 554         if (ret)
 555                 return -EINVAL;
 556
 557         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 558         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 559
 560         memset(&input, 0, sizeof(input));
 561         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 562         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 563         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 564                                             getsmuclockinfo);
 565
 566         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 567                                         (uint32_t *)&input);
 568         if (ret)
 569                 return -EINVAL;
 570
 571         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 572         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 573
 574         memset(&input, 0, sizeof(input));
 575         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 576         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 577         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 578                                             getsmuclockinfo);
 579
 580         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 581                                         (uint32_t *)&input);
 582         if (ret)
 583                 return -EINVAL;
 584
 585         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 586         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 587
 588         memset(&input, 0, sizeof(input));
 589         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 590         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 591         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 592                                             getsmuclockinfo);
 593
 594         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 595                                         (uint32_t *)&input);
 596         if (ret)
 597                 return -EINVAL;
 598
 599         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 600         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 601
 602         memset(&input, 0, sizeof(input));
 603         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 604         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 605         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 606                                             getsmuclockinfo);
 607
 608         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 609                                         (uint32_t *)&input);
 610         if (ret)
 611                 return -EINVAL;
 612
 613         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 614         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 615
 616         return 0;
 617 }
 618
 619 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 620 {
 621         struct smu_table_context *smu_table = &smu->smu_table;
 622         struct smu_table *memory_pool = &smu_table->memory_pool;
 623         int ret = 0;
 624         uint64_t address;
 625         uint32_t address_low, address_high;
 626
 627         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 628                 return ret;
 629
 630         address = (uintptr_t)memory_pool->cpu_addr;
 631         address_high = (uint32_t)upper_32_bits(address);
 632         address_low  = (uint32_t)lower_32_bits(address);
 633
 634         ret = smu_send_smc_msg_with_param(smu,
 635                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 636                                           address_high);
 637         if (ret)
 638                 return ret;
 639         ret = smu_send_smc_msg_with_param(smu,
 640                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 641                                           address_low);
 642         if (ret)
 643                 return ret;
 644
 645         address = memory_pool->mc_address;
 646         address_high = (uint32_t)upper_32_bits(address);
 647         address_low  = (uint32_t)lower_32_bits(address);
 648
 649         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 650                                           address_high);
 651         if (ret)
 652                 return ret;
 653         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 654                                           address_low);
 655         if (ret)
 656                 return ret;
 657         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 658                                           (uint32_t)memory_pool->size);
 659         if (ret)
 660                 return ret;
 661
 662         return ret;
 663 }
 664
 665 static int smu_v11_0_check_pptable(struct smu_context *smu)
 666 {
 667         int ret;
 668
 669         ret = smu_check_powerplay_table(smu);
 670         return ret;
 671 }
 672
 673 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 674 {
 675         int ret;
 676
 677         struct smu_table_context *table_context = &smu->smu_table;
 678
 679         if (table_context->driver_pptable)
 680                 return -EINVAL;
 681
 682         table_context->driver_pptable = kzalloc(sizeof(PPTable_t), GFP_KERNEL);
 683
 684         if (!table_context->driver_pptable)
 685                 return -ENOMEM;
 686
 687         ret = smu_store_powerplay_table(smu);
 688         if (ret)
 689                 return -EINVAL;
 690
 691         ret = smu_append_powerplay_table(smu);
 692
 693         return ret;
 694 }
 695
 696 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 697 {
 698         int ret;
 699
 700         ret = smu_set_default_dpm_table(smu);
 701
 702         return ret;
 703 }
 704
 705 static int smu_v11_0_write_pptable(struct smu_context *smu)
 706 {
 707         struct smu_table_context *table_context = &smu->smu_table;
 708         int ret = 0;
 709
 710         ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
 711                                table_context->driver_pptable, true);
 712
 713         return ret;
 714 }
 715
 716 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 717 {
 718         return smu_update_table(smu, SMU_TABLE_WATERMARKS,
 719                                 smu->smu_table.tables[SMU_TABLE_WATERMARKS].cpu_addr,
 720                                 true);
 721 }
 722
 723 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 724 {
 725         int ret;
 726
 727         ret = smu_send_smc_msg_with_param(smu,
 728                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 729         if (ret)
 730                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 731
 732         return ret;
 733 }
 734
 735 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 736 {
 737         struct smu_table_context *table_context = &smu->smu_table;
 738
 739         if (!smu->pm_enabled)
 740                 return 0;
 741         if (!table_context)
 742                 return -EINVAL;
 743
 744         return smu_set_deep_sleep_dcefclk(smu,
 745                                           table_context->boot_values.dcefclk / 100);
 746 }
 747
 748 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 749 {
 750         int ret = 0;
 751         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 752
 753         if (tool_table->mc_address) {
 754                 ret = smu_send_smc_msg_with_param(smu,
 755                                 SMU_MSG_SetToolsDramAddrHigh,
 756                                 upper_32_bits(tool_table->mc_address));
 757                 if (!ret)
 758                         ret = smu_send_smc_msg_with_param(smu,
 759                                 SMU_MSG_SetToolsDramAddrLow,
 760                                 lower_32_bits(tool_table->mc_address));
 761         }
 762
 763         return ret;
 764 }
 765
 766 static int smu_v11_0_init_display(struct smu_context *smu)
 767 {
 768         int ret = 0;
 769
 770         if (!smu->pm_enabled)
 771                 return ret;
 772         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 773         return ret;
 774 }
 775
 776 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 777 {
 778         uint32_t feature_low = 0, feature_high = 0;
 779         int ret = 0;
 780
 781         if (!smu->pm_enabled)
 782                 return ret;
 783         if (feature_id >= 0 && feature_id < 31)
 784                 feature_low = (1 << feature_id);
 785         else if (feature_id > 31 && feature_id < 63)
 786                 feature_high = (1 << feature_id);
 787         else
 788                 return -EINVAL;
 789
 790         if (enabled) {
 791                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 792                                                   feature_low);
 793                 if (ret)
 794                         return ret;
 795                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 796                                                   feature_high);
 797                 if (ret)
 798                         return ret;
 799
 800         } else {
 801                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 802                                                   feature_low);
 803                 if (ret)
 804                         return ret;
 805                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 806                                                   feature_high);
 807                 if (ret)
 808                         return ret;
 809
 810         }
 811
 812         return ret;
 813 }
 814
 815 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 816 {
 817         struct smu_feature *feature = &smu->smu_feature;
 818         int ret = 0;
 819         uint32_t feature_mask[2];
 820
 821         mutex_lock(&feature->mutex);
 822         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 823                 goto failed;
 824
 825         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 826
 827         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 828                                           feature_mask[1]);
 829         if (ret)
 830                 goto failed;
 831
 832         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 833                                           feature_mask[0]);
 834         if (ret)
 835                 goto failed;
 836
 837 failed:
 838         mutex_unlock(&feature->mutex);
 839         return ret;
 840 }
 841
 842 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 843                                       uint32_t *feature_mask, uint32_t num)
 844 {
 845         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 846         int ret = 0;
 847
 848         if (!feature_mask || num < 2)
 849                 return -EINVAL;
 850
 851         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 852         if (ret)
 853                 return ret;
 854         ret = smu_read_smc_arg(smu, &feature_mask_high);
 855         if (ret)
 856                 return ret;
 857
 858         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 859         if (ret)
 860                 return ret;
 861         ret = smu_read_smc_arg(smu, &feature_mask_low);
 862         if (ret)
 863                 return ret;
 864
 865         feature_mask[0] = feature_mask_low;
 866         feature_mask[1] = feature_mask_high;
 867
 868         return ret;
 869 }
 870
 871 static int smu_v11_0_system_features_control(struct smu_context *smu,
 872                                              bool en)
 873 {
 874         struct smu_feature *feature = &smu->smu_feature;
 875         uint32_t feature_mask[2];
 876         int ret = 0;
 877
 878         if (smu->pm_enabled) {
 879                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 880                                              SMU_MSG_DisableAllSmuFeatures));
 881                 if (ret)
 882                         return ret;
 883         }
 884
 885         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 886         if (ret)
 887                 return ret;
 888
 889         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 890                     feature->feature_num);
 891         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 892                     feature->feature_num);
 893
 894         return ret;
 895 }
 896
 897 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 898 {
 899         int ret = 0;
 900
 901         if (!smu->pm_enabled)
 902                 return ret;
 903         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 904             ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 905
 906         return ret;
 907 }
 908
 909 static int
 910 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 911                                     enum smu_clk_type clock_select)
 912 {
 913         int ret = 0;
 914
 915         if (!smu->pm_enabled)
 916                 return ret;
 917         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 918                                           smu_clk_get_index(smu, clock_select) << 16);
 919         if (ret) {
 920                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 921                 return ret;
 922         }
 923
 924         ret = smu_read_smc_arg(smu, clock);
 925         if (ret)
 926                 return ret;
 927
 928         if (*clock != 0)
 929                 return 0;
 930
 931         /* if DC limit is zero, return AC limit */
 932         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 933                                           smu_clk_get_index(smu, clock_select) << 16);
 934         if (ret) {
 935                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 936                 return ret;
 937         }
 938
 939         ret = smu_read_smc_arg(smu, clock);
 940
 941         return ret;
 942 }
 943
 944 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 945 {
 946         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 947         int ret = 0;
 948
 949         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 950                                          GFP_KERNEL);
 951         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 952
 953         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 954         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 955         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 956         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 957         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 958         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 959
 960         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 961                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 962                                                           &(max_sustainable_clocks->uclock),
 963                                                           SMU_UCLK);
 964                 if (ret) {
 965                         pr_err("[%s] failed to get max UCLK from SMC!",
 966                                __func__);
 967                         return ret;
 968                 }
 969         }
 970
 971         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 972                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 973                                                           &(max_sustainable_clocks->soc_clock),
 974                                                           SMU_SOCCLK);
 975                 if (ret) {
 976                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 977                                __func__);
 978                         return ret;
 979                 }
 980         }
 981
 982         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 983                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 984                                                           &(max_sustainable_clocks->dcef_clock),
 985                                                           SMU_DCEFCLK);
 986                 if (ret) {
 987                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
 988                                __func__);
 989                         return ret;
 990                 }
 991
 992                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 993                                                           &(max_sustainable_clocks->display_clock),
 994                                                           SMU_DISPCLK);
 995                 if (ret) {
 996                         pr_err("[%s] failed to get max DISPCLK from SMC!",
 997                                __func__);
 998                         return ret;
 999                 }
1000                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1001                                                           &(max_sustainable_clocks->phy_clock),
1002                                                           SMU_PHYCLK);
1003                 if (ret) {
1004                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1005                                __func__);
1006                         return ret;
1007                 }
1008                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1009                                                           &(max_sustainable_clocks->pixel_clock),
1010                                                           SMU_PIXCLK);
1011                 if (ret) {
1012                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1013                                __func__);
1014                         return ret;
1015                 }
1016         }
1017
1018         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1019                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1020
1021         return 0;
1022 }
1023
1024 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1025                                      uint32_t *limit,
1026                                      bool get_default)
1027 {
1028         int ret = 0;
1029
1030         if (get_default) {
1031                 mutex_lock(&smu->mutex);
1032                 *limit = smu->default_power_limit;
1033                 if (smu->od_enabled) {
1034                         *limit *= (100 + smu->smu_table.TDPODLimit);
1035                         *limit /= 100;
1036                 }
1037                 mutex_unlock(&smu->mutex);
1038         } else {
1039                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1040                                                   POWER_SOURCE_AC << 16);
1041                 if (ret) {
1042                         pr_err("[%s] get PPT limit failed!", __func__);
1043                         return ret;
1044                 }
1045                 smu_read_smc_arg(smu, limit);
1046                 smu->power_limit = *limit;
1047         }
1048
1049         return ret;
1050 }
1051
1052 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1053 {
1054         uint32_t max_power_limit;
1055         int ret = 0;
1056
1057         if (n == 0)
1058                 n = smu->default_power_limit;
1059
1060         max_power_limit = smu->default_power_limit;
1061
1062         if (smu->od_enabled) {
1063                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1064                 max_power_limit /= 100;
1065         }
1066
1067         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1068                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1069         if (ret) {
1070                 pr_err("[%s] Set power limit Failed!", __func__);
1071                 return ret;
1072         }
1073
1074         return ret;
1075 }
1076
1077 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1078                                           enum smu_clk_type clk_id,
1079                                           uint32_t *value)
1080 {
1081         int ret = 0;
1082         uint32_t freq;
1083
1084         if (clk_id >= SMU_CLK_COUNT || !value)
1085                 return -EINVAL;
1086
1087         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1088                                           (smu_clk_get_index(smu, clk_id) << 16));
1089         if (ret)
1090                 return ret;
1091
1092         ret = smu_read_smc_arg(smu, &freq);
1093         if (ret)
1094                 return ret;
1095
1096         freq *= 100;
1097         *value = freq;
1098
1099         return ret;
1100 }
1101
1102 static int smu_v11_0_get_thermal_range(struct smu_context *smu,
1103                                 struct PP_TemperatureRange *range)
1104 {
1105         PPTable_t *pptable = smu->smu_table.driver_pptable;
1106         memcpy(range, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
1107
1108         range->max = pptable->TedgeLimit *
1109                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1110         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1111                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1112         range->hotspot_crit_max = pptable->ThotspotLimit *
1113                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1114         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1115                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1116         range->mem_crit_max = pptable->ThbmLimit *
1117                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1118         range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
1119                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1120
1121         return 0;
1122 }
1123
1124 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1125                         struct PP_TemperatureRange *range)
1126 {
1127         struct amdgpu_device *adev = smu->adev;
1128         int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
1129                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1130         int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
1131                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1132         uint32_t val;
1133
1134         if (low < range->min)
1135                 low = range->min;
1136         if (high > range->max)
1137                 high = range->max;
1138
1139         if (low > high)
1140                 return -EINVAL;
1141
1142         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1143         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1144         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1145         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1146         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1147         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1148
1149         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1150
1151         return 0;
1152 }
1153
1154 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1155 {
1156         struct amdgpu_device *adev = smu->adev;
1157         uint32_t val = 0;
1158
1159         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1160         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1161         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1162
1163         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1164
1165         return 0;
1166 }
1167
1168 static int smu_v11_0_set_thermal_fan_table(struct smu_context *smu)
1169 {
1170         int ret;
1171         struct smu_table_context *table_context = &smu->smu_table;
1172         PPTable_t *pptable = table_context->driver_pptable;
1173
1174         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
1175                         (uint32_t)pptable->FanTargetTemperature);
1176
1177         return ret;
1178 }
1179
1180 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1181 {
1182         int ret = 0;
1183         struct PP_TemperatureRange range = {
1184                 TEMP_RANGE_MIN,
1185                 TEMP_RANGE_MAX,
1186                 TEMP_RANGE_MAX,
1187                 TEMP_RANGE_MIN,
1188                 TEMP_RANGE_MAX,
1189                 TEMP_RANGE_MAX,
1190                 TEMP_RANGE_MIN,
1191                 TEMP_RANGE_MAX,
1192                 TEMP_RANGE_MAX};
1193         struct amdgpu_device *adev = smu->adev;
1194
1195         if (!smu->pm_enabled)
1196                 return ret;
1197         smu_v11_0_get_thermal_range(smu, &range);
1198
1199         if (smu->smu_table.thermal_controller_type) {
1200                 ret = smu_v11_0_set_thermal_range(smu, &range);
1201                 if (ret)
1202                         return ret;
1203
1204                 ret = smu_v11_0_enable_thermal_alert(smu);
1205                 if (ret)
1206                         return ret;
1207                 ret = smu_v11_0_set_thermal_fan_table(smu);
1208                 if (ret)
1209                         return ret;
1210         }
1211
1212         adev->pm.dpm.thermal.min_temp = range.min;
1213         adev->pm.dpm.thermal.max_temp = range.max;
1214         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1215         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1216         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1217         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1218         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1219         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1220         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1221
1222         return ret;
1223 }
1224
1225 static int smu_v11_0_get_metrics_table(struct smu_context *smu,
1226                 SmuMetrics_t *metrics_table)
1227 {
1228         int ret = 0;
1229
1230         if (!smu->metrics_time || time_after(jiffies, smu->metrics_time + HZ / 1000)) {
1231                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
1232                                 (void *)metrics_table, false);
1233                 if (ret) {
1234                         pr_info("Failed to export SMU metrics table!\n");
1235                         return ret;
1236                 }
1237                 memcpy(smu->metrics_table, metrics_table, sizeof(SmuMetrics_t));
1238                 smu->metrics_time = jiffies;
1239         } else
1240                 memcpy(metrics_table, smu->metrics_table, sizeof(SmuMetrics_t));
1241
1242         return ret;
1243 }
1244
1245 static int smu_v11_0_get_current_activity_percent(struct smu_context *smu,
1246                                                   enum amd_pp_sensors sensor,
1247                                                   uint32_t *value)
1248 {
1249         int ret = 0;
1250         SmuMetrics_t metrics;
1251
1252         if (!value)
1253                 return -EINVAL;
1254
1255         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1256         if (ret)
1257                 return ret;
1258
1259         switch (sensor) {
1260         case AMDGPU_PP_SENSOR_GPU_LOAD:
1261                 *value = metrics.AverageGfxActivity;
1262                 break;
1263         case AMDGPU_PP_SENSOR_MEM_LOAD:
1264                 *value = metrics.AverageUclkActivity;
1265                 break;
1266         default:
1267                 pr_err("Invalid sensor for retrieving clock activity\n");
1268                 return -EINVAL;
1269         }
1270
1271         return 0;
1272 }
1273
1274 static int smu_v11_0_thermal_get_temperature(struct smu_context *smu,
1275                                              enum amd_pp_sensors sensor,
1276                                              uint32_t *value)
1277 {
1278         struct amdgpu_device *adev = smu->adev;
1279         SmuMetrics_t metrics;
1280         uint32_t temp = 0;
1281         int ret = 0;
1282
1283         if (!value)
1284                 return -EINVAL;
1285
1286         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1287         if (ret)
1288                 return ret;
1289
1290         switch (sensor) {
1291         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1292                 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
1293                 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
1294                                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
1295
1296                 temp = temp & 0x1ff;
1297                 temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
1298
1299                 *value = temp;
1300                 break;
1301         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1302                 *value = metrics.TemperatureEdge *
1303                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1304                 break;
1305         case AMDGPU_PP_SENSOR_MEM_TEMP:
1306                 *value = metrics.TemperatureHBM *
1307                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1308                 break;
1309         default:
1310                 pr_err("Invalid sensor for retrieving temp\n");
1311                 return -EINVAL;
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int smu_v11_0_get_gpu_power(struct smu_context *smu, uint32_t *value)
1318 {
1319         int ret = 0;
1320         SmuMetrics_t metrics;
1321
1322         if (!value)
1323                 return -EINVAL;
1324
1325         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1326         if (ret)
1327                 return ret;
1328
1329         *value = metrics.CurrSocketPower << 8;
1330
1331         return 0;
1332 }
1333
1334 static uint16_t convert_to_vddc(uint8_t vid)
1335 {
1336         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1337 }
1338
1339 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1340 {
1341         struct amdgpu_device *adev = smu->adev;
1342         uint32_t vdd = 0, val_vid = 0;
1343
1344         if (!value)
1345                 return -EINVAL;
1346         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1347                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1348                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1349
1350         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1351
1352         *value = vdd;
1353
1354         return 0;
1355
1356 }
1357
1358 static int smu_v11_0_read_sensor(struct smu_context *smu,
1359                                  enum amd_pp_sensors sensor,
1360                                  void *data, uint32_t *size)
1361 {
1362         struct smu_table_context *table_context = &smu->smu_table;
1363         PPTable_t *pptable = table_context->driver_pptable;
1364         int ret = 0;
1365         switch (sensor) {
1366         case AMDGPU_PP_SENSOR_GPU_LOAD:
1367         case AMDGPU_PP_SENSOR_MEM_LOAD:
1368                 ret = smu_v11_0_get_current_activity_percent(smu,
1369                                                              sensor,
1370                                                              (uint32_t *)data);
1371                 *size = 4;
1372                 break;
1373         case AMDGPU_PP_SENSOR_GFX_MCLK:
1374                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1375                 *size = 4;
1376                 break;
1377         case AMDGPU_PP_SENSOR_GFX_SCLK:
1378                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1379                 *size = 4;
1380                 break;
1381         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1382         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1383         case AMDGPU_PP_SENSOR_MEM_TEMP:
1384                 ret = smu_v11_0_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1385                 *size = 4;
1386                 break;
1387         case AMDGPU_PP_SENSOR_GPU_POWER:
1388                 ret = smu_v11_0_get_gpu_power(smu, (uint32_t *)data);
1389                 *size = 4;
1390                 break;
1391         case AMDGPU_PP_SENSOR_VDDGFX:
1392                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1393                 *size = 4;
1394                 break;
1395         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1396                 *(uint32_t *)data = 0;
1397                 *size = 4;
1398                 break;
1399         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1400                 *(uint32_t *)data = pptable->FanMaximumRpm;
1401                 *size = 4;
1402                 break;
1403         default:
1404                 ret = smu_common_read_sensor(smu, sensor, data, size);
1405                 break;
1406         }
1407
1408         /* try get sensor data by asic */
1409         if (ret)
1410                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1411
1412         if (ret)
1413                 *size = 0;
1414
1415         return ret;
1416 }
1417
1418 static int
1419 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1420                                         struct pp_display_clock_request
1421                                         *clock_req)
1422 {
1423         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1424         int ret = 0;
1425         enum smu_clk_type clk_select = 0;
1426         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1427
1428         if (!smu->pm_enabled)
1429                 return -EINVAL;
1430         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1431                 switch (clk_type) {
1432                 case amd_pp_dcef_clock:
1433                         clk_select = SMU_DCEFCLK;
1434                         break;
1435                 case amd_pp_disp_clock:
1436                         clk_select = SMU_DISPCLK;
1437                         break;
1438                 case amd_pp_pixel_clock:
1439                         clk_select = SMU_PIXCLK;
1440                         break;
1441                 case amd_pp_phy_clock:
1442                         clk_select = SMU_PHYCLK;
1443                         break;
1444                 default:
1445                         pr_info("[%s] Invalid Clock Type!", __func__);
1446                         ret = -EINVAL;
1447                         break;
1448                 }
1449
1450                 if (ret)
1451                         goto failed;
1452
1453                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1454                         (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1455         }
1456
1457 failed:
1458         return ret;
1459 }
1460
1461 static int smu_v11_0_set_watermarks_table(struct smu_context *smu,
1462                                           Watermarks_t *table, struct
1463                                           dm_pp_wm_sets_with_clock_ranges_soc15
1464                                           *clock_ranges)
1465 {
1466         int i;
1467
1468         if (!table || !clock_ranges)
1469                 return -EINVAL;
1470
1471         if (clock_ranges->num_wm_dmif_sets > 4 ||
1472             clock_ranges->num_wm_mcif_sets > 4)
1473                 return -EINVAL;
1474
1475         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1476                 table->WatermarkRow[1][i].MinClock =
1477                         cpu_to_le16((uint16_t)
1478                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1479                         1000));
1480                 table->WatermarkRow[1][i].MaxClock =
1481                         cpu_to_le16((uint16_t)
1482                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1483                         1000));
1484                 table->WatermarkRow[1][i].MinUclk =
1485                         cpu_to_le16((uint16_t)
1486                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1487                         1000));
1488                 table->WatermarkRow[1][i].MaxUclk =
1489                         cpu_to_le16((uint16_t)
1490                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1491                         1000));
1492                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1493                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1494         }
1495
1496         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1497                 table->WatermarkRow[0][i].MinClock =
1498                         cpu_to_le16((uint16_t)
1499                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1500                         1000));
1501                 table->WatermarkRow[0][i].MaxClock =
1502                         cpu_to_le16((uint16_t)
1503                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1504                         1000));
1505                 table->WatermarkRow[0][i].MinUclk =
1506                         cpu_to_le16((uint16_t)
1507                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1508                         1000));
1509                 table->WatermarkRow[0][i].MaxUclk =
1510                         cpu_to_le16((uint16_t)
1511                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1512                         1000));
1513                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1514                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1515         }
1516
1517         return 0;
1518 }
1519
1520 static int
1521 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1522                                           dm_pp_wm_sets_with_clock_ranges_soc15
1523                                           *clock_ranges)
1524 {
1525         int ret = 0;
1526         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1527         Watermarks_t *table = watermarks->cpu_addr;
1528
1529         if (!smu->disable_watermark &&
1530             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1531             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1532                 smu_v11_0_set_watermarks_table(smu, table, clock_ranges);
1533                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1534                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1535         }
1536
1537         return ret;
1538 }
1539
1540 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1541 {
1542         int ret = 0;
1543         struct amdgpu_device *adev = smu->adev;
1544
1545         switch (adev->asic_type) {
1546         case CHIP_VEGA20:
1547                 break;
1548         case CHIP_NAVI10:
1549                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1550                         return 0;
1551                 mutex_lock(&smu->mutex);
1552                 if (enable)
1553                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1554                 else
1555                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1556                 mutex_unlock(&smu->mutex);
1557                 break;
1558         default:
1559                 break;
1560         }
1561
1562         return ret;
1563 }
1564
1565
1566 static int smu_v11_0_get_clock_ranges(struct smu_context *smu,
1567                                       uint32_t *clock,
1568                                       enum smu_clk_type clock_select,
1569                                       bool max)
1570 {
1571         int ret;
1572         *clock = 0;
1573         if (max) {
1574                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
1575                                 smu_clk_get_index(smu, clock_select) << 16);
1576                 if (ret) {
1577                         pr_err("[GetClockRanges] Failed to get max clock from SMC!\n");
1578                         return ret;
1579                 }
1580                 smu_read_smc_arg(smu, clock);
1581         } else {
1582                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq,
1583                                 smu_clk_get_index(smu, clock_select) << 16);
1584                 if (ret) {
1585                         pr_err("[GetClockRanges] Failed to get min clock from SMC!\n");
1586                         return ret;
1587                 }
1588                 smu_read_smc_arg(smu, clock);
1589         }
1590
1591         return 0;
1592 }
1593
1594 static uint32_t smu_v11_0_dpm_get_sclk(struct smu_context *smu, bool low)
1595 {
1596         uint32_t gfx_clk;
1597         int ret;
1598
1599         if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1600                 pr_err("[GetSclks]: gfxclk dpm not enabled!\n");
1601                 return -EPERM;
1602         }
1603
1604         if (low) {
1605                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, false);
1606                 if (ret) {
1607                         pr_err("[GetSclks]: fail to get min SMU_GFXCLK\n");
1608                         return ret;
1609                 }
1610         } else {
1611                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, true);
1612                 if (ret) {
1613                         pr_err("[GetSclks]: fail to get max SMU_GFXCLK\n");
1614                         return ret;
1615                 }
1616         }
1617
1618         return (gfx_clk * 100);
1619 }
1620
1621 static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low)
1622 {
1623         uint32_t mem_clk;
1624         int ret;
1625
1626         if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1627                 pr_err("[GetMclks]: memclk dpm not enabled!\n");
1628                 return -EPERM;
1629         }
1630
1631         if (low) {
1632                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_UCLK, false);
1633                 if (ret) {
1634                         pr_err("[GetMclks]: fail to get min SMU_UCLK\n");
1635                         return ret;
1636                 }
1637         } else {
1638                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_GFXCLK, true);
1639                 if (ret) {
1640                         pr_err("[GetMclks]: fail to get max SMU_UCLK\n");
1641                         return ret;
1642                 }
1643         }
1644
1645         return (mem_clk * 100);
1646 }
1647
1648 static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
1649                                               bool initialize)
1650 {
1651         struct smu_table_context *table_context = &smu->smu_table;
1652         int ret;
1653
1654         /**
1655          * TODO: Enable overdrive for navi10, that replies on smc/pptable
1656          * support.
1657          */
1658         if (smu->adev->asic_type == CHIP_NAVI10)
1659                 return 0;
1660
1661         if (initialize) {
1662                 if (table_context->overdrive_table)
1663                         return -EINVAL;
1664
1665                 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1666
1667                 if (!table_context->overdrive_table)
1668                         return -ENOMEM;
1669
1670                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1671                                        table_context->overdrive_table, false);
1672                 if (ret) {
1673                         pr_err("Failed to export over drive table!\n");
1674                         return ret;
1675                 }
1676
1677                 smu_set_default_od8_settings(smu);
1678         }
1679
1680         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1681                                table_context->overdrive_table, true);
1682         if (ret) {
1683                 pr_err("Failed to import over drive table!\n");
1684                 return ret;
1685         }
1686
1687         return 0;
1688 }
1689
1690 static int smu_v11_0_update_od8_settings(struct smu_context *smu,
1691                                         uint32_t index,
1692                                         uint32_t value)
1693 {
1694         struct smu_table_context *table_context = &smu->smu_table;
1695         int ret;
1696
1697         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1698                                table_context->overdrive_table, false);
1699         if (ret) {
1700                 pr_err("Failed to export over drive table!\n");
1701                 return ret;
1702         }
1703
1704         smu_update_specified_od8_value(smu, index, value);
1705
1706         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1707                                table_context->overdrive_table, true);
1708         if (ret) {
1709                 pr_err("Failed to import over drive table!\n");
1710                 return ret;
1711         }
1712
1713         return 0;
1714 }
1715
1716 static int smu_v11_0_get_current_rpm(struct smu_context *smu,
1717                                      uint32_t *current_rpm)
1718 {
1719         int ret;
1720
1721         ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
1722
1723         if (ret) {
1724                 pr_err("Attempt to get current RPM from SMC Failed!\n");
1725                 return ret;
1726         }
1727
1728         smu_read_smc_arg(smu, current_rpm);
1729
1730         return 0;
1731 }
1732
1733 static uint32_t
1734 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1735 {
1736         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1737                 return AMD_FAN_CTRL_MANUAL;
1738         else
1739                 return AMD_FAN_CTRL_AUTO;
1740 }
1741
1742 static int
1743 smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
1744                                            uint32_t *speed)
1745 {
1746         int ret = 0;
1747         uint32_t percent = 0;
1748         uint32_t current_rpm;
1749         PPTable_t *pptable = smu->smu_table.driver_pptable;
1750
1751         ret = smu_v11_0_get_current_rpm(smu, &current_rpm);
1752         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1753         *speed = percent > 100 ? 100 : percent;
1754
1755         return ret;
1756 }
1757
1758 static int
1759 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1760 {
1761         int ret = 0;
1762
1763         if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1764                 return 0;
1765
1766         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1767         if (ret)
1768                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1769                        __func__, (start ? "Start" : "Stop"));
1770
1771         return ret;
1772 }
1773
1774 static int
1775 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1776 {
1777         struct amdgpu_device *adev = smu->adev;
1778
1779         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1780                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1781                                    CG_FDO_CTRL2, TMIN, 0));
1782         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1783                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1784                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1785
1786         return 0;
1787 }
1788
1789 static int
1790 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1791 {
1792         struct amdgpu_device *adev = smu->adev;
1793         uint32_t duty100;
1794         uint32_t duty;
1795         uint64_t tmp64;
1796         bool stop = 0;
1797
1798         if (speed > 100)
1799                 speed = 100;
1800
1801         if (smu_v11_0_smc_fan_control(smu, stop))
1802                 return -EINVAL;
1803         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1804                                 CG_FDO_CTRL1, FMAX_DUTY100);
1805         if (!duty100)
1806                 return -EINVAL;
1807
1808         tmp64 = (uint64_t)speed * duty100;
1809         do_div(tmp64, 100);
1810         duty = (uint32_t)tmp64;
1811
1812         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1813                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1814                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1815
1816         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1817 }
1818
1819 static int
1820 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1821                                uint32_t mode)
1822 {
1823         int ret = 0;
1824         bool start = 1;
1825         bool stop  = 0;
1826
1827         switch (mode) {
1828         case AMD_FAN_CTRL_NONE:
1829                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1830                 break;
1831         case AMD_FAN_CTRL_MANUAL:
1832                 ret = smu_v11_0_smc_fan_control(smu, stop);
1833                 break;
1834         case AMD_FAN_CTRL_AUTO:
1835                 ret = smu_v11_0_smc_fan_control(smu, start);
1836                 break;
1837         default:
1838                 break;
1839         }
1840
1841         if (ret) {
1842                 pr_err("[%s]Set fan control mode failed!", __func__);
1843                 return -EINVAL;
1844         }
1845
1846         return ret;
1847 }
1848
1849 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1850                                        uint32_t speed)
1851 {
1852         struct amdgpu_device *adev = smu->adev;
1853         int ret;
1854         uint32_t tach_period, crystal_clock_freq;
1855         bool stop = 0;
1856
1857         if (!speed)
1858                 return -EINVAL;
1859
1860         mutex_lock(&(smu->mutex));
1861         ret = smu_v11_0_smc_fan_control(smu, stop);
1862         if (ret)
1863                 goto set_fan_speed_rpm_failed;
1864
1865         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1866         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1867         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1868                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1869                                    CG_TACH_CTRL, TARGET_PERIOD,
1870                                    tach_period));
1871
1872         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1873
1874 set_fan_speed_rpm_failed:
1875         mutex_unlock(&(smu->mutex));
1876         return ret;
1877 }
1878
1879 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1880                                      uint32_t pstate)
1881 {
1882         int ret = 0;
1883         mutex_lock(&(smu->mutex));
1884         ret = smu_send_smc_msg_with_param(smu,
1885                                           SMU_MSG_SetXgmiMode,
1886                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1887         mutex_unlock(&(smu->mutex));
1888         return ret;
1889 }
1890
1891 static const struct smu_funcs smu_v11_0_funcs = {
1892         .init_microcode = smu_v11_0_init_microcode,
1893         .load_microcode = smu_v11_0_load_microcode,
1894         .check_fw_status = smu_v11_0_check_fw_status,
1895         .check_fw_version = smu_v11_0_check_fw_version,
1896         .send_smc_msg = smu_v11_0_send_msg,
1897         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1898         .read_smc_arg = smu_v11_0_read_arg,
1899         .setup_pptable = smu_v11_0_setup_pptable,
1900         .init_smc_tables = smu_v11_0_init_smc_tables,
1901         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1902         .init_power = smu_v11_0_init_power,
1903         .fini_power = smu_v11_0_fini_power,
1904         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1905         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1906         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1907         .check_pptable = smu_v11_0_check_pptable,
1908         .parse_pptable = smu_v11_0_parse_pptable,
1909         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1910         .write_pptable = smu_v11_0_write_pptable,
1911         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1912         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1913         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1914         .init_display = smu_v11_0_init_display,
1915         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1916         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1917         .system_features_control = smu_v11_0_system_features_control,
1918         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1919         .notify_display_change = smu_v11_0_notify_display_change,
1920         .get_power_limit = smu_v11_0_get_power_limit,
1921         .set_power_limit = smu_v11_0_set_power_limit,
1922         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1923         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1924         .start_thermal_control = smu_v11_0_start_thermal_control,
1925         .read_sensor = smu_v11_0_read_sensor,
1926         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1927         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1928         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1929         .get_sclk = smu_v11_0_dpm_get_sclk,
1930         .get_mclk = smu_v11_0_dpm_get_mclk,
1931         .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
1932         .update_od8_settings = smu_v11_0_update_od8_settings,
1933         .get_current_rpm = smu_v11_0_get_current_rpm,
1934         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1935         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1936         .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
1937         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1938         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1939         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1940         .gfx_off_control = smu_v11_0_gfx_off_control,
1941 };
1942
1943 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1944 {
1945         struct amdgpu_device *adev = smu->adev;
1946
1947         smu->funcs = &smu_v11_0_funcs;
1948         switch (adev->asic_type) {
1949         case CHIP_VEGA20:
1950                 vega20_set_ppt_funcs(smu);
1951                 break;
1952         case CHIP_NAVI10:
1953                 navi10_set_ppt_funcs(smu);
1954                 break;
1955         default:
1956                 pr_warn("Unknown asic for smu11\n");
1957         }
1958 }