drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pp_debug.h"
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "atomfirmware.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "smu_v11_0.h"
  30 #include "soc15_common.h"
  31 #include "atom.h"
  32 #include "vega20_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "pp_thermal.h"
  35
  36 #include "asic_reg/thm/thm_11_0_2_offset.h"
  37 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  38 #include "asic_reg/mp/mp_11_0_offset.h"
  39 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  40 #include "asic_reg/nbio/nbio_7_4_offset.h"
  41 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  42 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  43
  44 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  45 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  46
  47 #define SMU11_THERMAL_MINIMUM_ALERT_TEMP      0
  48 #define SMU11_THERMAL_MAXIMUM_ALERT_TEMP      255
  49
  50 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
  51 #define SMU11_VOLTAGE_SCALE 4
  52
  53 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  54                                               uint16_t msg)
  55 {
  56         struct amdgpu_device *adev = smu->adev;
  57         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  58         return 0;
  59 }
  60
  61 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  62 {
  63         struct amdgpu_device *adev = smu->adev;
  64
  65         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  66         return 0;
  67 }
  68
  69 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  70 {
  71         struct amdgpu_device *adev = smu->adev;
  72         uint32_t cur_value, i;
  73
  74         for (i = 0; i < adev->usec_timeout; i++) {
  75                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  76                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  77                         break;
  78                 udelay(1);
  79         }
  80
  81         /* timeout means wrong logic */
  82         if (i == adev->usec_timeout)
  83                 return -ETIME;
  84
  85         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  86 }
  87
  88 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  89 {
  90         struct amdgpu_device *adev = smu->adev;
  91         int ret = 0, index = 0;
  92
  93         index = smu_msg_get_index(smu, msg);
  94         if (index < 0)
  95                 return index;
  96
  97         smu_v11_0_wait_for_response(smu);
  98
  99         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 100
 101         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 102
 103         ret = smu_v11_0_wait_for_response(smu);
 104
 105         if (ret)
 106                 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 107                        ret);
 108
 109         return ret;
 110
 111 }
 112
 113 static int
 114 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 115                               uint32_t param)
 116 {
 117
 118         struct amdgpu_device *adev = smu->adev;
 119         int ret = 0, index = 0;
 120
 121         index = smu_msg_get_index(smu, msg);
 122         if (index < 0)
 123                 return index;
 124
 125         ret = smu_v11_0_wait_for_response(smu);
 126         if (ret)
 127                 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
 128                        index, ret, param);
 129
 130         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 131
 132         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 133
 134         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 135
 136         ret = smu_v11_0_wait_for_response(smu);
 137         if (ret)
 138                 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
 139                        index, ret, param);
 140
 141         return ret;
 142 }
 143
 144 static int smu_v11_0_init_microcode(struct smu_context *smu)
 145 {
 146         struct amdgpu_device *adev = smu->adev;
 147         const char *chip_name;
 148         char fw_name[30];
 149         int err = 0;
 150         const struct smc_firmware_header_v1_0 *hdr;
 151         const struct common_firmware_header *header;
 152         struct amdgpu_firmware_info *ucode = NULL;
 153
 154         switch (adev->asic_type) {
 155         case CHIP_VEGA20:
 156                 chip_name = "vega20";
 157                 break;
 158         case CHIP_NAVI10:
 159                 chip_name = "navi10";
 160                 break;
 161         default:
 162                 BUG();
 163         }
 164
 165         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 166
 167         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 168         if (err)
 169                 goto out;
 170         err = amdgpu_ucode_validate(adev->pm.fw);
 171         if (err)
 172                 goto out;
 173
 174         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 175         amdgpu_ucode_print_smc_hdr(&hdr->header);
 176         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 177
 178         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 179                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 180                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 181                 ucode->fw = adev->pm.fw;
 182                 header = (const struct common_firmware_header *)ucode->fw->data;
 183                 adev->firmware.fw_size +=
 184                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 185         }
 186
 187 out:
 188         if (err) {
 189                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 190                           fw_name);
 191                 release_firmware(adev->pm.fw);
 192                 adev->pm.fw = NULL;
 193         }
 194         return err;
 195 }
 196
 197 static int smu_v11_0_load_microcode(struct smu_context *smu)
 198 {
 199         struct amdgpu_device *adev = smu->adev;
 200         const uint32_t *src;
 201         const struct smc_firmware_header_v1_0 *hdr;
 202         uint32_t addr_start = MP1_SRAM;
 203         uint32_t i;
 204         uint32_t mp1_fw_flags;
 205
 206         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 207         src = (const uint32_t *)(adev->pm.fw->data +
 208                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 209
 210         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 211                 WREG32_PCIE(addr_start, src[i]);
 212                 addr_start += 4;
 213         }
 214
 215         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 216                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 217         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 218                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 219
 220         for (i = 0; i < adev->usec_timeout; i++) {
 221                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 222                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 223                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 224                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 225                         break;
 226                 udelay(1);
 227         }
 228
 229         if (i == adev->usec_timeout)
 230                 return -ETIME;
 231
 232         return 0;
 233 }
 234
 235 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 236 {
 237         struct amdgpu_device *adev = smu->adev;
 238         uint32_t mp1_fw_flags;
 239
 240         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 241                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 242
 243         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 244             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 245                 return 0;
 246
 247         return -EIO;
 248 }
 249
 250 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 251 {
 252         uint32_t if_version = 0xff, smu_version = 0xff;
 253         uint16_t smu_major;
 254         uint8_t smu_minor, smu_debug;
 255         int ret = 0;
 256
 257         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 258         if (ret)
 259                 return ret;
 260
 261         smu_major = (smu_version >> 16) & 0xffff;
 262         smu_minor = (smu_version >> 8) & 0xff;
 263         smu_debug = (smu_version >> 0) & 0xff;
 264
 265         pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x (%d.%d.%d)\n",
 266                 if_version, smu_version, smu_major, smu_minor, smu_debug);
 267
 268         if (if_version != smu->smc_if_version) {
 269                 pr_err("SMU driver if version not matched\n");
 270                 ret = -EINVAL;
 271         }
 272
 273         return ret;
 274 }
 275
 276 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 277 {
 278         struct amdgpu_device *adev = smu->adev;
 279         uint32_t ppt_offset_bytes;
 280         const struct smc_firmware_header_v2_0 *v2;
 281
 282         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 283
 284         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 285         *size = le32_to_cpu(v2->ppt_size_bytes);
 286         *table = (uint8_t *)v2 + ppt_offset_bytes;
 287
 288         return 0;
 289 }
 290
 291 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
 292 {
 293         struct amdgpu_device *adev = smu->adev;
 294         const struct smc_firmware_header_v2_1 *v2_1;
 295         struct smc_soft_pptable_entry *entries;
 296         uint32_t pptable_count = 0;
 297         int i = 0;
 298
 299         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 300         entries = (struct smc_soft_pptable_entry *)
 301                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 302         pptable_count = le32_to_cpu(v2_1->pptable_count);
 303         for (i = 0; i < pptable_count; i++) {
 304                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 305                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 306                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 307                         break;
 308                 }
 309         }
 310
 311         if (i == pptable_count)
 312                 return -EINVAL;
 313
 314         return 0;
 315 }
 316
 317 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 318 {
 319         struct amdgpu_device *adev = smu->adev;
 320         const struct smc_firmware_header_v1_0 *hdr;
 321         int ret, index;
 322         uint32_t size;
 323         uint8_t frev, crev;
 324         void *table;
 325         uint16_t version_major, version_minor;
 326
 327         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 328         version_major = le16_to_cpu(hdr->header.header_version_major);
 329         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 330         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 331                 switch (version_minor) {
 332                 case 0:
 333                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 334                         break;
 335                 case 1:
 336                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 337                                                          smu->smu_table.boot_values.pp_table_id);
 338                         break;
 339                 default:
 340                         ret = -EINVAL;
 341                         break;
 342                 }
 343                 if (ret)
 344                         return ret;
 345
 346         } else {
 347                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 348                                                     powerplayinfo);
 349
 350                 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
 351                                               (uint8_t **)&table);
 352                 if (ret)
 353                         return ret;
 354         }
 355
 356         if (!smu->smu_table.power_play_table)
 357                 smu->smu_table.power_play_table = table;
 358         if (!smu->smu_table.power_play_table_size)
 359                 smu->smu_table.power_play_table_size = size;
 360
 361         return 0;
 362 }
 363
 364 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 365 {
 366         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 367
 368         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 369                 return -EINVAL;
 370
 371         return smu_alloc_dpm_context(smu);
 372 }
 373
 374 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 375 {
 376         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 377
 378         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 379                 return -EINVAL;
 380
 381         kfree(smu_dpm->dpm_context);
 382         kfree(smu_dpm->golden_dpm_context);
 383         kfree(smu_dpm->dpm_current_power_state);
 384         kfree(smu_dpm->dpm_request_power_state);
 385         smu_dpm->dpm_context = NULL;
 386         smu_dpm->golden_dpm_context = NULL;
 387         smu_dpm->dpm_context_size = 0;
 388         smu_dpm->dpm_current_power_state = NULL;
 389         smu_dpm->dpm_request_power_state = NULL;
 390
 391         return 0;
 392 }
 393
 394 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 395 {
 396         struct smu_table_context *smu_table = &smu->smu_table;
 397         struct smu_table *tables = NULL;
 398         int ret = 0;
 399
 400         if (smu_table->tables || smu_table->table_count == 0)
 401                 return -EINVAL;
 402
 403         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 404                          GFP_KERNEL);
 405         if (!tables)
 406                 return -ENOMEM;
 407
 408         smu_table->tables = tables;
 409
 410         ret = smu_tables_init(smu, tables);
 411         if (ret)
 412                 return ret;
 413
 414         ret = smu_v11_0_init_dpm_context(smu);
 415         if (ret)
 416                 return ret;
 417
 418         return 0;
 419 }
 420
 421 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 422 {
 423         struct smu_table_context *smu_table = &smu->smu_table;
 424         int ret = 0;
 425
 426         if (!smu_table->tables || smu_table->table_count == 0)
 427                 return -EINVAL;
 428
 429         kfree(smu_table->tables);
 430         kfree(smu_table->metrics_table);
 431         smu_table->tables = NULL;
 432         smu_table->table_count = 0;
 433         smu_table->metrics_table = NULL;
 434         smu_table->metrics_time = 0;
 435
 436         ret = smu_v11_0_fini_dpm_context(smu);
 437         if (ret)
 438                 return ret;
 439         return 0;
 440 }
 441
 442 static int smu_v11_0_init_power(struct smu_context *smu)
 443 {
 444         struct smu_power_context *smu_power = &smu->smu_power;
 445
 446         if (!smu->pm_enabled)
 447                 return 0;
 448         if (smu_power->power_context || smu_power->power_context_size != 0)
 449                 return -EINVAL;
 450
 451         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 452                                            GFP_KERNEL);
 453         if (!smu_power->power_context)
 454                 return -ENOMEM;
 455         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 456
 457         return 0;
 458 }
 459
 460 static int smu_v11_0_fini_power(struct smu_context *smu)
 461 {
 462         struct smu_power_context *smu_power = &smu->smu_power;
 463
 464         if (!smu->pm_enabled)
 465                 return 0;
 466         if (!smu_power->power_context || smu_power->power_context_size == 0)
 467                 return -EINVAL;
 468
 469         kfree(smu_power->power_context);
 470         smu_power->power_context = NULL;
 471         smu_power->power_context_size = 0;
 472
 473         return 0;
 474 }
 475
 476 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 477 {
 478         int ret, index;
 479         uint16_t size;
 480         uint8_t frev, crev;
 481         struct atom_common_table_header *header;
 482         struct atom_firmware_info_v3_3 *v_3_3;
 483         struct atom_firmware_info_v3_1 *v_3_1;
 484
 485         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 486                                             firmwareinfo);
 487
 488         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 489                                       (uint8_t **)&header);
 490         if (ret)
 491                 return ret;
 492
 493         if (header->format_revision != 3) {
 494                 pr_err("unknown atom_firmware_info version! for smu11\n");
 495                 return -EINVAL;
 496         }
 497
 498         switch (header->content_revision) {
 499         case 0:
 500         case 1:
 501         case 2:
 502                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 503                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 504                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 505                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 506                 smu->smu_table.boot_values.socclk = 0;
 507                 smu->smu_table.boot_values.dcefclk = 0;
 508                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 509                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 510                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 511                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 512                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 513                 smu->smu_table.boot_values.pp_table_id = 0;
 514                 break;
 515         case 3:
 516         default:
 517                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 518                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 519                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 520                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 521                 smu->smu_table.boot_values.socclk = 0;
 522                 smu->smu_table.boot_values.dcefclk = 0;
 523                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 524                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 525                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 526                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 527                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 528                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 535 {
 536         int ret, index;
 537         struct amdgpu_device *adev = smu->adev;
 538         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 539         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 540
 541         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 542         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 543         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 544                                             getsmuclockinfo);
 545
 546         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 547                                         (uint32_t *)&input);
 548         if (ret)
 549                 return -EINVAL;
 550
 551         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 552         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 553
 554         memset(&input, 0, sizeof(input));
 555         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 556         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 557         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 558                                             getsmuclockinfo);
 559
 560         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 561                                         (uint32_t *)&input);
 562         if (ret)
 563                 return -EINVAL;
 564
 565         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 566         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 567
 568         memset(&input, 0, sizeof(input));
 569         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 570         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 571         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 572                                             getsmuclockinfo);
 573
 574         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 575                                         (uint32_t *)&input);
 576         if (ret)
 577                 return -EINVAL;
 578
 579         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 580         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 581
 582         memset(&input, 0, sizeof(input));
 583         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 584         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 585         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 586                                             getsmuclockinfo);
 587
 588         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 589                                         (uint32_t *)&input);
 590         if (ret)
 591                 return -EINVAL;
 592
 593         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 594         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 595
 596         memset(&input, 0, sizeof(input));
 597         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 598         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 599         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 600                                             getsmuclockinfo);
 601
 602         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 603                                         (uint32_t *)&input);
 604         if (ret)
 605                 return -EINVAL;
 606
 607         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 608         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 609
 610         return 0;
 611 }
 612
 613 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 614 {
 615         struct smu_table_context *smu_table = &smu->smu_table;
 616         struct smu_table *memory_pool = &smu_table->memory_pool;
 617         int ret = 0;
 618         uint64_t address;
 619         uint32_t address_low, address_high;
 620
 621         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 622                 return ret;
 623
 624         address = (uintptr_t)memory_pool->cpu_addr;
 625         address_high = (uint32_t)upper_32_bits(address);
 626         address_low  = (uint32_t)lower_32_bits(address);
 627
 628         ret = smu_send_smc_msg_with_param(smu,
 629                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 630                                           address_high);
 631         if (ret)
 632                 return ret;
 633         ret = smu_send_smc_msg_with_param(smu,
 634                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 635                                           address_low);
 636         if (ret)
 637                 return ret;
 638
 639         address = memory_pool->mc_address;
 640         address_high = (uint32_t)upper_32_bits(address);
 641         address_low  = (uint32_t)lower_32_bits(address);
 642
 643         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 644                                           address_high);
 645         if (ret)
 646                 return ret;
 647         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 648                                           address_low);
 649         if (ret)
 650                 return ret;
 651         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 652                                           (uint32_t)memory_pool->size);
 653         if (ret)
 654                 return ret;
 655
 656         return ret;
 657 }
 658
 659 static int smu_v11_0_check_pptable(struct smu_context *smu)
 660 {
 661         int ret;
 662
 663         ret = smu_check_powerplay_table(smu);
 664         return ret;
 665 }
 666
 667 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 668 {
 669         int ret;
 670
 671         struct smu_table_context *table_context = &smu->smu_table;
 672         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 673
 674         if (table_context->driver_pptable)
 675                 return -EINVAL;
 676
 677         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 678
 679         if (!table_context->driver_pptable)
 680                 return -ENOMEM;
 681
 682         ret = smu_store_powerplay_table(smu);
 683         if (ret)
 684                 return -EINVAL;
 685
 686         ret = smu_append_powerplay_table(smu);
 687
 688         return ret;
 689 }
 690
 691 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 692 {
 693         int ret;
 694
 695         ret = smu_set_default_dpm_table(smu);
 696
 697         return ret;
 698 }
 699
 700 static int smu_v11_0_write_pptable(struct smu_context *smu)
 701 {
 702         struct smu_table_context *table_context = &smu->smu_table;
 703         int ret = 0;
 704
 705         ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
 706                                table_context->driver_pptable, true);
 707
 708         return ret;
 709 }
 710
 711 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 712 {
 713         int ret = 0;
 714         struct smu_table_context *smu_table = &smu->smu_table;
 715         struct smu_table *table = NULL;
 716
 717         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
 718         if (!table)
 719                 return -EINVAL;
 720
 721         if (!table->cpu_addr)
 722                 return -EINVAL;
 723
 724         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
 725                                 true);
 726
 727         return ret;
 728 }
 729
 730 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 731 {
 732         int ret;
 733
 734         ret = smu_send_smc_msg_with_param(smu,
 735                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 736         if (ret)
 737                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 738
 739         return ret;
 740 }
 741
 742 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 743 {
 744         struct smu_table_context *table_context = &smu->smu_table;
 745
 746         if (!smu->pm_enabled)
 747                 return 0;
 748         if (!table_context)
 749                 return -EINVAL;
 750
 751         return smu_set_deep_sleep_dcefclk(smu,
 752                                           table_context->boot_values.dcefclk / 100);
 753 }
 754
 755 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 756 {
 757         int ret = 0;
 758         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 759
 760         if (tool_table->mc_address) {
 761                 ret = smu_send_smc_msg_with_param(smu,
 762                                 SMU_MSG_SetToolsDramAddrHigh,
 763                                 upper_32_bits(tool_table->mc_address));
 764                 if (!ret)
 765                         ret = smu_send_smc_msg_with_param(smu,
 766                                 SMU_MSG_SetToolsDramAddrLow,
 767                                 lower_32_bits(tool_table->mc_address));
 768         }
 769
 770         return ret;
 771 }
 772
 773 static int smu_v11_0_init_display(struct smu_context *smu)
 774 {
 775         int ret = 0;
 776
 777         if (!smu->pm_enabled)
 778                 return ret;
 779         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 780         return ret;
 781 }
 782
 783 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 784 {
 785         uint32_t feature_low = 0, feature_high = 0;
 786         int ret = 0;
 787
 788         if (!smu->pm_enabled)
 789                 return ret;
 790         if (feature_id >= 0 && feature_id < 31)
 791                 feature_low = (1 << feature_id);
 792         else if (feature_id > 31 && feature_id < 63)
 793                 feature_high = (1 << feature_id);
 794         else
 795                 return -EINVAL;
 796
 797         if (enabled) {
 798                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 799                                                   feature_low);
 800                 if (ret)
 801                         return ret;
 802                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 803                                                   feature_high);
 804                 if (ret)
 805                         return ret;
 806
 807         } else {
 808                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 809                                                   feature_low);
 810                 if (ret)
 811                         return ret;
 812                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 813                                                   feature_high);
 814                 if (ret)
 815                         return ret;
 816
 817         }
 818
 819         return ret;
 820 }
 821
 822 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 823 {
 824         struct smu_feature *feature = &smu->smu_feature;
 825         int ret = 0;
 826         uint32_t feature_mask[2];
 827
 828         mutex_lock(&feature->mutex);
 829         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 830                 goto failed;
 831
 832         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 833
 834         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 835                                           feature_mask[1]);
 836         if (ret)
 837                 goto failed;
 838
 839         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 840                                           feature_mask[0]);
 841         if (ret)
 842                 goto failed;
 843
 844 failed:
 845         mutex_unlock(&feature->mutex);
 846         return ret;
 847 }
 848
 849 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 850                                       uint32_t *feature_mask, uint32_t num)
 851 {
 852         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 853         int ret = 0;
 854
 855         if (!feature_mask || num < 2)
 856                 return -EINVAL;
 857
 858         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 859         if (ret)
 860                 return ret;
 861         ret = smu_read_smc_arg(smu, &feature_mask_high);
 862         if (ret)
 863                 return ret;
 864
 865         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 866         if (ret)
 867                 return ret;
 868         ret = smu_read_smc_arg(smu, &feature_mask_low);
 869         if (ret)
 870                 return ret;
 871
 872         feature_mask[0] = feature_mask_low;
 873         feature_mask[1] = feature_mask_high;
 874
 875         return ret;
 876 }
 877
 878 static int smu_v11_0_system_features_control(struct smu_context *smu,
 879                                              bool en)
 880 {
 881         struct smu_feature *feature = &smu->smu_feature;
 882         uint32_t feature_mask[2];
 883         int ret = 0;
 884
 885         if (smu->pm_enabled) {
 886                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 887                                              SMU_MSG_DisableAllSmuFeatures));
 888                 if (ret)
 889                         return ret;
 890         }
 891
 892         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 893         if (ret)
 894                 return ret;
 895
 896         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 897                     feature->feature_num);
 898         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 899                     feature->feature_num);
 900
 901         return ret;
 902 }
 903
 904 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 905 {
 906         int ret = 0;
 907
 908         if (!smu->pm_enabled)
 909                 return ret;
 910         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 911             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 912                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 913
 914         return ret;
 915 }
 916
 917 static int
 918 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 919                                     enum smu_clk_type clock_select)
 920 {
 921         int ret = 0;
 922
 923         if (!smu->pm_enabled)
 924                 return ret;
 925         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 926                                           smu_clk_get_index(smu, clock_select) << 16);
 927         if (ret) {
 928                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 929                 return ret;
 930         }
 931
 932         ret = smu_read_smc_arg(smu, clock);
 933         if (ret)
 934                 return ret;
 935
 936         if (*clock != 0)
 937                 return 0;
 938
 939         /* if DC limit is zero, return AC limit */
 940         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 941                                           smu_clk_get_index(smu, clock_select) << 16);
 942         if (ret) {
 943                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 944                 return ret;
 945         }
 946
 947         ret = smu_read_smc_arg(smu, clock);
 948
 949         return ret;
 950 }
 951
 952 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 953 {
 954         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 955         int ret = 0;
 956
 957         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 958                                          GFP_KERNEL);
 959         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 960
 961         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 962         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 963         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 964         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 965         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 966         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 967
 968         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 969                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 970                                                           &(max_sustainable_clocks->uclock),
 971                                                           SMU_UCLK);
 972                 if (ret) {
 973                         pr_err("[%s] failed to get max UCLK from SMC!",
 974                                __func__);
 975                         return ret;
 976                 }
 977         }
 978
 979         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 980                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 981                                                           &(max_sustainable_clocks->soc_clock),
 982                                                           SMU_SOCCLK);
 983                 if (ret) {
 984                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 985                                __func__);
 986                         return ret;
 987                 }
 988         }
 989
 990         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 991                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 992                                                           &(max_sustainable_clocks->dcef_clock),
 993                                                           SMU_DCEFCLK);
 994                 if (ret) {
 995                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
 996                                __func__);
 997                         return ret;
 998                 }
 999
1000                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1001                                                           &(max_sustainable_clocks->display_clock),
1002                                                           SMU_DISPCLK);
1003                 if (ret) {
1004                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1005                                __func__);
1006                         return ret;
1007                 }
1008                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1009                                                           &(max_sustainable_clocks->phy_clock),
1010                                                           SMU_PHYCLK);
1011                 if (ret) {
1012                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1013                                __func__);
1014                         return ret;
1015                 }
1016                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1017                                                           &(max_sustainable_clocks->pixel_clock),
1018                                                           SMU_PIXCLK);
1019                 if (ret) {
1020                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1021                                __func__);
1022                         return ret;
1023                 }
1024         }
1025
1026         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1027                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1028
1029         return 0;
1030 }
1031
1032 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1033                                      uint32_t *limit,
1034                                      bool get_default)
1035 {
1036         int ret = 0;
1037
1038         if (get_default) {
1039                 mutex_lock(&smu->mutex);
1040                 *limit = smu->default_power_limit;
1041                 if (smu->od_enabled) {
1042                         *limit *= (100 + smu->smu_table.TDPODLimit);
1043                         *limit /= 100;
1044                 }
1045                 mutex_unlock(&smu->mutex);
1046         } else {
1047                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1048                         smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
1049                 if (ret) {
1050                         pr_err("[%s] get PPT limit failed!", __func__);
1051                         return ret;
1052                 }
1053                 smu_read_smc_arg(smu, limit);
1054                 smu->power_limit = *limit;
1055         }
1056
1057         return ret;
1058 }
1059
1060 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1061 {
1062         uint32_t max_power_limit;
1063         int ret = 0;
1064
1065         if (n == 0)
1066                 n = smu->default_power_limit;
1067
1068         max_power_limit = smu->default_power_limit;
1069
1070         if (smu->od_enabled) {
1071                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1072                 max_power_limit /= 100;
1073         }
1074
1075         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1076                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1077         if (ret) {
1078                 pr_err("[%s] Set power limit Failed!", __func__);
1079                 return ret;
1080         }
1081
1082         return ret;
1083 }
1084
1085 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1086                                           enum smu_clk_type clk_id,
1087                                           uint32_t *value)
1088 {
1089         int ret = 0;
1090         uint32_t freq;
1091
1092         if (clk_id >= SMU_CLK_COUNT || !value)
1093                 return -EINVAL;
1094
1095         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1096         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
1097                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1098         else {
1099                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1100                                                   (smu_clk_get_index(smu, clk_id) << 16));
1101                 if (ret)
1102                         return ret;
1103
1104                 ret = smu_read_smc_arg(smu, &freq);
1105                 if (ret)
1106                         return ret;
1107         }
1108
1109         freq *= 100;
1110         *value = freq;
1111
1112         return ret;
1113 }
1114
1115 static int smu_v11_0_get_thermal_range(struct smu_context *smu,
1116                                 struct PP_TemperatureRange *range)
1117 {
1118         PPTable_t *pptable = smu->smu_table.driver_pptable;
1119         memcpy(range, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
1120
1121         range->max = pptable->TedgeLimit *
1122                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1123         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1124                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1125         range->hotspot_crit_max = pptable->ThotspotLimit *
1126                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1127         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1128                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1129         range->mem_crit_max = pptable->ThbmLimit *
1130                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1131         range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
1132                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1133
1134         return 0;
1135 }
1136
1137 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1138                         struct PP_TemperatureRange *range)
1139 {
1140         struct amdgpu_device *adev = smu->adev;
1141         int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
1142                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1143         int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
1144                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1145         uint32_t val;
1146
1147         if (low < range->min)
1148                 low = range->min;
1149         if (high > range->max)
1150                 high = range->max;
1151
1152         if (low > high)
1153                 return -EINVAL;
1154
1155         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1156         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1157         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1158         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1159         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1160         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1161
1162         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1163
1164         return 0;
1165 }
1166
1167 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1168 {
1169         struct amdgpu_device *adev = smu->adev;
1170         uint32_t val = 0;
1171
1172         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1173         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1174         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1175
1176         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1177
1178         return 0;
1179 }
1180
1181 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1182 {
1183         int ret = 0;
1184         struct PP_TemperatureRange range = {
1185                 TEMP_RANGE_MIN,
1186                 TEMP_RANGE_MAX,
1187                 TEMP_RANGE_MAX,
1188                 TEMP_RANGE_MIN,
1189                 TEMP_RANGE_MAX,
1190                 TEMP_RANGE_MAX,
1191                 TEMP_RANGE_MIN,
1192                 TEMP_RANGE_MAX,
1193                 TEMP_RANGE_MAX};
1194         struct amdgpu_device *adev = smu->adev;
1195
1196         if (!smu->pm_enabled)
1197                 return ret;
1198         smu_v11_0_get_thermal_range(smu, &range);
1199
1200         if (smu->smu_table.thermal_controller_type) {
1201                 ret = smu_v11_0_set_thermal_range(smu, &range);
1202                 if (ret)
1203                         return ret;
1204
1205                 ret = smu_v11_0_enable_thermal_alert(smu);
1206                 if (ret)
1207                         return ret;
1208                 ret = smu_set_thermal_fan_table(smu);
1209                 if (ret)
1210                         return ret;
1211         }
1212
1213         adev->pm.dpm.thermal.min_temp = range.min;
1214         adev->pm.dpm.thermal.max_temp = range.max;
1215         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1216         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1217         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1218         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1219         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1220         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1221         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1222
1223         return ret;
1224 }
1225
1226 static int smu_v11_0_thermal_get_temperature(struct smu_context *smu,
1227                                              enum amd_pp_sensors sensor,
1228                                              uint32_t *value)
1229 {
1230         struct amdgpu_device *adev = smu->adev;
1231         SmuMetrics_t metrics;
1232         uint32_t temp = 0;
1233         int ret = 0;
1234
1235         if (!value)
1236                 return -EINVAL;
1237
1238         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1239         if (ret)
1240                 return ret;
1241
1242         switch (sensor) {
1243         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1244                 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
1245                 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
1246                                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
1247
1248                 temp = temp & 0x1ff;
1249                 temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
1250
1251                 *value = temp;
1252                 break;
1253         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1254                 *value = metrics.TemperatureEdge *
1255                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1256                 break;
1257         case AMDGPU_PP_SENSOR_MEM_TEMP:
1258                 *value = metrics.TemperatureHBM *
1259                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1260                 break;
1261         default:
1262                 pr_err("Invalid sensor for retrieving temp\n");
1263                 return -EINVAL;
1264         }
1265
1266         return 0;
1267 }
1268 static uint16_t convert_to_vddc(uint8_t vid)
1269 {
1270         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1271 }
1272
1273 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1274 {
1275         struct amdgpu_device *adev = smu->adev;
1276         uint32_t vdd = 0, val_vid = 0;
1277
1278         if (!value)
1279                 return -EINVAL;
1280         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1281                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1282                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1283
1284         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1285
1286         *value = vdd;
1287
1288         return 0;
1289
1290 }
1291
1292 static int smu_v11_0_read_sensor(struct smu_context *smu,
1293                                  enum amd_pp_sensors sensor,
1294                                  void *data, uint32_t *size)
1295 {
1296         int ret = 0;
1297         switch (sensor) {
1298         case AMDGPU_PP_SENSOR_GFX_MCLK:
1299                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1300                 *size = 4;
1301                 break;
1302         case AMDGPU_PP_SENSOR_GFX_SCLK:
1303                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1304                 *size = 4;
1305                 break;
1306         case AMDGPU_PP_SENSOR_VDDGFX:
1307                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1308                 *size = 4;
1309                 break;
1310         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1311                 *(uint32_t *)data = 0;
1312                 *size = 4;
1313                 break;
1314         default:
1315                 ret = smu_common_read_sensor(smu, sensor, data, size);
1316                 break;
1317         }
1318
1319         /* try get sensor data by asic */
1320         if (ret)
1321                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1322
1323         if (ret)
1324                 *size = 0;
1325
1326         return ret;
1327 }
1328
1329 static int
1330 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1331                                         struct pp_display_clock_request
1332                                         *clock_req)
1333 {
1334         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1335         int ret = 0;
1336         enum smu_clk_type clk_select = 0;
1337         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1338
1339         if (!smu->pm_enabled)
1340                 return -EINVAL;
1341         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1342                 switch (clk_type) {
1343                 case amd_pp_dcef_clock:
1344                         clk_select = SMU_DCEFCLK;
1345                         break;
1346                 case amd_pp_disp_clock:
1347                         clk_select = SMU_DISPCLK;
1348                         break;
1349                 case amd_pp_pixel_clock:
1350                         clk_select = SMU_PIXCLK;
1351                         break;
1352                 case amd_pp_phy_clock:
1353                         clk_select = SMU_PHYCLK;
1354                         break;
1355                 default:
1356                         pr_info("[%s] Invalid Clock Type!", __func__);
1357                         ret = -EINVAL;
1358                         break;
1359                 }
1360
1361                 if (ret)
1362                         goto failed;
1363
1364                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1365                         (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1366         }
1367
1368 failed:
1369         return ret;
1370 }
1371
1372 static int
1373 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1374                                           dm_pp_wm_sets_with_clock_ranges_soc15
1375                                           *clock_ranges)
1376 {
1377         int ret = 0;
1378         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1379         void *table = watermarks->cpu_addr;
1380
1381         if (!smu->disable_watermark &&
1382             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1383             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1384                 smu_set_watermarks_table(smu, table, clock_ranges);
1385                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1386                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1387         }
1388
1389         return ret;
1390 }
1391
1392 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1393 {
1394         int ret = 0;
1395         struct amdgpu_device *adev = smu->adev;
1396
1397         switch (adev->asic_type) {
1398         case CHIP_VEGA20:
1399                 break;
1400         case CHIP_NAVI10:
1401                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1402                         return 0;
1403                 mutex_lock(&smu->mutex);
1404                 if (enable)
1405                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1406                 else
1407                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1408                 mutex_unlock(&smu->mutex);
1409                 break;
1410         default:
1411                 break;
1412         }
1413
1414         return ret;
1415 }
1416
1417
1418 static int smu_v11_0_get_clock_ranges(struct smu_context *smu,
1419                                       uint32_t *clock,
1420                                       enum smu_clk_type clock_select,
1421                                       bool max)
1422 {
1423         int ret;
1424         *clock = 0;
1425         if (max) {
1426                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
1427                                 smu_clk_get_index(smu, clock_select) << 16);
1428                 if (ret) {
1429                         pr_err("[GetClockRanges] Failed to get max clock from SMC!\n");
1430                         return ret;
1431                 }
1432                 smu_read_smc_arg(smu, clock);
1433         } else {
1434                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq,
1435                                 smu_clk_get_index(smu, clock_select) << 16);
1436                 if (ret) {
1437                         pr_err("[GetClockRanges] Failed to get min clock from SMC!\n");
1438                         return ret;
1439                 }
1440                 smu_read_smc_arg(smu, clock);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static uint32_t smu_v11_0_dpm_get_sclk(struct smu_context *smu, bool low)
1447 {
1448         uint32_t gfx_clk;
1449         int ret;
1450
1451         if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1452                 pr_err("[GetSclks]: gfxclk dpm not enabled!\n");
1453                 return -EPERM;
1454         }
1455
1456         if (low) {
1457                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, false);
1458                 if (ret) {
1459                         pr_err("[GetSclks]: fail to get min SMU_GFXCLK\n");
1460                         return ret;
1461                 }
1462         } else {
1463                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, true);
1464                 if (ret) {
1465                         pr_err("[GetSclks]: fail to get max SMU_GFXCLK\n");
1466                         return ret;
1467                 }
1468         }
1469
1470         return (gfx_clk * 100);
1471 }
1472
1473 static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low)
1474 {
1475         uint32_t mem_clk;
1476         int ret;
1477
1478         if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1479                 pr_err("[GetMclks]: memclk dpm not enabled!\n");
1480                 return -EPERM;
1481         }
1482
1483         if (low) {
1484                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_UCLK, false);
1485                 if (ret) {
1486                         pr_err("[GetMclks]: fail to get min SMU_UCLK\n");
1487                         return ret;
1488                 }
1489         } else {
1490                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_GFXCLK, true);
1491                 if (ret) {
1492                         pr_err("[GetMclks]: fail to get max SMU_UCLK\n");
1493                         return ret;
1494                 }
1495         }
1496
1497         return (mem_clk * 100);
1498 }
1499
1500 static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
1501                                               bool initialize)
1502 {
1503         struct smu_table_context *table_context = &smu->smu_table;
1504         struct smu_table *table = &table_context->tables[SMU_TABLE_OVERDRIVE];
1505         int ret;
1506
1507         /**
1508          * TODO: Enable overdrive for navi10, that replies on smc/pptable
1509          * support.
1510          */
1511         if (smu->adev->asic_type == CHIP_NAVI10)
1512                 return 0;
1513
1514         if (initialize) {
1515                 if (table_context->overdrive_table)
1516                         return -EINVAL;
1517
1518                 table_context->overdrive_table = kzalloc(table->size, GFP_KERNEL);
1519
1520                 if (!table_context->overdrive_table)
1521                         return -ENOMEM;
1522
1523                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1524                                        table_context->overdrive_table, false);
1525                 if (ret) {
1526                         pr_err("Failed to export over drive table!\n");
1527                         return ret;
1528                 }
1529
1530                 smu_set_default_od8_settings(smu);
1531         }
1532
1533         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1534                                table_context->overdrive_table, true);
1535         if (ret) {
1536                 pr_err("Failed to import over drive table!\n");
1537                 return ret;
1538         }
1539
1540         return 0;
1541 }
1542
1543 static int smu_v11_0_update_od8_settings(struct smu_context *smu,
1544                                         uint32_t index,
1545                                         uint32_t value)
1546 {
1547         struct smu_table_context *table_context = &smu->smu_table;
1548         int ret;
1549
1550         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1551                                table_context->overdrive_table, false);
1552         if (ret) {
1553                 pr_err("Failed to export over drive table!\n");
1554                 return ret;
1555         }
1556
1557         smu_update_specified_od8_value(smu, index, value);
1558
1559         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1560                                table_context->overdrive_table, true);
1561         if (ret) {
1562                 pr_err("Failed to import over drive table!\n");
1563                 return ret;
1564         }
1565
1566         return 0;
1567 }
1568
1569 static int smu_v11_0_get_current_rpm(struct smu_context *smu,
1570                                      uint32_t *current_rpm)
1571 {
1572         int ret;
1573
1574         ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
1575
1576         if (ret) {
1577                 pr_err("Attempt to get current RPM from SMC Failed!\n");
1578                 return ret;
1579         }
1580
1581         smu_read_smc_arg(smu, current_rpm);
1582
1583         return 0;
1584 }
1585
1586 static uint32_t
1587 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1588 {
1589         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1590                 return AMD_FAN_CTRL_MANUAL;
1591         else
1592                 return AMD_FAN_CTRL_AUTO;
1593 }
1594
1595 static int
1596 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1597 {
1598         int ret = 0;
1599
1600         if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1601                 return 0;
1602
1603         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1604         if (ret)
1605                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1606                        __func__, (start ? "Start" : "Stop"));
1607
1608         return ret;
1609 }
1610
1611 static int
1612 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1613 {
1614         struct amdgpu_device *adev = smu->adev;
1615
1616         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1617                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1618                                    CG_FDO_CTRL2, TMIN, 0));
1619         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1620                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1621                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1622
1623         return 0;
1624 }
1625
1626 static int
1627 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1628 {
1629         struct amdgpu_device *adev = smu->adev;
1630         uint32_t duty100;
1631         uint32_t duty;
1632         uint64_t tmp64;
1633         bool stop = 0;
1634
1635         if (speed > 100)
1636                 speed = 100;
1637
1638         if (smu_v11_0_smc_fan_control(smu, stop))
1639                 return -EINVAL;
1640         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1641                                 CG_FDO_CTRL1, FMAX_DUTY100);
1642         if (!duty100)
1643                 return -EINVAL;
1644
1645         tmp64 = (uint64_t)speed * duty100;
1646         do_div(tmp64, 100);
1647         duty = (uint32_t)tmp64;
1648
1649         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1650                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1651                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1652
1653         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1654 }
1655
1656 static int
1657 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1658                                uint32_t mode)
1659 {
1660         int ret = 0;
1661         bool start = 1;
1662         bool stop  = 0;
1663
1664         switch (mode) {
1665         case AMD_FAN_CTRL_NONE:
1666                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1667                 break;
1668         case AMD_FAN_CTRL_MANUAL:
1669                 ret = smu_v11_0_smc_fan_control(smu, stop);
1670                 break;
1671         case AMD_FAN_CTRL_AUTO:
1672                 ret = smu_v11_0_smc_fan_control(smu, start);
1673                 break;
1674         default:
1675                 break;
1676         }
1677
1678         if (ret) {
1679                 pr_err("[%s]Set fan control mode failed!", __func__);
1680                 return -EINVAL;
1681         }
1682
1683         return ret;
1684 }
1685
1686 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1687                                        uint32_t speed)
1688 {
1689         struct amdgpu_device *adev = smu->adev;
1690         int ret;
1691         uint32_t tach_period, crystal_clock_freq;
1692         bool stop = 0;
1693
1694         if (!speed)
1695                 return -EINVAL;
1696
1697         mutex_lock(&(smu->mutex));
1698         ret = smu_v11_0_smc_fan_control(smu, stop);
1699         if (ret)
1700                 goto set_fan_speed_rpm_failed;
1701
1702         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1703         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1704         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1705                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1706                                    CG_TACH_CTRL, TARGET_PERIOD,
1707                                    tach_period));
1708
1709         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1710
1711 set_fan_speed_rpm_failed:
1712         mutex_unlock(&(smu->mutex));
1713         return ret;
1714 }
1715
1716 #define XGMI_STATE_D0 1
1717 #define XGMI_STATE_D3 0
1718
1719 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1720                                      uint32_t pstate)
1721 {
1722         int ret = 0;
1723         mutex_lock(&(smu->mutex));
1724         ret = smu_send_smc_msg_with_param(smu,
1725                                           SMU_MSG_SetXgmiMode,
1726                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1727         mutex_unlock(&(smu->mutex));
1728         return ret;
1729 }
1730
1731 static const struct smu_funcs smu_v11_0_funcs = {
1732         .init_microcode = smu_v11_0_init_microcode,
1733         .load_microcode = smu_v11_0_load_microcode,
1734         .check_fw_status = smu_v11_0_check_fw_status,
1735         .check_fw_version = smu_v11_0_check_fw_version,
1736         .send_smc_msg = smu_v11_0_send_msg,
1737         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1738         .read_smc_arg = smu_v11_0_read_arg,
1739         .setup_pptable = smu_v11_0_setup_pptable,
1740         .init_smc_tables = smu_v11_0_init_smc_tables,
1741         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1742         .init_power = smu_v11_0_init_power,
1743         .fini_power = smu_v11_0_fini_power,
1744         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1745         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1746         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1747         .check_pptable = smu_v11_0_check_pptable,
1748         .parse_pptable = smu_v11_0_parse_pptable,
1749         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1750         .write_pptable = smu_v11_0_write_pptable,
1751         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1752         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1753         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1754         .init_display = smu_v11_0_init_display,
1755         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1756         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1757         .system_features_control = smu_v11_0_system_features_control,
1758         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1759         .notify_display_change = smu_v11_0_notify_display_change,
1760         .get_power_limit = smu_v11_0_get_power_limit,
1761         .set_power_limit = smu_v11_0_set_power_limit,
1762         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1763         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1764         .start_thermal_control = smu_v11_0_start_thermal_control,
1765         .read_sensor = smu_v11_0_read_sensor,
1766         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1767         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1768         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1769         .get_sclk = smu_v11_0_dpm_get_sclk,
1770         .get_mclk = smu_v11_0_dpm_get_mclk,
1771         .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
1772         .update_od8_settings = smu_v11_0_update_od8_settings,
1773         .get_current_rpm = smu_v11_0_get_current_rpm,
1774         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1775         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1776         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1777         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1778         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1779         .gfx_off_control = smu_v11_0_gfx_off_control,
1780 };
1781
1782 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1783 {
1784         struct amdgpu_device *adev = smu->adev;
1785
1786         smu->funcs = &smu_v11_0_funcs;
1787         switch (adev->asic_type) {
1788         case CHIP_VEGA20:
1789                 vega20_set_ppt_funcs(smu);
1790                 break;
1791         case CHIP_NAVI10:
1792                 navi10_set_ppt_funcs(smu);
1793                 break;
1794         default:
1795                 pr_warn("Unknown asic for smu11\n");
1796         }
1797 }