2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
27 #define SMU_11_0_PARTIAL_PPTABLE
31 #include "amdgpu_smu.h"
32 #include "smu_internal.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "smu_v11_0.h"
36 #include "smu_v11_0_pptable.h"
37 #include "soc15_common.h"
41 #include "asic_reg/thm/thm_11_0_2_offset.h"
42 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
43 #include "asic_reg/mp/mp_11_0_offset.h"
44 #include "asic_reg/mp/mp_11_0_sh_mask.h"
45 #include "asic_reg/nbio/nbio_7_4_offset.h"
46 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
47 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
48 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
50 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
51 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
52 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
53 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
54 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
56 #define SMU11_VOLTAGE_SCALE 4
58 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
61 struct amdgpu_device *adev = smu->adev;
62 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
66 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
68 struct amdgpu_device *adev = smu->adev;
70 *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
74 static int smu_v11_0_wait_for_response(struct smu_context *smu)
76 struct amdgpu_device *adev = smu->adev;
77 uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
79 for (i = 0; i < timeout; i++) {
80 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
81 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
86 /* timeout means wrong logic */
90 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
94 smu_v11_0_send_msg_with_param(struct smu_context *smu,
95 enum smu_message_type msg,
98 struct amdgpu_device *adev = smu->adev;
99 int ret = 0, index = 0;
101 index = smu_msg_get_index(smu, msg);
105 ret = smu_v11_0_wait_for_response(smu);
107 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
108 smu_get_message_name(smu, msg), index, param, ret);
110 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
112 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
114 smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
116 ret = smu_v11_0_wait_for_response(smu);
118 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
119 smu_get_message_name(smu, msg), index, param, ret);
124 int smu_v11_0_init_microcode(struct smu_context *smu)
126 struct amdgpu_device *adev = smu->adev;
127 const char *chip_name;
130 const struct smc_firmware_header_v1_0 *hdr;
131 const struct common_firmware_header *header;
132 struct amdgpu_firmware_info *ucode = NULL;
134 switch (adev->asic_type) {
136 chip_name = "vega20";
139 chip_name = "arcturus";
142 chip_name = "navi10";
145 chip_name = "navi14";
148 chip_name = "navi12";
154 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
156 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
159 err = amdgpu_ucode_validate(adev->pm.fw);
163 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
164 amdgpu_ucode_print_smc_hdr(&hdr->header);
165 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
167 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
168 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
169 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
170 ucode->fw = adev->pm.fw;
171 header = (const struct common_firmware_header *)ucode->fw->data;
172 adev->firmware.fw_size +=
173 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
178 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
180 release_firmware(adev->pm.fw);
186 int smu_v11_0_load_microcode(struct smu_context *smu)
188 struct amdgpu_device *adev = smu->adev;
190 const struct smc_firmware_header_v1_0 *hdr;
191 uint32_t addr_start = MP1_SRAM;
193 uint32_t mp1_fw_flags;
195 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
196 src = (const uint32_t *)(adev->pm.fw->data +
197 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
199 for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
200 WREG32_PCIE(addr_start, src[i]);
204 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
205 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
206 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
207 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
209 for (i = 0; i < adev->usec_timeout; i++) {
210 mp1_fw_flags = RREG32_PCIE(MP1_Public |
211 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
212 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
213 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
218 if (i == adev->usec_timeout)
224 int smu_v11_0_check_fw_status(struct smu_context *smu)
226 struct amdgpu_device *adev = smu->adev;
227 uint32_t mp1_fw_flags;
229 mp1_fw_flags = RREG32_PCIE(MP1_Public |
230 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
232 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
233 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
239 int smu_v11_0_check_fw_version(struct smu_context *smu)
241 uint32_t if_version = 0xff, smu_version = 0xff;
243 uint8_t smu_minor, smu_debug;
246 ret = smu_get_smc_version(smu, &if_version, &smu_version);
250 smu_major = (smu_version >> 16) & 0xffff;
251 smu_minor = (smu_version >> 8) & 0xff;
252 smu_debug = (smu_version >> 0) & 0xff;
254 switch (smu->adev->asic_type) {
256 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
259 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
262 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
265 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
268 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
269 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
274 * 1. if_version mismatch is not critical as our fw is designed
275 * to be backward compatible.
276 * 2. New fw usually brings some optimizations. But that's visible
277 * only on the paired driver.
278 * Considering above, we just leave user a warning message instead
279 * of halt driver loading.
281 if (if_version != smu->smc_if_version) {
282 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
283 "smu fw version = 0x%08x (%d.%d.%d)\n",
284 smu->smc_if_version, if_version,
285 smu_version, smu_major, smu_minor, smu_debug);
286 pr_warn("SMU driver if version not matched\n");
292 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
294 struct amdgpu_device *adev = smu->adev;
295 uint32_t ppt_offset_bytes;
296 const struct smc_firmware_header_v2_0 *v2;
298 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
300 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
301 *size = le32_to_cpu(v2->ppt_size_bytes);
302 *table = (uint8_t *)v2 + ppt_offset_bytes;
307 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
308 uint32_t *size, uint32_t pptable_id)
310 struct amdgpu_device *adev = smu->adev;
311 const struct smc_firmware_header_v2_1 *v2_1;
312 struct smc_soft_pptable_entry *entries;
313 uint32_t pptable_count = 0;
316 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
317 entries = (struct smc_soft_pptable_entry *)
318 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
319 pptable_count = le32_to_cpu(v2_1->pptable_count);
320 for (i = 0; i < pptable_count; i++) {
321 if (le32_to_cpu(entries[i].id) == pptable_id) {
322 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
323 *size = le32_to_cpu(entries[i].ppt_size_bytes);
328 if (i == pptable_count)
334 int smu_v11_0_setup_pptable(struct smu_context *smu)
336 struct amdgpu_device *adev = smu->adev;
337 const struct smc_firmware_header_v1_0 *hdr;
340 uint16_t atom_table_size;
343 uint16_t version_major, version_minor;
345 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
346 version_major = le16_to_cpu(hdr->header.header_version_major);
347 version_minor = le16_to_cpu(hdr->header.header_version_minor);
348 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
349 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
350 switch (version_minor) {
352 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
355 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
356 smu->smu_table.boot_values.pp_table_id);
366 pr_info("use vbios provided pptable\n");
367 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
370 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
374 size = atom_table_size;
377 if (!smu->smu_table.power_play_table)
378 smu->smu_table.power_play_table = table;
379 if (!smu->smu_table.power_play_table_size)
380 smu->smu_table.power_play_table_size = size;
385 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
387 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
389 if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
392 return smu_alloc_dpm_context(smu);
395 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
397 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
399 if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
402 kfree(smu_dpm->dpm_context);
403 kfree(smu_dpm->golden_dpm_context);
404 kfree(smu_dpm->dpm_current_power_state);
405 kfree(smu_dpm->dpm_request_power_state);
406 smu_dpm->dpm_context = NULL;
407 smu_dpm->golden_dpm_context = NULL;
408 smu_dpm->dpm_context_size = 0;
409 smu_dpm->dpm_current_power_state = NULL;
410 smu_dpm->dpm_request_power_state = NULL;
415 int smu_v11_0_init_smc_tables(struct smu_context *smu)
417 struct smu_table_context *smu_table = &smu->smu_table;
418 struct smu_table *tables = NULL;
421 if (smu_table->tables)
424 tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
429 smu_table->tables = tables;
431 ret = smu_tables_init(smu, tables);
435 ret = smu_v11_0_init_dpm_context(smu);
442 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
444 struct smu_table_context *smu_table = &smu->smu_table;
447 if (!smu_table->tables)
450 kfree(smu_table->tables);
451 kfree(smu_table->metrics_table);
452 smu_table->tables = NULL;
453 smu_table->metrics_table = NULL;
454 smu_table->metrics_time = 0;
456 ret = smu_v11_0_fini_dpm_context(smu);
462 int smu_v11_0_init_power(struct smu_context *smu)
464 struct smu_power_context *smu_power = &smu->smu_power;
466 if (!smu->pm_enabled)
468 if (smu_power->power_context || smu_power->power_context_size != 0)
471 smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
473 if (!smu_power->power_context)
475 smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
480 int smu_v11_0_fini_power(struct smu_context *smu)
482 struct smu_power_context *smu_power = &smu->smu_power;
484 if (!smu->pm_enabled)
486 if (!smu_power->power_context || smu_power->power_context_size == 0)
489 kfree(smu_power->power_context);
490 smu_power->power_context = NULL;
491 smu_power->power_context_size = 0;
496 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
501 struct atom_common_table_header *header;
502 struct atom_firmware_info_v3_3 *v_3_3;
503 struct atom_firmware_info_v3_1 *v_3_1;
505 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
508 ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
509 (uint8_t **)&header);
513 if (header->format_revision != 3) {
514 pr_err("unknown atom_firmware_info version! for smu11\n");
518 switch (header->content_revision) {
522 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
523 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
524 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
525 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
526 smu->smu_table.boot_values.socclk = 0;
527 smu->smu_table.boot_values.dcefclk = 0;
528 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
529 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
530 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
531 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
532 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
533 smu->smu_table.boot_values.pp_table_id = 0;
537 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
538 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
539 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
540 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
541 smu->smu_table.boot_values.socclk = 0;
542 smu->smu_table.boot_values.dcefclk = 0;
543 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
544 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
545 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
546 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
547 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
548 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
551 smu->smu_table.boot_values.format_revision = header->format_revision;
552 smu->smu_table.boot_values.content_revision = header->content_revision;
557 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
560 struct amdgpu_device *adev = smu->adev;
561 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
562 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
564 input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
565 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
566 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
569 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
574 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
575 smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
577 memset(&input, 0, sizeof(input));
578 input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
579 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
580 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
583 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
588 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
589 smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
591 memset(&input, 0, sizeof(input));
592 input.clk_id = SMU11_SYSPLL0_ECLK_ID;
593 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
594 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
597 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
602 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
603 smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
605 memset(&input, 0, sizeof(input));
606 input.clk_id = SMU11_SYSPLL0_VCLK_ID;
607 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
608 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
611 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
616 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
617 smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
619 memset(&input, 0, sizeof(input));
620 input.clk_id = SMU11_SYSPLL0_DCLK_ID;
621 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
622 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
625 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
630 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
631 smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
633 if ((smu->smu_table.boot_values.format_revision == 3) &&
634 (smu->smu_table.boot_values.content_revision >= 2)) {
635 memset(&input, 0, sizeof(input));
636 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
637 input.syspll_id = SMU11_SYSPLL1_2_ID;
638 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
639 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
642 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
647 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
648 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
654 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
656 struct smu_table_context *smu_table = &smu->smu_table;
657 struct smu_table *memory_pool = &smu_table->memory_pool;
660 uint32_t address_low, address_high;
662 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
665 address = (uintptr_t)memory_pool->cpu_addr;
666 address_high = (uint32_t)upper_32_bits(address);
667 address_low = (uint32_t)lower_32_bits(address);
669 ret = smu_send_smc_msg_with_param(smu,
670 SMU_MSG_SetSystemVirtualDramAddrHigh,
674 ret = smu_send_smc_msg_with_param(smu,
675 SMU_MSG_SetSystemVirtualDramAddrLow,
680 address = memory_pool->mc_address;
681 address_high = (uint32_t)upper_32_bits(address);
682 address_low = (uint32_t)lower_32_bits(address);
684 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
688 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
692 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
693 (uint32_t)memory_pool->size);
700 int smu_v11_0_check_pptable(struct smu_context *smu)
704 ret = smu_check_powerplay_table(smu);
708 int smu_v11_0_parse_pptable(struct smu_context *smu)
712 struct smu_table_context *table_context = &smu->smu_table;
713 struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
715 if (table_context->driver_pptable)
718 table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
720 if (!table_context->driver_pptable)
723 ret = smu_store_powerplay_table(smu);
727 ret = smu_append_powerplay_table(smu);
732 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
736 ret = smu_set_default_dpm_table(smu);
741 int smu_v11_0_write_pptable(struct smu_context *smu)
743 struct smu_table_context *table_context = &smu->smu_table;
746 ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
747 table_context->driver_pptable, true);
752 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
756 ret = smu_send_smc_msg_with_param(smu,
757 SMU_MSG_SetMinDeepSleepDcefclk, clk);
759 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
764 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
766 struct smu_table_context *table_context = &smu->smu_table;
768 if (!smu->pm_enabled)
773 return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
776 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
779 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
781 if (tool_table->mc_address) {
782 ret = smu_send_smc_msg_with_param(smu,
783 SMU_MSG_SetToolsDramAddrHigh,
784 upper_32_bits(tool_table->mc_address));
786 ret = smu_send_smc_msg_with_param(smu,
787 SMU_MSG_SetToolsDramAddrLow,
788 lower_32_bits(tool_table->mc_address));
794 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
798 if (!smu->pm_enabled)
801 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
806 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
808 struct smu_feature *feature = &smu->smu_feature;
810 uint32_t feature_mask[2];
812 mutex_lock(&feature->mutex);
813 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
816 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
818 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
823 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
829 mutex_unlock(&feature->mutex);
833 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
834 uint32_t *feature_mask, uint32_t num)
836 uint32_t feature_mask_high = 0, feature_mask_low = 0;
839 if (!feature_mask || num < 2)
842 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
845 ret = smu_read_smc_arg(smu, &feature_mask_high);
849 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
852 ret = smu_read_smc_arg(smu, &feature_mask_low);
856 feature_mask[0] = feature_mask_low;
857 feature_mask[1] = feature_mask_high;
862 int smu_v11_0_system_features_control(struct smu_context *smu,
865 struct smu_feature *feature = &smu->smu_feature;
866 uint32_t feature_mask[2];
869 if (smu->pm_enabled) {
870 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
871 SMU_MSG_DisableAllSmuFeatures));
876 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
880 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
881 feature->feature_num);
882 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
883 feature->feature_num);
888 int smu_v11_0_notify_display_change(struct smu_context *smu)
892 if (!smu->pm_enabled)
894 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
895 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
896 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
902 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
903 enum smu_clk_type clock_select)
908 if (!smu->pm_enabled)
911 if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
912 (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
915 clk_id = smu_clk_get_index(smu, clock_select);
919 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
922 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
926 ret = smu_read_smc_arg(smu, clock);
933 /* if DC limit is zero, return AC limit */
934 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
937 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
941 ret = smu_read_smc_arg(smu, clock);
946 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
948 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
951 max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
953 smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
955 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
956 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
957 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
958 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
959 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
960 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
962 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
963 ret = smu_v11_0_get_max_sustainable_clock(smu,
964 &(max_sustainable_clocks->uclock),
967 pr_err("[%s] failed to get max UCLK from SMC!",
973 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
974 ret = smu_v11_0_get_max_sustainable_clock(smu,
975 &(max_sustainable_clocks->soc_clock),
978 pr_err("[%s] failed to get max SOCCLK from SMC!",
984 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
985 ret = smu_v11_0_get_max_sustainable_clock(smu,
986 &(max_sustainable_clocks->dcef_clock),
989 pr_err("[%s] failed to get max DCEFCLK from SMC!",
994 ret = smu_v11_0_get_max_sustainable_clock(smu,
995 &(max_sustainable_clocks->display_clock),
998 pr_err("[%s] failed to get max DISPCLK from SMC!",
1002 ret = smu_v11_0_get_max_sustainable_clock(smu,
1003 &(max_sustainable_clocks->phy_clock),
1006 pr_err("[%s] failed to get max PHYCLK from SMC!",
1010 ret = smu_v11_0_get_max_sustainable_clock(smu,
1011 &(max_sustainable_clocks->pixel_clock),
1014 pr_err("[%s] failed to get max PIXCLK from SMC!",
1020 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1021 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1026 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1027 uint32_t od_limit, max_power_limit;
1028 struct smu_11_0_powerplay_table *powerplay_table = NULL;
1029 struct smu_table_context *table_context = &smu->smu_table;
1030 powerplay_table = table_context->power_play_table;
1032 max_power_limit = smu_get_pptable_power_limit(smu);
1034 if (!max_power_limit) {
1035 // If we couldn't get the table limit, fall back on first-read value
1036 if (!smu->default_power_limit)
1037 smu->default_power_limit = smu->power_limit;
1038 max_power_limit = smu->default_power_limit;
1041 if (smu->od_enabled) {
1042 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1044 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1046 max_power_limit *= (100 + od_limit);
1047 max_power_limit /= 100;
1050 return max_power_limit;
1053 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1056 uint32_t max_power_limit;
1058 max_power_limit = smu_v11_0_get_max_power_limit(smu);
1060 if (n > max_power_limit) {
1061 pr_err("New power limit (%d) is over the max allowed %d\n",
1068 n = smu->default_power_limit;
1070 if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1071 pr_err("Setting new power limit is not supported!\n");
1075 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1077 pr_err("[%s] Set power limit Failed!\n", __func__);
1080 smu->power_limit = n;
1085 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1086 enum smu_clk_type clk_id,
1093 if (clk_id >= SMU_CLK_COUNT || !value)
1096 asic_clk_id = smu_clk_get_index(smu, clk_id);
1097 if (asic_clk_id < 0)
1100 /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1101 if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1102 ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1104 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1105 (asic_clk_id << 16));
1109 ret = smu_read_smc_arg(smu, &freq);
1120 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1121 struct smu_temperature_range range)
1123 struct amdgpu_device *adev = smu->adev;
1124 int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1125 int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1128 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1129 range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1130 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1131 range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1136 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1137 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1138 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1139 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1140 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1141 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1142 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1143 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1145 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1150 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1152 struct amdgpu_device *adev = smu->adev;
1155 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1156 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1157 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1159 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1164 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1167 struct smu_temperature_range range;
1168 struct amdgpu_device *adev = smu->adev;
1170 if (!smu->pm_enabled)
1173 memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1175 ret = smu_get_thermal_temperature_range(smu, &range);
1179 if (smu->smu_table.thermal_controller_type) {
1180 ret = smu_v11_0_set_thermal_range(smu, range);
1184 ret = smu_v11_0_enable_thermal_alert(smu);
1188 ret = smu_set_thermal_fan_table(smu);
1193 adev->pm.dpm.thermal.min_temp = range.min;
1194 adev->pm.dpm.thermal.max_temp = range.max;
1195 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1196 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1197 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1198 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1199 adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1200 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1201 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1206 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1208 struct amdgpu_device *adev = smu->adev;
1210 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1215 static uint16_t convert_to_vddc(uint8_t vid)
1217 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1220 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1222 struct amdgpu_device *adev = smu->adev;
1223 uint32_t vdd = 0, val_vid = 0;
1227 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1228 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1229 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1231 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1239 int smu_v11_0_read_sensor(struct smu_context *smu,
1240 enum amd_pp_sensors sensor,
1241 void *data, uint32_t *size)
1249 case AMDGPU_PP_SENSOR_GFX_MCLK:
1250 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1253 case AMDGPU_PP_SENSOR_GFX_SCLK:
1254 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1257 case AMDGPU_PP_SENSOR_VDDGFX:
1258 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1261 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1262 *(uint32_t *)data = 0;
1266 ret = smu_common_read_sensor(smu, sensor, data, size);
1277 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1278 struct pp_display_clock_request
1281 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1283 enum smu_clk_type clk_select = 0;
1284 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1286 if (!smu->pm_enabled)
1289 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1290 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1292 case amd_pp_dcef_clock:
1293 clk_select = SMU_DCEFCLK;
1295 case amd_pp_disp_clock:
1296 clk_select = SMU_DISPCLK;
1298 case amd_pp_pixel_clock:
1299 clk_select = SMU_PIXCLK;
1301 case amd_pp_phy_clock:
1302 clk_select = SMU_PHYCLK;
1304 case amd_pp_mem_clock:
1305 clk_select = SMU_UCLK;
1308 pr_info("[%s] Invalid Clock Type!", __func__);
1316 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1319 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1321 if(clk_select == SMU_UCLK)
1322 smu->hard_min_uclk_req_from_dal = clk_freq;
1329 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1332 struct amdgpu_device *adev = smu->adev;
1334 switch (adev->asic_type) {
1340 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1343 ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1345 ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1355 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1357 if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1358 return AMD_FAN_CTRL_MANUAL;
1360 return AMD_FAN_CTRL_AUTO;
1364 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1368 if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1371 ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1373 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1374 __func__, (auto_fan_control ? "Start" : "Stop"));
1380 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1382 struct amdgpu_device *adev = smu->adev;
1384 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1385 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1386 CG_FDO_CTRL2, TMIN, 0));
1387 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1388 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1389 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1395 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1397 struct amdgpu_device *adev = smu->adev;
1398 uint32_t duty100, duty;
1404 if (smu_v11_0_auto_fan_control(smu, 0))
1407 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1408 CG_FDO_CTRL1, FMAX_DUTY100);
1412 tmp64 = (uint64_t)speed * duty100;
1414 duty = (uint32_t)tmp64;
1416 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1417 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1418 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1420 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1424 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1430 case AMD_FAN_CTRL_NONE:
1431 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1433 case AMD_FAN_CTRL_MANUAL:
1434 ret = smu_v11_0_auto_fan_control(smu, 0);
1436 case AMD_FAN_CTRL_AUTO:
1437 ret = smu_v11_0_auto_fan_control(smu, 1);
1444 pr_err("[%s]Set fan control mode failed!", __func__);
1451 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1454 struct amdgpu_device *adev = smu->adev;
1456 uint32_t tach_period, crystal_clock_freq;
1461 ret = smu_v11_0_auto_fan_control(smu, 0);
1465 crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1466 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1467 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1468 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1469 CG_TACH_CTRL, TARGET_PERIOD,
1472 ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1477 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1481 ret = smu_send_smc_msg_with_param(smu,
1482 SMU_MSG_SetXgmiMode,
1483 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
1487 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1488 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1490 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1491 struct amdgpu_irq_src *source,
1492 struct amdgpu_iv_entry *entry)
1494 uint32_t client_id = entry->client_id;
1495 uint32_t src_id = entry->src_id;
1497 if (client_id == SOC15_IH_CLIENTID_THM) {
1499 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1500 pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1501 PCI_BUS_NUM(adev->pdev->devfn),
1502 PCI_SLOT(adev->pdev->devfn),
1503 PCI_FUNC(adev->pdev->devfn));
1505 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1506 pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1507 PCI_BUS_NUM(adev->pdev->devfn),
1508 PCI_SLOT(adev->pdev->devfn),
1509 PCI_FUNC(adev->pdev->devfn));
1512 pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1514 PCI_BUS_NUM(adev->pdev->devfn),
1515 PCI_SLOT(adev->pdev->devfn),
1516 PCI_FUNC(adev->pdev->devfn));
1525 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1527 .process = smu_v11_0_irq_process,
1530 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1532 struct amdgpu_device *adev = smu->adev;
1533 struct amdgpu_irq_src *irq_src = smu->irq_source;
1536 /* already register */
1540 irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1543 smu->irq_source = irq_src;
1545 irq_src->funcs = &smu_v11_0_irq_funcs;
1547 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1548 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1553 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1554 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1562 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1563 struct pp_smu_nv_clock_table *max_clocks)
1565 struct smu_table_context *table_context = &smu->smu_table;
1566 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1568 if (!max_clocks || !table_context->max_sustainable_clocks)
1571 sustainable_clocks = table_context->max_sustainable_clocks;
1573 max_clocks->dcfClockInKhz =
1574 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1575 max_clocks->displayClockInKhz =
1576 (unsigned int) sustainable_clocks->display_clock * 1000;
1577 max_clocks->phyClockInKhz =
1578 (unsigned int) sustainable_clocks->phy_clock * 1000;
1579 max_clocks->pixelClockInKhz =
1580 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1581 max_clocks->uClockInKhz =
1582 (unsigned int) sustainable_clocks->uclock * 1000;
1583 max_clocks->socClockInKhz =
1584 (unsigned int) sustainable_clocks->soc_clock * 1000;
1585 max_clocks->dscClockInKhz = 0;
1586 max_clocks->dppClockInKhz = 0;
1587 max_clocks->fabricClockInKhz = 0;
1592 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1596 ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1601 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1603 return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1606 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1608 struct amdgpu_device *adev = smu->adev;
1609 struct smu_baco_context *smu_baco = &smu->smu_baco;
1613 mutex_lock(&smu_baco->mutex);
1614 baco_support = smu_baco->platform_support;
1615 mutex_unlock(&smu_baco->mutex);
1620 if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1623 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1624 if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1630 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1632 struct smu_baco_context *smu_baco = &smu->smu_baco;
1633 enum smu_baco_state baco_state;
1635 mutex_lock(&smu_baco->mutex);
1636 baco_state = smu_baco->state;
1637 mutex_unlock(&smu_baco->mutex);
1642 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1645 struct smu_baco_context *smu_baco = &smu->smu_baco;
1648 if (smu_v11_0_baco_get_state(smu) == state)
1651 mutex_lock(&smu_baco->mutex);
1653 if (state == SMU_BACO_STATE_ENTER)
1654 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
1656 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1660 smu_baco->state = state;
1662 mutex_unlock(&smu_baco->mutex);
1666 int smu_v11_0_baco_reset(struct smu_context *smu)
1670 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1674 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1680 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1687 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1688 uint32_t *min, uint32_t *max)
1690 int ret = 0, clk_id = 0;
1693 clk_id = smu_clk_get_index(smu, clk_type);
1698 param = (clk_id & 0xffff) << 16;
1701 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
1704 ret = smu_read_smc_arg(smu, max);
1710 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
1713 ret = smu_read_smc_arg(smu, min);
1722 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1723 uint32_t min, uint32_t max)
1725 int ret = 0, clk_id = 0;
1728 clk_id = smu_clk_get_index(smu, clk_type);
1733 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1734 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1741 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1742 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1751 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1753 struct amdgpu_device *adev = smu->adev;
1754 uint32_t pcie_gen = 0, pcie_width = 0;
1757 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1759 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1761 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1763 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1766 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1767 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1768 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1770 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1772 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1774 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1776 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1778 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1780 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1783 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1786 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1792 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1794 struct smu_table_context *table_context = &smu->smu_table;
1798 if (table_context->overdrive_table) {
1801 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1802 if (!table_context->overdrive_table) {
1805 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1807 pr_err("Failed to export overdrive table!\n");
1811 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1813 pr_err("Failed to import overdrive table!\n");