drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #define SMU_11_0_PARTIAL_PPTABLE
  28
  29 #include "pp_debug.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_smu.h"
  32 #include "smu_internal.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "smu_v11_0.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amd_pcie.h"
  40 #include "amdgpu_ras.h"
  41
  42 #include "asic_reg/thm/thm_11_0_2_offset.h"
  43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_11_0_offset.h"
  45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  46 #include "asic_reg/nbio/nbio_7_4_offset.h"
  47 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  48 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  49 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  50
  51 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  52 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  53 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  54 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  55 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  56
  57 #define SMU11_VOLTAGE_SCALE 4
  58
  59 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  60                                               uint16_t msg)
  61 {
  62         struct amdgpu_device *adev = smu->adev;
  63         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  64         return 0;
  65 }
  66
  67 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  68 {
  69         struct amdgpu_device *adev = smu->adev;
  70
  71         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  72         return 0;
  73 }
  74
  75 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  76 {
  77         struct amdgpu_device *adev = smu->adev;
  78         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  79
  80         for (i = 0; i < timeout; i++) {
  81                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  82                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  83                         return cur_value == 0x1 ? 0 : -EIO;
  84
  85                 udelay(1);
  86         }
  87
  88         /* timeout means wrong logic */
  89         return -ETIME;
  90 }
  91
  92 int
  93 smu_v11_0_send_msg_with_param(struct smu_context *smu,
  94                               enum smu_message_type msg,
  95                               uint32_t param)
  96 {
  97         struct amdgpu_device *adev = smu->adev;
  98         int ret = 0, index = 0;
  99
 100         index = smu_msg_get_index(smu, msg);
 101         if (index < 0)
 102                 return index;
 103
 104         ret = smu_v11_0_wait_for_response(smu);
 105         if (ret) {
 106                 pr_err("Msg issuing pre-check failed and "
 107                        "SMU may be not in the right state!\n");
 108                 return ret;
 109         }
 110
 111         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 112
 113         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 114
 115         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 116
 117         ret = smu_v11_0_wait_for_response(smu);
 118         if (ret)
 119                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 120                        smu_get_message_name(smu, msg), index, param, ret);
 121
 122         return ret;
 123 }
 124
 125 int smu_v11_0_init_microcode(struct smu_context *smu)
 126 {
 127         struct amdgpu_device *adev = smu->adev;
 128         const char *chip_name;
 129         char fw_name[30];
 130         int err = 0;
 131         const struct smc_firmware_header_v1_0 *hdr;
 132         const struct common_firmware_header *header;
 133         struct amdgpu_firmware_info *ucode = NULL;
 134
 135         switch (adev->asic_type) {
 136         case CHIP_VEGA20:
 137                 chip_name = "vega20";
 138                 break;
 139         case CHIP_ARCTURUS:
 140                 chip_name = "arcturus";
 141                 break;
 142         case CHIP_NAVI10:
 143                 chip_name = "navi10";
 144                 break;
 145         case CHIP_NAVI14:
 146                 chip_name = "navi14";
 147                 break;
 148         case CHIP_NAVI12:
 149                 chip_name = "navi12";
 150                 break;
 151         default:
 152                 BUG();
 153         }
 154
 155         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 156
 157         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 158         if (err)
 159                 goto out;
 160         err = amdgpu_ucode_validate(adev->pm.fw);
 161         if (err)
 162                 goto out;
 163
 164         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 165         amdgpu_ucode_print_smc_hdr(&hdr->header);
 166         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 167
 168         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 169                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 170                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 171                 ucode->fw = adev->pm.fw;
 172                 header = (const struct common_firmware_header *)ucode->fw->data;
 173                 adev->firmware.fw_size +=
 174                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 175         }
 176
 177 out:
 178         if (err) {
 179                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 180                           fw_name);
 181                 release_firmware(adev->pm.fw);
 182                 adev->pm.fw = NULL;
 183         }
 184         return err;
 185 }
 186
 187 int smu_v11_0_load_microcode(struct smu_context *smu)
 188 {
 189         struct amdgpu_device *adev = smu->adev;
 190         const uint32_t *src;
 191         const struct smc_firmware_header_v1_0 *hdr;
 192         uint32_t addr_start = MP1_SRAM;
 193         uint32_t i;
 194         uint32_t mp1_fw_flags;
 195
 196         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 197         src = (const uint32_t *)(adev->pm.fw->data +
 198                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 199
 200         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 201                 WREG32_PCIE(addr_start, src[i]);
 202                 addr_start += 4;
 203         }
 204
 205         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 206                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 207         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 208                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 209
 210         for (i = 0; i < adev->usec_timeout; i++) {
 211                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 212                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 213                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 214                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 215                         break;
 216                 udelay(1);
 217         }
 218
 219         if (i == adev->usec_timeout)
 220                 return -ETIME;
 221
 222         return 0;
 223 }
 224
 225 int smu_v11_0_check_fw_status(struct smu_context *smu)
 226 {
 227         struct amdgpu_device *adev = smu->adev;
 228         uint32_t mp1_fw_flags;
 229
 230         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 231                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 232
 233         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 234             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 235                 return 0;
 236
 237         return -EIO;
 238 }
 239
 240 int smu_v11_0_check_fw_version(struct smu_context *smu)
 241 {
 242         uint32_t if_version = 0xff, smu_version = 0xff;
 243         uint16_t smu_major;
 244         uint8_t smu_minor, smu_debug;
 245         int ret = 0;
 246
 247         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 248         if (ret)
 249                 return ret;
 250
 251         smu_major = (smu_version >> 16) & 0xffff;
 252         smu_minor = (smu_version >> 8) & 0xff;
 253         smu_debug = (smu_version >> 0) & 0xff;
 254
 255         switch (smu->adev->asic_type) {
 256         case CHIP_VEGA20:
 257                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
 258                 break;
 259         case CHIP_ARCTURUS:
 260                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 261                 break;
 262         case CHIP_NAVI10:
 263                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 264                 break;
 265         case CHIP_NAVI14:
 266                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 267                 break;
 268         default:
 269                 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
 270                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
 271                 break;
 272         }
 273
 274         /*
 275          * 1. if_version mismatch is not critical as our fw is designed
 276          * to be backward compatible.
 277          * 2. New fw usually brings some optimizations. But that's visible
 278          * only on the paired driver.
 279          * Considering above, we just leave user a warning message instead
 280          * of halt driver loading.
 281          */
 282         if (if_version != smu->smc_if_version) {
 283                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 284                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 285                         smu->smc_if_version, if_version,
 286                         smu_version, smu_major, smu_minor, smu_debug);
 287                 pr_warn("SMU driver if version not matched\n");
 288         }
 289
 290         return ret;
 291 }
 292
 293 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 294 {
 295         struct amdgpu_device *adev = smu->adev;
 296         uint32_t ppt_offset_bytes;
 297         const struct smc_firmware_header_v2_0 *v2;
 298
 299         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 300
 301         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 302         *size = le32_to_cpu(v2->ppt_size_bytes);
 303         *table = (uint8_t *)v2 + ppt_offset_bytes;
 304
 305         return 0;
 306 }
 307
 308 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 309                                       uint32_t *size, uint32_t pptable_id)
 310 {
 311         struct amdgpu_device *adev = smu->adev;
 312         const struct smc_firmware_header_v2_1 *v2_1;
 313         struct smc_soft_pptable_entry *entries;
 314         uint32_t pptable_count = 0;
 315         int i = 0;
 316
 317         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 318         entries = (struct smc_soft_pptable_entry *)
 319                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 320         pptable_count = le32_to_cpu(v2_1->pptable_count);
 321         for (i = 0; i < pptable_count; i++) {
 322                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 323                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 324                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 325                         break;
 326                 }
 327         }
 328
 329         if (i == pptable_count)
 330                 return -EINVAL;
 331
 332         return 0;
 333 }
 334
 335 int smu_v11_0_setup_pptable(struct smu_context *smu)
 336 {
 337         struct amdgpu_device *adev = smu->adev;
 338         const struct smc_firmware_header_v1_0 *hdr;
 339         int ret, index;
 340         uint32_t size = 0;
 341         uint16_t atom_table_size;
 342         uint8_t frev, crev;
 343         void *table;
 344         uint16_t version_major, version_minor;
 345
 346         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 347         version_major = le16_to_cpu(hdr->header.header_version_major);
 348         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 349         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 350                 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 351                 switch (version_minor) {
 352                 case 0:
 353                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 354                         break;
 355                 case 1:
 356                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 357                                                          smu->smu_table.boot_values.pp_table_id);
 358                         break;
 359                 default:
 360                         ret = -EINVAL;
 361                         break;
 362                 }
 363                 if (ret)
 364                         return ret;
 365
 366         } else {
 367                 pr_info("use vbios provided pptable\n");
 368                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 369                                                     powerplayinfo);
 370
 371                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 372                                               (uint8_t **)&table);
 373                 if (ret)
 374                         return ret;
 375                 size = atom_table_size;
 376         }
 377
 378         if (!smu->smu_table.power_play_table)
 379                 smu->smu_table.power_play_table = table;
 380         if (!smu->smu_table.power_play_table_size)
 381                 smu->smu_table.power_play_table_size = size;
 382
 383         return 0;
 384 }
 385
 386 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 387 {
 388         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 389
 390         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 391                 return -EINVAL;
 392
 393         return smu_alloc_dpm_context(smu);
 394 }
 395
 396 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 397 {
 398         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 399
 400         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 401                 return -EINVAL;
 402
 403         kfree(smu_dpm->dpm_context);
 404         kfree(smu_dpm->golden_dpm_context);
 405         kfree(smu_dpm->dpm_current_power_state);
 406         kfree(smu_dpm->dpm_request_power_state);
 407         smu_dpm->dpm_context = NULL;
 408         smu_dpm->golden_dpm_context = NULL;
 409         smu_dpm->dpm_context_size = 0;
 410         smu_dpm->dpm_current_power_state = NULL;
 411         smu_dpm->dpm_request_power_state = NULL;
 412
 413         return 0;
 414 }
 415
 416 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 417 {
 418         struct smu_table_context *smu_table = &smu->smu_table;
 419         struct smu_table *tables = NULL;
 420         int ret = 0;
 421
 422         if (smu_table->tables)
 423                 return -EINVAL;
 424
 425         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 426                          GFP_KERNEL);
 427         if (!tables)
 428                 return -ENOMEM;
 429
 430         smu_table->tables = tables;
 431
 432         ret = smu_tables_init(smu, tables);
 433         if (ret)
 434                 return ret;
 435
 436         ret = smu_v11_0_init_dpm_context(smu);
 437         if (ret)
 438                 return ret;
 439
 440         return 0;
 441 }
 442
 443 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 444 {
 445         struct smu_table_context *smu_table = &smu->smu_table;
 446         int ret = 0;
 447
 448         if (!smu_table->tables)
 449                 return -EINVAL;
 450
 451         kfree(smu_table->tables);
 452         kfree(smu_table->metrics_table);
 453         smu_table->tables = NULL;
 454         smu_table->metrics_table = NULL;
 455         smu_table->metrics_time = 0;
 456
 457         ret = smu_v11_0_fini_dpm_context(smu);
 458         if (ret)
 459                 return ret;
 460         return 0;
 461 }
 462
 463 int smu_v11_0_init_power(struct smu_context *smu)
 464 {
 465         struct smu_power_context *smu_power = &smu->smu_power;
 466
 467         if (!smu->pm_enabled)
 468                 return 0;
 469         if (smu_power->power_context || smu_power->power_context_size != 0)
 470                 return -EINVAL;
 471
 472         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 473                                            GFP_KERNEL);
 474         if (!smu_power->power_context)
 475                 return -ENOMEM;
 476         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 477
 478         return 0;
 479 }
 480
 481 int smu_v11_0_fini_power(struct smu_context *smu)
 482 {
 483         struct smu_power_context *smu_power = &smu->smu_power;
 484
 485         if (!smu->pm_enabled)
 486                 return 0;
 487         if (!smu_power->power_context || smu_power->power_context_size == 0)
 488                 return -EINVAL;
 489
 490         kfree(smu_power->power_context);
 491         smu_power->power_context = NULL;
 492         smu_power->power_context_size = 0;
 493
 494         return 0;
 495 }
 496
 497 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 498 {
 499         int ret, index;
 500         uint16_t size;
 501         uint8_t frev, crev;
 502         struct atom_common_table_header *header;
 503         struct atom_firmware_info_v3_3 *v_3_3;
 504         struct atom_firmware_info_v3_1 *v_3_1;
 505
 506         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 507                                             firmwareinfo);
 508
 509         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 510                                       (uint8_t **)&header);
 511         if (ret)
 512                 return ret;
 513
 514         if (header->format_revision != 3) {
 515                 pr_err("unknown atom_firmware_info version! for smu11\n");
 516                 return -EINVAL;
 517         }
 518
 519         switch (header->content_revision) {
 520         case 0:
 521         case 1:
 522         case 2:
 523                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 524                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 525                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 526                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 527                 smu->smu_table.boot_values.socclk = 0;
 528                 smu->smu_table.boot_values.dcefclk = 0;
 529                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 530                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 531                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 532                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 533                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 534                 smu->smu_table.boot_values.pp_table_id = 0;
 535                 break;
 536         case 3:
 537         default:
 538                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 539                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 540                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 541                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 542                 smu->smu_table.boot_values.socclk = 0;
 543                 smu->smu_table.boot_values.dcefclk = 0;
 544                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 545                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 546                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 547                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 548                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 549                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 550         }
 551
 552         smu->smu_table.boot_values.format_revision = header->format_revision;
 553         smu->smu_table.boot_values.content_revision = header->content_revision;
 554
 555         return 0;
 556 }
 557
 558 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 559 {
 560         int ret, index;
 561         struct amdgpu_device *adev = smu->adev;
 562         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 563         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 564
 565         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 566         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 567         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 568                                             getsmuclockinfo);
 569
 570         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 571                                         (uint32_t *)&input);
 572         if (ret)
 573                 return -EINVAL;
 574
 575         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 576         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 577
 578         memset(&input, 0, sizeof(input));
 579         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 580         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 581         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 582                                             getsmuclockinfo);
 583
 584         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 585                                         (uint32_t *)&input);
 586         if (ret)
 587                 return -EINVAL;
 588
 589         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 590         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 591
 592         memset(&input, 0, sizeof(input));
 593         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 594         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 595         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 596                                             getsmuclockinfo);
 597
 598         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 599                                         (uint32_t *)&input);
 600         if (ret)
 601                 return -EINVAL;
 602
 603         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 604         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 605
 606         memset(&input, 0, sizeof(input));
 607         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 608         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 609         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 610                                             getsmuclockinfo);
 611
 612         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 613                                         (uint32_t *)&input);
 614         if (ret)
 615                 return -EINVAL;
 616
 617         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 618         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 619
 620         memset(&input, 0, sizeof(input));
 621         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 622         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 623         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 624                                             getsmuclockinfo);
 625
 626         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 627                                         (uint32_t *)&input);
 628         if (ret)
 629                 return -EINVAL;
 630
 631         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 632         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 633
 634         if ((smu->smu_table.boot_values.format_revision == 3) &&
 635             (smu->smu_table.boot_values.content_revision >= 2)) {
 636                 memset(&input, 0, sizeof(input));
 637                 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
 638                 input.syspll_id = SMU11_SYSPLL1_2_ID;
 639                 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 640                 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 641                                                     getsmuclockinfo);
 642
 643                 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 644                                                 (uint32_t *)&input);
 645                 if (ret)
 646                         return -EINVAL;
 647
 648                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 649                 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 650         }
 651
 652         return 0;
 653 }
 654
 655 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 656 {
 657         struct smu_table_context *smu_table = &smu->smu_table;
 658         struct smu_table *memory_pool = &smu_table->memory_pool;
 659         int ret = 0;
 660         uint64_t address;
 661         uint32_t address_low, address_high;
 662
 663         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 664                 return ret;
 665
 666         address = (uintptr_t)memory_pool->cpu_addr;
 667         address_high = (uint32_t)upper_32_bits(address);
 668         address_low  = (uint32_t)lower_32_bits(address);
 669
 670         ret = smu_send_smc_msg_with_param(smu,
 671                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 672                                           address_high);
 673         if (ret)
 674                 return ret;
 675         ret = smu_send_smc_msg_with_param(smu,
 676                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 677                                           address_low);
 678         if (ret)
 679                 return ret;
 680
 681         address = memory_pool->mc_address;
 682         address_high = (uint32_t)upper_32_bits(address);
 683         address_low  = (uint32_t)lower_32_bits(address);
 684
 685         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 686                                           address_high);
 687         if (ret)
 688                 return ret;
 689         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 690                                           address_low);
 691         if (ret)
 692                 return ret;
 693         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 694                                           (uint32_t)memory_pool->size);
 695         if (ret)
 696                 return ret;
 697
 698         return ret;
 699 }
 700
 701 int smu_v11_0_check_pptable(struct smu_context *smu)
 702 {
 703         int ret;
 704
 705         ret = smu_check_powerplay_table(smu);
 706         return ret;
 707 }
 708
 709 int smu_v11_0_parse_pptable(struct smu_context *smu)
 710 {
 711         int ret;
 712
 713         struct smu_table_context *table_context = &smu->smu_table;
 714         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 715
 716         if (table_context->driver_pptable)
 717                 return -EINVAL;
 718
 719         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 720
 721         if (!table_context->driver_pptable)
 722                 return -ENOMEM;
 723
 724         ret = smu_store_powerplay_table(smu);
 725         if (ret)
 726                 return -EINVAL;
 727
 728         ret = smu_append_powerplay_table(smu);
 729
 730         return ret;
 731 }
 732
 733 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 734 {
 735         int ret;
 736
 737         ret = smu_set_default_dpm_table(smu);
 738
 739         return ret;
 740 }
 741
 742 int smu_v11_0_write_pptable(struct smu_context *smu)
 743 {
 744         struct smu_table_context *table_context = &smu->smu_table;
 745         int ret = 0;
 746
 747         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 748                                table_context->driver_pptable, true);
 749
 750         return ret;
 751 }
 752
 753 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 754 {
 755         int ret;
 756
 757         ret = smu_send_smc_msg_with_param(smu,
 758                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 759         if (ret)
 760                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 761
 762         return ret;
 763 }
 764
 765 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 766 {
 767         struct smu_table_context *table_context = &smu->smu_table;
 768
 769         if (!smu->pm_enabled)
 770                 return 0;
 771         if (!table_context)
 772                 return -EINVAL;
 773
 774         return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
 775 }
 776
 777 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 778 {
 779         int ret = 0;
 780         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 781
 782         if (tool_table->mc_address) {
 783                 ret = smu_send_smc_msg_with_param(smu,
 784                                 SMU_MSG_SetToolsDramAddrHigh,
 785                                 upper_32_bits(tool_table->mc_address));
 786                 if (!ret)
 787                         ret = smu_send_smc_msg_with_param(smu,
 788                                 SMU_MSG_SetToolsDramAddrLow,
 789                                 lower_32_bits(tool_table->mc_address));
 790         }
 791
 792         return ret;
 793 }
 794
 795 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 796 {
 797         int ret = 0;
 798
 799         if (!smu->pm_enabled)
 800                 return ret;
 801
 802         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 803         return ret;
 804 }
 805
 806
 807 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 808 {
 809         struct smu_feature *feature = &smu->smu_feature;
 810         int ret = 0;
 811         uint32_t feature_mask[2];
 812
 813         mutex_lock(&feature->mutex);
 814         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 815                 goto failed;
 816
 817         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 818
 819         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 820                                           feature_mask[1]);
 821         if (ret)
 822                 goto failed;
 823
 824         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 825                                           feature_mask[0]);
 826         if (ret)
 827                 goto failed;
 828
 829 failed:
 830         mutex_unlock(&feature->mutex);
 831         return ret;
 832 }
 833
 834 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 835                                       uint32_t *feature_mask, uint32_t num)
 836 {
 837         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 838         int ret = 0;
 839
 840         if (!feature_mask || num < 2)
 841                 return -EINVAL;
 842
 843         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 844         if (ret)
 845                 return ret;
 846         ret = smu_read_smc_arg(smu, &feature_mask_high);
 847         if (ret)
 848                 return ret;
 849
 850         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 851         if (ret)
 852                 return ret;
 853         ret = smu_read_smc_arg(smu, &feature_mask_low);
 854         if (ret)
 855                 return ret;
 856
 857         feature_mask[0] = feature_mask_low;
 858         feature_mask[1] = feature_mask_high;
 859
 860         return ret;
 861 }
 862
 863 int smu_v11_0_system_features_control(struct smu_context *smu,
 864                                              bool en)
 865 {
 866         struct smu_feature *feature = &smu->smu_feature;
 867         uint32_t feature_mask[2];
 868         int ret = 0;
 869
 870         if (smu->pm_enabled) {
 871                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 872                                              SMU_MSG_DisableAllSmuFeatures));
 873                 if (ret)
 874                         return ret;
 875         }
 876
 877         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 878         if (ret)
 879                 return ret;
 880
 881         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 882                     feature->feature_num);
 883         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 884                     feature->feature_num);
 885
 886         return ret;
 887 }
 888
 889 int smu_v11_0_notify_display_change(struct smu_context *smu)
 890 {
 891         int ret = 0;
 892
 893         if (!smu->pm_enabled)
 894                 return ret;
 895         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 896             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 897                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 898
 899         return ret;
 900 }
 901
 902 static int
 903 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 904                                     enum smu_clk_type clock_select)
 905 {
 906         int ret = 0;
 907         int clk_id;
 908
 909         if (!smu->pm_enabled)
 910                 return ret;
 911
 912         if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 913             (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
 914                 return 0;
 915
 916         clk_id = smu_clk_get_index(smu, clock_select);
 917         if (clk_id < 0)
 918                 return -EINVAL;
 919
 920         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 921                                           clk_id << 16);
 922         if (ret) {
 923                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 924                 return ret;
 925         }
 926
 927         ret = smu_read_smc_arg(smu, clock);
 928         if (ret)
 929                 return ret;
 930
 931         if (*clock != 0)
 932                 return 0;
 933
 934         /* if DC limit is zero, return AC limit */
 935         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 936                                           clk_id << 16);
 937         if (ret) {
 938                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 939                 return ret;
 940         }
 941
 942         ret = smu_read_smc_arg(smu, clock);
 943
 944         return ret;
 945 }
 946
 947 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 948 {
 949         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 950         int ret = 0;
 951
 952         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 953                                          GFP_KERNEL);
 954         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 955
 956         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 957         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 958         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 959         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 960         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 961         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 962
 963         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 964                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 965                                                           &(max_sustainable_clocks->uclock),
 966                                                           SMU_UCLK);
 967                 if (ret) {
 968                         pr_err("[%s] failed to get max UCLK from SMC!",
 969                                __func__);
 970                         return ret;
 971                 }
 972         }
 973
 974         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 975                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 976                                                           &(max_sustainable_clocks->soc_clock),
 977                                                           SMU_SOCCLK);
 978                 if (ret) {
 979                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 980                                __func__);
 981                         return ret;
 982                 }
 983         }
 984
 985         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 986                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 987                                                           &(max_sustainable_clocks->dcef_clock),
 988                                                           SMU_DCEFCLK);
 989                 if (ret) {
 990                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
 991                                __func__);
 992                         return ret;
 993                 }
 994
 995                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 996                                                           &(max_sustainable_clocks->display_clock),
 997                                                           SMU_DISPCLK);
 998                 if (ret) {
 999                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1000                                __func__);
1001                         return ret;
1002                 }
1003                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1004                                                           &(max_sustainable_clocks->phy_clock),
1005                                                           SMU_PHYCLK);
1006                 if (ret) {
1007                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1008                                __func__);
1009                         return ret;
1010                 }
1011                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1012                                                           &(max_sustainable_clocks->pixel_clock),
1013                                                           SMU_PIXCLK);
1014                 if (ret) {
1015                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1016                                __func__);
1017                         return ret;
1018                 }
1019         }
1020
1021         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1022                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1023
1024         return 0;
1025 }
1026
1027 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1028         uint32_t od_limit, max_power_limit;
1029         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1030         struct smu_table_context *table_context = &smu->smu_table;
1031         powerplay_table = table_context->power_play_table;
1032
1033         max_power_limit = smu_get_pptable_power_limit(smu);
1034
1035         if (!max_power_limit) {
1036                 // If we couldn't get the table limit, fall back on first-read value
1037                 if (!smu->default_power_limit)
1038                         smu->default_power_limit = smu->power_limit;
1039                 max_power_limit = smu->default_power_limit;
1040         }
1041
1042         if (smu->od_enabled) {
1043                 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1044
1045                 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1046
1047                 max_power_limit *= (100 + od_limit);
1048                 max_power_limit /= 100;
1049         }
1050
1051         return max_power_limit;
1052 }
1053
1054 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1055 {
1056         int ret = 0;
1057         uint32_t max_power_limit;
1058
1059         max_power_limit = smu_v11_0_get_max_power_limit(smu);
1060
1061         if (n > max_power_limit) {
1062                 pr_err("New power limit (%d) is over the max allowed %d\n",
1063                                 n,
1064                                 max_power_limit);
1065                 return -EINVAL;
1066         }
1067
1068         if (n == 0)
1069                 n = smu->default_power_limit;
1070
1071         if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1072                 pr_err("Setting new power limit is not supported!\n");
1073                 return -EOPNOTSUPP;
1074         }
1075
1076         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1077         if (ret) {
1078                 pr_err("[%s] Set power limit Failed!\n", __func__);
1079                 return ret;
1080         }
1081         smu->power_limit = n;
1082
1083         return 0;
1084 }
1085
1086 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1087                                           enum smu_clk_type clk_id,
1088                                           uint32_t *value)
1089 {
1090         int ret = 0;
1091         uint32_t freq = 0;
1092         int asic_clk_id;
1093
1094         if (clk_id >= SMU_CLK_COUNT || !value)
1095                 return -EINVAL;
1096
1097         asic_clk_id = smu_clk_get_index(smu, clk_id);
1098         if (asic_clk_id < 0)
1099                 return -EINVAL;
1100
1101         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1102         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1103                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1104         else {
1105                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1106                                                   (asic_clk_id << 16));
1107                 if (ret)
1108                         return ret;
1109
1110                 ret = smu_read_smc_arg(smu, &freq);
1111                 if (ret)
1112                         return ret;
1113         }
1114
1115         freq *= 100;
1116         *value = freq;
1117
1118         return ret;
1119 }
1120
1121 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1122                                        struct smu_temperature_range range)
1123 {
1124         struct amdgpu_device *adev = smu->adev;
1125         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1126         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1127         uint32_t val;
1128
1129         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1130                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1131         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1132                         range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1133
1134         if (low > high)
1135                 return -EINVAL;
1136
1137         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1138         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1139         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1140         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1141         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1142         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1143         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1144         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1145
1146         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1147
1148         return 0;
1149 }
1150
1151 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1152 {
1153         struct amdgpu_device *adev = smu->adev;
1154         uint32_t val = 0;
1155
1156         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1157         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1158         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1159
1160         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1161
1162         return 0;
1163 }
1164
1165 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1166 {
1167         int ret = 0;
1168         struct smu_temperature_range range;
1169         struct amdgpu_device *adev = smu->adev;
1170
1171         if (!smu->pm_enabled)
1172                 return ret;
1173
1174         memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1175
1176         ret = smu_get_thermal_temperature_range(smu, &range);
1177         if (ret)
1178                 return ret;
1179
1180         if (smu->smu_table.thermal_controller_type) {
1181                 ret = smu_v11_0_set_thermal_range(smu, range);
1182                 if (ret)
1183                         return ret;
1184
1185                 ret = smu_v11_0_enable_thermal_alert(smu);
1186                 if (ret)
1187                         return ret;
1188
1189                 ret = smu_set_thermal_fan_table(smu);
1190                 if (ret)
1191                         return ret;
1192         }
1193
1194         adev->pm.dpm.thermal.min_temp = range.min;
1195         adev->pm.dpm.thermal.max_temp = range.max;
1196         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1197         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1198         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1199         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1200         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1201         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1202         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1203
1204         return ret;
1205 }
1206
1207 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1208 {
1209         struct amdgpu_device *adev = smu->adev;
1210
1211         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1212
1213         return 0;
1214 }
1215
1216 static uint16_t convert_to_vddc(uint8_t vid)
1217 {
1218         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1219 }
1220
1221 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1222 {
1223         struct amdgpu_device *adev = smu->adev;
1224         uint32_t vdd = 0, val_vid = 0;
1225
1226         if (!value)
1227                 return -EINVAL;
1228         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1229                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1230                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1231
1232         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1233
1234         *value = vdd;
1235
1236         return 0;
1237
1238 }
1239
1240 int smu_v11_0_read_sensor(struct smu_context *smu,
1241                                  enum amd_pp_sensors sensor,
1242                                  void *data, uint32_t *size)
1243 {
1244         int ret = 0;
1245
1246         if(!data || !size)
1247                 return -EINVAL;
1248
1249         switch (sensor) {
1250         case AMDGPU_PP_SENSOR_GFX_MCLK:
1251                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1252                 *size = 4;
1253                 break;
1254         case AMDGPU_PP_SENSOR_GFX_SCLK:
1255                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1256                 *size = 4;
1257                 break;
1258         case AMDGPU_PP_SENSOR_VDDGFX:
1259                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1260                 *size = 4;
1261                 break;
1262         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1263                 *(uint32_t *)data = 0;
1264                 *size = 4;
1265                 break;
1266         default:
1267                 ret = smu_common_read_sensor(smu, sensor, data, size);
1268                 break;
1269         }
1270
1271         if (ret)
1272                 *size = 0;
1273
1274         return ret;
1275 }
1276
1277 int
1278 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1279                                         struct pp_display_clock_request
1280                                         *clock_req)
1281 {
1282         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1283         int ret = 0;
1284         enum smu_clk_type clk_select = 0;
1285         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1286
1287         if (!smu->pm_enabled)
1288                 return -EINVAL;
1289
1290         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1291                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1292                 switch (clk_type) {
1293                 case amd_pp_dcef_clock:
1294                         clk_select = SMU_DCEFCLK;
1295                         break;
1296                 case amd_pp_disp_clock:
1297                         clk_select = SMU_DISPCLK;
1298                         break;
1299                 case amd_pp_pixel_clock:
1300                         clk_select = SMU_PIXCLK;
1301                         break;
1302                 case amd_pp_phy_clock:
1303                         clk_select = SMU_PHYCLK;
1304                         break;
1305                 case amd_pp_mem_clock:
1306                         clk_select = SMU_UCLK;
1307                         break;
1308                 default:
1309                         pr_info("[%s] Invalid Clock Type!", __func__);
1310                         ret = -EINVAL;
1311                         break;
1312                 }
1313
1314                 if (ret)
1315                         goto failed;
1316
1317                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1318                         return 0;
1319
1320                 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1321
1322                 if(clk_select == SMU_UCLK)
1323                         smu->hard_min_uclk_req_from_dal = clk_freq;
1324         }
1325
1326 failed:
1327         return ret;
1328 }
1329
1330 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1331 {
1332         int ret = 0;
1333         struct amdgpu_device *adev = smu->adev;
1334
1335         switch (adev->asic_type) {
1336         case CHIP_VEGA20:
1337                 break;
1338         case CHIP_NAVI10:
1339         case CHIP_NAVI14:
1340         case CHIP_NAVI12:
1341                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1342                         return 0;
1343                 if (enable)
1344                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1345                 else
1346                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1347                 break;
1348         default:
1349                 break;
1350         }
1351
1352         return ret;
1353 }
1354
1355 uint32_t
1356 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1357 {
1358         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1359                 return AMD_FAN_CTRL_MANUAL;
1360         else
1361                 return AMD_FAN_CTRL_AUTO;
1362 }
1363
1364 static int
1365 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1366 {
1367         int ret = 0;
1368
1369         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1370                 return 0;
1371
1372         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1373         if (ret)
1374                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1375                        __func__, (auto_fan_control ? "Start" : "Stop"));
1376
1377         return ret;
1378 }
1379
1380 static int
1381 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1382 {
1383         struct amdgpu_device *adev = smu->adev;
1384
1385         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1386                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1387                                    CG_FDO_CTRL2, TMIN, 0));
1388         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1389                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1390                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1391
1392         return 0;
1393 }
1394
1395 int
1396 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1397 {
1398         struct amdgpu_device *adev = smu->adev;
1399         uint32_t duty100, duty;
1400         uint64_t tmp64;
1401
1402         if (speed > 100)
1403                 speed = 100;
1404
1405         if (smu_v11_0_auto_fan_control(smu, 0))
1406                 return -EINVAL;
1407
1408         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1409                                 CG_FDO_CTRL1, FMAX_DUTY100);
1410         if (!duty100)
1411                 return -EINVAL;
1412
1413         tmp64 = (uint64_t)speed * duty100;
1414         do_div(tmp64, 100);
1415         duty = (uint32_t)tmp64;
1416
1417         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1418                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1419                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1420
1421         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1422 }
1423
1424 int
1425 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1426                                uint32_t mode)
1427 {
1428         int ret = 0;
1429
1430         switch (mode) {
1431         case AMD_FAN_CTRL_NONE:
1432                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1433                 break;
1434         case AMD_FAN_CTRL_MANUAL:
1435                 ret = smu_v11_0_auto_fan_control(smu, 0);
1436                 break;
1437         case AMD_FAN_CTRL_AUTO:
1438                 ret = smu_v11_0_auto_fan_control(smu, 1);
1439                 break;
1440         default:
1441                 break;
1442         }
1443
1444         if (ret) {
1445                 pr_err("[%s]Set fan control mode failed!", __func__);
1446                 return -EINVAL;
1447         }
1448
1449         return ret;
1450 }
1451
1452 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1453                                        uint32_t speed)
1454 {
1455         struct amdgpu_device *adev = smu->adev;
1456         int ret;
1457         uint32_t tach_period, crystal_clock_freq;
1458
1459         if (!speed)
1460                 return -EINVAL;
1461
1462         ret = smu_v11_0_auto_fan_control(smu, 0);
1463         if (ret)
1464                 return ret;
1465
1466         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1467         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1468         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1469                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1470                                    CG_TACH_CTRL, TARGET_PERIOD,
1471                                    tach_period));
1472
1473         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1474
1475         return ret;
1476 }
1477
1478 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1479                                      uint32_t pstate)
1480 {
1481         int ret = 0;
1482         ret = smu_send_smc_msg_with_param(smu,
1483                                           SMU_MSG_SetXgmiMode,
1484                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
1485         return ret;
1486 }
1487
1488 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1489 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1490
1491 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1492                                  struct amdgpu_irq_src *source,
1493                                  struct amdgpu_iv_entry *entry)
1494 {
1495         uint32_t client_id = entry->client_id;
1496         uint32_t src_id = entry->src_id;
1497
1498         if (client_id == SOC15_IH_CLIENTID_THM) {
1499                 switch (src_id) {
1500                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1501                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1502                                 PCI_BUS_NUM(adev->pdev->devfn),
1503                                 PCI_SLOT(adev->pdev->devfn),
1504                                 PCI_FUNC(adev->pdev->devfn));
1505                 break;
1506                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1507                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1508                                 PCI_BUS_NUM(adev->pdev->devfn),
1509                                 PCI_SLOT(adev->pdev->devfn),
1510                                 PCI_FUNC(adev->pdev->devfn));
1511                 break;
1512                 default:
1513                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1514                                 src_id,
1515                                 PCI_BUS_NUM(adev->pdev->devfn),
1516                                 PCI_SLOT(adev->pdev->devfn),
1517                                 PCI_FUNC(adev->pdev->devfn));
1518                 break;
1519
1520                 }
1521         }
1522
1523         return 0;
1524 }
1525
1526 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1527 {
1528         .process = smu_v11_0_irq_process,
1529 };
1530
1531 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1532 {
1533         struct amdgpu_device *adev = smu->adev;
1534         struct amdgpu_irq_src *irq_src = smu->irq_source;
1535         int ret = 0;
1536
1537         /* already register */
1538         if (irq_src)
1539                 return 0;
1540
1541         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1542         if (!irq_src)
1543                 return -ENOMEM;
1544         smu->irq_source = irq_src;
1545
1546         irq_src->funcs = &smu_v11_0_irq_funcs;
1547
1548         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1549                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1550                                 irq_src);
1551         if (ret)
1552                 return ret;
1553
1554         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1555                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1556                                 irq_src);
1557         if (ret)
1558                 return ret;
1559
1560         return ret;
1561 }
1562
1563 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1564                 struct pp_smu_nv_clock_table *max_clocks)
1565 {
1566         struct smu_table_context *table_context = &smu->smu_table;
1567         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1568
1569         if (!max_clocks || !table_context->max_sustainable_clocks)
1570                 return -EINVAL;
1571
1572         sustainable_clocks = table_context->max_sustainable_clocks;
1573
1574         max_clocks->dcfClockInKhz =
1575                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1576         max_clocks->displayClockInKhz =
1577                         (unsigned int) sustainable_clocks->display_clock * 1000;
1578         max_clocks->phyClockInKhz =
1579                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1580         max_clocks->pixelClockInKhz =
1581                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1582         max_clocks->uClockInKhz =
1583                         (unsigned int) sustainable_clocks->uclock * 1000;
1584         max_clocks->socClockInKhz =
1585                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1586         max_clocks->dscClockInKhz = 0;
1587         max_clocks->dppClockInKhz = 0;
1588         max_clocks->fabricClockInKhz = 0;
1589
1590         return 0;
1591 }
1592
1593 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1594 {
1595         int ret = 0;
1596
1597         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1598
1599         return ret;
1600 }
1601
1602 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1603 {
1604         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1605 }
1606
1607 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1608 {
1609         struct amdgpu_device *adev = smu->adev;
1610         struct smu_baco_context *smu_baco = &smu->smu_baco;
1611         uint32_t val;
1612         bool baco_support;
1613
1614         mutex_lock(&smu_baco->mutex);
1615         baco_support = smu_baco->platform_support;
1616         mutex_unlock(&smu_baco->mutex);
1617
1618         if (!baco_support)
1619                 return false;
1620
1621         /* Arcturus does not support this bit mask */
1622         if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1623            !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1624                 return false;
1625
1626         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1627         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1628                 return true;
1629
1630         return false;
1631 }
1632
1633 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1634 {
1635         struct smu_baco_context *smu_baco = &smu->smu_baco;
1636         enum smu_baco_state baco_state;
1637
1638         mutex_lock(&smu_baco->mutex);
1639         baco_state = smu_baco->state;
1640         mutex_unlock(&smu_baco->mutex);
1641
1642         return baco_state;
1643 }
1644
1645 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1646 {
1647
1648         struct smu_baco_context *smu_baco = &smu->smu_baco;
1649         struct amdgpu_device *adev = smu->adev;
1650         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1651         uint32_t bif_doorbell_intr_cntl;
1652         uint32_t data;
1653         int ret = 0;
1654
1655         if (smu_v11_0_baco_get_state(smu) == state)
1656                 return 0;
1657
1658         mutex_lock(&smu_baco->mutex);
1659
1660         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
1661
1662         if (state == SMU_BACO_STATE_ENTER) {
1663                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1664                                                 BIF_DOORBELL_INT_CNTL,
1665                                                 DOORBELL_INTERRUPT_DISABLE, 1);
1666                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1667
1668                 if (!ras || !ras->supported) {
1669                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1670                         data |= 0x80000000;
1671                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1672
1673                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0);
1674                 } else {
1675                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1);
1676                 }
1677         } else {
1678                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1679                 if (ret)
1680                         goto out;
1681
1682                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1683                                                 BIF_DOORBELL_INT_CNTL,
1684                                                 DOORBELL_INTERRUPT_DISABLE, 0);
1685                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1686
1687                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1688                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1689                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1690         }
1691         if (ret)
1692                 goto out;
1693
1694         smu_baco->state = state;
1695 out:
1696         mutex_unlock(&smu_baco->mutex);
1697         return ret;
1698 }
1699
1700 int smu_v11_0_baco_enter(struct smu_context *smu)
1701 {
1702         struct amdgpu_device *adev = smu->adev;
1703         int ret = 0;
1704
1705         /* Arcturus does not need this audio workaround */
1706         if (adev->asic_type != CHIP_ARCTURUS) {
1707                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1708                 if (ret)
1709                         return ret;
1710         }
1711
1712         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1713         if (ret)
1714                 return ret;
1715
1716         msleep(10);
1717
1718         return ret;
1719 }
1720
1721 int smu_v11_0_baco_exit(struct smu_context *smu)
1722 {
1723         int ret = 0;
1724
1725         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1726         if (ret)
1727                 return ret;
1728
1729         return ret;
1730 }
1731
1732 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1733                                                  uint32_t *min, uint32_t *max)
1734 {
1735         int ret = 0, clk_id = 0;
1736         uint32_t param = 0;
1737
1738         clk_id = smu_clk_get_index(smu, clk_type);
1739         if (clk_id < 0) {
1740                 ret = -EINVAL;
1741                 goto failed;
1742         }
1743         param = (clk_id & 0xffff) << 16;
1744
1745         if (max) {
1746                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
1747                 if (ret)
1748                         goto failed;
1749                 ret = smu_read_smc_arg(smu, max);
1750                 if (ret)
1751                         goto failed;
1752         }
1753
1754         if (min) {
1755                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
1756                 if (ret)
1757                         goto failed;
1758                 ret = smu_read_smc_arg(smu, min);
1759                 if (ret)
1760                         goto failed;
1761         }
1762
1763 failed:
1764         return ret;
1765 }
1766
1767 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1768                             uint32_t min, uint32_t max)
1769 {
1770         int ret = 0, clk_id = 0;
1771         uint32_t param;
1772
1773         clk_id = smu_clk_get_index(smu, clk_type);
1774         if (clk_id < 0)
1775                 return clk_id;
1776
1777         if (max > 0) {
1778                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1779                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1780                                                   param);
1781                 if (ret)
1782                         return ret;
1783         }
1784
1785         if (min > 0) {
1786                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1787                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1788                                                   param);
1789                 if (ret)
1790                         return ret;
1791         }
1792
1793         return ret;
1794 }
1795
1796 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1797 {
1798         struct amdgpu_device *adev = smu->adev;
1799         uint32_t pcie_gen = 0, pcie_width = 0;
1800         int ret;
1801
1802         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1803                 pcie_gen = 3;
1804         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1805                 pcie_gen = 2;
1806         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1807                 pcie_gen = 1;
1808         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1809                 pcie_gen = 0;
1810
1811         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1812          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1813          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1814          */
1815         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1816                 pcie_width = 6;
1817         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1818                 pcie_width = 5;
1819         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1820                 pcie_width = 4;
1821         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1822                 pcie_width = 3;
1823         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1824                 pcie_width = 2;
1825         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1826                 pcie_width = 1;
1827
1828         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1829
1830         if (ret)
1831                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1832
1833         return ret;
1834
1835 }
1836
1837 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1838 {
1839         struct smu_table_context *table_context = &smu->smu_table;
1840         int ret = 0;
1841
1842         if (initialize) {
1843                 if (table_context->overdrive_table) {
1844                         return -EINVAL;
1845                 }
1846                 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1847                 if (!table_context->overdrive_table) {
1848                         return -ENOMEM;
1849                 }
1850                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1851                 if (ret) {
1852                         pr_err("Failed to export overdrive table!\n");
1853                         return ret;
1854                 }
1855         }
1856         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1857         if (ret) {
1858                 pr_err("Failed to import overdrive table!\n");
1859                 return ret;
1860         }
1861         return ret;
1862 }