drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #define SMU_11_0_PARTIAL_PPTABLE
  28
  29 #include "pp_debug.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_smu.h"
  32 #include "smu_internal.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "smu_v11_0.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amd_pcie.h"
  40
  41 #include "asic_reg/thm/thm_11_0_2_offset.h"
  42 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  43 #include "asic_reg/mp/mp_11_0_offset.h"
  44 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  45 #include "asic_reg/nbio/nbio_7_4_offset.h"
  46 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  48 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  49
  50 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  51 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  52 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  53 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  54 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  55
  56 #define SMU11_VOLTAGE_SCALE 4
  57
  58 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  59                                               uint16_t msg)
  60 {
  61         struct amdgpu_device *adev = smu->adev;
  62         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  63         return 0;
  64 }
  65
  66 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  67 {
  68         struct amdgpu_device *adev = smu->adev;
  69
  70         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  71         return 0;
  72 }
  73
  74 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  75 {
  76         struct amdgpu_device *adev = smu->adev;
  77         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  78
  79         for (i = 0; i < timeout; i++) {
  80                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  81                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  82                         break;
  83                 udelay(1);
  84         }
  85
  86         /* timeout means wrong logic */
  87         if (i == timeout)
  88                 return -ETIME;
  89
  90         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  91 }
  92
  93 int
  94 smu_v11_0_send_msg_with_param(struct smu_context *smu,
  95                               enum smu_message_type msg,
  96                               uint32_t param)
  97 {
  98         struct amdgpu_device *adev = smu->adev;
  99         int ret = 0, index = 0;
 100
 101         index = smu_msg_get_index(smu, msg);
 102         if (index < 0)
 103                 return index;
 104
 105         ret = smu_v11_0_wait_for_response(smu);
 106         if (ret)
 107                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 108                        smu_get_message_name(smu, msg), index, param, ret);
 109
 110         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 111
 112         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 113
 114         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 115
 116         ret = smu_v11_0_wait_for_response(smu);
 117         if (ret)
 118                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 119                        smu_get_message_name(smu, msg), index, param, ret);
 120
 121         return ret;
 122 }
 123
 124 int smu_v11_0_init_microcode(struct smu_context *smu)
 125 {
 126         struct amdgpu_device *adev = smu->adev;
 127         const char *chip_name;
 128         char fw_name[30];
 129         int err = 0;
 130         const struct smc_firmware_header_v1_0 *hdr;
 131         const struct common_firmware_header *header;
 132         struct amdgpu_firmware_info *ucode = NULL;
 133
 134         switch (adev->asic_type) {
 135         case CHIP_VEGA20:
 136                 chip_name = "vega20";
 137                 break;
 138         case CHIP_ARCTURUS:
 139                 chip_name = "arcturus";
 140                 break;
 141         case CHIP_NAVI10:
 142                 chip_name = "navi10";
 143                 break;
 144         case CHIP_NAVI14:
 145                 chip_name = "navi14";
 146                 break;
 147         case CHIP_NAVI12:
 148                 chip_name = "navi12";
 149                 break;
 150         default:
 151                 BUG();
 152         }
 153
 154         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 155
 156         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 157         if (err)
 158                 goto out;
 159         err = amdgpu_ucode_validate(adev->pm.fw);
 160         if (err)
 161                 goto out;
 162
 163         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 164         amdgpu_ucode_print_smc_hdr(&hdr->header);
 165         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 166
 167         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 168                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 169                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 170                 ucode->fw = adev->pm.fw;
 171                 header = (const struct common_firmware_header *)ucode->fw->data;
 172                 adev->firmware.fw_size +=
 173                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 174         }
 175
 176 out:
 177         if (err) {
 178                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 179                           fw_name);
 180                 release_firmware(adev->pm.fw);
 181                 adev->pm.fw = NULL;
 182         }
 183         return err;
 184 }
 185
 186 int smu_v11_0_load_microcode(struct smu_context *smu)
 187 {
 188         struct amdgpu_device *adev = smu->adev;
 189         const uint32_t *src;
 190         const struct smc_firmware_header_v1_0 *hdr;
 191         uint32_t addr_start = MP1_SRAM;
 192         uint32_t i;
 193         uint32_t mp1_fw_flags;
 194
 195         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 196         src = (const uint32_t *)(adev->pm.fw->data +
 197                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 198
 199         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 200                 WREG32_PCIE(addr_start, src[i]);
 201                 addr_start += 4;
 202         }
 203
 204         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 205                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 206         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 207                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 208
 209         for (i = 0; i < adev->usec_timeout; i++) {
 210                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 211                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 212                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 213                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 214                         break;
 215                 udelay(1);
 216         }
 217
 218         if (i == adev->usec_timeout)
 219                 return -ETIME;
 220
 221         return 0;
 222 }
 223
 224 int smu_v11_0_check_fw_status(struct smu_context *smu)
 225 {
 226         struct amdgpu_device *adev = smu->adev;
 227         uint32_t mp1_fw_flags;
 228
 229         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 230                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 231
 232         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 233             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 234                 return 0;
 235
 236         return -EIO;
 237 }
 238
 239 int smu_v11_0_check_fw_version(struct smu_context *smu)
 240 {
 241         uint32_t if_version = 0xff, smu_version = 0xff;
 242         uint16_t smu_major;
 243         uint8_t smu_minor, smu_debug;
 244         int ret = 0;
 245
 246         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 247         if (ret)
 248                 return ret;
 249
 250         smu_major = (smu_version >> 16) & 0xffff;
 251         smu_minor = (smu_version >> 8) & 0xff;
 252         smu_debug = (smu_version >> 0) & 0xff;
 253
 254         switch (smu->adev->asic_type) {
 255         case CHIP_VEGA20:
 256                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
 257                 break;
 258         case CHIP_ARCTURUS:
 259                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 260                 break;
 261         case CHIP_NAVI10:
 262                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 263                 break;
 264         case CHIP_NAVI14:
 265                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 266                 break;
 267         default:
 268                 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
 269                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
 270                 break;
 271         }
 272
 273         /*
 274          * 1. if_version mismatch is not critical as our fw is designed
 275          * to be backward compatible.
 276          * 2. New fw usually brings some optimizations. But that's visible
 277          * only on the paired driver.
 278          * Considering above, we just leave user a warning message instead
 279          * of halt driver loading.
 280          */
 281         if (if_version != smu->smc_if_version) {
 282                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 283                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 284                         smu->smc_if_version, if_version,
 285                         smu_version, smu_major, smu_minor, smu_debug);
 286                 pr_warn("SMU driver if version not matched\n");
 287         }
 288
 289         return ret;
 290 }
 291
 292 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 293 {
 294         struct amdgpu_device *adev = smu->adev;
 295         uint32_t ppt_offset_bytes;
 296         const struct smc_firmware_header_v2_0 *v2;
 297
 298         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 299
 300         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 301         *size = le32_to_cpu(v2->ppt_size_bytes);
 302         *table = (uint8_t *)v2 + ppt_offset_bytes;
 303
 304         return 0;
 305 }
 306
 307 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 308                                       uint32_t *size, uint32_t pptable_id)
 309 {
 310         struct amdgpu_device *adev = smu->adev;
 311         const struct smc_firmware_header_v2_1 *v2_1;
 312         struct smc_soft_pptable_entry *entries;
 313         uint32_t pptable_count = 0;
 314         int i = 0;
 315
 316         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 317         entries = (struct smc_soft_pptable_entry *)
 318                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 319         pptable_count = le32_to_cpu(v2_1->pptable_count);
 320         for (i = 0; i < pptable_count; i++) {
 321                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 322                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 323                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 324                         break;
 325                 }
 326         }
 327
 328         if (i == pptable_count)
 329                 return -EINVAL;
 330
 331         return 0;
 332 }
 333
 334 int smu_v11_0_setup_pptable(struct smu_context *smu)
 335 {
 336         struct amdgpu_device *adev = smu->adev;
 337         const struct smc_firmware_header_v1_0 *hdr;
 338         int ret, index;
 339         uint32_t size = 0;
 340         uint16_t atom_table_size;
 341         uint8_t frev, crev;
 342         void *table;
 343         uint16_t version_major, version_minor;
 344
 345         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 346         version_major = le16_to_cpu(hdr->header.header_version_major);
 347         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 348         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 349                 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 350                 switch (version_minor) {
 351                 case 0:
 352                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 353                         break;
 354                 case 1:
 355                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 356                                                          smu->smu_table.boot_values.pp_table_id);
 357                         break;
 358                 default:
 359                         ret = -EINVAL;
 360                         break;
 361                 }
 362                 if (ret)
 363                         return ret;
 364
 365         } else {
 366                 pr_info("use vbios provided pptable\n");
 367                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 368                                                     powerplayinfo);
 369
 370                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 371                                               (uint8_t **)&table);
 372                 if (ret)
 373                         return ret;
 374                 size = atom_table_size;
 375         }
 376
 377         if (!smu->smu_table.power_play_table)
 378                 smu->smu_table.power_play_table = table;
 379         if (!smu->smu_table.power_play_table_size)
 380                 smu->smu_table.power_play_table_size = size;
 381
 382         return 0;
 383 }
 384
 385 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 386 {
 387         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 388
 389         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 390                 return -EINVAL;
 391
 392         return smu_alloc_dpm_context(smu);
 393 }
 394
 395 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 396 {
 397         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 398
 399         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 400                 return -EINVAL;
 401
 402         kfree(smu_dpm->dpm_context);
 403         kfree(smu_dpm->golden_dpm_context);
 404         kfree(smu_dpm->dpm_current_power_state);
 405         kfree(smu_dpm->dpm_request_power_state);
 406         smu_dpm->dpm_context = NULL;
 407         smu_dpm->golden_dpm_context = NULL;
 408         smu_dpm->dpm_context_size = 0;
 409         smu_dpm->dpm_current_power_state = NULL;
 410         smu_dpm->dpm_request_power_state = NULL;
 411
 412         return 0;
 413 }
 414
 415 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 416 {
 417         struct smu_table_context *smu_table = &smu->smu_table;
 418         struct smu_table *tables = NULL;
 419         int ret = 0;
 420
 421         if (smu_table->tables)
 422                 return -EINVAL;
 423
 424         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 425                          GFP_KERNEL);
 426         if (!tables)
 427                 return -ENOMEM;
 428
 429         smu_table->tables = tables;
 430
 431         ret = smu_tables_init(smu, tables);
 432         if (ret)
 433                 return ret;
 434
 435         ret = smu_v11_0_init_dpm_context(smu);
 436         if (ret)
 437                 return ret;
 438
 439         return 0;
 440 }
 441
 442 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 443 {
 444         struct smu_table_context *smu_table = &smu->smu_table;
 445         int ret = 0;
 446
 447         if (!smu_table->tables)
 448                 return -EINVAL;
 449
 450         kfree(smu_table->tables);
 451         kfree(smu_table->metrics_table);
 452         smu_table->tables = NULL;
 453         smu_table->metrics_table = NULL;
 454         smu_table->metrics_time = 0;
 455
 456         ret = smu_v11_0_fini_dpm_context(smu);
 457         if (ret)
 458                 return ret;
 459         return 0;
 460 }
 461
 462 int smu_v11_0_init_power(struct smu_context *smu)
 463 {
 464         struct smu_power_context *smu_power = &smu->smu_power;
 465
 466         if (!smu->pm_enabled)
 467                 return 0;
 468         if (smu_power->power_context || smu_power->power_context_size != 0)
 469                 return -EINVAL;
 470
 471         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 472                                            GFP_KERNEL);
 473         if (!smu_power->power_context)
 474                 return -ENOMEM;
 475         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 476
 477         return 0;
 478 }
 479
 480 int smu_v11_0_fini_power(struct smu_context *smu)
 481 {
 482         struct smu_power_context *smu_power = &smu->smu_power;
 483
 484         if (!smu->pm_enabled)
 485                 return 0;
 486         if (!smu_power->power_context || smu_power->power_context_size == 0)
 487                 return -EINVAL;
 488
 489         kfree(smu_power->power_context);
 490         smu_power->power_context = NULL;
 491         smu_power->power_context_size = 0;
 492
 493         return 0;
 494 }
 495
 496 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 497 {
 498         int ret, index;
 499         uint16_t size;
 500         uint8_t frev, crev;
 501         struct atom_common_table_header *header;
 502         struct atom_firmware_info_v3_3 *v_3_3;
 503         struct atom_firmware_info_v3_1 *v_3_1;
 504
 505         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 506                                             firmwareinfo);
 507
 508         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 509                                       (uint8_t **)&header);
 510         if (ret)
 511                 return ret;
 512
 513         if (header->format_revision != 3) {
 514                 pr_err("unknown atom_firmware_info version! for smu11\n");
 515                 return -EINVAL;
 516         }
 517
 518         switch (header->content_revision) {
 519         case 0:
 520         case 1:
 521         case 2:
 522                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 523                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 524                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 525                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 526                 smu->smu_table.boot_values.socclk = 0;
 527                 smu->smu_table.boot_values.dcefclk = 0;
 528                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 529                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 530                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 531                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 532                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 533                 smu->smu_table.boot_values.pp_table_id = 0;
 534                 break;
 535         case 3:
 536         default:
 537                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 538                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 539                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 540                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 541                 smu->smu_table.boot_values.socclk = 0;
 542                 smu->smu_table.boot_values.dcefclk = 0;
 543                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 544                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 545                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 546                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 547                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 548                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 549         }
 550
 551         smu->smu_table.boot_values.format_revision = header->format_revision;
 552         smu->smu_table.boot_values.content_revision = header->content_revision;
 553
 554         return 0;
 555 }
 556
 557 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 558 {
 559         int ret, index;
 560         struct amdgpu_device *adev = smu->adev;
 561         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 562         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 563
 564         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 565         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 566         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 567                                             getsmuclockinfo);
 568
 569         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 570                                         (uint32_t *)&input);
 571         if (ret)
 572                 return -EINVAL;
 573
 574         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 575         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 576
 577         memset(&input, 0, sizeof(input));
 578         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 579         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 580         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 581                                             getsmuclockinfo);
 582
 583         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 584                                         (uint32_t *)&input);
 585         if (ret)
 586                 return -EINVAL;
 587
 588         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 589         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 590
 591         memset(&input, 0, sizeof(input));
 592         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 593         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 594         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 595                                             getsmuclockinfo);
 596
 597         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 598                                         (uint32_t *)&input);
 599         if (ret)
 600                 return -EINVAL;
 601
 602         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 603         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 604
 605         memset(&input, 0, sizeof(input));
 606         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 607         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 608         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 609                                             getsmuclockinfo);
 610
 611         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 612                                         (uint32_t *)&input);
 613         if (ret)
 614                 return -EINVAL;
 615
 616         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 617         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 618
 619         memset(&input, 0, sizeof(input));
 620         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 621         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 622         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 623                                             getsmuclockinfo);
 624
 625         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 626                                         (uint32_t *)&input);
 627         if (ret)
 628                 return -EINVAL;
 629
 630         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 631         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 632
 633         if ((smu->smu_table.boot_values.format_revision == 3) &&
 634             (smu->smu_table.boot_values.content_revision >= 2)) {
 635                 memset(&input, 0, sizeof(input));
 636                 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
 637                 input.syspll_id = SMU11_SYSPLL1_2_ID;
 638                 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 639                 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 640                                                     getsmuclockinfo);
 641
 642                 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 643                                                 (uint32_t *)&input);
 644                 if (ret)
 645                         return -EINVAL;
 646
 647                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 648                 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 649         }
 650
 651         return 0;
 652 }
 653
 654 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 655 {
 656         struct smu_table_context *smu_table = &smu->smu_table;
 657         struct smu_table *memory_pool = &smu_table->memory_pool;
 658         int ret = 0;
 659         uint64_t address;
 660         uint32_t address_low, address_high;
 661
 662         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 663                 return ret;
 664
 665         address = (uintptr_t)memory_pool->cpu_addr;
 666         address_high = (uint32_t)upper_32_bits(address);
 667         address_low  = (uint32_t)lower_32_bits(address);
 668
 669         ret = smu_send_smc_msg_with_param(smu,
 670                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 671                                           address_high);
 672         if (ret)
 673                 return ret;
 674         ret = smu_send_smc_msg_with_param(smu,
 675                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 676                                           address_low);
 677         if (ret)
 678                 return ret;
 679
 680         address = memory_pool->mc_address;
 681         address_high = (uint32_t)upper_32_bits(address);
 682         address_low  = (uint32_t)lower_32_bits(address);
 683
 684         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 685                                           address_high);
 686         if (ret)
 687                 return ret;
 688         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 689                                           address_low);
 690         if (ret)
 691                 return ret;
 692         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 693                                           (uint32_t)memory_pool->size);
 694         if (ret)
 695                 return ret;
 696
 697         return ret;
 698 }
 699
 700 int smu_v11_0_check_pptable(struct smu_context *smu)
 701 {
 702         int ret;
 703
 704         ret = smu_check_powerplay_table(smu);
 705         return ret;
 706 }
 707
 708 int smu_v11_0_parse_pptable(struct smu_context *smu)
 709 {
 710         int ret;
 711
 712         struct smu_table_context *table_context = &smu->smu_table;
 713         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 714
 715         if (table_context->driver_pptable)
 716                 return -EINVAL;
 717
 718         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 719
 720         if (!table_context->driver_pptable)
 721                 return -ENOMEM;
 722
 723         ret = smu_store_powerplay_table(smu);
 724         if (ret)
 725                 return -EINVAL;
 726
 727         ret = smu_append_powerplay_table(smu);
 728
 729         return ret;
 730 }
 731
 732 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 733 {
 734         int ret;
 735
 736         ret = smu_set_default_dpm_table(smu);
 737
 738         return ret;
 739 }
 740
 741 int smu_v11_0_write_pptable(struct smu_context *smu)
 742 {
 743         struct smu_table_context *table_context = &smu->smu_table;
 744         int ret = 0;
 745
 746         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 747                                table_context->driver_pptable, true);
 748
 749         return ret;
 750 }
 751
 752 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 753 {
 754         int ret;
 755
 756         ret = smu_send_smc_msg_with_param(smu,
 757                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 758         if (ret)
 759                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 760
 761         return ret;
 762 }
 763
 764 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 765 {
 766         struct smu_table_context *table_context = &smu->smu_table;
 767
 768         if (!smu->pm_enabled)
 769                 return 0;
 770         if (!table_context)
 771                 return -EINVAL;
 772
 773         return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
 774 }
 775
 776 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 777 {
 778         int ret = 0;
 779         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 780
 781         if (tool_table->mc_address) {
 782                 ret = smu_send_smc_msg_with_param(smu,
 783                                 SMU_MSG_SetToolsDramAddrHigh,
 784                                 upper_32_bits(tool_table->mc_address));
 785                 if (!ret)
 786                         ret = smu_send_smc_msg_with_param(smu,
 787                                 SMU_MSG_SetToolsDramAddrLow,
 788                                 lower_32_bits(tool_table->mc_address));
 789         }
 790
 791         return ret;
 792 }
 793
 794 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 795 {
 796         int ret = 0;
 797
 798         if (!smu->pm_enabled)
 799                 return ret;
 800
 801         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 802         return ret;
 803 }
 804
 805
 806 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 807 {
 808         struct smu_feature *feature = &smu->smu_feature;
 809         int ret = 0;
 810         uint32_t feature_mask[2];
 811
 812         mutex_lock(&feature->mutex);
 813         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 814                 goto failed;
 815
 816         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 817
 818         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 819                                           feature_mask[1]);
 820         if (ret)
 821                 goto failed;
 822
 823         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 824                                           feature_mask[0]);
 825         if (ret)
 826                 goto failed;
 827
 828 failed:
 829         mutex_unlock(&feature->mutex);
 830         return ret;
 831 }
 832
 833 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 834                                       uint32_t *feature_mask, uint32_t num)
 835 {
 836         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 837         int ret = 0;
 838
 839         if (!feature_mask || num < 2)
 840                 return -EINVAL;
 841
 842         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 843         if (ret)
 844                 return ret;
 845         ret = smu_read_smc_arg(smu, &feature_mask_high);
 846         if (ret)
 847                 return ret;
 848
 849         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 850         if (ret)
 851                 return ret;
 852         ret = smu_read_smc_arg(smu, &feature_mask_low);
 853         if (ret)
 854                 return ret;
 855
 856         feature_mask[0] = feature_mask_low;
 857         feature_mask[1] = feature_mask_high;
 858
 859         return ret;
 860 }
 861
 862 int smu_v11_0_system_features_control(struct smu_context *smu,
 863                                              bool en)
 864 {
 865         struct smu_feature *feature = &smu->smu_feature;
 866         uint32_t feature_mask[2];
 867         int ret = 0;
 868
 869         if (smu->pm_enabled) {
 870                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 871                                              SMU_MSG_DisableAllSmuFeatures));
 872                 if (ret)
 873                         return ret;
 874         }
 875
 876         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 877         if (ret)
 878                 return ret;
 879
 880         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 881                     feature->feature_num);
 882         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 883                     feature->feature_num);
 884
 885         return ret;
 886 }
 887
 888 int smu_v11_0_notify_display_change(struct smu_context *smu)
 889 {
 890         int ret = 0;
 891
 892         if (!smu->pm_enabled)
 893                 return ret;
 894         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 895             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 896                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 897
 898         return ret;
 899 }
 900
 901 static int
 902 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 903                                     enum smu_clk_type clock_select)
 904 {
 905         int ret = 0;
 906         int clk_id;
 907
 908         if (!smu->pm_enabled)
 909                 return ret;
 910
 911         if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 912             (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
 913                 return 0;
 914
 915         clk_id = smu_clk_get_index(smu, clock_select);
 916         if (clk_id < 0)
 917                 return -EINVAL;
 918
 919         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 920                                           clk_id << 16);
 921         if (ret) {
 922                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 923                 return ret;
 924         }
 925
 926         ret = smu_read_smc_arg(smu, clock);
 927         if (ret)
 928                 return ret;
 929
 930         if (*clock != 0)
 931                 return 0;
 932
 933         /* if DC limit is zero, return AC limit */
 934         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 935                                           clk_id << 16);
 936         if (ret) {
 937                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 938                 return ret;
 939         }
 940
 941         ret = smu_read_smc_arg(smu, clock);
 942
 943         return ret;
 944 }
 945
 946 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 947 {
 948         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 949         int ret = 0;
 950
 951         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 952                                          GFP_KERNEL);
 953         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 954
 955         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 956         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 957         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 958         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 959         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 960         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 961
 962         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 963                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 964                                                           &(max_sustainable_clocks->uclock),
 965                                                           SMU_UCLK);
 966                 if (ret) {
 967                         pr_err("[%s] failed to get max UCLK from SMC!",
 968                                __func__);
 969                         return ret;
 970                 }
 971         }
 972
 973         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 974                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 975                                                           &(max_sustainable_clocks->soc_clock),
 976                                                           SMU_SOCCLK);
 977                 if (ret) {
 978                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 979                                __func__);
 980                         return ret;
 981                 }
 982         }
 983
 984         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 985                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 986                                                           &(max_sustainable_clocks->dcef_clock),
 987                                                           SMU_DCEFCLK);
 988                 if (ret) {
 989                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
 990                                __func__);
 991                         return ret;
 992                 }
 993
 994                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 995                                                           &(max_sustainable_clocks->display_clock),
 996                                                           SMU_DISPCLK);
 997                 if (ret) {
 998                         pr_err("[%s] failed to get max DISPCLK from SMC!",
 999                                __func__);
1000                         return ret;
1001                 }
1002                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1003                                                           &(max_sustainable_clocks->phy_clock),
1004                                                           SMU_PHYCLK);
1005                 if (ret) {
1006                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1007                                __func__);
1008                         return ret;
1009                 }
1010                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1011                                                           &(max_sustainable_clocks->pixel_clock),
1012                                                           SMU_PIXCLK);
1013                 if (ret) {
1014                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1015                                __func__);
1016                         return ret;
1017                 }
1018         }
1019
1020         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1021                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1022
1023         return 0;
1024 }
1025
1026 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1027         uint32_t od_limit, max_power_limit;
1028         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1029         struct smu_table_context *table_context = &smu->smu_table;
1030         powerplay_table = table_context->power_play_table;
1031
1032         max_power_limit = smu_get_pptable_power_limit(smu);
1033
1034         if (!max_power_limit) {
1035                 // If we couldn't get the table limit, fall back on first-read value
1036                 if (!smu->default_power_limit)
1037                         smu->default_power_limit = smu->power_limit;
1038                 max_power_limit = smu->default_power_limit;
1039         }
1040
1041         if (smu->od_enabled) {
1042                 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1043
1044                 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1045
1046                 max_power_limit *= (100 + od_limit);
1047                 max_power_limit /= 100;
1048         }
1049
1050         return max_power_limit;
1051 }
1052
1053 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1054 {
1055         int ret = 0;
1056         uint32_t max_power_limit;
1057
1058         max_power_limit = smu_v11_0_get_max_power_limit(smu);
1059
1060         if (n > max_power_limit) {
1061                 pr_err("New power limit (%d) is over the max allowed %d\n",
1062                                 n,
1063                                 max_power_limit);
1064                 return -EINVAL;
1065         }
1066
1067         if (n == 0)
1068                 n = smu->default_power_limit;
1069
1070         if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1071                 pr_err("Setting new power limit is not supported!\n");
1072                 return -EOPNOTSUPP;
1073         }
1074
1075         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1076         if (ret) {
1077                 pr_err("[%s] Set power limit Failed!\n", __func__);
1078                 return ret;
1079         }
1080         smu->power_limit = n;
1081
1082         return 0;
1083 }
1084
1085 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1086                                           enum smu_clk_type clk_id,
1087                                           uint32_t *value)
1088 {
1089         int ret = 0;
1090         uint32_t freq = 0;
1091         int asic_clk_id;
1092
1093         if (clk_id >= SMU_CLK_COUNT || !value)
1094                 return -EINVAL;
1095
1096         asic_clk_id = smu_clk_get_index(smu, clk_id);
1097         if (asic_clk_id < 0)
1098                 return -EINVAL;
1099
1100         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1101         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1102                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1103         else {
1104                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1105                                                   (asic_clk_id << 16));
1106                 if (ret)
1107                         return ret;
1108
1109                 ret = smu_read_smc_arg(smu, &freq);
1110                 if (ret)
1111                         return ret;
1112         }
1113
1114         freq *= 100;
1115         *value = freq;
1116
1117         return ret;
1118 }
1119
1120 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1121                                        struct smu_temperature_range range)
1122 {
1123         struct amdgpu_device *adev = smu->adev;
1124         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1125         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1126         uint32_t val;
1127
1128         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1129                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1130         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1131                         range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1132
1133         if (low > high)
1134                 return -EINVAL;
1135
1136         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1137         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1138         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1139         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1140         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1141         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1142         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1143         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1144
1145         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1146
1147         return 0;
1148 }
1149
1150 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1151 {
1152         struct amdgpu_device *adev = smu->adev;
1153         uint32_t val = 0;
1154
1155         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1156         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1157         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1158
1159         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1160
1161         return 0;
1162 }
1163
1164 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1165 {
1166         int ret = 0;
1167         struct smu_temperature_range range;
1168         struct amdgpu_device *adev = smu->adev;
1169
1170         if (!smu->pm_enabled)
1171                 return ret;
1172
1173         memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1174
1175         ret = smu_get_thermal_temperature_range(smu, &range);
1176         if (ret)
1177                 return ret;
1178
1179         if (smu->smu_table.thermal_controller_type) {
1180                 ret = smu_v11_0_set_thermal_range(smu, range);
1181                 if (ret)
1182                         return ret;
1183
1184                 ret = smu_v11_0_enable_thermal_alert(smu);
1185                 if (ret)
1186                         return ret;
1187
1188                 ret = smu_set_thermal_fan_table(smu);
1189                 if (ret)
1190                         return ret;
1191         }
1192
1193         adev->pm.dpm.thermal.min_temp = range.min;
1194         adev->pm.dpm.thermal.max_temp = range.max;
1195         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1196         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1197         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1198         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1199         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1200         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1201         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1202
1203         return ret;
1204 }
1205
1206 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1207 {
1208         struct amdgpu_device *adev = smu->adev;
1209
1210         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1211
1212         return 0;
1213 }
1214
1215 static uint16_t convert_to_vddc(uint8_t vid)
1216 {
1217         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1218 }
1219
1220 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1221 {
1222         struct amdgpu_device *adev = smu->adev;
1223         uint32_t vdd = 0, val_vid = 0;
1224
1225         if (!value)
1226                 return -EINVAL;
1227         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1228                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1229                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1230
1231         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1232
1233         *value = vdd;
1234
1235         return 0;
1236
1237 }
1238
1239 int smu_v11_0_read_sensor(struct smu_context *smu,
1240                                  enum amd_pp_sensors sensor,
1241                                  void *data, uint32_t *size)
1242 {
1243         int ret = 0;
1244
1245         if(!data || !size)
1246                 return -EINVAL;
1247
1248         switch (sensor) {
1249         case AMDGPU_PP_SENSOR_GFX_MCLK:
1250                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1251                 *size = 4;
1252                 break;
1253         case AMDGPU_PP_SENSOR_GFX_SCLK:
1254                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1255                 *size = 4;
1256                 break;
1257         case AMDGPU_PP_SENSOR_VDDGFX:
1258                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1259                 *size = 4;
1260                 break;
1261         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1262                 *(uint32_t *)data = 0;
1263                 *size = 4;
1264                 break;
1265         default:
1266                 ret = smu_common_read_sensor(smu, sensor, data, size);
1267                 break;
1268         }
1269
1270         if (ret)
1271                 *size = 0;
1272
1273         return ret;
1274 }
1275
1276 int
1277 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1278                                         struct pp_display_clock_request
1279                                         *clock_req)
1280 {
1281         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1282         int ret = 0;
1283         enum smu_clk_type clk_select = 0;
1284         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1285
1286         if (!smu->pm_enabled)
1287                 return -EINVAL;
1288
1289         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1290                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1291                 switch (clk_type) {
1292                 case amd_pp_dcef_clock:
1293                         clk_select = SMU_DCEFCLK;
1294                         break;
1295                 case amd_pp_disp_clock:
1296                         clk_select = SMU_DISPCLK;
1297                         break;
1298                 case amd_pp_pixel_clock:
1299                         clk_select = SMU_PIXCLK;
1300                         break;
1301                 case amd_pp_phy_clock:
1302                         clk_select = SMU_PHYCLK;
1303                         break;
1304                 case amd_pp_mem_clock:
1305                         clk_select = SMU_UCLK;
1306                         break;
1307                 default:
1308                         pr_info("[%s] Invalid Clock Type!", __func__);
1309                         ret = -EINVAL;
1310                         break;
1311                 }
1312
1313                 if (ret)
1314                         goto failed;
1315
1316                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1317                         return 0;
1318
1319                 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1320
1321                 if(clk_select == SMU_UCLK)
1322                         smu->hard_min_uclk_req_from_dal = clk_freq;
1323         }
1324
1325 failed:
1326         return ret;
1327 }
1328
1329 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1330 {
1331         int ret = 0;
1332         struct amdgpu_device *adev = smu->adev;
1333
1334         switch (adev->asic_type) {
1335         case CHIP_VEGA20:
1336                 break;
1337         case CHIP_NAVI10:
1338         case CHIP_NAVI14:
1339         case CHIP_NAVI12:
1340                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1341                         return 0;
1342                 if (enable)
1343                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1344                 else
1345                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1346                 break;
1347         default:
1348                 break;
1349         }
1350
1351         return ret;
1352 }
1353
1354 uint32_t
1355 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1356 {
1357         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1358                 return AMD_FAN_CTRL_MANUAL;
1359         else
1360                 return AMD_FAN_CTRL_AUTO;
1361 }
1362
1363 static int
1364 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1365 {
1366         int ret = 0;
1367
1368         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1369                 return 0;
1370
1371         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1372         if (ret)
1373                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1374                        __func__, (auto_fan_control ? "Start" : "Stop"));
1375
1376         return ret;
1377 }
1378
1379 static int
1380 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1381 {
1382         struct amdgpu_device *adev = smu->adev;
1383
1384         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1385                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1386                                    CG_FDO_CTRL2, TMIN, 0));
1387         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1388                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1389                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1390
1391         return 0;
1392 }
1393
1394 int
1395 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1396 {
1397         struct amdgpu_device *adev = smu->adev;
1398         uint32_t duty100, duty;
1399         uint64_t tmp64;
1400
1401         if (speed > 100)
1402                 speed = 100;
1403
1404         if (smu_v11_0_auto_fan_control(smu, 0))
1405                 return -EINVAL;
1406
1407         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1408                                 CG_FDO_CTRL1, FMAX_DUTY100);
1409         if (!duty100)
1410                 return -EINVAL;
1411
1412         tmp64 = (uint64_t)speed * duty100;
1413         do_div(tmp64, 100);
1414         duty = (uint32_t)tmp64;
1415
1416         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1417                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1418                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1419
1420         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1421 }
1422
1423 int
1424 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1425                                uint32_t mode)
1426 {
1427         int ret = 0;
1428
1429         switch (mode) {
1430         case AMD_FAN_CTRL_NONE:
1431                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1432                 break;
1433         case AMD_FAN_CTRL_MANUAL:
1434                 ret = smu_v11_0_auto_fan_control(smu, 0);
1435                 break;
1436         case AMD_FAN_CTRL_AUTO:
1437                 ret = smu_v11_0_auto_fan_control(smu, 1);
1438                 break;
1439         default:
1440                 break;
1441         }
1442
1443         if (ret) {
1444                 pr_err("[%s]Set fan control mode failed!", __func__);
1445                 return -EINVAL;
1446         }
1447
1448         return ret;
1449 }
1450
1451 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1452                                        uint32_t speed)
1453 {
1454         struct amdgpu_device *adev = smu->adev;
1455         int ret;
1456         uint32_t tach_period, crystal_clock_freq;
1457
1458         if (!speed)
1459                 return -EINVAL;
1460
1461         ret = smu_v11_0_auto_fan_control(smu, 0);
1462         if (ret)
1463                 return ret;
1464
1465         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1466         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1467         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1468                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1469                                    CG_TACH_CTRL, TARGET_PERIOD,
1470                                    tach_period));
1471
1472         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1473
1474         return ret;
1475 }
1476
1477 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1478                                      uint32_t pstate)
1479 {
1480         int ret = 0;
1481         ret = smu_send_smc_msg_with_param(smu,
1482                                           SMU_MSG_SetXgmiMode,
1483                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
1484         return ret;
1485 }
1486
1487 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1488 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1489
1490 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1491                                  struct amdgpu_irq_src *source,
1492                                  struct amdgpu_iv_entry *entry)
1493 {
1494         uint32_t client_id = entry->client_id;
1495         uint32_t src_id = entry->src_id;
1496
1497         if (client_id == SOC15_IH_CLIENTID_THM) {
1498                 switch (src_id) {
1499                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1500                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1501                                 PCI_BUS_NUM(adev->pdev->devfn),
1502                                 PCI_SLOT(adev->pdev->devfn),
1503                                 PCI_FUNC(adev->pdev->devfn));
1504                 break;
1505                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1506                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1507                                 PCI_BUS_NUM(adev->pdev->devfn),
1508                                 PCI_SLOT(adev->pdev->devfn),
1509                                 PCI_FUNC(adev->pdev->devfn));
1510                 break;
1511                 default:
1512                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1513                                 src_id,
1514                                 PCI_BUS_NUM(adev->pdev->devfn),
1515                                 PCI_SLOT(adev->pdev->devfn),
1516                                 PCI_FUNC(adev->pdev->devfn));
1517                 break;
1518
1519                 }
1520         }
1521
1522         return 0;
1523 }
1524
1525 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1526 {
1527         .process = smu_v11_0_irq_process,
1528 };
1529
1530 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1531 {
1532         struct amdgpu_device *adev = smu->adev;
1533         struct amdgpu_irq_src *irq_src = smu->irq_source;
1534         int ret = 0;
1535
1536         /* already register */
1537         if (irq_src)
1538                 return 0;
1539
1540         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1541         if (!irq_src)
1542                 return -ENOMEM;
1543         smu->irq_source = irq_src;
1544
1545         irq_src->funcs = &smu_v11_0_irq_funcs;
1546
1547         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1548                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1549                                 irq_src);
1550         if (ret)
1551                 return ret;
1552
1553         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1554                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1555                                 irq_src);
1556         if (ret)
1557                 return ret;
1558
1559         return ret;
1560 }
1561
1562 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1563                 struct pp_smu_nv_clock_table *max_clocks)
1564 {
1565         struct smu_table_context *table_context = &smu->smu_table;
1566         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1567
1568         if (!max_clocks || !table_context->max_sustainable_clocks)
1569                 return -EINVAL;
1570
1571         sustainable_clocks = table_context->max_sustainable_clocks;
1572
1573         max_clocks->dcfClockInKhz =
1574                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1575         max_clocks->displayClockInKhz =
1576                         (unsigned int) sustainable_clocks->display_clock * 1000;
1577         max_clocks->phyClockInKhz =
1578                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1579         max_clocks->pixelClockInKhz =
1580                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1581         max_clocks->uClockInKhz =
1582                         (unsigned int) sustainable_clocks->uclock * 1000;
1583         max_clocks->socClockInKhz =
1584                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1585         max_clocks->dscClockInKhz = 0;
1586         max_clocks->dppClockInKhz = 0;
1587         max_clocks->fabricClockInKhz = 0;
1588
1589         return 0;
1590 }
1591
1592 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1593 {
1594         int ret = 0;
1595
1596         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1597
1598         return ret;
1599 }
1600
1601 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1602 {
1603         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1604 }
1605
1606 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1607 {
1608         struct amdgpu_device *adev = smu->adev;
1609         struct smu_baco_context *smu_baco = &smu->smu_baco;
1610         uint32_t val;
1611         bool baco_support;
1612
1613         mutex_lock(&smu_baco->mutex);
1614         baco_support = smu_baco->platform_support;
1615         mutex_unlock(&smu_baco->mutex);
1616
1617         if (!baco_support)
1618                 return false;
1619
1620         if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1621                 return false;
1622
1623         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1624         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1625                 return true;
1626
1627         return false;
1628 }
1629
1630 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1631 {
1632         struct smu_baco_context *smu_baco = &smu->smu_baco;
1633         enum smu_baco_state baco_state;
1634
1635         mutex_lock(&smu_baco->mutex);
1636         baco_state = smu_baco->state;
1637         mutex_unlock(&smu_baco->mutex);
1638
1639         return baco_state;
1640 }
1641
1642 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1643 {
1644
1645         struct smu_baco_context *smu_baco = &smu->smu_baco;
1646         int ret = 0;
1647
1648         if (smu_v11_0_baco_get_state(smu) == state)
1649                 return 0;
1650
1651         mutex_lock(&smu_baco->mutex);
1652
1653         if (state == SMU_BACO_STATE_ENTER)
1654                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
1655         else
1656                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1657         if (ret)
1658                 goto out;
1659
1660         smu_baco->state = state;
1661 out:
1662         mutex_unlock(&smu_baco->mutex);
1663         return ret;
1664 }
1665
1666 int smu_v11_0_baco_reset(struct smu_context *smu)
1667 {
1668         int ret = 0;
1669
1670         ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1671         if (ret)
1672                 return ret;
1673
1674         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1675         if (ret)
1676                 return ret;
1677
1678         msleep(10);
1679
1680         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1681         if (ret)
1682                 return ret;
1683
1684         return ret;
1685 }
1686
1687 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1688                                                  uint32_t *min, uint32_t *max)
1689 {
1690         int ret = 0, clk_id = 0;
1691         uint32_t param = 0;
1692
1693         clk_id = smu_clk_get_index(smu, clk_type);
1694         if (clk_id < 0) {
1695                 ret = -EINVAL;
1696                 goto failed;
1697         }
1698         param = (clk_id & 0xffff) << 16;
1699
1700         if (max) {
1701                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
1702                 if (ret)
1703                         goto failed;
1704                 ret = smu_read_smc_arg(smu, max);
1705                 if (ret)
1706                         goto failed;
1707         }
1708
1709         if (min) {
1710                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
1711                 if (ret)
1712                         goto failed;
1713                 ret = smu_read_smc_arg(smu, min);
1714                 if (ret)
1715                         goto failed;
1716         }
1717
1718 failed:
1719         return ret;
1720 }
1721
1722 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1723                             uint32_t min, uint32_t max)
1724 {
1725         int ret = 0, clk_id = 0;
1726         uint32_t param;
1727
1728         clk_id = smu_clk_get_index(smu, clk_type);
1729         if (clk_id < 0)
1730                 return clk_id;
1731
1732         if (max > 0) {
1733                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1734                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1735                                                   param);
1736                 if (ret)
1737                         return ret;
1738         }
1739
1740         if (min > 0) {
1741                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1742                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1743                                                   param);
1744                 if (ret)
1745                         return ret;
1746         }
1747
1748         return ret;
1749 }
1750
1751 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1752 {
1753         struct amdgpu_device *adev = smu->adev;
1754         uint32_t pcie_gen = 0, pcie_width = 0;
1755         int ret;
1756
1757         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1758                 pcie_gen = 3;
1759         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1760                 pcie_gen = 2;
1761         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1762                 pcie_gen = 1;
1763         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1764                 pcie_gen = 0;
1765
1766         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1767          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1768          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1769          */
1770         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1771                 pcie_width = 6;
1772         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1773                 pcie_width = 5;
1774         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1775                 pcie_width = 4;
1776         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1777                 pcie_width = 3;
1778         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1779                 pcie_width = 2;
1780         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1781                 pcie_width = 1;
1782
1783         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1784
1785         if (ret)
1786                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1787
1788         return ret;
1789
1790 }
1791
1792 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1793 {
1794         struct smu_table_context *table_context = &smu->smu_table;
1795         int ret = 0;
1796
1797         if (initialize) {
1798                 if (table_context->overdrive_table) {
1799                         return -EINVAL;
1800                 }
1801                 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1802                 if (!table_context->overdrive_table) {
1803                         return -ENOMEM;
1804                 }
1805                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1806                 if (ret) {
1807                         pr_err("Failed to export overdrive table!\n");
1808                         return ret;
1809                 }
1810         }
1811         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1812         if (ret) {
1813                 pr_err("Failed to import overdrive table!\n");
1814                 return ret;
1815         }
1816         return ret;
1817 }