drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "pp_debug.h"
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "atomfirmware.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "smu_v11_0.h"
  30 #include "smu_11_0_driver_if.h"
  31 #include "soc15_common.h"
  32 #include "atom.h"
  33 #include "vega20_ppt.h"
  34 #include "navi10_ppt.h"
  35 #include "pp_thermal.h"
  36
  37 #include "asic_reg/thm/thm_11_0_2_offset.h"
  38 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  39 #include "asic_reg/mp/mp_11_0_offset.h"
  40 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  41 #include "asic_reg/nbio/nbio_7_4_offset.h"
  42 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  43 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  44
  45 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  47
  48 #define SMU11_TOOL_SIZE         0x19000
  49 #define SMU11_THERMAL_MINIMUM_ALERT_TEMP      0
  50 #define SMU11_THERMAL_MAXIMUM_ALERT_TEMP      255
  51
  52 #define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
  53 #define SMU11_VOLTAGE_SCALE 4
  54
  55 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  56                                               uint16_t msg)
  57 {
  58         struct amdgpu_device *adev = smu->adev;
  59         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  60         return 0;
  61 }
  62
  63 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  64 {
  65         struct amdgpu_device *adev = smu->adev;
  66
  67         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  68         return 0;
  69 }
  70
  71 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  72 {
  73         struct amdgpu_device *adev = smu->adev;
  74         uint32_t cur_value, i;
  75
  76         for (i = 0; i < adev->usec_timeout; i++) {
  77                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  78                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  79                         break;
  80                 udelay(1);
  81         }
  82
  83         /* timeout means wrong logic */
  84         if (i == adev->usec_timeout)
  85                 return -ETIME;
  86
  87         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  88 }
  89
  90 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  91 {
  92         struct amdgpu_device *adev = smu->adev;
  93         int ret = 0, index = 0;
  94
  95         index = smu_msg_get_index(smu, msg);
  96         if (index < 0)
  97                 return index;
  98
  99         smu_v11_0_wait_for_response(smu);
 100
 101         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 102
 103         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 104
 105         ret = smu_v11_0_wait_for_response(smu);
 106
 107         if (ret)
 108                 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 109                        ret);
 110
 111         return ret;
 112
 113 }
 114
 115 static int
 116 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 117                               uint32_t param)
 118 {
 119
 120         struct amdgpu_device *adev = smu->adev;
 121         int ret = 0, index = 0;
 122
 123         index = smu_msg_get_index(smu, msg);
 124         if (index < 0)
 125                 return index;
 126
 127         ret = smu_v11_0_wait_for_response(smu);
 128         if (ret)
 129                 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
 130                        index, ret, param);
 131
 132         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 133
 134         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 135
 136         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 137
 138         ret = smu_v11_0_wait_for_response(smu);
 139         if (ret)
 140                 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
 141                        index, ret, param);
 142
 143         return ret;
 144 }
 145
 146 static int smu_v11_0_init_microcode(struct smu_context *smu)
 147 {
 148         struct amdgpu_device *adev = smu->adev;
 149         const char *chip_name;
 150         char fw_name[30];
 151         int err = 0;
 152         const struct smc_firmware_header_v1_0 *hdr;
 153         const struct common_firmware_header *header;
 154         struct amdgpu_firmware_info *ucode = NULL;
 155
 156         switch (adev->asic_type) {
 157         case CHIP_VEGA20:
 158                 chip_name = "vega20";
 159                 break;
 160         case CHIP_NAVI10:
 161                 chip_name = "navi10";
 162                 break;
 163         default:
 164                 BUG();
 165         }
 166
 167         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 168
 169         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 170         if (err)
 171                 goto out;
 172         err = amdgpu_ucode_validate(adev->pm.fw);
 173         if (err)
 174                 goto out;
 175
 176         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 177         amdgpu_ucode_print_smc_hdr(&hdr->header);
 178         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 179
 180         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 181                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 182                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 183                 ucode->fw = adev->pm.fw;
 184                 header = (const struct common_firmware_header *)ucode->fw->data;
 185                 adev->firmware.fw_size +=
 186                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 187         }
 188
 189 out:
 190         if (err) {
 191                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 192                           fw_name);
 193                 release_firmware(adev->pm.fw);
 194                 adev->pm.fw = NULL;
 195         }
 196         return err;
 197 }
 198
 199 static int smu_v11_0_load_microcode(struct smu_context *smu)
 200 {
 201         struct amdgpu_device *adev = smu->adev;
 202         const uint32_t *src;
 203         const struct smc_firmware_header_v1_0 *hdr;
 204         uint32_t addr_start = MP1_SRAM;
 205         uint32_t i;
 206         uint32_t mp1_fw_flags;
 207
 208         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 209         src = (const uint32_t *)(adev->pm.fw->data +
 210                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 211
 212         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 213                 WREG32_PCIE(addr_start, src[i]);
 214                 addr_start += 4;
 215         }
 216
 217         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 218                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 219         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 220                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 221
 222         for (i = 0; i < adev->usec_timeout; i++) {
 223                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 224                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 225                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 226                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 227                         break;
 228                 udelay(1);
 229         }
 230
 231         if (i == adev->usec_timeout)
 232                 return -ETIME;
 233
 234         return 0;
 235 }
 236
 237 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 238 {
 239         struct amdgpu_device *adev = smu->adev;
 240         uint32_t mp1_fw_flags;
 241
 242         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 243                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 244
 245         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 246             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 247                 return 0;
 248
 249         return -EIO;
 250 }
 251
 252 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 253 {
 254         uint32_t if_version = 0xff, smu_version = 0xff;
 255         uint16_t smu_major;
 256         uint8_t smu_minor, smu_debug;
 257         int ret = 0;
 258
 259         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 260         if (ret)
 261                 return ret;
 262
 263         smu_major = (smu_version >> 16) & 0xffff;
 264         smu_minor = (smu_version >> 8) & 0xff;
 265         smu_debug = (smu_version >> 0) & 0xff;
 266
 267         pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x (%d.%d.%d)\n",
 268                 if_version, smu_version, smu_major, smu_minor, smu_debug);
 269
 270         if (if_version != smu->smc_if_version) {
 271                 pr_err("SMU driver if version not matched\n");
 272                 ret = -EINVAL;
 273         }
 274
 275         return ret;
 276 }
 277
 278 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 279 {
 280         struct amdgpu_device *adev = smu->adev;
 281         uint32_t ppt_offset_bytes;
 282         const struct smc_firmware_header_v2_0 *v2;
 283
 284         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 285
 286         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 287         *size = le32_to_cpu(v2->ppt_size_bytes);
 288         *table = (uint8_t *)v2 + ppt_offset_bytes;
 289
 290         return 0;
 291 }
 292
 293 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
 294 {
 295         struct amdgpu_device *adev = smu->adev;
 296         const struct smc_firmware_header_v2_1 *v2_1;
 297         struct smc_soft_pptable_entry *entries;
 298         uint32_t pptable_count = 0;
 299         int i = 0;
 300
 301         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 302         entries = (struct smc_soft_pptable_entry *)
 303                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 304         pptable_count = le32_to_cpu(v2_1->pptable_count);
 305         for (i = 0; i < pptable_count; i++) {
 306                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 307                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 308                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 309                         break;
 310                 }
 311         }
 312
 313         if (i == pptable_count)
 314                 return -EINVAL;
 315
 316         return 0;
 317 }
 318
 319 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 320 {
 321         struct amdgpu_device *adev = smu->adev;
 322         const struct smc_firmware_header_v1_0 *hdr;
 323         int ret, index;
 324         uint32_t size;
 325         uint8_t frev, crev;
 326         void *table;
 327         uint16_t version_major, version_minor;
 328
 329         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 330         version_major = le16_to_cpu(hdr->header.header_version_major);
 331         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 332
 333         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 334                 switch (version_minor) {
 335                 case 0:
 336                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 337                         break;
 338                 case 1:
 339                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 340                                                          smu->smu_table.boot_values.pp_table_id);
 341                         break;
 342                 default:
 343                         ret = -EINVAL;
 344                         break;
 345                 }
 346                 if (ret)
 347                         return ret;
 348
 349         } else {
 350                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 351                                                     powerplayinfo);
 352
 353                 ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
 354                                               (uint8_t **)&table);
 355                 if (ret)
 356                         return ret;
 357         }
 358
 359         if (!smu->smu_table.power_play_table)
 360                 smu->smu_table.power_play_table = table;
 361         if (!smu->smu_table.power_play_table_size)
 362                 smu->smu_table.power_play_table_size = size;
 363
 364         return 0;
 365 }
 366
 367 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 368 {
 369         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 370
 371         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 372                 return -EINVAL;
 373
 374         return smu_alloc_dpm_context(smu);
 375 }
 376
 377 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 378 {
 379         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 380
 381         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 382                 return -EINVAL;
 383
 384         kfree(smu_dpm->dpm_context);
 385         kfree(smu_dpm->golden_dpm_context);
 386         kfree(smu_dpm->dpm_current_power_state);
 387         kfree(smu_dpm->dpm_request_power_state);
 388         smu_dpm->dpm_context = NULL;
 389         smu_dpm->golden_dpm_context = NULL;
 390         smu_dpm->dpm_context_size = 0;
 391         smu_dpm->dpm_current_power_state = NULL;
 392         smu_dpm->dpm_request_power_state = NULL;
 393
 394         return 0;
 395 }
 396
 397 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 398 {
 399         struct smu_table_context *smu_table = &smu->smu_table;
 400         struct smu_table *tables = NULL;
 401         int ret = 0;
 402
 403         if (smu_table->tables || smu_table->table_count != 0)
 404                 return -EINVAL;
 405
 406         tables = kcalloc(TABLE_COUNT, sizeof(struct smu_table), GFP_KERNEL);
 407         if (!tables)
 408                 return -ENOMEM;
 409
 410         smu_table->tables = tables;
 411         smu_table->table_count = TABLE_COUNT;
 412
 413         SMU_TABLE_INIT(tables, TABLE_PPTABLE, sizeof(PPTable_t),
 414                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 415         SMU_TABLE_INIT(tables, TABLE_WATERMARKS, sizeof(Watermarks_t),
 416                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 417         SMU_TABLE_INIT(tables, TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 418                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 419         SMU_TABLE_INIT(tables, TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 420                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 421         SMU_TABLE_INIT(tables, TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, PAGE_SIZE,
 422                        AMDGPU_GEM_DOMAIN_VRAM);
 423         SMU_TABLE_INIT(tables, TABLE_ACTIVITY_MONITOR_COEFF,
 424                        sizeof(DpmActivityMonitorCoeffInt_t),
 425                        PAGE_SIZE,
 426                        AMDGPU_GEM_DOMAIN_VRAM);
 427
 428         ret = smu_v11_0_init_dpm_context(smu);
 429         if (ret)
 430                 return ret;
 431
 432         return 0;
 433 }
 434
 435 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 436 {
 437         struct smu_table_context *smu_table = &smu->smu_table;
 438         int ret = 0;
 439
 440         if (!smu_table->tables || smu_table->table_count == 0)
 441                 return -EINVAL;
 442
 443         kfree(smu_table->tables);
 444         smu_table->tables = NULL;
 445         smu_table->table_count = 0;
 446
 447         ret = smu_v11_0_fini_dpm_context(smu);
 448         if (ret)
 449                 return ret;
 450         return 0;
 451 }
 452
 453 static int smu_v11_0_init_power(struct smu_context *smu)
 454 {
 455         struct smu_power_context *smu_power = &smu->smu_power;
 456
 457         if (!smu->pm_enabled)
 458                 return 0;
 459         if (smu_power->power_context || smu_power->power_context_size != 0)
 460                 return -EINVAL;
 461
 462         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 463                                            GFP_KERNEL);
 464         if (!smu_power->power_context)
 465                 return -ENOMEM;
 466         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 467
 468         smu->metrics_time = 0;
 469         smu->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 470         if (!smu->metrics_table) {
 471                 kfree(smu_power->power_context);
 472                 return -ENOMEM;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static int smu_v11_0_fini_power(struct smu_context *smu)
 479 {
 480         struct smu_power_context *smu_power = &smu->smu_power;
 481
 482         if (!smu->pm_enabled)
 483                 return 0;
 484         if (!smu_power->power_context || smu_power->power_context_size == 0)
 485                 return -EINVAL;
 486
 487         kfree(smu->metrics_table);
 488         kfree(smu_power->power_context);
 489         smu->metrics_table = NULL;
 490         smu_power->power_context = NULL;
 491         smu_power->power_context_size = 0;
 492
 493         return 0;
 494 }
 495
 496 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 497 {
 498         int ret, index;
 499         uint16_t size;
 500         uint8_t frev, crev;
 501         struct atom_common_table_header *header;
 502         struct atom_firmware_info_v3_3 *v_3_3;
 503         struct atom_firmware_info_v3_1 *v_3_1;
 504
 505         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 506                                             firmwareinfo);
 507
 508         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 509                                       (uint8_t **)&header);
 510         if (ret)
 511                 return ret;
 512
 513         if (header->format_revision != 3) {
 514                 pr_err("unknown atom_firmware_info version! for smu11\n");
 515                 return -EINVAL;
 516         }
 517
 518         switch (header->content_revision) {
 519         case 0:
 520         case 1:
 521         case 2:
 522                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 523                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 524                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 525                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 526                 smu->smu_table.boot_values.socclk = 0;
 527                 smu->smu_table.boot_values.dcefclk = 0;
 528                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 529                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 530                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 531                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 532                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 533                 smu->smu_table.boot_values.pp_table_id = 0;
 534                 break;
 535         case 3:
 536         default:
 537                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 538                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 539                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 540                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 541                 smu->smu_table.boot_values.socclk = 0;
 542                 smu->smu_table.boot_values.dcefclk = 0;
 543                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 544                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 545                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 546                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 547                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 548                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 555 {
 556         int ret, index;
 557         struct amdgpu_device *adev = smu->adev;
 558         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 559         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 560
 561         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 562         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 563         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 564                                             getsmuclockinfo);
 565
 566         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 567                                         (uint32_t *)&input);
 568         if (ret)
 569                 return -EINVAL;
 570
 571         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 572         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 573
 574         memset(&input, 0, sizeof(input));
 575         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 576         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 577         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 578                                             getsmuclockinfo);
 579
 580         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 581                                         (uint32_t *)&input);
 582         if (ret)
 583                 return -EINVAL;
 584
 585         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 586         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 587
 588         memset(&input, 0, sizeof(input));
 589         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 590         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 591         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 592                                             getsmuclockinfo);
 593
 594         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 595                                         (uint32_t *)&input);
 596         if (ret)
 597                 return -EINVAL;
 598
 599         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 600         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 601
 602         memset(&input, 0, sizeof(input));
 603         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 604         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 605         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 606                                             getsmuclockinfo);
 607
 608         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 609                                         (uint32_t *)&input);
 610         if (ret)
 611                 return -EINVAL;
 612
 613         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 614         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 615
 616         memset(&input, 0, sizeof(input));
 617         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 618         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 619         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 620                                             getsmuclockinfo);
 621
 622         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 623                                         (uint32_t *)&input);
 624         if (ret)
 625                 return -EINVAL;
 626
 627         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 628         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 629
 630         return 0;
 631 }
 632
 633 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 634 {
 635         struct smu_table_context *smu_table = &smu->smu_table;
 636         struct smu_table *memory_pool = &smu_table->memory_pool;
 637         int ret = 0;
 638         uint64_t address;
 639         uint32_t address_low, address_high;
 640
 641         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 642                 return ret;
 643
 644         address = (uintptr_t)memory_pool->cpu_addr;
 645         address_high = (uint32_t)upper_32_bits(address);
 646         address_low  = (uint32_t)lower_32_bits(address);
 647
 648         ret = smu_send_smc_msg_with_param(smu,
 649                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 650                                           address_high);
 651         if (ret)
 652                 return ret;
 653         ret = smu_send_smc_msg_with_param(smu,
 654                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 655                                           address_low);
 656         if (ret)
 657                 return ret;
 658
 659         address = memory_pool->mc_address;
 660         address_high = (uint32_t)upper_32_bits(address);
 661         address_low  = (uint32_t)lower_32_bits(address);
 662
 663         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 664                                           address_high);
 665         if (ret)
 666                 return ret;
 667         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 668                                           address_low);
 669         if (ret)
 670                 return ret;
 671         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 672                                           (uint32_t)memory_pool->size);
 673         if (ret)
 674                 return ret;
 675
 676         return ret;
 677 }
 678
 679 static int smu_v11_0_check_pptable(struct smu_context *smu)
 680 {
 681         int ret;
 682
 683         ret = smu_check_powerplay_table(smu);
 684         return ret;
 685 }
 686
 687 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 688 {
 689         int ret;
 690
 691         struct smu_table_context *table_context = &smu->smu_table;
 692
 693         if (table_context->driver_pptable)
 694                 return -EINVAL;
 695
 696         table_context->driver_pptable = kzalloc(sizeof(PPTable_t), GFP_KERNEL);
 697
 698         if (!table_context->driver_pptable)
 699                 return -ENOMEM;
 700
 701         ret = smu_store_powerplay_table(smu);
 702         if (ret)
 703                 return -EINVAL;
 704
 705         ret = smu_append_powerplay_table(smu);
 706
 707         return ret;
 708 }
 709
 710 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 711 {
 712         int ret;
 713
 714         ret = smu_set_default_dpm_table(smu);
 715
 716         return ret;
 717 }
 718
 719 static int smu_v11_0_write_pptable(struct smu_context *smu)
 720 {
 721         struct smu_table_context *table_context = &smu->smu_table;
 722         int ret = 0;
 723
 724         ret = smu_update_table(smu, TABLE_PPTABLE, table_context->driver_pptable, true);
 725
 726         return ret;
 727 }
 728
 729 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 730 {
 731         return smu_update_table(smu, TABLE_WATERMARKS,
 732                                 smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr, true);
 733 }
 734
 735 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 736 {
 737         int ret;
 738
 739         ret = smu_send_smc_msg_with_param(smu,
 740                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 741         if (ret)
 742                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 743
 744         return ret;
 745 }
 746
 747 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 748 {
 749         struct smu_table_context *table_context = &smu->smu_table;
 750
 751         if (!smu->pm_enabled)
 752                 return 0;
 753         if (!table_context)
 754                 return -EINVAL;
 755
 756         return smu_set_deep_sleep_dcefclk(smu,
 757                                           table_context->boot_values.dcefclk / 100);
 758 }
 759
 760 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 761 {
 762         int ret = 0;
 763         struct smu_table *tool_table = &smu->smu_table.tables[TABLE_PMSTATUSLOG];
 764
 765         if (tool_table->mc_address) {
 766                 ret = smu_send_smc_msg_with_param(smu,
 767                                 SMU_MSG_SetToolsDramAddrHigh,
 768                                 upper_32_bits(tool_table->mc_address));
 769                 if (!ret)
 770                         ret = smu_send_smc_msg_with_param(smu,
 771                                 SMU_MSG_SetToolsDramAddrLow,
 772                                 lower_32_bits(tool_table->mc_address));
 773         }
 774
 775         return ret;
 776 }
 777
 778 static int smu_v11_0_init_display(struct smu_context *smu)
 779 {
 780         int ret = 0;
 781
 782         if (!smu->pm_enabled)
 783                 return ret;
 784         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 785         return ret;
 786 }
 787
 788 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 789 {
 790         uint32_t feature_low = 0, feature_high = 0;
 791         int ret = 0;
 792
 793         if (!smu->pm_enabled)
 794                 return ret;
 795         if (feature_id >= 0 && feature_id < 31)
 796                 feature_low = (1 << feature_id);
 797         else if (feature_id > 31 && feature_id < 63)
 798                 feature_high = (1 << feature_id);
 799         else
 800                 return -EINVAL;
 801
 802         if (enabled) {
 803                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 804                                                   feature_low);
 805                 if (ret)
 806                         return ret;
 807                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 808                                                   feature_high);
 809                 if (ret)
 810                         return ret;
 811
 812         } else {
 813                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 814                                                   feature_low);
 815                 if (ret)
 816                         return ret;
 817                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 818                                                   feature_high);
 819                 if (ret)
 820                         return ret;
 821
 822         }
 823
 824         return ret;
 825 }
 826
 827 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 828 {
 829         struct smu_feature *feature = &smu->smu_feature;
 830         int ret = 0;
 831         uint32_t feature_mask[2];
 832
 833         mutex_lock(&feature->mutex);
 834         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 835                 goto failed;
 836
 837         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 838
 839         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 840                                           feature_mask[1]);
 841         if (ret)
 842                 goto failed;
 843
 844         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 845                                           feature_mask[0]);
 846         if (ret)
 847                 goto failed;
 848
 849 failed:
 850         mutex_unlock(&feature->mutex);
 851         return ret;
 852 }
 853
 854 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 855                                       uint32_t *feature_mask, uint32_t num)
 856 {
 857         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 858         int ret = 0;
 859
 860         if (!feature_mask || num < 2)
 861                 return -EINVAL;
 862
 863         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 864         if (ret)
 865                 return ret;
 866         ret = smu_read_smc_arg(smu, &feature_mask_high);
 867         if (ret)
 868                 return ret;
 869
 870         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 871         if (ret)
 872                 return ret;
 873         ret = smu_read_smc_arg(smu, &feature_mask_low);
 874         if (ret)
 875                 return ret;
 876
 877         feature_mask[0] = feature_mask_low;
 878         feature_mask[1] = feature_mask_high;
 879
 880         return ret;
 881 }
 882
 883 static int smu_v11_0_system_features_control(struct smu_context *smu,
 884                                              bool en)
 885 {
 886         struct smu_feature *feature = &smu->smu_feature;
 887         uint32_t feature_mask[2];
 888         int ret = 0;
 889
 890         if (smu->pm_enabled) {
 891                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 892                                              SMU_MSG_DisableAllSmuFeatures));
 893                 if (ret)
 894                         return ret;
 895         }
 896
 897         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 898         if (ret)
 899                 return ret;
 900
 901         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 902                     feature->feature_num);
 903         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 904                     feature->feature_num);
 905
 906         return ret;
 907 }
 908
 909 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 910 {
 911         int ret = 0;
 912
 913         if (!smu->pm_enabled)
 914                 return ret;
 915         if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT))
 916             ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 917
 918         return ret;
 919 }
 920
 921 static int
 922 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 923                                     PPCLK_e clock_select)
 924 {
 925         int ret = 0;
 926
 927         if (!smu->pm_enabled)
 928                 return ret;
 929         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 930                                           clock_select << 16);
 931         if (ret) {
 932                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 933                 return ret;
 934         }
 935
 936         ret = smu_read_smc_arg(smu, clock);
 937         if (ret)
 938                 return ret;
 939
 940         if (*clock != 0)
 941                 return 0;
 942
 943         /* if DC limit is zero, return AC limit */
 944         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 945                                           clock_select << 16);
 946         if (ret) {
 947                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 948                 return ret;
 949         }
 950
 951         ret = smu_read_smc_arg(smu, clock);
 952
 953         return ret;
 954 }
 955
 956 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 957 {
 958         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 959         int ret = 0;
 960
 961         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 962                                          GFP_KERNEL);
 963         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 964
 965         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 966         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 967         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 968         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 969         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 970         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 971
 972         if (smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
 973                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 974                                                           &(max_sustainable_clocks->uclock),
 975                                                           PPCLK_UCLK);
 976                 if (ret) {
 977                         pr_err("[%s] failed to get max UCLK from SMC!",
 978                                __func__);
 979                         return ret;
 980                 }
 981         }
 982
 983         if (smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
 984                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 985                                                           &(max_sustainable_clocks->soc_clock),
 986                                                           PPCLK_SOCCLK);
 987                 if (ret) {
 988                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 989                                __func__);
 990                         return ret;
 991                 }
 992         }
 993
 994         if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
 995                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 996                                                           &(max_sustainable_clocks->dcef_clock),
 997                                                           PPCLK_DCEFCLK);
 998                 if (ret) {
 999                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1000                                __func__);
1001                         return ret;
1002                 }
1003
1004                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1005                                                           &(max_sustainable_clocks->display_clock),
1006                                                           PPCLK_DISPCLK);
1007                 if (ret) {
1008                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1009                                __func__);
1010                         return ret;
1011                 }
1012                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1013                                                           &(max_sustainable_clocks->phy_clock),
1014                                                           PPCLK_PHYCLK);
1015                 if (ret) {
1016                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1017                                __func__);
1018                         return ret;
1019                 }
1020                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1021                                                           &(max_sustainable_clocks->pixel_clock),
1022                                                           PPCLK_PIXCLK);
1023                 if (ret) {
1024                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1025                                __func__);
1026                         return ret;
1027                 }
1028         }
1029
1030         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1031                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1032
1033         return 0;
1034 }
1035
1036 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1037                                      uint32_t *limit,
1038                                      bool get_default)
1039 {
1040         int ret = 0;
1041
1042         if (get_default) {
1043                 mutex_lock(&smu->mutex);
1044                 *limit = smu->default_power_limit;
1045                 if (smu->od_enabled) {
1046                         *limit *= (100 + smu->smu_table.TDPODLimit);
1047                         *limit /= 100;
1048                 }
1049                 mutex_unlock(&smu->mutex);
1050         } else {
1051                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1052                                                   POWER_SOURCE_AC << 16);
1053                 if (ret) {
1054                         pr_err("[%s] get PPT limit failed!", __func__);
1055                         return ret;
1056                 }
1057                 smu_read_smc_arg(smu, limit);
1058                 smu->power_limit = *limit;
1059         }
1060
1061         return ret;
1062 }
1063
1064 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1065 {
1066         uint32_t max_power_limit;
1067         int ret = 0;
1068
1069         if (n == 0)
1070                 n = smu->default_power_limit;
1071
1072         max_power_limit = smu->default_power_limit;
1073
1074         if (smu->od_enabled) {
1075                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1076                 max_power_limit /= 100;
1077         }
1078
1079         if (smu_feature_is_enabled(smu, FEATURE_PPT_BIT))
1080                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1081         if (ret) {
1082                 pr_err("[%s] Set power limit Failed!", __func__);
1083                 return ret;
1084         }
1085
1086         return ret;
1087 }
1088
1089 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu, uint32_t clk_id, uint32_t *value)
1090 {
1091         int ret = 0;
1092         uint32_t freq;
1093
1094         if (clk_id >= PPCLK_COUNT || !value)
1095                 return -EINVAL;
1096
1097         ret = smu_send_smc_msg_with_param(smu,
1098                         SMU_MSG_GetDpmClockFreq, (clk_id << 16));
1099         if (ret)
1100                 return ret;
1101
1102         ret = smu_read_smc_arg(smu, &freq);
1103         if (ret)
1104                 return ret;
1105
1106         freq *= 100;
1107         *value = freq;
1108
1109         return ret;
1110 }
1111
1112 static int smu_v11_0_get_thermal_range(struct smu_context *smu,
1113                                 struct PP_TemperatureRange *range)
1114 {
1115         PPTable_t *pptable = smu->smu_table.driver_pptable;
1116         memcpy(range, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
1117
1118         range->max = pptable->TedgeLimit *
1119                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1120         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1121                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1122         range->hotspot_crit_max = pptable->ThotspotLimit *
1123                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1124         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1125                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1126         range->mem_crit_max = pptable->ThbmLimit *
1127                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1128         range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
1129                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1130
1131         return 0;
1132 }
1133
1134 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1135                         struct PP_TemperatureRange *range)
1136 {
1137         struct amdgpu_device *adev = smu->adev;
1138         int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
1139                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1140         int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
1141                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1142         uint32_t val;
1143
1144         if (low < range->min)
1145                 low = range->min;
1146         if (high > range->max)
1147                 high = range->max;
1148
1149         if (low > high)
1150                 return -EINVAL;
1151
1152         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1153         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1154         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1155         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1156         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
1157         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1158
1159         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1160
1161         return 0;
1162 }
1163
1164 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1165 {
1166         struct amdgpu_device *adev = smu->adev;
1167         uint32_t val = 0;
1168
1169         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1170         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1171         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1172
1173         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1174
1175         return 0;
1176 }
1177
1178 static int smu_v11_0_set_thermal_fan_table(struct smu_context *smu)
1179 {
1180         int ret;
1181         struct smu_table_context *table_context = &smu->smu_table;
1182         PPTable_t *pptable = table_context->driver_pptable;
1183
1184         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
1185                         (uint32_t)pptable->FanTargetTemperature);
1186
1187         return ret;
1188 }
1189
1190 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1191 {
1192         int ret = 0;
1193         struct PP_TemperatureRange range = {
1194                 TEMP_RANGE_MIN,
1195                 TEMP_RANGE_MAX,
1196                 TEMP_RANGE_MAX,
1197                 TEMP_RANGE_MIN,
1198                 TEMP_RANGE_MAX,
1199                 TEMP_RANGE_MAX,
1200                 TEMP_RANGE_MIN,
1201                 TEMP_RANGE_MAX,
1202                 TEMP_RANGE_MAX};
1203         struct amdgpu_device *adev = smu->adev;
1204
1205         if (!smu->pm_enabled)
1206                 return ret;
1207         smu_v11_0_get_thermal_range(smu, &range);
1208
1209         if (smu->smu_table.thermal_controller_type) {
1210                 ret = smu_v11_0_set_thermal_range(smu, &range);
1211                 if (ret)
1212                         return ret;
1213
1214                 ret = smu_v11_0_enable_thermal_alert(smu);
1215                 if (ret)
1216                         return ret;
1217                 ret = smu_v11_0_set_thermal_fan_table(smu);
1218                 if (ret)
1219                         return ret;
1220         }
1221
1222         adev->pm.dpm.thermal.min_temp = range.min;
1223         adev->pm.dpm.thermal.max_temp = range.max;
1224         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1225         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1226         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1227         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1228         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1229         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1230         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1231
1232         return ret;
1233 }
1234
1235 static int smu_v11_0_get_metrics_table(struct smu_context *smu,
1236                 SmuMetrics_t *metrics_table)
1237 {
1238         int ret = 0;
1239
1240         if (!smu->metrics_time || time_after(jiffies, smu->metrics_time + HZ / 1000)) {
1241                 ret = smu_update_table(smu, TABLE_SMU_METRICS,
1242                                 (void *)metrics_table, false);
1243                 if (ret) {
1244                         pr_info("Failed to export SMU metrics table!\n");
1245                         return ret;
1246                 }
1247                 memcpy(smu->metrics_table, metrics_table, sizeof(SmuMetrics_t));
1248                 smu->metrics_time = jiffies;
1249         } else
1250                 memcpy(metrics_table, smu->metrics_table, sizeof(SmuMetrics_t));
1251
1252         return ret;
1253 }
1254
1255 static int smu_v11_0_get_current_activity_percent(struct smu_context *smu,
1256                                                   enum amd_pp_sensors sensor,
1257                                                   uint32_t *value)
1258 {
1259         int ret = 0;
1260         SmuMetrics_t metrics;
1261
1262         if (!value)
1263                 return -EINVAL;
1264
1265         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1266         if (ret)
1267                 return ret;
1268
1269         switch (sensor) {
1270         case AMDGPU_PP_SENSOR_GPU_LOAD:
1271                 *value = metrics.AverageGfxActivity;
1272                 break;
1273         case AMDGPU_PP_SENSOR_MEM_LOAD:
1274                 *value = metrics.AverageUclkActivity;
1275                 break;
1276         default:
1277                 pr_err("Invalid sensor for retrieving clock activity\n");
1278                 return -EINVAL;
1279         }
1280
1281         return 0;
1282 }
1283
1284 static int smu_v11_0_thermal_get_temperature(struct smu_context *smu,
1285                                              enum amd_pp_sensors sensor,
1286                                              uint32_t *value)
1287 {
1288         struct amdgpu_device *adev = smu->adev;
1289         SmuMetrics_t metrics;
1290         uint32_t temp = 0;
1291         int ret = 0;
1292
1293         if (!value)
1294                 return -EINVAL;
1295
1296         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1297         if (ret)
1298                 return ret;
1299
1300         switch (sensor) {
1301         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1302                 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
1303                 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
1304                                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
1305
1306                 temp = temp & 0x1ff;
1307                 temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
1308
1309                 *value = temp;
1310                 break;
1311         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1312                 *value = metrics.TemperatureEdge *
1313                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1314                 break;
1315         case AMDGPU_PP_SENSOR_MEM_TEMP:
1316                 *value = metrics.TemperatureHBM *
1317                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1318                 break;
1319         default:
1320                 pr_err("Invalid sensor for retrieving temp\n");
1321                 return -EINVAL;
1322         }
1323
1324         return 0;
1325 }
1326
1327 static int smu_v11_0_get_gpu_power(struct smu_context *smu, uint32_t *value)
1328 {
1329         int ret = 0;
1330         SmuMetrics_t metrics;
1331
1332         if (!value)
1333                 return -EINVAL;
1334
1335         ret = smu_v11_0_get_metrics_table(smu, &metrics);
1336         if (ret)
1337                 return ret;
1338
1339         *value = metrics.CurrSocketPower << 8;
1340
1341         return 0;
1342 }
1343
1344 static uint16_t convert_to_vddc(uint8_t vid)
1345 {
1346         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1347 }
1348
1349 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1350 {
1351         struct amdgpu_device *adev = smu->adev;
1352         uint32_t vdd = 0, val_vid = 0;
1353
1354         if (!value)
1355                 return -EINVAL;
1356         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1357                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1358                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1359
1360         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1361
1362         *value = vdd;
1363
1364         return 0;
1365
1366 }
1367
1368 static int smu_v11_0_read_sensor(struct smu_context *smu,
1369                                  enum amd_pp_sensors sensor,
1370                                  void *data, uint32_t *size)
1371 {
1372         struct smu_table_context *table_context = &smu->smu_table;
1373         PPTable_t *pptable = table_context->driver_pptable;
1374         int ret = 0;
1375         switch (sensor) {
1376         case AMDGPU_PP_SENSOR_GPU_LOAD:
1377         case AMDGPU_PP_SENSOR_MEM_LOAD:
1378                 ret = smu_v11_0_get_current_activity_percent(smu,
1379                                                              sensor,
1380                                                              (uint32_t *)data);
1381                 *size = 4;
1382                 break;
1383         case AMDGPU_PP_SENSOR_GFX_MCLK:
1384                 ret = smu_get_current_clk_freq(smu, PPCLK_UCLK, (uint32_t *)data);
1385                 *size = 4;
1386                 break;
1387         case AMDGPU_PP_SENSOR_GFX_SCLK:
1388                 ret = smu_get_current_clk_freq(smu, PPCLK_GFXCLK, (uint32_t *)data);
1389                 *size = 4;
1390                 break;
1391         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1392         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1393         case AMDGPU_PP_SENSOR_MEM_TEMP:
1394                 ret = smu_v11_0_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1395                 *size = 4;
1396                 break;
1397         case AMDGPU_PP_SENSOR_GPU_POWER:
1398                 ret = smu_v11_0_get_gpu_power(smu, (uint32_t *)data);
1399                 *size = 4;
1400                 break;
1401         case AMDGPU_PP_SENSOR_VDDGFX:
1402                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1403                 *size = 4;
1404                 break;
1405         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1406                 *(uint32_t *)data = 0;
1407                 *size = 4;
1408                 break;
1409         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1410                 *(uint32_t *)data = pptable->FanMaximumRpm;
1411                 *size = 4;
1412                 break;
1413         default:
1414                 ret = smu_common_read_sensor(smu, sensor, data, size);
1415                 break;
1416         }
1417
1418         /* try get sensor data by asic */
1419         if (ret)
1420                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1421
1422         if (ret)
1423                 *size = 0;
1424
1425         return ret;
1426 }
1427
1428 static int
1429 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1430                                         struct pp_display_clock_request
1431                                         *clock_req)
1432 {
1433         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1434         int ret = 0;
1435         PPCLK_e clk_select = 0;
1436         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1437
1438         if (!smu->pm_enabled)
1439                 return -EINVAL;
1440         if (smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT)) {
1441                 switch (clk_type) {
1442                 case amd_pp_dcef_clock:
1443                         clk_select = PPCLK_DCEFCLK;
1444                         break;
1445                 case amd_pp_disp_clock:
1446                         clk_select = PPCLK_DISPCLK;
1447                         break;
1448                 case amd_pp_pixel_clock:
1449                         clk_select = PPCLK_PIXCLK;
1450                         break;
1451                 case amd_pp_phy_clock:
1452                         clk_select = PPCLK_PHYCLK;
1453                         break;
1454                 default:
1455                         pr_info("[%s] Invalid Clock Type!", __func__);
1456                         ret = -EINVAL;
1457                         break;
1458                 }
1459
1460                 if (ret)
1461                         goto failed;
1462
1463                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1464                                                   (clk_select << 16) | clk_freq);
1465         }
1466
1467 failed:
1468         return ret;
1469 }
1470
1471 static int smu_v11_0_set_watermarks_table(struct smu_context *smu,
1472                                           Watermarks_t *table, struct
1473                                           dm_pp_wm_sets_with_clock_ranges_soc15
1474                                           *clock_ranges)
1475 {
1476         int i;
1477
1478         if (!table || !clock_ranges)
1479                 return -EINVAL;
1480
1481         if (clock_ranges->num_wm_dmif_sets > 4 ||
1482             clock_ranges->num_wm_mcif_sets > 4)
1483                 return -EINVAL;
1484
1485         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1486                 table->WatermarkRow[1][i].MinClock =
1487                         cpu_to_le16((uint16_t)
1488                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1489                         1000));
1490                 table->WatermarkRow[1][i].MaxClock =
1491                         cpu_to_le16((uint16_t)
1492                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1493                         1000));
1494                 table->WatermarkRow[1][i].MinUclk =
1495                         cpu_to_le16((uint16_t)
1496                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1497                         1000));
1498                 table->WatermarkRow[1][i].MaxUclk =
1499                         cpu_to_le16((uint16_t)
1500                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1501                         1000));
1502                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1503                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1504         }
1505
1506         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1507                 table->WatermarkRow[0][i].MinClock =
1508                         cpu_to_le16((uint16_t)
1509                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1510                         1000));
1511                 table->WatermarkRow[0][i].MaxClock =
1512                         cpu_to_le16((uint16_t)
1513                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1514                         1000));
1515                 table->WatermarkRow[0][i].MinUclk =
1516                         cpu_to_le16((uint16_t)
1517                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1518                         1000));
1519                 table->WatermarkRow[0][i].MaxUclk =
1520                         cpu_to_le16((uint16_t)
1521                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1522                         1000));
1523                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1524                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1525         }
1526
1527         return 0;
1528 }
1529
1530 static int
1531 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1532                                           dm_pp_wm_sets_with_clock_ranges_soc15
1533                                           *clock_ranges)
1534 {
1535         int ret = 0;
1536         struct smu_table *watermarks = &smu->smu_table.tables[TABLE_WATERMARKS];
1537         Watermarks_t *table = watermarks->cpu_addr;
1538
1539         if (!smu->disable_watermark &&
1540             smu_feature_is_enabled(smu, FEATURE_DPM_DCEFCLK_BIT) &&
1541             smu_feature_is_enabled(smu, FEATURE_DPM_SOCCLK_BIT)) {
1542                 smu_v11_0_set_watermarks_table(smu, table, clock_ranges);
1543                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1544                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1545         }
1546
1547         return ret;
1548 }
1549
1550 static int smu_v11_0_get_clock_ranges(struct smu_context *smu,
1551                                       uint32_t *clock,
1552                                       PPCLK_e clock_select,
1553                                       bool max)
1554 {
1555         int ret;
1556         *clock = 0;
1557         if (max) {
1558                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
1559                                             (clock_select << 16));
1560                 if (ret) {
1561                         pr_err("[GetClockRanges] Failed to get max clock from SMC!\n");
1562                         return ret;
1563                 }
1564                 smu_read_smc_arg(smu, clock);
1565         } else {
1566                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq,
1567                                             (clock_select << 16));
1568                 if (ret) {
1569                         pr_err("[GetClockRanges] Failed to get min clock from SMC!\n");
1570                         return ret;
1571                 }
1572                 smu_read_smc_arg(smu, clock);
1573         }
1574
1575         return 0;
1576 }
1577
1578 static uint32_t smu_v11_0_dpm_get_sclk(struct smu_context *smu, bool low)
1579 {
1580         uint32_t gfx_clk;
1581         int ret;
1582
1583         if (!smu_feature_is_enabled(smu, FEATURE_DPM_GFXCLK_BIT)) {
1584                 pr_err("[GetSclks]: gfxclk dpm not enabled!\n");
1585                 return -EPERM;
1586         }
1587
1588         if (low) {
1589                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, PPCLK_GFXCLK, false);
1590                 if (ret) {
1591                         pr_err("[GetSclks]: fail to get min PPCLK_GFXCLK\n");
1592                         return ret;
1593                 }
1594         } else {
1595                 ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, PPCLK_GFXCLK, true);
1596                 if (ret) {
1597                         pr_err("[GetSclks]: fail to get max PPCLK_GFXCLK\n");
1598                         return ret;
1599                 }
1600         }
1601
1602         return (gfx_clk * 100);
1603 }
1604
1605 static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low)
1606 {
1607         uint32_t mem_clk;
1608         int ret;
1609
1610         if (!smu_feature_is_enabled(smu, FEATURE_DPM_UCLK_BIT)) {
1611                 pr_err("[GetMclks]: memclk dpm not enabled!\n");
1612                 return -EPERM;
1613         }
1614
1615         if (low) {
1616                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, PPCLK_UCLK, false);
1617                 if (ret) {
1618                         pr_err("[GetMclks]: fail to get min PPCLK_UCLK\n");
1619                         return ret;
1620                 }
1621         } else {
1622                 ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, PPCLK_GFXCLK, true);
1623                 if (ret) {
1624                         pr_err("[GetMclks]: fail to get max PPCLK_UCLK\n");
1625                         return ret;
1626                 }
1627         }
1628
1629         return (mem_clk * 100);
1630 }
1631
1632 static int smu_v11_0_set_od8_default_settings(struct smu_context *smu,
1633                                               bool initialize)
1634 {
1635         struct smu_table_context *table_context = &smu->smu_table;
1636         int ret;
1637
1638         /**
1639          * TODO: Enable overdrive for navi10, that replies on smc/pptable
1640          * support.
1641          */
1642         if (smu->adev->asic_type == CHIP_NAVI10)
1643                 return 0;
1644
1645         if (initialize) {
1646                 if (table_context->overdrive_table)
1647                         return -EINVAL;
1648
1649                 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1650
1651                 if (!table_context->overdrive_table)
1652                         return -ENOMEM;
1653
1654                 ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
1655                 if (ret) {
1656                         pr_err("Failed to export over drive table!\n");
1657                         return ret;
1658                 }
1659
1660                 smu_set_default_od8_settings(smu);
1661         }
1662
1663         ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
1664         if (ret) {
1665                 pr_err("Failed to import over drive table!\n");
1666                 return ret;
1667         }
1668
1669         return 0;
1670 }
1671
1672 static int smu_v11_0_update_od8_settings(struct smu_context *smu,
1673                                         uint32_t index,
1674                                         uint32_t value)
1675 {
1676         struct smu_table_context *table_context = &smu->smu_table;
1677         int ret;
1678
1679         ret = smu_update_table(smu, TABLE_OVERDRIVE,
1680                                table_context->overdrive_table, false);
1681         if (ret) {
1682                 pr_err("Failed to export over drive table!\n");
1683                 return ret;
1684         }
1685
1686         smu_update_specified_od8_value(smu, index, value);
1687
1688         ret = smu_update_table(smu, TABLE_OVERDRIVE,
1689                                table_context->overdrive_table, true);
1690         if (ret) {
1691                 pr_err("Failed to import over drive table!\n");
1692                 return ret;
1693         }
1694
1695         return 0;
1696 }
1697
1698 static int smu_v11_0_get_current_rpm(struct smu_context *smu,
1699                                      uint32_t *current_rpm)
1700 {
1701         int ret;
1702
1703         ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
1704
1705         if (ret) {
1706                 pr_err("Attempt to get current RPM from SMC Failed!\n");
1707                 return ret;
1708         }
1709
1710         smu_read_smc_arg(smu, current_rpm);
1711
1712         return 0;
1713 }
1714
1715 static uint32_t
1716 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1717 {
1718         if (!smu_feature_is_enabled(smu, FEATURE_FAN_CONTROL_BIT))
1719                 return AMD_FAN_CTRL_MANUAL;
1720         else
1721                 return AMD_FAN_CTRL_AUTO;
1722 }
1723
1724 static int
1725 smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
1726                                            uint32_t *speed)
1727 {
1728         int ret = 0;
1729         uint32_t percent = 0;
1730         uint32_t current_rpm;
1731         PPTable_t *pptable = smu->smu_table.driver_pptable;
1732
1733         ret = smu_v11_0_get_current_rpm(smu, &current_rpm);
1734         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1735         *speed = percent > 100 ? 100 : percent;
1736
1737         return ret;
1738 }
1739
1740 static int
1741 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1742 {
1743         int ret = 0;
1744
1745         if (smu_feature_is_supported(smu, FEATURE_FAN_CONTROL_BIT))
1746                 return 0;
1747
1748         ret = smu_feature_set_enabled(smu, FEATURE_FAN_CONTROL_BIT, start);
1749         if (ret)
1750                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1751                        __func__, (start ? "Start" : "Stop"));
1752
1753         return ret;
1754 }
1755
1756 static int
1757 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1758 {
1759         struct amdgpu_device *adev = smu->adev;
1760
1761         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1762                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1763                                    CG_FDO_CTRL2, TMIN, 0));
1764         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1765                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1766                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1767
1768         return 0;
1769 }
1770
1771 static int
1772 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1773 {
1774         struct amdgpu_device *adev = smu->adev;
1775         uint32_t duty100;
1776         uint32_t duty;
1777         uint64_t tmp64;
1778         bool stop = 0;
1779
1780         if (speed > 100)
1781                 speed = 100;
1782
1783         if (smu_v11_0_smc_fan_control(smu, stop))
1784                 return -EINVAL;
1785         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1786                                 CG_FDO_CTRL1, FMAX_DUTY100);
1787         if (!duty100)
1788                 return -EINVAL;
1789
1790         tmp64 = (uint64_t)speed * duty100;
1791         do_div(tmp64, 100);
1792         duty = (uint32_t)tmp64;
1793
1794         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1795                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1796                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1797
1798         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1799 }
1800
1801 static int
1802 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1803                                uint32_t mode)
1804 {
1805         int ret = 0;
1806         bool start = 1;
1807         bool stop  = 0;
1808
1809         switch (mode) {
1810         case AMD_FAN_CTRL_NONE:
1811                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1812                 break;
1813         case AMD_FAN_CTRL_MANUAL:
1814                 ret = smu_v11_0_smc_fan_control(smu, stop);
1815                 break;
1816         case AMD_FAN_CTRL_AUTO:
1817                 ret = smu_v11_0_smc_fan_control(smu, start);
1818                 break;
1819         default:
1820                 break;
1821         }
1822
1823         if (ret) {
1824                 pr_err("[%s]Set fan control mode failed!", __func__);
1825                 return -EINVAL;
1826         }
1827
1828         return ret;
1829 }
1830
1831 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1832                                        uint32_t speed)
1833 {
1834         struct amdgpu_device *adev = smu->adev;
1835         int ret;
1836         uint32_t tach_period, crystal_clock_freq;
1837         bool stop = 0;
1838
1839         if (!speed)
1840                 return -EINVAL;
1841
1842         mutex_lock(&(smu->mutex));
1843         ret = smu_v11_0_smc_fan_control(smu, stop);
1844         if (ret)
1845                 goto set_fan_speed_rpm_failed;
1846
1847         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1848         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1849         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1850                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1851                                    CG_TACH_CTRL, TARGET_PERIOD,
1852                                    tach_period));
1853
1854         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1855
1856 set_fan_speed_rpm_failed:
1857         mutex_unlock(&(smu->mutex));
1858         return ret;
1859 }
1860
1861 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1862                                      uint32_t pstate)
1863 {
1864         int ret = 0;
1865         mutex_lock(&(smu->mutex));
1866         ret = smu_send_smc_msg_with_param(smu,
1867                                           SMU_MSG_SetXgmiMode,
1868                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1869         mutex_unlock(&(smu->mutex));
1870         return ret;
1871 }
1872
1873 static const struct smu_funcs smu_v11_0_funcs = {
1874         .init_microcode = smu_v11_0_init_microcode,
1875         .load_microcode = smu_v11_0_load_microcode,
1876         .check_fw_status = smu_v11_0_check_fw_status,
1877         .check_fw_version = smu_v11_0_check_fw_version,
1878         .send_smc_msg = smu_v11_0_send_msg,
1879         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1880         .read_smc_arg = smu_v11_0_read_arg,
1881         .setup_pptable = smu_v11_0_setup_pptable,
1882         .init_smc_tables = smu_v11_0_init_smc_tables,
1883         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1884         .init_power = smu_v11_0_init_power,
1885         .fini_power = smu_v11_0_fini_power,
1886         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1887         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1888         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1889         .check_pptable = smu_v11_0_check_pptable,
1890         .parse_pptable = smu_v11_0_parse_pptable,
1891         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1892         .write_pptable = smu_v11_0_write_pptable,
1893         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1894         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1895         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1896         .init_display = smu_v11_0_init_display,
1897         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1898         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1899         .system_features_control = smu_v11_0_system_features_control,
1900         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1901         .notify_display_change = smu_v11_0_notify_display_change,
1902         .get_power_limit = smu_v11_0_get_power_limit,
1903         .set_power_limit = smu_v11_0_set_power_limit,
1904         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1905         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1906         .start_thermal_control = smu_v11_0_start_thermal_control,
1907         .read_sensor = smu_v11_0_read_sensor,
1908         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1909         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1910         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1911         .get_sclk = smu_v11_0_dpm_get_sclk,
1912         .get_mclk = smu_v11_0_dpm_get_mclk,
1913         .set_od8_default_settings = smu_v11_0_set_od8_default_settings,
1914         .update_od8_settings = smu_v11_0_update_od8_settings,
1915         .get_current_rpm = smu_v11_0_get_current_rpm,
1916         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1917         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1918         .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
1919         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1920         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1921         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1922 };
1923
1924 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1925 {
1926         struct amdgpu_device *adev = smu->adev;
1927
1928         smu->funcs = &smu_v11_0_funcs;
1929         switch (adev->asic_type) {
1930         case CHIP_VEGA20:
1931                 vega20_set_ppt_funcs(smu);
1932                 break;
1933         case CHIP_NAVI10:
1934                 navi10_set_ppt_funcs(smu);
1935                 break;
1936         default:
1937                 pr_warn("Unknown asic for smu11\n");
1938         }
1939 }