drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #define SMU_11_0_PARTIAL_PPTABLE
  28
  29 #include "pp_debug.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_smu.h"
  32 #include "smu_internal.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "smu_v11_0.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amd_pcie.h"
  40 #include "amdgpu_ras.h"
  41
  42 #include "asic_reg/thm/thm_11_0_2_offset.h"
  43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_11_0_offset.h"
  45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  46 #include "asic_reg/nbio/nbio_7_4_offset.h"
  47 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  48 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  49 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  50
  51 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  52 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  53 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  54 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  55 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  56
  57 #define SMU11_VOLTAGE_SCALE 4
  58
  59 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  60                                               uint16_t msg)
  61 {
  62         struct amdgpu_device *adev = smu->adev;
  63         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  64         return 0;
  65 }
  66
  67 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  68 {
  69         struct amdgpu_device *adev = smu->adev;
  70
  71         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  72         return 0;
  73 }
  74
  75 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  76 {
  77         struct amdgpu_device *adev = smu->adev;
  78         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  79
  80         for (i = 0; i < timeout; i++) {
  81                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  82                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  83                         return cur_value == 0x1 ? 0 : -EIO;
  84
  85                 udelay(1);
  86         }
  87
  88         /* timeout means wrong logic */
  89         return -ETIME;
  90 }
  91
  92 int
  93 smu_v11_0_send_msg_with_param(struct smu_context *smu,
  94                               enum smu_message_type msg,
  95                               uint32_t param)
  96 {
  97         struct amdgpu_device *adev = smu->adev;
  98         int ret = 0, index = 0;
  99
 100         index = smu_msg_get_index(smu, msg);
 101         if (index < 0)
 102                 return index;
 103
 104         ret = smu_v11_0_wait_for_response(smu);
 105         if (ret) {
 106                 pr_err("Msg issuing pre-check failed and "
 107                        "SMU may be not in the right state!\n");
 108                 return ret;
 109         }
 110
 111         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 112
 113         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 114
 115         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 116
 117         ret = smu_v11_0_wait_for_response(smu);
 118         if (ret)
 119                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 120                        smu_get_message_name(smu, msg), index, param, ret);
 121
 122         return ret;
 123 }
 124
 125 int smu_v11_0_init_microcode(struct smu_context *smu)
 126 {
 127         struct amdgpu_device *adev = smu->adev;
 128         const char *chip_name;
 129         char fw_name[30];
 130         int err = 0;
 131         const struct smc_firmware_header_v1_0 *hdr;
 132         const struct common_firmware_header *header;
 133         struct amdgpu_firmware_info *ucode = NULL;
 134
 135         switch (adev->asic_type) {
 136         case CHIP_VEGA20:
 137                 chip_name = "vega20";
 138                 break;
 139         case CHIP_ARCTURUS:
 140                 chip_name = "arcturus";
 141                 break;
 142         case CHIP_NAVI10:
 143                 chip_name = "navi10";
 144                 break;
 145         case CHIP_NAVI14:
 146                 chip_name = "navi14";
 147                 break;
 148         case CHIP_NAVI12:
 149                 chip_name = "navi12";
 150                 break;
 151         default:
 152                 BUG();
 153         }
 154
 155         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 156
 157         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 158         if (err)
 159                 goto out;
 160         err = amdgpu_ucode_validate(adev->pm.fw);
 161         if (err)
 162                 goto out;
 163
 164         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 165         amdgpu_ucode_print_smc_hdr(&hdr->header);
 166         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 167
 168         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 169                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 170                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 171                 ucode->fw = adev->pm.fw;
 172                 header = (const struct common_firmware_header *)ucode->fw->data;
 173                 adev->firmware.fw_size +=
 174                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 175         }
 176
 177 out:
 178         if (err) {
 179                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 180                           fw_name);
 181                 release_firmware(adev->pm.fw);
 182                 adev->pm.fw = NULL;
 183         }
 184         return err;
 185 }
 186
 187 int smu_v11_0_load_microcode(struct smu_context *smu)
 188 {
 189         struct amdgpu_device *adev = smu->adev;
 190         const uint32_t *src;
 191         const struct smc_firmware_header_v1_0 *hdr;
 192         uint32_t addr_start = MP1_SRAM;
 193         uint32_t i;
 194         uint32_t mp1_fw_flags;
 195
 196         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 197         src = (const uint32_t *)(adev->pm.fw->data +
 198                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 199
 200         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 201                 WREG32_PCIE(addr_start, src[i]);
 202                 addr_start += 4;
 203         }
 204
 205         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 206                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 207         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 208                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 209
 210         for (i = 0; i < adev->usec_timeout; i++) {
 211                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 212                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 213                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 214                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 215                         break;
 216                 udelay(1);
 217         }
 218
 219         if (i == adev->usec_timeout)
 220                 return -ETIME;
 221
 222         return 0;
 223 }
 224
 225 int smu_v11_0_check_fw_status(struct smu_context *smu)
 226 {
 227         struct amdgpu_device *adev = smu->adev;
 228         uint32_t mp1_fw_flags;
 229
 230         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 231                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 232
 233         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 234             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 235                 return 0;
 236
 237         return -EIO;
 238 }
 239
 240 int smu_v11_0_check_fw_version(struct smu_context *smu)
 241 {
 242         uint32_t if_version = 0xff, smu_version = 0xff;
 243         uint16_t smu_major;
 244         uint8_t smu_minor, smu_debug;
 245         int ret = 0;
 246
 247         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 248         if (ret)
 249                 return ret;
 250
 251         smu_major = (smu_version >> 16) & 0xffff;
 252         smu_minor = (smu_version >> 8) & 0xff;
 253         smu_debug = (smu_version >> 0) & 0xff;
 254
 255         switch (smu->adev->asic_type) {
 256         case CHIP_VEGA20:
 257                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
 258                 break;
 259         case CHIP_ARCTURUS:
 260                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 261                 break;
 262         case CHIP_NAVI10:
 263                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 264                 break;
 265         case CHIP_NAVI14:
 266                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 267                 break;
 268         default:
 269                 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
 270                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
 271                 break;
 272         }
 273
 274         /*
 275          * 1. if_version mismatch is not critical as our fw is designed
 276          * to be backward compatible.
 277          * 2. New fw usually brings some optimizations. But that's visible
 278          * only on the paired driver.
 279          * Considering above, we just leave user a warning message instead
 280          * of halt driver loading.
 281          */
 282         if (if_version != smu->smc_if_version) {
 283                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 284                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 285                         smu->smc_if_version, if_version,
 286                         smu_version, smu_major, smu_minor, smu_debug);
 287                 pr_warn("SMU driver if version not matched\n");
 288         }
 289
 290         return ret;
 291 }
 292
 293 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 294 {
 295         struct amdgpu_device *adev = smu->adev;
 296         uint32_t ppt_offset_bytes;
 297         const struct smc_firmware_header_v2_0 *v2;
 298
 299         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 300
 301         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 302         *size = le32_to_cpu(v2->ppt_size_bytes);
 303         *table = (uint8_t *)v2 + ppt_offset_bytes;
 304
 305         return 0;
 306 }
 307
 308 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 309                                       uint32_t *size, uint32_t pptable_id)
 310 {
 311         struct amdgpu_device *adev = smu->adev;
 312         const struct smc_firmware_header_v2_1 *v2_1;
 313         struct smc_soft_pptable_entry *entries;
 314         uint32_t pptable_count = 0;
 315         int i = 0;
 316
 317         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 318         entries = (struct smc_soft_pptable_entry *)
 319                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 320         pptable_count = le32_to_cpu(v2_1->pptable_count);
 321         for (i = 0; i < pptable_count; i++) {
 322                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 323                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 324                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 325                         break;
 326                 }
 327         }
 328
 329         if (i == pptable_count)
 330                 return -EINVAL;
 331
 332         return 0;
 333 }
 334
 335 int smu_v11_0_setup_pptable(struct smu_context *smu)
 336 {
 337         struct amdgpu_device *adev = smu->adev;
 338         const struct smc_firmware_header_v1_0 *hdr;
 339         int ret, index;
 340         uint32_t size = 0;
 341         uint16_t atom_table_size;
 342         uint8_t frev, crev;
 343         void *table;
 344         uint16_t version_major, version_minor;
 345
 346         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 347         version_major = le16_to_cpu(hdr->header.header_version_major);
 348         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 349         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 350                 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 351                 switch (version_minor) {
 352                 case 0:
 353                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 354                         break;
 355                 case 1:
 356                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 357                                                          smu->smu_table.boot_values.pp_table_id);
 358                         break;
 359                 default:
 360                         ret = -EINVAL;
 361                         break;
 362                 }
 363                 if (ret)
 364                         return ret;
 365
 366         } else {
 367                 pr_info("use vbios provided pptable\n");
 368                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 369                                                     powerplayinfo);
 370
 371                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 372                                               (uint8_t **)&table);
 373                 if (ret)
 374                         return ret;
 375                 size = atom_table_size;
 376         }
 377
 378         if (!smu->smu_table.power_play_table)
 379                 smu->smu_table.power_play_table = table;
 380         if (!smu->smu_table.power_play_table_size)
 381                 smu->smu_table.power_play_table_size = size;
 382
 383         return 0;
 384 }
 385
 386 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 387 {
 388         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 389
 390         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 391                 return -EINVAL;
 392
 393         return smu_alloc_dpm_context(smu);
 394 }
 395
 396 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 397 {
 398         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 399
 400         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 401                 return -EINVAL;
 402
 403         kfree(smu_dpm->dpm_context);
 404         kfree(smu_dpm->golden_dpm_context);
 405         kfree(smu_dpm->dpm_current_power_state);
 406         kfree(smu_dpm->dpm_request_power_state);
 407         smu_dpm->dpm_context = NULL;
 408         smu_dpm->golden_dpm_context = NULL;
 409         smu_dpm->dpm_context_size = 0;
 410         smu_dpm->dpm_current_power_state = NULL;
 411         smu_dpm->dpm_request_power_state = NULL;
 412
 413         return 0;
 414 }
 415
 416 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 417 {
 418         struct smu_table_context *smu_table = &smu->smu_table;
 419         struct smu_table *tables = NULL;
 420         int ret = 0;
 421
 422         if (smu_table->tables)
 423                 return -EINVAL;
 424
 425         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 426                          GFP_KERNEL);
 427         if (!tables)
 428                 return -ENOMEM;
 429
 430         smu_table->tables = tables;
 431
 432         ret = smu_tables_init(smu, tables);
 433         if (ret)
 434                 return ret;
 435
 436         ret = smu_v11_0_init_dpm_context(smu);
 437         if (ret)
 438                 return ret;
 439
 440         return 0;
 441 }
 442
 443 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 444 {
 445         struct smu_table_context *smu_table = &smu->smu_table;
 446         int ret = 0;
 447
 448         if (!smu_table->tables)
 449                 return -EINVAL;
 450
 451         kfree(smu_table->tables);
 452         kfree(smu_table->metrics_table);
 453         kfree(smu_table->watermarks_table);
 454         smu_table->tables = NULL;
 455         smu_table->metrics_table = NULL;
 456         smu_table->watermarks_table = NULL;
 457         smu_table->metrics_time = 0;
 458
 459         ret = smu_v11_0_fini_dpm_context(smu);
 460         if (ret)
 461                 return ret;
 462         return 0;
 463 }
 464
 465 int smu_v11_0_init_power(struct smu_context *smu)
 466 {
 467         struct smu_power_context *smu_power = &smu->smu_power;
 468
 469         if (!smu->pm_enabled)
 470                 return 0;
 471         if (smu_power->power_context || smu_power->power_context_size != 0)
 472                 return -EINVAL;
 473
 474         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 475                                            GFP_KERNEL);
 476         if (!smu_power->power_context)
 477                 return -ENOMEM;
 478         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 479
 480         return 0;
 481 }
 482
 483 int smu_v11_0_fini_power(struct smu_context *smu)
 484 {
 485         struct smu_power_context *smu_power = &smu->smu_power;
 486
 487         if (!smu->pm_enabled)
 488                 return 0;
 489         if (!smu_power->power_context || smu_power->power_context_size == 0)
 490                 return -EINVAL;
 491
 492         kfree(smu_power->power_context);
 493         smu_power->power_context = NULL;
 494         smu_power->power_context_size = 0;
 495
 496         return 0;
 497 }
 498
 499 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 500 {
 501         int ret, index;
 502         uint16_t size;
 503         uint8_t frev, crev;
 504         struct atom_common_table_header *header;
 505         struct atom_firmware_info_v3_3 *v_3_3;
 506         struct atom_firmware_info_v3_1 *v_3_1;
 507
 508         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 509                                             firmwareinfo);
 510
 511         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 512                                       (uint8_t **)&header);
 513         if (ret)
 514                 return ret;
 515
 516         if (header->format_revision != 3) {
 517                 pr_err("unknown atom_firmware_info version! for smu11\n");
 518                 return -EINVAL;
 519         }
 520
 521         switch (header->content_revision) {
 522         case 0:
 523         case 1:
 524         case 2:
 525                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 526                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 527                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 528                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 529                 smu->smu_table.boot_values.socclk = 0;
 530                 smu->smu_table.boot_values.dcefclk = 0;
 531                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 532                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 533                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 534                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 535                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 536                 smu->smu_table.boot_values.pp_table_id = 0;
 537                 break;
 538         case 3:
 539         default:
 540                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 541                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 542                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 543                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 544                 smu->smu_table.boot_values.socclk = 0;
 545                 smu->smu_table.boot_values.dcefclk = 0;
 546                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 547                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 548                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 549                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 550                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 551                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 552         }
 553
 554         smu->smu_table.boot_values.format_revision = header->format_revision;
 555         smu->smu_table.boot_values.content_revision = header->content_revision;
 556
 557         return 0;
 558 }
 559
 560 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 561 {
 562         int ret, index;
 563         struct amdgpu_device *adev = smu->adev;
 564         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 565         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 566
 567         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 568         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 569         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 570                                             getsmuclockinfo);
 571
 572         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 573                                         (uint32_t *)&input);
 574         if (ret)
 575                 return -EINVAL;
 576
 577         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 578         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 579
 580         memset(&input, 0, sizeof(input));
 581         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 582         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 583         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 584                                             getsmuclockinfo);
 585
 586         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 587                                         (uint32_t *)&input);
 588         if (ret)
 589                 return -EINVAL;
 590
 591         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 592         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 593
 594         memset(&input, 0, sizeof(input));
 595         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 596         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 597         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 598                                             getsmuclockinfo);
 599
 600         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 601                                         (uint32_t *)&input);
 602         if (ret)
 603                 return -EINVAL;
 604
 605         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 606         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 607
 608         memset(&input, 0, sizeof(input));
 609         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 610         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 611         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 612                                             getsmuclockinfo);
 613
 614         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 615                                         (uint32_t *)&input);
 616         if (ret)
 617                 return -EINVAL;
 618
 619         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 620         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 621
 622         memset(&input, 0, sizeof(input));
 623         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 624         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 625         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 626                                             getsmuclockinfo);
 627
 628         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 629                                         (uint32_t *)&input);
 630         if (ret)
 631                 return -EINVAL;
 632
 633         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 634         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 635
 636         if ((smu->smu_table.boot_values.format_revision == 3) &&
 637             (smu->smu_table.boot_values.content_revision >= 2)) {
 638                 memset(&input, 0, sizeof(input));
 639                 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
 640                 input.syspll_id = SMU11_SYSPLL1_2_ID;
 641                 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 642                 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 643                                                     getsmuclockinfo);
 644
 645                 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 646                                                 (uint32_t *)&input);
 647                 if (ret)
 648                         return -EINVAL;
 649
 650                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 651                 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 652         }
 653
 654         return 0;
 655 }
 656
 657 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 658 {
 659         struct smu_table_context *smu_table = &smu->smu_table;
 660         struct smu_table *memory_pool = &smu_table->memory_pool;
 661         int ret = 0;
 662         uint64_t address;
 663         uint32_t address_low, address_high;
 664
 665         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 666                 return ret;
 667
 668         address = (uintptr_t)memory_pool->cpu_addr;
 669         address_high = (uint32_t)upper_32_bits(address);
 670         address_low  = (uint32_t)lower_32_bits(address);
 671
 672         ret = smu_send_smc_msg_with_param(smu,
 673                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 674                                           address_high);
 675         if (ret)
 676                 return ret;
 677         ret = smu_send_smc_msg_with_param(smu,
 678                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 679                                           address_low);
 680         if (ret)
 681                 return ret;
 682
 683         address = memory_pool->mc_address;
 684         address_high = (uint32_t)upper_32_bits(address);
 685         address_low  = (uint32_t)lower_32_bits(address);
 686
 687         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 688                                           address_high);
 689         if (ret)
 690                 return ret;
 691         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 692                                           address_low);
 693         if (ret)
 694                 return ret;
 695         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 696                                           (uint32_t)memory_pool->size);
 697         if (ret)
 698                 return ret;
 699
 700         return ret;
 701 }
 702
 703 int smu_v11_0_check_pptable(struct smu_context *smu)
 704 {
 705         int ret;
 706
 707         ret = smu_check_powerplay_table(smu);
 708         return ret;
 709 }
 710
 711 int smu_v11_0_parse_pptable(struct smu_context *smu)
 712 {
 713         int ret;
 714
 715         struct smu_table_context *table_context = &smu->smu_table;
 716         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 717
 718         if (table_context->driver_pptable)
 719                 return -EINVAL;
 720
 721         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 722
 723         if (!table_context->driver_pptable)
 724                 return -ENOMEM;
 725
 726         ret = smu_store_powerplay_table(smu);
 727         if (ret)
 728                 return -EINVAL;
 729
 730         ret = smu_append_powerplay_table(smu);
 731
 732         return ret;
 733 }
 734
 735 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 736 {
 737         int ret;
 738
 739         ret = smu_set_default_dpm_table(smu);
 740
 741         return ret;
 742 }
 743
 744 int smu_v11_0_write_pptable(struct smu_context *smu)
 745 {
 746         struct smu_table_context *table_context = &smu->smu_table;
 747         int ret = 0;
 748
 749         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 750                                table_context->driver_pptable, true);
 751
 752         return ret;
 753 }
 754
 755 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 756 {
 757         int ret;
 758
 759         ret = smu_send_smc_msg_with_param(smu,
 760                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 761         if (ret)
 762                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 763
 764         return ret;
 765 }
 766
 767 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 768 {
 769         struct smu_table_context *table_context = &smu->smu_table;
 770
 771         if (!smu->pm_enabled)
 772                 return 0;
 773         if (!table_context)
 774                 return -EINVAL;
 775
 776         return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
 777 }
 778
 779 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 780 {
 781         struct smu_table *driver_table = &smu->smu_table.driver_table;
 782         int ret = 0;
 783
 784         if (driver_table->mc_address) {
 785                 ret = smu_send_smc_msg_with_param(smu,
 786                                 SMU_MSG_SetDriverDramAddrHigh,
 787                                 upper_32_bits(driver_table->mc_address));
 788                 if (!ret)
 789                         ret = smu_send_smc_msg_with_param(smu,
 790                                 SMU_MSG_SetDriverDramAddrLow,
 791                                 lower_32_bits(driver_table->mc_address));
 792         }
 793
 794         return ret;
 795 }
 796
 797 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 798 {
 799         int ret = 0;
 800         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 801
 802         if (tool_table->mc_address) {
 803                 ret = smu_send_smc_msg_with_param(smu,
 804                                 SMU_MSG_SetToolsDramAddrHigh,
 805                                 upper_32_bits(tool_table->mc_address));
 806                 if (!ret)
 807                         ret = smu_send_smc_msg_with_param(smu,
 808                                 SMU_MSG_SetToolsDramAddrLow,
 809                                 lower_32_bits(tool_table->mc_address));
 810         }
 811
 812         return ret;
 813 }
 814
 815 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 816 {
 817         int ret = 0;
 818
 819         if (!smu->pm_enabled)
 820                 return ret;
 821
 822         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 823         return ret;
 824 }
 825
 826
 827 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 828 {
 829         struct smu_feature *feature = &smu->smu_feature;
 830         int ret = 0;
 831         uint32_t feature_mask[2];
 832
 833         mutex_lock(&feature->mutex);
 834         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 835                 goto failed;
 836
 837         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 838
 839         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 840                                           feature_mask[1]);
 841         if (ret)
 842                 goto failed;
 843
 844         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 845                                           feature_mask[0]);
 846         if (ret)
 847                 goto failed;
 848
 849 failed:
 850         mutex_unlock(&feature->mutex);
 851         return ret;
 852 }
 853
 854 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 855                                       uint32_t *feature_mask, uint32_t num)
 856 {
 857         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 858         struct smu_feature *feature = &smu->smu_feature;
 859         int ret = 0;
 860
 861         if (!feature_mask || num < 2)
 862                 return -EINVAL;
 863
 864         if (bitmap_empty(feature->enabled, feature->feature_num)) {
 865                 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 866                 if (ret)
 867                         return ret;
 868                 ret = smu_read_smc_arg(smu, &feature_mask_high);
 869                 if (ret)
 870                         return ret;
 871
 872                 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 873                 if (ret)
 874                         return ret;
 875                 ret = smu_read_smc_arg(smu, &feature_mask_low);
 876                 if (ret)
 877                         return ret;
 878
 879                 feature_mask[0] = feature_mask_low;
 880                 feature_mask[1] = feature_mask_high;
 881         } else {
 882                 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
 883                              feature->feature_num);
 884         }
 885
 886         return ret;
 887 }
 888
 889 int smu_v11_0_system_features_control(struct smu_context *smu,
 890                                              bool en)
 891 {
 892         struct smu_feature *feature = &smu->smu_feature;
 893         uint32_t feature_mask[2];
 894         int ret = 0;
 895
 896         ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 897                                      SMU_MSG_DisableAllSmuFeatures));
 898         if (ret)
 899                 return ret;
 900
 901         if (en) {
 902                 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 903                 if (ret)
 904                         return ret;
 905
 906                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 907                             feature->feature_num);
 908                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 909                             feature->feature_num);
 910         } else {
 911                 bitmap_zero(feature->enabled, feature->feature_num);
 912                 bitmap_zero(feature->supported, feature->feature_num);
 913         }
 914
 915         return ret;
 916 }
 917
 918 int smu_v11_0_notify_display_change(struct smu_context *smu)
 919 {
 920         int ret = 0;
 921
 922         if (!smu->pm_enabled)
 923                 return ret;
 924         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 925             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 926                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 927
 928         return ret;
 929 }
 930
 931 static int
 932 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 933                                     enum smu_clk_type clock_select)
 934 {
 935         int ret = 0;
 936         int clk_id;
 937
 938         if (!smu->pm_enabled)
 939                 return ret;
 940
 941         if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 942             (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
 943                 return 0;
 944
 945         clk_id = smu_clk_get_index(smu, clock_select);
 946         if (clk_id < 0)
 947                 return -EINVAL;
 948
 949         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 950                                           clk_id << 16);
 951         if (ret) {
 952                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 953                 return ret;
 954         }
 955
 956         ret = smu_read_smc_arg(smu, clock);
 957         if (ret)
 958                 return ret;
 959
 960         if (*clock != 0)
 961                 return 0;
 962
 963         /* if DC limit is zero, return AC limit */
 964         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 965                                           clk_id << 16);
 966         if (ret) {
 967                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 968                 return ret;
 969         }
 970
 971         ret = smu_read_smc_arg(smu, clock);
 972
 973         return ret;
 974 }
 975
 976 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 977 {
 978         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 979         int ret = 0;
 980
 981         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 982                                          GFP_KERNEL);
 983         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 984
 985         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 986         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 987         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 988         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 989         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 990         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 991
 992         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 993                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 994                                                           &(max_sustainable_clocks->uclock),
 995                                                           SMU_UCLK);
 996                 if (ret) {
 997                         pr_err("[%s] failed to get max UCLK from SMC!",
 998                                __func__);
 999                         return ret;
1000                 }
1001         }
1002
1003         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1004                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1005                                                           &(max_sustainable_clocks->soc_clock),
1006                                                           SMU_SOCCLK);
1007                 if (ret) {
1008                         pr_err("[%s] failed to get max SOCCLK from SMC!",
1009                                __func__);
1010                         return ret;
1011                 }
1012         }
1013
1014         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1015                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1016                                                           &(max_sustainable_clocks->dcef_clock),
1017                                                           SMU_DCEFCLK);
1018                 if (ret) {
1019                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1020                                __func__);
1021                         return ret;
1022                 }
1023
1024                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1025                                                           &(max_sustainable_clocks->display_clock),
1026                                                           SMU_DISPCLK);
1027                 if (ret) {
1028                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1029                                __func__);
1030                         return ret;
1031                 }
1032                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1033                                                           &(max_sustainable_clocks->phy_clock),
1034                                                           SMU_PHYCLK);
1035                 if (ret) {
1036                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1037                                __func__);
1038                         return ret;
1039                 }
1040                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1041                                                           &(max_sustainable_clocks->pixel_clock),
1042                                                           SMU_PIXCLK);
1043                 if (ret) {
1044                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1045                                __func__);
1046                         return ret;
1047                 }
1048         }
1049
1050         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1051                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1052
1053         return 0;
1054 }
1055
1056 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1057         uint32_t od_limit, max_power_limit;
1058         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1059         struct smu_table_context *table_context = &smu->smu_table;
1060         powerplay_table = table_context->power_play_table;
1061
1062         max_power_limit = smu_get_pptable_power_limit(smu);
1063
1064         if (!max_power_limit) {
1065                 // If we couldn't get the table limit, fall back on first-read value
1066                 if (!smu->default_power_limit)
1067                         smu->default_power_limit = smu->power_limit;
1068                 max_power_limit = smu->default_power_limit;
1069         }
1070
1071         if (smu->od_enabled) {
1072                 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1073
1074                 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1075
1076                 max_power_limit *= (100 + od_limit);
1077                 max_power_limit /= 100;
1078         }
1079
1080         return max_power_limit;
1081 }
1082
1083 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1084 {
1085         int ret = 0;
1086         uint32_t max_power_limit;
1087
1088         max_power_limit = smu_v11_0_get_max_power_limit(smu);
1089
1090         if (n > max_power_limit) {
1091                 pr_err("New power limit (%d) is over the max allowed %d\n",
1092                                 n,
1093                                 max_power_limit);
1094                 return -EINVAL;
1095         }
1096
1097         if (n == 0)
1098                 n = smu->default_power_limit;
1099
1100         if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1101                 pr_err("Setting new power limit is not supported!\n");
1102                 return -EOPNOTSUPP;
1103         }
1104
1105         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1106         if (ret) {
1107                 pr_err("[%s] Set power limit Failed!\n", __func__);
1108                 return ret;
1109         }
1110         smu->power_limit = n;
1111
1112         return 0;
1113 }
1114
1115 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1116                                           enum smu_clk_type clk_id,
1117                                           uint32_t *value)
1118 {
1119         int ret = 0;
1120         uint32_t freq = 0;
1121         int asic_clk_id;
1122
1123         if (clk_id >= SMU_CLK_COUNT || !value)
1124                 return -EINVAL;
1125
1126         asic_clk_id = smu_clk_get_index(smu, clk_id);
1127         if (asic_clk_id < 0)
1128                 return -EINVAL;
1129
1130         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1131         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1132                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1133         else {
1134                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1135                                                   (asic_clk_id << 16));
1136                 if (ret)
1137                         return ret;
1138
1139                 ret = smu_read_smc_arg(smu, &freq);
1140                 if (ret)
1141                         return ret;
1142         }
1143
1144         freq *= 100;
1145         *value = freq;
1146
1147         return ret;
1148 }
1149
1150 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1151                                        struct smu_temperature_range range)
1152 {
1153         struct amdgpu_device *adev = smu->adev;
1154         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1155         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1156         uint32_t val;
1157
1158         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1159                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1160         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1161                         range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1162
1163         if (low > high)
1164                 return -EINVAL;
1165
1166         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1167         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1168         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1169         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1170         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1171         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1172         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1173         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1174
1175         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1176
1177         return 0;
1178 }
1179
1180 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1181 {
1182         struct amdgpu_device *adev = smu->adev;
1183         uint32_t val = 0;
1184
1185         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1186         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1187         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1188
1189         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1190
1191         return 0;
1192 }
1193
1194 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1195 {
1196         int ret = 0;
1197         struct smu_temperature_range range;
1198         struct amdgpu_device *adev = smu->adev;
1199
1200         if (!smu->pm_enabled)
1201                 return ret;
1202
1203         memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1204
1205         ret = smu_get_thermal_temperature_range(smu, &range);
1206         if (ret)
1207                 return ret;
1208
1209         if (smu->smu_table.thermal_controller_type) {
1210                 ret = smu_v11_0_set_thermal_range(smu, range);
1211                 if (ret)
1212                         return ret;
1213
1214                 ret = smu_v11_0_enable_thermal_alert(smu);
1215                 if (ret)
1216                         return ret;
1217
1218                 ret = smu_set_thermal_fan_table(smu);
1219                 if (ret)
1220                         return ret;
1221         }
1222
1223         adev->pm.dpm.thermal.min_temp = range.min;
1224         adev->pm.dpm.thermal.max_temp = range.max;
1225         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1226         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1227         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1228         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1229         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1230         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1231         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1232
1233         return ret;
1234 }
1235
1236 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1237 {
1238         struct amdgpu_device *adev = smu->adev;
1239
1240         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1241
1242         return 0;
1243 }
1244
1245 static uint16_t convert_to_vddc(uint8_t vid)
1246 {
1247         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1248 }
1249
1250 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1251 {
1252         struct amdgpu_device *adev = smu->adev;
1253         uint32_t vdd = 0, val_vid = 0;
1254
1255         if (!value)
1256                 return -EINVAL;
1257         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1258                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1259                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1260
1261         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1262
1263         *value = vdd;
1264
1265         return 0;
1266
1267 }
1268
1269 int smu_v11_0_read_sensor(struct smu_context *smu,
1270                                  enum amd_pp_sensors sensor,
1271                                  void *data, uint32_t *size)
1272 {
1273         int ret = 0;
1274
1275         if(!data || !size)
1276                 return -EINVAL;
1277
1278         switch (sensor) {
1279         case AMDGPU_PP_SENSOR_GFX_MCLK:
1280                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1281                 *size = 4;
1282                 break;
1283         case AMDGPU_PP_SENSOR_GFX_SCLK:
1284                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1285                 *size = 4;
1286                 break;
1287         case AMDGPU_PP_SENSOR_VDDGFX:
1288                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1289                 *size = 4;
1290                 break;
1291         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1292                 *(uint32_t *)data = 0;
1293                 *size = 4;
1294                 break;
1295         default:
1296                 ret = smu_common_read_sensor(smu, sensor, data, size);
1297                 break;
1298         }
1299
1300         if (ret)
1301                 *size = 0;
1302
1303         return ret;
1304 }
1305
1306 int
1307 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1308                                         struct pp_display_clock_request
1309                                         *clock_req)
1310 {
1311         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1312         int ret = 0;
1313         enum smu_clk_type clk_select = 0;
1314         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1315
1316         if (!smu->pm_enabled)
1317                 return -EINVAL;
1318
1319         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1320                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1321                 switch (clk_type) {
1322                 case amd_pp_dcef_clock:
1323                         clk_select = SMU_DCEFCLK;
1324                         break;
1325                 case amd_pp_disp_clock:
1326                         clk_select = SMU_DISPCLK;
1327                         break;
1328                 case amd_pp_pixel_clock:
1329                         clk_select = SMU_PIXCLK;
1330                         break;
1331                 case amd_pp_phy_clock:
1332                         clk_select = SMU_PHYCLK;
1333                         break;
1334                 case amd_pp_mem_clock:
1335                         clk_select = SMU_UCLK;
1336                         break;
1337                 default:
1338                         pr_info("[%s] Invalid Clock Type!", __func__);
1339                         ret = -EINVAL;
1340                         break;
1341                 }
1342
1343                 if (ret)
1344                         goto failed;
1345
1346                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1347                         return 0;
1348
1349                 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1350
1351                 if(clk_select == SMU_UCLK)
1352                         smu->hard_min_uclk_req_from_dal = clk_freq;
1353         }
1354
1355 failed:
1356         return ret;
1357 }
1358
1359 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1360 {
1361         int ret = 0;
1362         struct amdgpu_device *adev = smu->adev;
1363
1364         switch (adev->asic_type) {
1365         case CHIP_VEGA20:
1366                 break;
1367         case CHIP_NAVI10:
1368         case CHIP_NAVI14:
1369         case CHIP_NAVI12:
1370                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1371                         return 0;
1372                 if (enable)
1373                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1374                 else
1375                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1376                 break;
1377         default:
1378                 break;
1379         }
1380
1381         return ret;
1382 }
1383
1384 uint32_t
1385 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1386 {
1387         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1388                 return AMD_FAN_CTRL_MANUAL;
1389         else
1390                 return AMD_FAN_CTRL_AUTO;
1391 }
1392
1393 static int
1394 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1395 {
1396         int ret = 0;
1397
1398         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1399                 return 0;
1400
1401         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1402         if (ret)
1403                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1404                        __func__, (auto_fan_control ? "Start" : "Stop"));
1405
1406         return ret;
1407 }
1408
1409 static int
1410 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1411 {
1412         struct amdgpu_device *adev = smu->adev;
1413
1414         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1415                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1416                                    CG_FDO_CTRL2, TMIN, 0));
1417         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1418                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1419                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1420
1421         return 0;
1422 }
1423
1424 int
1425 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1426 {
1427         struct amdgpu_device *adev = smu->adev;
1428         uint32_t duty100, duty;
1429         uint64_t tmp64;
1430
1431         if (speed > 100)
1432                 speed = 100;
1433
1434         if (smu_v11_0_auto_fan_control(smu, 0))
1435                 return -EINVAL;
1436
1437         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1438                                 CG_FDO_CTRL1, FMAX_DUTY100);
1439         if (!duty100)
1440                 return -EINVAL;
1441
1442         tmp64 = (uint64_t)speed * duty100;
1443         do_div(tmp64, 100);
1444         duty = (uint32_t)tmp64;
1445
1446         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1447                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1448                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1449
1450         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1451 }
1452
1453 int
1454 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1455                                uint32_t mode)
1456 {
1457         int ret = 0;
1458
1459         switch (mode) {
1460         case AMD_FAN_CTRL_NONE:
1461                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1462                 break;
1463         case AMD_FAN_CTRL_MANUAL:
1464                 ret = smu_v11_0_auto_fan_control(smu, 0);
1465                 break;
1466         case AMD_FAN_CTRL_AUTO:
1467                 ret = smu_v11_0_auto_fan_control(smu, 1);
1468                 break;
1469         default:
1470                 break;
1471         }
1472
1473         if (ret) {
1474                 pr_err("[%s]Set fan control mode failed!", __func__);
1475                 return -EINVAL;
1476         }
1477
1478         return ret;
1479 }
1480
1481 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1482                                        uint32_t speed)
1483 {
1484         struct amdgpu_device *adev = smu->adev;
1485         int ret;
1486         uint32_t tach_period, crystal_clock_freq;
1487
1488         if (!speed)
1489                 return -EINVAL;
1490
1491         ret = smu_v11_0_auto_fan_control(smu, 0);
1492         if (ret)
1493                 return ret;
1494
1495         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1496         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1497         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1498                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1499                                    CG_TACH_CTRL, TARGET_PERIOD,
1500                                    tach_period));
1501
1502         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1503
1504         return ret;
1505 }
1506
1507 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1508                                      uint32_t pstate)
1509 {
1510         int ret = 0;
1511         ret = smu_send_smc_msg_with_param(smu,
1512                                           SMU_MSG_SetXgmiMode,
1513                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
1514         return ret;
1515 }
1516
1517 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1518 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1519
1520 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1521                                  struct amdgpu_irq_src *source,
1522                                  struct amdgpu_iv_entry *entry)
1523 {
1524         uint32_t client_id = entry->client_id;
1525         uint32_t src_id = entry->src_id;
1526
1527         if (client_id == SOC15_IH_CLIENTID_THM) {
1528                 switch (src_id) {
1529                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1530                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1531                                 PCI_BUS_NUM(adev->pdev->devfn),
1532                                 PCI_SLOT(adev->pdev->devfn),
1533                                 PCI_FUNC(adev->pdev->devfn));
1534                 break;
1535                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1536                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1537                                 PCI_BUS_NUM(adev->pdev->devfn),
1538                                 PCI_SLOT(adev->pdev->devfn),
1539                                 PCI_FUNC(adev->pdev->devfn));
1540                 break;
1541                 default:
1542                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1543                                 src_id,
1544                                 PCI_BUS_NUM(adev->pdev->devfn),
1545                                 PCI_SLOT(adev->pdev->devfn),
1546                                 PCI_FUNC(adev->pdev->devfn));
1547                 break;
1548
1549                 }
1550         }
1551
1552         return 0;
1553 }
1554
1555 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1556 {
1557         .process = smu_v11_0_irq_process,
1558 };
1559
1560 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1561 {
1562         struct amdgpu_device *adev = smu->adev;
1563         struct amdgpu_irq_src *irq_src = smu->irq_source;
1564         int ret = 0;
1565
1566         /* already register */
1567         if (irq_src)
1568                 return 0;
1569
1570         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1571         if (!irq_src)
1572                 return -ENOMEM;
1573         smu->irq_source = irq_src;
1574
1575         irq_src->funcs = &smu_v11_0_irq_funcs;
1576
1577         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1578                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1579                                 irq_src);
1580         if (ret)
1581                 return ret;
1582
1583         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1584                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1585                                 irq_src);
1586         if (ret)
1587                 return ret;
1588
1589         return ret;
1590 }
1591
1592 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1593                 struct pp_smu_nv_clock_table *max_clocks)
1594 {
1595         struct smu_table_context *table_context = &smu->smu_table;
1596         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1597
1598         if (!max_clocks || !table_context->max_sustainable_clocks)
1599                 return -EINVAL;
1600
1601         sustainable_clocks = table_context->max_sustainable_clocks;
1602
1603         max_clocks->dcfClockInKhz =
1604                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1605         max_clocks->displayClockInKhz =
1606                         (unsigned int) sustainable_clocks->display_clock * 1000;
1607         max_clocks->phyClockInKhz =
1608                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1609         max_clocks->pixelClockInKhz =
1610                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1611         max_clocks->uClockInKhz =
1612                         (unsigned int) sustainable_clocks->uclock * 1000;
1613         max_clocks->socClockInKhz =
1614                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1615         max_clocks->dscClockInKhz = 0;
1616         max_clocks->dppClockInKhz = 0;
1617         max_clocks->fabricClockInKhz = 0;
1618
1619         return 0;
1620 }
1621
1622 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1623 {
1624         int ret = 0;
1625
1626         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1627
1628         return ret;
1629 }
1630
1631 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1632 {
1633         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1634 }
1635
1636 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1637 {
1638         struct amdgpu_device *adev = smu->adev;
1639         struct smu_baco_context *smu_baco = &smu->smu_baco;
1640         uint32_t val;
1641         bool baco_support;
1642
1643         mutex_lock(&smu_baco->mutex);
1644         baco_support = smu_baco->platform_support;
1645         mutex_unlock(&smu_baco->mutex);
1646
1647         if (!baco_support)
1648                 return false;
1649
1650         /* Arcturus does not support this bit mask */
1651         if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1652            !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1653                 return false;
1654
1655         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1656         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1657                 return true;
1658
1659         return false;
1660 }
1661
1662 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1663 {
1664         struct smu_baco_context *smu_baco = &smu->smu_baco;
1665         enum smu_baco_state baco_state;
1666
1667         mutex_lock(&smu_baco->mutex);
1668         baco_state = smu_baco->state;
1669         mutex_unlock(&smu_baco->mutex);
1670
1671         return baco_state;
1672 }
1673
1674 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1675 {
1676
1677         struct smu_baco_context *smu_baco = &smu->smu_baco;
1678         struct amdgpu_device *adev = smu->adev;
1679         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1680         uint32_t bif_doorbell_intr_cntl;
1681         uint32_t data;
1682         int ret = 0;
1683
1684         if (smu_v11_0_baco_get_state(smu) == state)
1685                 return 0;
1686
1687         mutex_lock(&smu_baco->mutex);
1688
1689         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
1690
1691         if (state == SMU_BACO_STATE_ENTER) {
1692                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1693                                                 BIF_DOORBELL_INT_CNTL,
1694                                                 DOORBELL_INTERRUPT_DISABLE, 1);
1695                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1696
1697                 if (!ras || !ras->supported) {
1698                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1699                         data |= 0x80000000;
1700                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1701
1702                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0);
1703                 } else {
1704                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1);
1705                 }
1706         } else {
1707                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1708                 if (ret)
1709                         goto out;
1710
1711                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1712                                                 BIF_DOORBELL_INT_CNTL,
1713                                                 DOORBELL_INTERRUPT_DISABLE, 0);
1714                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1715
1716                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1717                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1718                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1719         }
1720         if (ret)
1721                 goto out;
1722
1723         smu_baco->state = state;
1724 out:
1725         mutex_unlock(&smu_baco->mutex);
1726         return ret;
1727 }
1728
1729 int smu_v11_0_baco_enter(struct smu_context *smu)
1730 {
1731         struct amdgpu_device *adev = smu->adev;
1732         int ret = 0;
1733
1734         /* Arcturus does not need this audio workaround */
1735         if (adev->asic_type != CHIP_ARCTURUS) {
1736                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1737                 if (ret)
1738                         return ret;
1739         }
1740
1741         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1742         if (ret)
1743                 return ret;
1744
1745         msleep(10);
1746
1747         return ret;
1748 }
1749
1750 int smu_v11_0_baco_exit(struct smu_context *smu)
1751 {
1752         int ret = 0;
1753
1754         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1755         if (ret)
1756                 return ret;
1757
1758         return ret;
1759 }
1760
1761 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1762                                                  uint32_t *min, uint32_t *max)
1763 {
1764         int ret = 0, clk_id = 0;
1765         uint32_t param = 0;
1766
1767         clk_id = smu_clk_get_index(smu, clk_type);
1768         if (clk_id < 0) {
1769                 ret = -EINVAL;
1770                 goto failed;
1771         }
1772         param = (clk_id & 0xffff) << 16;
1773
1774         if (max) {
1775                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
1776                 if (ret)
1777                         goto failed;
1778                 ret = smu_read_smc_arg(smu, max);
1779                 if (ret)
1780                         goto failed;
1781         }
1782
1783         if (min) {
1784                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
1785                 if (ret)
1786                         goto failed;
1787                 ret = smu_read_smc_arg(smu, min);
1788                 if (ret)
1789                         goto failed;
1790         }
1791
1792 failed:
1793         return ret;
1794 }
1795
1796 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1797                             uint32_t min, uint32_t max)
1798 {
1799         int ret = 0, clk_id = 0;
1800         uint32_t param;
1801
1802         clk_id = smu_clk_get_index(smu, clk_type);
1803         if (clk_id < 0)
1804                 return clk_id;
1805
1806         if (max > 0) {
1807                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1808                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1809                                                   param);
1810                 if (ret)
1811                         return ret;
1812         }
1813
1814         if (min > 0) {
1815                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1816                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1817                                                   param);
1818                 if (ret)
1819                         return ret;
1820         }
1821
1822         return ret;
1823 }
1824
1825 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1826 {
1827         struct amdgpu_device *adev = smu->adev;
1828         uint32_t pcie_gen = 0, pcie_width = 0;
1829         int ret;
1830
1831         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1832                 pcie_gen = 3;
1833         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1834                 pcie_gen = 2;
1835         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1836                 pcie_gen = 1;
1837         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1838                 pcie_gen = 0;
1839
1840         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1841          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1842          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1843          */
1844         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1845                 pcie_width = 6;
1846         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1847                 pcie_width = 5;
1848         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1849                 pcie_width = 4;
1850         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1851                 pcie_width = 3;
1852         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1853                 pcie_width = 2;
1854         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1855                 pcie_width = 1;
1856
1857         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1858
1859         if (ret)
1860                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1861
1862         return ret;
1863
1864 }
1865
1866 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1867 {
1868         struct smu_table_context *table_context = &smu->smu_table;
1869         int ret = 0;
1870
1871         if (initialize) {
1872                 if (table_context->overdrive_table) {
1873                         return -EINVAL;
1874                 }
1875                 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1876                 if (!table_context->overdrive_table) {
1877                         return -ENOMEM;
1878                 }
1879                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1880                 if (ret) {
1881                         pr_err("Failed to export overdrive table!\n");
1882                         return ret;
1883                 }
1884         }
1885         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1886         if (ret) {
1887                 pr_err("Failed to import overdrive table!\n");
1888                 return ret;
1889         }
1890         return ret;
1891 }
1892
1893 int smu_v11_0_set_performance_level(struct smu_context *smu,
1894                                     enum amd_dpm_forced_level level)
1895 {
1896         int ret = 0;
1897         uint32_t sclk_mask, mclk_mask, soc_mask;
1898
1899         switch (level) {
1900         case AMD_DPM_FORCED_LEVEL_HIGH:
1901                 ret = smu_force_dpm_limit_value(smu, true);
1902                 break;
1903         case AMD_DPM_FORCED_LEVEL_LOW:
1904                 ret = smu_force_dpm_limit_value(smu, false);
1905                 break;
1906         case AMD_DPM_FORCED_LEVEL_AUTO:
1907         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1908                 ret = smu_unforce_dpm_levels(smu);
1909                 break;
1910         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1911         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1912         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1913                 ret = smu_get_profiling_clk_mask(smu, level,
1914                                                  &sclk_mask,
1915                                                  &mclk_mask,
1916                                                  &soc_mask);
1917                 if (ret)
1918                         return ret;
1919                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1920                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1921                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1922                 break;
1923         case AMD_DPM_FORCED_LEVEL_MANUAL:
1924         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1925         default:
1926                 break;
1927         }
1928         return ret;
1929 }
1930