drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #define SMU_11_0_PARTIAL_PPTABLE
  28
  29 #include "pp_debug.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_smu.h"
  32 #include "smu_internal.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "smu_v11_0.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amd_pcie.h"
  40
  41 #include "asic_reg/thm/thm_11_0_2_offset.h"
  42 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  43 #include "asic_reg/mp/mp_11_0_offset.h"
  44 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  45 #include "asic_reg/nbio/nbio_7_4_offset.h"
  46 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  48 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  49
  50 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  51 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  52 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  53 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  54 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  55
  56 #define SMU11_VOLTAGE_SCALE 4
  57
  58 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  59                                               uint16_t msg)
  60 {
  61         struct amdgpu_device *adev = smu->adev;
  62         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  63         return 0;
  64 }
  65
  66 int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  67 {
  68         struct amdgpu_device *adev = smu->adev;
  69
  70         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  71         return 0;
  72 }
  73
  74 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  75 {
  76         struct amdgpu_device *adev = smu->adev;
  77         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  78
  79         for (i = 0; i < timeout; i++) {
  80                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  81                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  82                         break;
  83                 udelay(1);
  84         }
  85
  86         /* timeout means wrong logic */
  87         if (i == timeout)
  88                 return -ETIME;
  89
  90         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  91 }
  92
  93 int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  94 {
  95         struct amdgpu_device *adev = smu->adev;
  96         int ret = 0, index = 0;
  97
  98         index = smu_msg_get_index(smu, msg);
  99         if (index < 0)
 100                 return index;
 101
 102         smu_v11_0_wait_for_response(smu);
 103
 104         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 105
 106         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 107
 108         ret = smu_v11_0_wait_for_response(smu);
 109
 110         if (ret)
 111                 pr_err("failed send message: %10s (%d) response %#x\n",
 112                        smu_get_message_name(smu, msg), index, ret);
 113
 114         return ret;
 115
 116 }
 117
 118 int
 119 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 120                               uint32_t param)
 121 {
 122
 123         struct amdgpu_device *adev = smu->adev;
 124         int ret = 0, index = 0;
 125
 126         index = smu_msg_get_index(smu, msg);
 127         if (index < 0)
 128                 return index;
 129
 130         ret = smu_v11_0_wait_for_response(smu);
 131         if (ret)
 132                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 133                        smu_get_message_name(smu, msg), index, param, ret);
 134
 135         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 136
 137         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 138
 139         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 140
 141         ret = smu_v11_0_wait_for_response(smu);
 142         if (ret)
 143                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 144                        smu_get_message_name(smu, msg), index, param, ret);
 145
 146         return ret;
 147 }
 148
 149 int smu_v11_0_init_microcode(struct smu_context *smu)
 150 {
 151         struct amdgpu_device *adev = smu->adev;
 152         const char *chip_name;
 153         char fw_name[30];
 154         int err = 0;
 155         const struct smc_firmware_header_v1_0 *hdr;
 156         const struct common_firmware_header *header;
 157         struct amdgpu_firmware_info *ucode = NULL;
 158
 159         switch (adev->asic_type) {
 160         case CHIP_VEGA20:
 161                 chip_name = "vega20";
 162                 break;
 163         case CHIP_ARCTURUS:
 164                 chip_name = "arcturus";
 165                 break;
 166         case CHIP_NAVI10:
 167                 chip_name = "navi10";
 168                 break;
 169         case CHIP_NAVI14:
 170                 chip_name = "navi14";
 171                 break;
 172         case CHIP_NAVI12:
 173                 chip_name = "navi12";
 174                 break;
 175         default:
 176                 BUG();
 177         }
 178
 179         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 180
 181         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 182         if (err)
 183                 goto out;
 184         err = amdgpu_ucode_validate(adev->pm.fw);
 185         if (err)
 186                 goto out;
 187
 188         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 189         amdgpu_ucode_print_smc_hdr(&hdr->header);
 190         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 191
 192         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 193                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 194                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 195                 ucode->fw = adev->pm.fw;
 196                 header = (const struct common_firmware_header *)ucode->fw->data;
 197                 adev->firmware.fw_size +=
 198                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 199         }
 200
 201 out:
 202         if (err) {
 203                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 204                           fw_name);
 205                 release_firmware(adev->pm.fw);
 206                 adev->pm.fw = NULL;
 207         }
 208         return err;
 209 }
 210
 211 int smu_v11_0_load_microcode(struct smu_context *smu)
 212 {
 213         struct amdgpu_device *adev = smu->adev;
 214         const uint32_t *src;
 215         const struct smc_firmware_header_v1_0 *hdr;
 216         uint32_t addr_start = MP1_SRAM;
 217         uint32_t i;
 218         uint32_t mp1_fw_flags;
 219
 220         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 221         src = (const uint32_t *)(adev->pm.fw->data +
 222                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 223
 224         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 225                 WREG32_PCIE(addr_start, src[i]);
 226                 addr_start += 4;
 227         }
 228
 229         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 230                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 231         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 232                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 233
 234         for (i = 0; i < adev->usec_timeout; i++) {
 235                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 236                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 237                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 238                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 239                         break;
 240                 udelay(1);
 241         }
 242
 243         if (i == adev->usec_timeout)
 244                 return -ETIME;
 245
 246         return 0;
 247 }
 248
 249 int smu_v11_0_check_fw_status(struct smu_context *smu)
 250 {
 251         struct amdgpu_device *adev = smu->adev;
 252         uint32_t mp1_fw_flags;
 253
 254         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 255                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 256
 257         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 258             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 259                 return 0;
 260
 261         return -EIO;
 262 }
 263
 264 int smu_v11_0_check_fw_version(struct smu_context *smu)
 265 {
 266         uint32_t if_version = 0xff, smu_version = 0xff;
 267         uint16_t smu_major;
 268         uint8_t smu_minor, smu_debug;
 269         int ret = 0;
 270
 271         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 272         if (ret)
 273                 return ret;
 274
 275         smu_major = (smu_version >> 16) & 0xffff;
 276         smu_minor = (smu_version >> 8) & 0xff;
 277         smu_debug = (smu_version >> 0) & 0xff;
 278
 279         switch (smu->adev->asic_type) {
 280         case CHIP_VEGA20:
 281                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
 282                 break;
 283         case CHIP_ARCTURUS:
 284                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 285                 break;
 286         case CHIP_NAVI10:
 287                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 288                 break;
 289         case CHIP_NAVI14:
 290                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 291                 break;
 292         default:
 293                 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
 294                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
 295                 break;
 296         }
 297
 298         /*
 299          * 1. if_version mismatch is not critical as our fw is designed
 300          * to be backward compatible.
 301          * 2. New fw usually brings some optimizations. But that's visible
 302          * only on the paired driver.
 303          * Considering above, we just leave user a warning message instead
 304          * of halt driver loading.
 305          */
 306         if (if_version != smu->smc_if_version) {
 307                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 308                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 309                         smu->smc_if_version, if_version,
 310                         smu_version, smu_major, smu_minor, smu_debug);
 311                 pr_warn("SMU driver if version not matched\n");
 312         }
 313
 314         return ret;
 315 }
 316
 317 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 318 {
 319         struct amdgpu_device *adev = smu->adev;
 320         uint32_t ppt_offset_bytes;
 321         const struct smc_firmware_header_v2_0 *v2;
 322
 323         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 324
 325         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 326         *size = le32_to_cpu(v2->ppt_size_bytes);
 327         *table = (uint8_t *)v2 + ppt_offset_bytes;
 328
 329         return 0;
 330 }
 331
 332 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 333                                       uint32_t *size, uint32_t pptable_id)
 334 {
 335         struct amdgpu_device *adev = smu->adev;
 336         const struct smc_firmware_header_v2_1 *v2_1;
 337         struct smc_soft_pptable_entry *entries;
 338         uint32_t pptable_count = 0;
 339         int i = 0;
 340
 341         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 342         entries = (struct smc_soft_pptable_entry *)
 343                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 344         pptable_count = le32_to_cpu(v2_1->pptable_count);
 345         for (i = 0; i < pptable_count; i++) {
 346                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 347                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 348                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 349                         break;
 350                 }
 351         }
 352
 353         if (i == pptable_count)
 354                 return -EINVAL;
 355
 356         return 0;
 357 }
 358
 359 int smu_v11_0_setup_pptable(struct smu_context *smu)
 360 {
 361         struct amdgpu_device *adev = smu->adev;
 362         const struct smc_firmware_header_v1_0 *hdr;
 363         int ret, index;
 364         uint32_t size = 0;
 365         uint16_t atom_table_size;
 366         uint8_t frev, crev;
 367         void *table;
 368         uint16_t version_major, version_minor;
 369
 370         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 371         version_major = le16_to_cpu(hdr->header.header_version_major);
 372         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 373         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 374                 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 375                 switch (version_minor) {
 376                 case 0:
 377                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 378                         break;
 379                 case 1:
 380                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 381                                                          smu->smu_table.boot_values.pp_table_id);
 382                         break;
 383                 default:
 384                         ret = -EINVAL;
 385                         break;
 386                 }
 387                 if (ret)
 388                         return ret;
 389
 390         } else {
 391                 pr_info("use vbios provided pptable\n");
 392                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 393                                                     powerplayinfo);
 394
 395                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 396                                               (uint8_t **)&table);
 397                 if (ret)
 398                         return ret;
 399                 size = atom_table_size;
 400         }
 401
 402         if (!smu->smu_table.power_play_table)
 403                 smu->smu_table.power_play_table = table;
 404         if (!smu->smu_table.power_play_table_size)
 405                 smu->smu_table.power_play_table_size = size;
 406
 407         return 0;
 408 }
 409
 410 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 411 {
 412         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 413
 414         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 415                 return -EINVAL;
 416
 417         return smu_alloc_dpm_context(smu);
 418 }
 419
 420 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 421 {
 422         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 423
 424         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 425                 return -EINVAL;
 426
 427         kfree(smu_dpm->dpm_context);
 428         kfree(smu_dpm->golden_dpm_context);
 429         kfree(smu_dpm->dpm_current_power_state);
 430         kfree(smu_dpm->dpm_request_power_state);
 431         smu_dpm->dpm_context = NULL;
 432         smu_dpm->golden_dpm_context = NULL;
 433         smu_dpm->dpm_context_size = 0;
 434         smu_dpm->dpm_current_power_state = NULL;
 435         smu_dpm->dpm_request_power_state = NULL;
 436
 437         return 0;
 438 }
 439
 440 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 441 {
 442         struct smu_table_context *smu_table = &smu->smu_table;
 443         struct smu_table *tables = NULL;
 444         int ret = 0;
 445
 446         if (smu_table->tables)
 447                 return -EINVAL;
 448
 449         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 450                          GFP_KERNEL);
 451         if (!tables)
 452                 return -ENOMEM;
 453
 454         smu_table->tables = tables;
 455
 456         ret = smu_tables_init(smu, tables);
 457         if (ret)
 458                 return ret;
 459
 460         ret = smu_v11_0_init_dpm_context(smu);
 461         if (ret)
 462                 return ret;
 463
 464         return 0;
 465 }
 466
 467 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 468 {
 469         struct smu_table_context *smu_table = &smu->smu_table;
 470         int ret = 0;
 471
 472         if (!smu_table->tables)
 473                 return -EINVAL;
 474
 475         kfree(smu_table->tables);
 476         kfree(smu_table->metrics_table);
 477         smu_table->tables = NULL;
 478         smu_table->metrics_table = NULL;
 479         smu_table->metrics_time = 0;
 480
 481         ret = smu_v11_0_fini_dpm_context(smu);
 482         if (ret)
 483                 return ret;
 484         return 0;
 485 }
 486
 487 int smu_v11_0_init_power(struct smu_context *smu)
 488 {
 489         struct smu_power_context *smu_power = &smu->smu_power;
 490
 491         if (!smu->pm_enabled)
 492                 return 0;
 493         if (smu_power->power_context || smu_power->power_context_size != 0)
 494                 return -EINVAL;
 495
 496         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 497                                            GFP_KERNEL);
 498         if (!smu_power->power_context)
 499                 return -ENOMEM;
 500         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 501
 502         return 0;
 503 }
 504
 505 int smu_v11_0_fini_power(struct smu_context *smu)
 506 {
 507         struct smu_power_context *smu_power = &smu->smu_power;
 508
 509         if (!smu->pm_enabled)
 510                 return 0;
 511         if (!smu_power->power_context || smu_power->power_context_size == 0)
 512                 return -EINVAL;
 513
 514         kfree(smu_power->power_context);
 515         smu_power->power_context = NULL;
 516         smu_power->power_context_size = 0;
 517
 518         return 0;
 519 }
 520
 521 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 522 {
 523         int ret, index;
 524         uint16_t size;
 525         uint8_t frev, crev;
 526         struct atom_common_table_header *header;
 527         struct atom_firmware_info_v3_3 *v_3_3;
 528         struct atom_firmware_info_v3_1 *v_3_1;
 529
 530         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 531                                             firmwareinfo);
 532
 533         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 534                                       (uint8_t **)&header);
 535         if (ret)
 536                 return ret;
 537
 538         if (header->format_revision != 3) {
 539                 pr_err("unknown atom_firmware_info version! for smu11\n");
 540                 return -EINVAL;
 541         }
 542
 543         switch (header->content_revision) {
 544         case 0:
 545         case 1:
 546         case 2:
 547                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 548                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 549                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 550                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 551                 smu->smu_table.boot_values.socclk = 0;
 552                 smu->smu_table.boot_values.dcefclk = 0;
 553                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 554                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 555                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 556                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 557                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 558                 smu->smu_table.boot_values.pp_table_id = 0;
 559                 break;
 560         case 3:
 561         default:
 562                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 563                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 564                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 565                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 566                 smu->smu_table.boot_values.socclk = 0;
 567                 smu->smu_table.boot_values.dcefclk = 0;
 568                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 569                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 570                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 571                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 572                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 573                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 574         }
 575
 576         smu->smu_table.boot_values.format_revision = header->format_revision;
 577         smu->smu_table.boot_values.content_revision = header->content_revision;
 578
 579         return 0;
 580 }
 581
 582 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 583 {
 584         int ret, index;
 585         struct amdgpu_device *adev = smu->adev;
 586         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 587         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 588
 589         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 590         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 591         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 592                                             getsmuclockinfo);
 593
 594         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 595                                         (uint32_t *)&input);
 596         if (ret)
 597                 return -EINVAL;
 598
 599         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 600         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 601
 602         memset(&input, 0, sizeof(input));
 603         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 604         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 605         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 606                                             getsmuclockinfo);
 607
 608         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 609                                         (uint32_t *)&input);
 610         if (ret)
 611                 return -EINVAL;
 612
 613         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 614         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 615
 616         memset(&input, 0, sizeof(input));
 617         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 618         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 619         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 620                                             getsmuclockinfo);
 621
 622         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 623                                         (uint32_t *)&input);
 624         if (ret)
 625                 return -EINVAL;
 626
 627         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 628         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 629
 630         memset(&input, 0, sizeof(input));
 631         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 632         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 633         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 634                                             getsmuclockinfo);
 635
 636         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 637                                         (uint32_t *)&input);
 638         if (ret)
 639                 return -EINVAL;
 640
 641         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 642         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 643
 644         memset(&input, 0, sizeof(input));
 645         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 646         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 647         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 648                                             getsmuclockinfo);
 649
 650         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 651                                         (uint32_t *)&input);
 652         if (ret)
 653                 return -EINVAL;
 654
 655         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 656         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 657
 658         if ((smu->smu_table.boot_values.format_revision == 3) &&
 659             (smu->smu_table.boot_values.content_revision >= 2)) {
 660                 memset(&input, 0, sizeof(input));
 661                 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
 662                 input.syspll_id = SMU11_SYSPLL1_2_ID;
 663                 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 664                 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 665                                                     getsmuclockinfo);
 666
 667                 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 668                                                 (uint32_t *)&input);
 669                 if (ret)
 670                         return -EINVAL;
 671
 672                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 673                 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 674         }
 675
 676         return 0;
 677 }
 678
 679 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 680 {
 681         struct smu_table_context *smu_table = &smu->smu_table;
 682         struct smu_table *memory_pool = &smu_table->memory_pool;
 683         int ret = 0;
 684         uint64_t address;
 685         uint32_t address_low, address_high;
 686
 687         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 688                 return ret;
 689
 690         address = (uintptr_t)memory_pool->cpu_addr;
 691         address_high = (uint32_t)upper_32_bits(address);
 692         address_low  = (uint32_t)lower_32_bits(address);
 693
 694         ret = smu_send_smc_msg_with_param(smu,
 695                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 696                                           address_high);
 697         if (ret)
 698                 return ret;
 699         ret = smu_send_smc_msg_with_param(smu,
 700                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 701                                           address_low);
 702         if (ret)
 703                 return ret;
 704
 705         address = memory_pool->mc_address;
 706         address_high = (uint32_t)upper_32_bits(address);
 707         address_low  = (uint32_t)lower_32_bits(address);
 708
 709         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 710                                           address_high);
 711         if (ret)
 712                 return ret;
 713         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 714                                           address_low);
 715         if (ret)
 716                 return ret;
 717         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 718                                           (uint32_t)memory_pool->size);
 719         if (ret)
 720                 return ret;
 721
 722         return ret;
 723 }
 724
 725 int smu_v11_0_check_pptable(struct smu_context *smu)
 726 {
 727         int ret;
 728
 729         ret = smu_check_powerplay_table(smu);
 730         return ret;
 731 }
 732
 733 int smu_v11_0_parse_pptable(struct smu_context *smu)
 734 {
 735         int ret;
 736
 737         struct smu_table_context *table_context = &smu->smu_table;
 738         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 739
 740         if (table_context->driver_pptable)
 741                 return -EINVAL;
 742
 743         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 744
 745         if (!table_context->driver_pptable)
 746                 return -ENOMEM;
 747
 748         ret = smu_store_powerplay_table(smu);
 749         if (ret)
 750                 return -EINVAL;
 751
 752         ret = smu_append_powerplay_table(smu);
 753
 754         return ret;
 755 }
 756
 757 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 758 {
 759         int ret;
 760
 761         ret = smu_set_default_dpm_table(smu);
 762
 763         return ret;
 764 }
 765
 766 int smu_v11_0_write_pptable(struct smu_context *smu)
 767 {
 768         struct smu_table_context *table_context = &smu->smu_table;
 769         int ret = 0;
 770
 771         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 772                                table_context->driver_pptable, true);
 773
 774         return ret;
 775 }
 776
 777 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 778 {
 779         int ret;
 780
 781         ret = smu_send_smc_msg_with_param(smu,
 782                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 783         if (ret)
 784                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 785
 786         return ret;
 787 }
 788
 789 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 790 {
 791         struct smu_table_context *table_context = &smu->smu_table;
 792
 793         if (!smu->pm_enabled)
 794                 return 0;
 795         if (!table_context)
 796                 return -EINVAL;
 797
 798         return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
 799 }
 800
 801 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 802 {
 803         int ret = 0;
 804         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 805
 806         if (tool_table->mc_address) {
 807                 ret = smu_send_smc_msg_with_param(smu,
 808                                 SMU_MSG_SetToolsDramAddrHigh,
 809                                 upper_32_bits(tool_table->mc_address));
 810                 if (!ret)
 811                         ret = smu_send_smc_msg_with_param(smu,
 812                                 SMU_MSG_SetToolsDramAddrLow,
 813                                 lower_32_bits(tool_table->mc_address));
 814         }
 815
 816         return ret;
 817 }
 818
 819 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 820 {
 821         int ret = 0;
 822
 823         if (!smu->pm_enabled)
 824                 return ret;
 825
 826         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 827         return ret;
 828 }
 829
 830
 831 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 832 {
 833         struct smu_feature *feature = &smu->smu_feature;
 834         int ret = 0;
 835         uint32_t feature_mask[2];
 836
 837         mutex_lock(&feature->mutex);
 838         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 839                 goto failed;
 840
 841         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 842
 843         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 844                                           feature_mask[1]);
 845         if (ret)
 846                 goto failed;
 847
 848         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 849                                           feature_mask[0]);
 850         if (ret)
 851                 goto failed;
 852
 853 failed:
 854         mutex_unlock(&feature->mutex);
 855         return ret;
 856 }
 857
 858 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 859                                       uint32_t *feature_mask, uint32_t num)
 860 {
 861         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 862         int ret = 0;
 863
 864         if (!feature_mask || num < 2)
 865                 return -EINVAL;
 866
 867         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 868         if (ret)
 869                 return ret;
 870         ret = smu_read_smc_arg(smu, &feature_mask_high);
 871         if (ret)
 872                 return ret;
 873
 874         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 875         if (ret)
 876                 return ret;
 877         ret = smu_read_smc_arg(smu, &feature_mask_low);
 878         if (ret)
 879                 return ret;
 880
 881         feature_mask[0] = feature_mask_low;
 882         feature_mask[1] = feature_mask_high;
 883
 884         return ret;
 885 }
 886
 887 int smu_v11_0_system_features_control(struct smu_context *smu,
 888                                              bool en)
 889 {
 890         struct smu_feature *feature = &smu->smu_feature;
 891         uint32_t feature_mask[2];
 892         int ret = 0;
 893
 894         if (smu->pm_enabled) {
 895                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 896                                              SMU_MSG_DisableAllSmuFeatures));
 897                 if (ret)
 898                         return ret;
 899         }
 900
 901         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 902         if (ret)
 903                 return ret;
 904
 905         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 906                     feature->feature_num);
 907         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 908                     feature->feature_num);
 909
 910         return ret;
 911 }
 912
 913 int smu_v11_0_notify_display_change(struct smu_context *smu)
 914 {
 915         int ret = 0;
 916
 917         if (!smu->pm_enabled)
 918                 return ret;
 919         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 920             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 921                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 922
 923         return ret;
 924 }
 925
 926 static int
 927 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 928                                     enum smu_clk_type clock_select)
 929 {
 930         int ret = 0;
 931         int clk_id;
 932
 933         if (!smu->pm_enabled)
 934                 return ret;
 935
 936         if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 937             (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
 938                 return 0;
 939
 940         clk_id = smu_clk_get_index(smu, clock_select);
 941         if (clk_id < 0)
 942                 return -EINVAL;
 943
 944         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 945                                           clk_id << 16);
 946         if (ret) {
 947                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 948                 return ret;
 949         }
 950
 951         ret = smu_read_smc_arg(smu, clock);
 952         if (ret)
 953                 return ret;
 954
 955         if (*clock != 0)
 956                 return 0;
 957
 958         /* if DC limit is zero, return AC limit */
 959         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 960                                           clk_id << 16);
 961         if (ret) {
 962                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 963                 return ret;
 964         }
 965
 966         ret = smu_read_smc_arg(smu, clock);
 967
 968         return ret;
 969 }
 970
 971 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 972 {
 973         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 974         int ret = 0;
 975
 976         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 977                                          GFP_KERNEL);
 978         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 979
 980         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 981         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 982         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 983         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 984         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 985         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 986
 987         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 988                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 989                                                           &(max_sustainable_clocks->uclock),
 990                                                           SMU_UCLK);
 991                 if (ret) {
 992                         pr_err("[%s] failed to get max UCLK from SMC!",
 993                                __func__);
 994                         return ret;
 995                 }
 996         }
 997
 998         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 999                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1000                                                           &(max_sustainable_clocks->soc_clock),
1001                                                           SMU_SOCCLK);
1002                 if (ret) {
1003                         pr_err("[%s] failed to get max SOCCLK from SMC!",
1004                                __func__);
1005                         return ret;
1006                 }
1007         }
1008
1009         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1010                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1011                                                           &(max_sustainable_clocks->dcef_clock),
1012                                                           SMU_DCEFCLK);
1013                 if (ret) {
1014                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1015                                __func__);
1016                         return ret;
1017                 }
1018
1019                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1020                                                           &(max_sustainable_clocks->display_clock),
1021                                                           SMU_DISPCLK);
1022                 if (ret) {
1023                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1024                                __func__);
1025                         return ret;
1026                 }
1027                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1028                                                           &(max_sustainable_clocks->phy_clock),
1029                                                           SMU_PHYCLK);
1030                 if (ret) {
1031                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1032                                __func__);
1033                         return ret;
1034                 }
1035                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1036                                                           &(max_sustainable_clocks->pixel_clock),
1037                                                           SMU_PIXCLK);
1038                 if (ret) {
1039                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1040                                __func__);
1041                         return ret;
1042                 }
1043         }
1044
1045         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1046                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1047
1048         return 0;
1049 }
1050
1051 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1052         uint32_t od_limit, max_power_limit;
1053         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1054         struct smu_table_context *table_context = &smu->smu_table;
1055         powerplay_table = table_context->power_play_table;
1056
1057         max_power_limit = smu_get_pptable_power_limit(smu);
1058
1059         if (!max_power_limit) {
1060                 // If we couldn't get the table limit, fall back on first-read value
1061                 if (!smu->default_power_limit)
1062                         smu->default_power_limit = smu->power_limit;
1063                 max_power_limit = smu->default_power_limit;
1064         }
1065
1066         if (smu->od_enabled) {
1067                 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1068
1069                 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1070
1071                 max_power_limit *= (100 + od_limit);
1072                 max_power_limit /= 100;
1073         }
1074
1075         return max_power_limit;
1076 }
1077
1078 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1079 {
1080         int ret = 0;
1081         uint32_t max_power_limit;
1082
1083         max_power_limit = smu_v11_0_get_max_power_limit(smu);
1084
1085         if (n > max_power_limit) {
1086                 pr_err("New power limit (%d) is over the max allowed %d\n",
1087                                 n,
1088                                 max_power_limit);
1089                 return -EINVAL;
1090         }
1091
1092         if (n == 0)
1093                 n = smu->default_power_limit;
1094
1095         if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1096                 pr_err("Setting new power limit is not supported!\n");
1097                 return -EOPNOTSUPP;
1098         }
1099
1100         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1101         if (ret) {
1102                 pr_err("[%s] Set power limit Failed!\n", __func__);
1103                 return ret;
1104         }
1105         smu->power_limit = n;
1106
1107         return 0;
1108 }
1109
1110 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1111                                           enum smu_clk_type clk_id,
1112                                           uint32_t *value)
1113 {
1114         int ret = 0;
1115         uint32_t freq = 0;
1116         int asic_clk_id;
1117
1118         if (clk_id >= SMU_CLK_COUNT || !value)
1119                 return -EINVAL;
1120
1121         asic_clk_id = smu_clk_get_index(smu, clk_id);
1122         if (asic_clk_id < 0)
1123                 return -EINVAL;
1124
1125         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1126         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1127                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1128         else {
1129                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1130                                                   (asic_clk_id << 16));
1131                 if (ret)
1132                         return ret;
1133
1134                 ret = smu_read_smc_arg(smu, &freq);
1135                 if (ret)
1136                         return ret;
1137         }
1138
1139         freq *= 100;
1140         *value = freq;
1141
1142         return ret;
1143 }
1144
1145 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1146                                        struct smu_temperature_range range)
1147 {
1148         struct amdgpu_device *adev = smu->adev;
1149         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1150         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1151         uint32_t val;
1152
1153         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1154                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1155         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1156                         range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1157
1158         if (low > high)
1159                 return -EINVAL;
1160
1161         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1162         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1163         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1164         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1165         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1166         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1167         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1168         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1169
1170         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1171
1172         return 0;
1173 }
1174
1175 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1176 {
1177         struct amdgpu_device *adev = smu->adev;
1178         uint32_t val = 0;
1179
1180         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1181         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1182         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1183
1184         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1185
1186         return 0;
1187 }
1188
1189 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1190 {
1191         int ret = 0;
1192         struct smu_temperature_range range;
1193         struct amdgpu_device *adev = smu->adev;
1194
1195         if (!smu->pm_enabled)
1196                 return ret;
1197
1198         memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1199
1200         ret = smu_get_thermal_temperature_range(smu, &range);
1201         if (ret)
1202                 return ret;
1203
1204         if (smu->smu_table.thermal_controller_type) {
1205                 ret = smu_v11_0_set_thermal_range(smu, range);
1206                 if (ret)
1207                         return ret;
1208
1209                 ret = smu_v11_0_enable_thermal_alert(smu);
1210                 if (ret)
1211                         return ret;
1212
1213                 ret = smu_set_thermal_fan_table(smu);
1214                 if (ret)
1215                         return ret;
1216         }
1217
1218         adev->pm.dpm.thermal.min_temp = range.min;
1219         adev->pm.dpm.thermal.max_temp = range.max;
1220         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1221         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1222         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1223         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1224         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1225         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1226         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1227
1228         return ret;
1229 }
1230
1231 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1232 {
1233         struct amdgpu_device *adev = smu->adev;
1234
1235         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1236
1237         return 0;
1238 }
1239
1240 static uint16_t convert_to_vddc(uint8_t vid)
1241 {
1242         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1243 }
1244
1245 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1246 {
1247         struct amdgpu_device *adev = smu->adev;
1248         uint32_t vdd = 0, val_vid = 0;
1249
1250         if (!value)
1251                 return -EINVAL;
1252         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1253                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1254                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1255
1256         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1257
1258         *value = vdd;
1259
1260         return 0;
1261
1262 }
1263
1264 int smu_v11_0_read_sensor(struct smu_context *smu,
1265                                  enum amd_pp_sensors sensor,
1266                                  void *data, uint32_t *size)
1267 {
1268         int ret = 0;
1269
1270         if(!data || !size)
1271                 return -EINVAL;
1272
1273         switch (sensor) {
1274         case AMDGPU_PP_SENSOR_GFX_MCLK:
1275                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1276                 *size = 4;
1277                 break;
1278         case AMDGPU_PP_SENSOR_GFX_SCLK:
1279                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1280                 *size = 4;
1281                 break;
1282         case AMDGPU_PP_SENSOR_VDDGFX:
1283                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1284                 *size = 4;
1285                 break;
1286         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1287                 *(uint32_t *)data = 0;
1288                 *size = 4;
1289                 break;
1290         default:
1291                 ret = smu_common_read_sensor(smu, sensor, data, size);
1292                 break;
1293         }
1294
1295         if (ret)
1296                 *size = 0;
1297
1298         return ret;
1299 }
1300
1301 int
1302 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1303                                         struct pp_display_clock_request
1304                                         *clock_req)
1305 {
1306         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1307         int ret = 0;
1308         enum smu_clk_type clk_select = 0;
1309         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1310
1311         if (!smu->pm_enabled)
1312                 return -EINVAL;
1313
1314         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1315                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1316                 switch (clk_type) {
1317                 case amd_pp_dcef_clock:
1318                         clk_select = SMU_DCEFCLK;
1319                         break;
1320                 case amd_pp_disp_clock:
1321                         clk_select = SMU_DISPCLK;
1322                         break;
1323                 case amd_pp_pixel_clock:
1324                         clk_select = SMU_PIXCLK;
1325                         break;
1326                 case amd_pp_phy_clock:
1327                         clk_select = SMU_PHYCLK;
1328                         break;
1329                 case amd_pp_mem_clock:
1330                         clk_select = SMU_UCLK;
1331                         break;
1332                 default:
1333                         pr_info("[%s] Invalid Clock Type!", __func__);
1334                         ret = -EINVAL;
1335                         break;
1336                 }
1337
1338                 if (ret)
1339                         goto failed;
1340
1341                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1342                         return 0;
1343
1344                 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1345
1346                 if(clk_select == SMU_UCLK)
1347                         smu->hard_min_uclk_req_from_dal = clk_freq;
1348         }
1349
1350 failed:
1351         return ret;
1352 }
1353
1354 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1355 {
1356         int ret = 0;
1357         struct amdgpu_device *adev = smu->adev;
1358
1359         switch (adev->asic_type) {
1360         case CHIP_VEGA20:
1361                 break;
1362         case CHIP_NAVI10:
1363         case CHIP_NAVI14:
1364         case CHIP_NAVI12:
1365                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1366                         return 0;
1367                 if (enable)
1368                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1369                 else
1370                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1371                 break;
1372         default:
1373                 break;
1374         }
1375
1376         return ret;
1377 }
1378
1379 uint32_t
1380 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1381 {
1382         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1383                 return AMD_FAN_CTRL_MANUAL;
1384         else
1385                 return AMD_FAN_CTRL_AUTO;
1386 }
1387
1388 static int
1389 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1390 {
1391         int ret = 0;
1392
1393         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1394                 return 0;
1395
1396         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1397         if (ret)
1398                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1399                        __func__, (auto_fan_control ? "Start" : "Stop"));
1400
1401         return ret;
1402 }
1403
1404 static int
1405 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1406 {
1407         struct amdgpu_device *adev = smu->adev;
1408
1409         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1410                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1411                                    CG_FDO_CTRL2, TMIN, 0));
1412         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1413                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1414                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1415
1416         return 0;
1417 }
1418
1419 int
1420 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1421 {
1422         struct amdgpu_device *adev = smu->adev;
1423         uint32_t duty100, duty;
1424         uint64_t tmp64;
1425
1426         if (speed > 100)
1427                 speed = 100;
1428
1429         if (smu_v11_0_auto_fan_control(smu, 0))
1430                 return -EINVAL;
1431
1432         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1433                                 CG_FDO_CTRL1, FMAX_DUTY100);
1434         if (!duty100)
1435                 return -EINVAL;
1436
1437         tmp64 = (uint64_t)speed * duty100;
1438         do_div(tmp64, 100);
1439         duty = (uint32_t)tmp64;
1440
1441         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1442                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1443                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1444
1445         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1446 }
1447
1448 int
1449 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1450                                uint32_t mode)
1451 {
1452         int ret = 0;
1453
1454         switch (mode) {
1455         case AMD_FAN_CTRL_NONE:
1456                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1457                 break;
1458         case AMD_FAN_CTRL_MANUAL:
1459                 ret = smu_v11_0_auto_fan_control(smu, 0);
1460                 break;
1461         case AMD_FAN_CTRL_AUTO:
1462                 ret = smu_v11_0_auto_fan_control(smu, 1);
1463                 break;
1464         default:
1465                 break;
1466         }
1467
1468         if (ret) {
1469                 pr_err("[%s]Set fan control mode failed!", __func__);
1470                 return -EINVAL;
1471         }
1472
1473         return ret;
1474 }
1475
1476 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1477                                        uint32_t speed)
1478 {
1479         struct amdgpu_device *adev = smu->adev;
1480         int ret;
1481         uint32_t tach_period, crystal_clock_freq;
1482
1483         if (!speed)
1484                 return -EINVAL;
1485
1486         ret = smu_v11_0_auto_fan_control(smu, 0);
1487         if (ret)
1488                 return ret;
1489
1490         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1491         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1492         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1493                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1494                                    CG_TACH_CTRL, TARGET_PERIOD,
1495                                    tach_period));
1496
1497         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1498
1499         return ret;
1500 }
1501
1502 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1503                                      uint32_t pstate)
1504 {
1505         int ret = 0;
1506         ret = smu_send_smc_msg_with_param(smu,
1507                                           SMU_MSG_SetXgmiMode,
1508                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
1509         return ret;
1510 }
1511
1512 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1513 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1514
1515 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1516                                  struct amdgpu_irq_src *source,
1517                                  struct amdgpu_iv_entry *entry)
1518 {
1519         uint32_t client_id = entry->client_id;
1520         uint32_t src_id = entry->src_id;
1521
1522         if (client_id == SOC15_IH_CLIENTID_THM) {
1523                 switch (src_id) {
1524                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1525                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1526                                 PCI_BUS_NUM(adev->pdev->devfn),
1527                                 PCI_SLOT(adev->pdev->devfn),
1528                                 PCI_FUNC(adev->pdev->devfn));
1529                 break;
1530                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1531                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1532                                 PCI_BUS_NUM(adev->pdev->devfn),
1533                                 PCI_SLOT(adev->pdev->devfn),
1534                                 PCI_FUNC(adev->pdev->devfn));
1535                 break;
1536                 default:
1537                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1538                                 src_id,
1539                                 PCI_BUS_NUM(adev->pdev->devfn),
1540                                 PCI_SLOT(adev->pdev->devfn),
1541                                 PCI_FUNC(adev->pdev->devfn));
1542                 break;
1543
1544                 }
1545         }
1546
1547         return 0;
1548 }
1549
1550 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1551 {
1552         .process = smu_v11_0_irq_process,
1553 };
1554
1555 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1556 {
1557         struct amdgpu_device *adev = smu->adev;
1558         struct amdgpu_irq_src *irq_src = smu->irq_source;
1559         int ret = 0;
1560
1561         /* already register */
1562         if (irq_src)
1563                 return 0;
1564
1565         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1566         if (!irq_src)
1567                 return -ENOMEM;
1568         smu->irq_source = irq_src;
1569
1570         irq_src->funcs = &smu_v11_0_irq_funcs;
1571
1572         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1573                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1574                                 irq_src);
1575         if (ret)
1576                 return ret;
1577
1578         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1579                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1580                                 irq_src);
1581         if (ret)
1582                 return ret;
1583
1584         return ret;
1585 }
1586
1587 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1588                 struct pp_smu_nv_clock_table *max_clocks)
1589 {
1590         struct smu_table_context *table_context = &smu->smu_table;
1591         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1592
1593         if (!max_clocks || !table_context->max_sustainable_clocks)
1594                 return -EINVAL;
1595
1596         sustainable_clocks = table_context->max_sustainable_clocks;
1597
1598         max_clocks->dcfClockInKhz =
1599                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1600         max_clocks->displayClockInKhz =
1601                         (unsigned int) sustainable_clocks->display_clock * 1000;
1602         max_clocks->phyClockInKhz =
1603                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1604         max_clocks->pixelClockInKhz =
1605                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1606         max_clocks->uClockInKhz =
1607                         (unsigned int) sustainable_clocks->uclock * 1000;
1608         max_clocks->socClockInKhz =
1609                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1610         max_clocks->dscClockInKhz = 0;
1611         max_clocks->dppClockInKhz = 0;
1612         max_clocks->fabricClockInKhz = 0;
1613
1614         return 0;
1615 }
1616
1617 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1618 {
1619         int ret = 0;
1620
1621         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1622
1623         return ret;
1624 }
1625
1626 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1627 {
1628         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1629 }
1630
1631 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1632 {
1633         struct amdgpu_device *adev = smu->adev;
1634         struct smu_baco_context *smu_baco = &smu->smu_baco;
1635         uint32_t val;
1636         bool baco_support;
1637
1638         mutex_lock(&smu_baco->mutex);
1639         baco_support = smu_baco->platform_support;
1640         mutex_unlock(&smu_baco->mutex);
1641
1642         if (!baco_support)
1643                 return false;
1644
1645         if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1646                 return false;
1647
1648         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1649         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1650                 return true;
1651
1652         return false;
1653 }
1654
1655 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1656 {
1657         struct smu_baco_context *smu_baco = &smu->smu_baco;
1658         enum smu_baco_state baco_state;
1659
1660         mutex_lock(&smu_baco->mutex);
1661         baco_state = smu_baco->state;
1662         mutex_unlock(&smu_baco->mutex);
1663
1664         return baco_state;
1665 }
1666
1667 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1668 {
1669
1670         struct smu_baco_context *smu_baco = &smu->smu_baco;
1671         int ret = 0;
1672
1673         if (smu_v11_0_baco_get_state(smu) == state)
1674                 return 0;
1675
1676         mutex_lock(&smu_baco->mutex);
1677
1678         if (state == SMU_BACO_STATE_ENTER)
1679                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
1680         else
1681                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1682         if (ret)
1683                 goto out;
1684
1685         smu_baco->state = state;
1686 out:
1687         mutex_unlock(&smu_baco->mutex);
1688         return ret;
1689 }
1690
1691 int smu_v11_0_baco_reset(struct smu_context *smu)
1692 {
1693         int ret = 0;
1694
1695         ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1696         if (ret)
1697                 return ret;
1698
1699         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1700         if (ret)
1701                 return ret;
1702
1703         msleep(10);
1704
1705         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1706         if (ret)
1707                 return ret;
1708
1709         return ret;
1710 }
1711
1712 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1713                                                  uint32_t *min, uint32_t *max)
1714 {
1715         int ret = 0, clk_id = 0;
1716         uint32_t param = 0;
1717
1718         clk_id = smu_clk_get_index(smu, clk_type);
1719         if (clk_id < 0) {
1720                 ret = -EINVAL;
1721                 goto failed;
1722         }
1723         param = (clk_id & 0xffff) << 16;
1724
1725         if (max) {
1726                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
1727                 if (ret)
1728                         goto failed;
1729                 ret = smu_read_smc_arg(smu, max);
1730                 if (ret)
1731                         goto failed;
1732         }
1733
1734         if (min) {
1735                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
1736                 if (ret)
1737                         goto failed;
1738                 ret = smu_read_smc_arg(smu, min);
1739                 if (ret)
1740                         goto failed;
1741         }
1742
1743 failed:
1744         return ret;
1745 }
1746
1747 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1748                             uint32_t min, uint32_t max)
1749 {
1750         int ret = 0, clk_id = 0;
1751         uint32_t param;
1752
1753         clk_id = smu_clk_get_index(smu, clk_type);
1754         if (clk_id < 0)
1755                 return clk_id;
1756
1757         if (max > 0) {
1758                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1759                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1760                                                   param);
1761                 if (ret)
1762                         return ret;
1763         }
1764
1765         if (min > 0) {
1766                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1767                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1768                                                   param);
1769                 if (ret)
1770                         return ret;
1771         }
1772
1773         return ret;
1774 }
1775
1776 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1777 {
1778         struct amdgpu_device *adev = smu->adev;
1779         uint32_t pcie_gen = 0, pcie_width = 0;
1780         int ret;
1781
1782         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1783                 pcie_gen = 3;
1784         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1785                 pcie_gen = 2;
1786         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1787                 pcie_gen = 1;
1788         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1789                 pcie_gen = 0;
1790
1791         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1792          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1793          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1794          */
1795         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1796                 pcie_width = 6;
1797         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1798                 pcie_width = 5;
1799         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1800                 pcie_width = 4;
1801         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1802                 pcie_width = 3;
1803         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1804                 pcie_width = 2;
1805         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1806                 pcie_width = 1;
1807
1808         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1809
1810         if (ret)
1811                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1812
1813         return ret;
1814
1815 }
1816
1817 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1818 {
1819         struct smu_table_context *table_context = &smu->smu_table;
1820         int ret = 0;
1821
1822         if (initialize) {
1823                 if (table_context->overdrive_table) {
1824                         return -EINVAL;
1825                 }
1826                 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1827                 if (!table_context->overdrive_table) {
1828                         return -ENOMEM;
1829                 }
1830                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1831                 if (ret) {
1832                         pr_err("Failed to export overdrive table!\n");
1833                         return ret;
1834                 }
1835         }
1836         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1837         if (ret) {
1838                 pr_err("Failed to import overdrive table!\n");
1839                 return ret;
1840         }
1841         return ret;
1842 }