drivers/gpu/drm/amd/powerplay/vega20_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "vega20_ppt.h"
  36 #include "vega20_pptable.h"
  37 #include "vega20_ppsmc.h"
  38 #include "nbio/nbio_7_4_sh_mask.h"
  39 #include "asic_reg/thm/thm_11_0_2_offset.h"
  40 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  41
  42 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  43 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  44
  45 #define CTF_OFFSET_EDGE                 5
  46 #define CTF_OFFSET_HOTSPOT              5
  47 #define CTF_OFFSET_HBM                  5
  48
  49 #define MSG_MAP(msg) \
  50         [SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
  51
  52 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
  53                          FEATURE_DPM_GFXCLK_MASK | \
  54                          FEATURE_DPM_UCLK_MASK | \
  55                          FEATURE_DPM_SOCCLK_MASK | \
  56                          FEATURE_DPM_UVD_MASK | \
  57                          FEATURE_DPM_VCE_MASK | \
  58                          FEATURE_DPM_MP0CLK_MASK | \
  59                          FEATURE_DPM_LINK_MASK | \
  60                          FEATURE_DPM_DCEFCLK_MASK)
  61
  62 static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
  63         MSG_MAP(TestMessage),
  64         MSG_MAP(GetSmuVersion),
  65         MSG_MAP(GetDriverIfVersion),
  66         MSG_MAP(SetAllowedFeaturesMaskLow),
  67         MSG_MAP(SetAllowedFeaturesMaskHigh),
  68         MSG_MAP(EnableAllSmuFeatures),
  69         MSG_MAP(DisableAllSmuFeatures),
  70         MSG_MAP(EnableSmuFeaturesLow),
  71         MSG_MAP(EnableSmuFeaturesHigh),
  72         MSG_MAP(DisableSmuFeaturesLow),
  73         MSG_MAP(DisableSmuFeaturesHigh),
  74         MSG_MAP(GetEnabledSmuFeaturesLow),
  75         MSG_MAP(GetEnabledSmuFeaturesHigh),
  76         MSG_MAP(SetWorkloadMask),
  77         MSG_MAP(SetPptLimit),
  78         MSG_MAP(SetDriverDramAddrHigh),
  79         MSG_MAP(SetDriverDramAddrLow),
  80         MSG_MAP(SetToolsDramAddrHigh),
  81         MSG_MAP(SetToolsDramAddrLow),
  82         MSG_MAP(TransferTableSmu2Dram),
  83         MSG_MAP(TransferTableDram2Smu),
  84         MSG_MAP(UseDefaultPPTable),
  85         MSG_MAP(UseBackupPPTable),
  86         MSG_MAP(RunBtc),
  87         MSG_MAP(RequestI2CBus),
  88         MSG_MAP(ReleaseI2CBus),
  89         MSG_MAP(SetFloorSocVoltage),
  90         MSG_MAP(SoftReset),
  91         MSG_MAP(StartBacoMonitor),
  92         MSG_MAP(CancelBacoMonitor),
  93         MSG_MAP(EnterBaco),
  94         MSG_MAP(SetSoftMinByFreq),
  95         MSG_MAP(SetSoftMaxByFreq),
  96         MSG_MAP(SetHardMinByFreq),
  97         MSG_MAP(SetHardMaxByFreq),
  98         MSG_MAP(GetMinDpmFreq),
  99         MSG_MAP(GetMaxDpmFreq),
 100         MSG_MAP(GetDpmFreqByIndex),
 101         MSG_MAP(GetDpmClockFreq),
 102         MSG_MAP(GetSsVoltageByDpm),
 103         MSG_MAP(SetMemoryChannelConfig),
 104         MSG_MAP(SetGeminiMode),
 105         MSG_MAP(SetGeminiApertureHigh),
 106         MSG_MAP(SetGeminiApertureLow),
 107         MSG_MAP(SetMinLinkDpmByIndex),
 108         MSG_MAP(OverridePcieParameters),
 109         MSG_MAP(OverDriveSetPercentage),
 110         MSG_MAP(SetMinDeepSleepDcefclk),
 111         MSG_MAP(ReenableAcDcInterrupt),
 112         MSG_MAP(NotifyPowerSource),
 113         MSG_MAP(SetUclkFastSwitch),
 114         MSG_MAP(SetUclkDownHyst),
 115         MSG_MAP(GetCurrentRpm),
 116         MSG_MAP(SetVideoFps),
 117         MSG_MAP(SetTjMax),
 118         MSG_MAP(SetFanTemperatureTarget),
 119         MSG_MAP(PrepareMp1ForUnload),
 120         MSG_MAP(DramLogSetDramAddrHigh),
 121         MSG_MAP(DramLogSetDramAddrLow),
 122         MSG_MAP(DramLogSetDramSize),
 123         MSG_MAP(SetFanMaxRpm),
 124         MSG_MAP(SetFanMinPwm),
 125         MSG_MAP(ConfigureGfxDidt),
 126         MSG_MAP(NumOfDisplays),
 127         MSG_MAP(RemoveMargins),
 128         MSG_MAP(ReadSerialNumTop32),
 129         MSG_MAP(ReadSerialNumBottom32),
 130         MSG_MAP(SetSystemVirtualDramAddrHigh),
 131         MSG_MAP(SetSystemVirtualDramAddrLow),
 132         MSG_MAP(WaflTest),
 133         MSG_MAP(SetFclkGfxClkRatio),
 134         MSG_MAP(AllowGfxOff),
 135         MSG_MAP(DisallowGfxOff),
 136         MSG_MAP(GetPptLimit),
 137         MSG_MAP(GetDcModeMaxDpmFreq),
 138         MSG_MAP(GetDebugData),
 139         MSG_MAP(SetXgmiMode),
 140         MSG_MAP(RunAfllBtc),
 141         MSG_MAP(ExitBaco),
 142         MSG_MAP(PrepareMp1ForReset),
 143         MSG_MAP(PrepareMp1ForShutdown),
 144         MSG_MAP(SetMGpuFanBoostLimitRpm),
 145         MSG_MAP(GetAVFSVoltageByDpm),
 146 };
 147
 148 static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
 149         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 150         CLK_MAP(VCLK, PPCLK_VCLK),
 151         CLK_MAP(DCLK, PPCLK_DCLK),
 152         CLK_MAP(ECLK, PPCLK_ECLK),
 153         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 154         CLK_MAP(UCLK, PPCLK_UCLK),
 155         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 156         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 157         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 158         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 159         CLK_MAP(FCLK, PPCLK_FCLK),
 160 };
 161
 162 static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
 163         FEA_MAP(DPM_PREFETCHER),
 164         FEA_MAP(DPM_GFXCLK),
 165         FEA_MAP(DPM_UCLK),
 166         FEA_MAP(DPM_SOCCLK),
 167         FEA_MAP(DPM_UVD),
 168         FEA_MAP(DPM_VCE),
 169         FEA_MAP(ULV),
 170         FEA_MAP(DPM_MP0CLK),
 171         FEA_MAP(DPM_LINK),
 172         FEA_MAP(DPM_DCEFCLK),
 173         FEA_MAP(DS_GFXCLK),
 174         FEA_MAP(DS_SOCCLK),
 175         FEA_MAP(DS_LCLK),
 176         FEA_MAP(PPT),
 177         FEA_MAP(TDC),
 178         FEA_MAP(THERMAL),
 179         FEA_MAP(GFX_PER_CU_CG),
 180         FEA_MAP(RM),
 181         FEA_MAP(DS_DCEFCLK),
 182         FEA_MAP(ACDC),
 183         FEA_MAP(VR0HOT),
 184         FEA_MAP(VR1HOT),
 185         FEA_MAP(FW_CTF),
 186         FEA_MAP(LED_DISPLAY),
 187         FEA_MAP(FAN_CONTROL),
 188         FEA_MAP(GFX_EDC),
 189         FEA_MAP(GFXOFF),
 190         FEA_MAP(CG),
 191         FEA_MAP(DPM_FCLK),
 192         FEA_MAP(DS_FCLK),
 193         FEA_MAP(DS_MP1CLK),
 194         FEA_MAP(DS_MP0CLK),
 195         FEA_MAP(XGMI),
 196 };
 197
 198 static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
 199         TAB_MAP(PPTABLE),
 200         TAB_MAP(WATERMARKS),
 201         TAB_MAP(AVFS),
 202         TAB_MAP(AVFS_PSM_DEBUG),
 203         TAB_MAP(AVFS_FUSE_OVERRIDE),
 204         TAB_MAP(PMSTATUSLOG),
 205         TAB_MAP(SMU_METRICS),
 206         TAB_MAP(DRIVER_SMU_CONFIG),
 207         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 208         TAB_MAP(OVERDRIVE),
 209 };
 210
 211 static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 212         PWR_MAP(AC),
 213         PWR_MAP(DC),
 214 };
 215
 216 static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 217         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_DEFAULT_BIT),
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 223         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 224 };
 225
 226 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
 227 {
 228         struct smu_11_0_cmn2aisc_mapping mapping;
 229
 230         if (index >= SMU_TABLE_COUNT)
 231                 return -EINVAL;
 232
 233         mapping = vega20_table_map[index];
 234         if (!(mapping.valid_mapping)) {
 235                 return -EINVAL;
 236         }
 237
 238         return mapping.map_to;
 239 }
 240
 241 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 242 {
 243         struct smu_11_0_cmn2aisc_mapping mapping;
 244
 245         if (index >= SMU_POWER_SOURCE_COUNT)
 246                 return -EINVAL;
 247
 248         mapping = vega20_pwr_src_map[index];
 249         if (!(mapping.valid_mapping)) {
 250                 return -EINVAL;
 251         }
 252
 253         return mapping.map_to;
 254 }
 255
 256 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 257 {
 258         struct smu_11_0_cmn2aisc_mapping mapping;
 259
 260         if (index >= SMU_FEATURE_COUNT)
 261                 return -EINVAL;
 262
 263         mapping = vega20_feature_mask_map[index];
 264         if (!(mapping.valid_mapping)) {
 265                 return -EINVAL;
 266         }
 267
 268         return mapping.map_to;
 269 }
 270
 271 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 272 {
 273         struct smu_11_0_cmn2aisc_mapping mapping;
 274
 275         if (index >= SMU_CLK_COUNT)
 276                 return -EINVAL;
 277
 278         mapping = vega20_clk_map[index];
 279         if (!(mapping.valid_mapping)) {
 280                 return -EINVAL;
 281         }
 282
 283         return mapping.map_to;
 284 }
 285
 286 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 287 {
 288         struct smu_11_0_cmn2aisc_mapping mapping;
 289
 290         if (index >= SMU_MSG_MAX_COUNT)
 291                 return -EINVAL;
 292
 293         mapping = vega20_message_map[index];
 294         if (!(mapping.valid_mapping)) {
 295                 return -EINVAL;
 296         }
 297
 298         return mapping.map_to;
 299 }
 300
 301 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 302 {
 303         struct smu_11_0_cmn2aisc_mapping mapping;
 304
 305         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 306                 return -EINVAL;
 307
 308         mapping = vega20_workload_map[profile];
 309         if (!(mapping.valid_mapping)) {
 310                 return -EINVAL;
 311         }
 312
 313         return mapping.map_to;
 314 }
 315
 316 static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
 317 {
 318         struct smu_table_context *smu_table = &smu->smu_table;
 319
 320         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 321                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 322         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 323                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 324         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 325                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 326         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 327                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 328         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 329                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 330         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 331                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 332                        AMDGPU_GEM_DOMAIN_VRAM);
 333
 334         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 335         if (!smu_table->metrics_table)
 336                 return -ENOMEM;
 337         smu_table->metrics_time = 0;
 338
 339         return 0;
 340 }
 341
 342 static int vega20_allocate_dpm_context(struct smu_context *smu)
 343 {
 344         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 345
 346         if (smu_dpm->dpm_context)
 347                 return -EINVAL;
 348
 349         smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
 350                                        GFP_KERNEL);
 351         if (!smu_dpm->dpm_context)
 352                 return -ENOMEM;
 353
 354         if (smu_dpm->golden_dpm_context)
 355                 return -EINVAL;
 356
 357         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
 358                                               GFP_KERNEL);
 359         if (!smu_dpm->golden_dpm_context)
 360                 return -ENOMEM;
 361
 362         smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
 363
 364         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 365                                        GFP_KERNEL);
 366         if (!smu_dpm->dpm_current_power_state)
 367                 return -ENOMEM;
 368
 369         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 370                                        GFP_KERNEL);
 371         if (!smu_dpm->dpm_request_power_state)
 372                 return -ENOMEM;
 373
 374         return 0;
 375 }
 376
 377 static int vega20_setup_od8_information(struct smu_context *smu)
 378 {
 379         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 380         struct smu_table_context *table_context = &smu->smu_table;
 381         struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
 382
 383         uint32_t od_feature_count, od_feature_array_size,
 384                  od_setting_count, od_setting_array_size;
 385
 386         if (!table_context->power_play_table)
 387                 return -EINVAL;
 388
 389         powerplay_table = table_context->power_play_table;
 390
 391         if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
 392                 /* Setup correct ODFeatureCount, and store ODFeatureArray from
 393                  * powerplay table to od_feature_capabilities */
 394                 od_feature_count =
 395                         (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
 396                          ATOM_VEGA20_ODFEATURE_COUNT) ?
 397                         ATOM_VEGA20_ODFEATURE_COUNT :
 398                         le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
 399
 400                 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
 401
 402                 if (od8_settings->od_feature_capabilities)
 403                         return -EINVAL;
 404
 405                 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
 406                                                                  od_feature_array_size,
 407                                                                  GFP_KERNEL);
 408                 if (!od8_settings->od_feature_capabilities)
 409                         return -ENOMEM;
 410
 411                 /* Setup correct ODSettingCount, and store ODSettingArray from
 412                  * powerplay table to od_settings_max and od_setting_min */
 413                 od_setting_count =
 414                         (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
 415                          ATOM_VEGA20_ODSETTING_COUNT) ?
 416                         ATOM_VEGA20_ODSETTING_COUNT :
 417                         le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
 418
 419                 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
 420
 421                 if (od8_settings->od_settings_max)
 422                         return -EINVAL;
 423
 424                 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
 425                                                          od_setting_array_size,
 426                                                          GFP_KERNEL);
 427
 428                 if (!od8_settings->od_settings_max) {
 429                         kfree(od8_settings->od_feature_capabilities);
 430                         od8_settings->od_feature_capabilities = NULL;
 431                         return -ENOMEM;
 432                 }
 433
 434                 if (od8_settings->od_settings_min)
 435                         return -EINVAL;
 436
 437                 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
 438                                                          od_setting_array_size,
 439                                                          GFP_KERNEL);
 440
 441                 if (!od8_settings->od_settings_min) {
 442                         kfree(od8_settings->od_feature_capabilities);
 443                         od8_settings->od_feature_capabilities = NULL;
 444                         kfree(od8_settings->od_settings_max);
 445                         od8_settings->od_settings_max = NULL;
 446                         return -ENOMEM;
 447                 }
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int vega20_store_powerplay_table(struct smu_context *smu)
 454 {
 455         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 456         struct smu_table_context *table_context = &smu->smu_table;
 457
 458         if (!table_context->power_play_table)
 459                 return -EINVAL;
 460
 461         powerplay_table = table_context->power_play_table;
 462
 463         memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
 464                sizeof(PPTable_t));
 465
 466         table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
 467         table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
 468         table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
 469
 470         return 0;
 471 }
 472
 473 static int vega20_append_powerplay_table(struct smu_context *smu)
 474 {
 475         struct smu_table_context *table_context = &smu->smu_table;
 476         PPTable_t *smc_pptable = table_context->driver_pptable;
 477         struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
 478         int index, i, ret;
 479
 480         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 481                                            smc_dpm_info);
 482
 483         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 484                                       (uint8_t **)&smc_dpm_table);
 485         if (ret)
 486                 return ret;
 487
 488         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
 489         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
 490
 491         smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
 492         smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
 493         smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
 494         smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
 495
 496         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
 497         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
 498         smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
 499
 500         smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
 501         smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
 502         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
 503
 504         smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
 505         smc_pptable->SocOffset = smc_dpm_table->socoffset;
 506         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
 507
 508         smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
 509         smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
 510         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
 511
 512         smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
 513         smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
 514         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
 515
 516         smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
 517         smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
 518         smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
 519         smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
 520
 521         smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
 522         smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
 523         smc_pptable->Padding1 = smc_dpm_table->padding1;
 524         smc_pptable->Padding2 = smc_dpm_table->padding2;
 525
 526         smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
 527         smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
 528         smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
 529
 530         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
 531         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
 532         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
 533
 534         smc_pptable->UclkSpreadEnabled = 0;
 535         smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
 536         smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
 537
 538         smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
 539         smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
 540         smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
 541
 542         smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
 543         smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
 544         smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
 545
 546         for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
 547                 smc_pptable->I2cControllers[i].Enabled =
 548                         smc_dpm_table->i2ccontrollers[i].enabled;
 549                 smc_pptable->I2cControllers[i].SlaveAddress =
 550                         smc_dpm_table->i2ccontrollers[i].slaveaddress;
 551                 smc_pptable->I2cControllers[i].ControllerPort =
 552                         smc_dpm_table->i2ccontrollers[i].controllerport;
 553                 smc_pptable->I2cControllers[i].ThermalThrottler =
 554                         smc_dpm_table->i2ccontrollers[i].thermalthrottler;
 555                 smc_pptable->I2cControllers[i].I2cProtocol =
 556                         smc_dpm_table->i2ccontrollers[i].i2cprotocol;
 557                 smc_pptable->I2cControllers[i].I2cSpeed =
 558                         smc_dpm_table->i2ccontrollers[i].i2cspeed;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static int vega20_check_powerplay_table(struct smu_context *smu)
 565 {
 566         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 567         struct smu_table_context *table_context = &smu->smu_table;
 568
 569         powerplay_table = table_context->power_play_table;
 570
 571         if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
 572                 pr_err("Unsupported PPTable format!");
 573                 return -EINVAL;
 574         }
 575
 576         if (!powerplay_table->sHeader.structuresize) {
 577                 pr_err("Invalid PowerPlay Table!");
 578                 return -EINVAL;
 579         }
 580
 581         return 0;
 582 }
 583
 584 static int vega20_run_btc_afll(struct smu_context *smu)
 585 {
 586         return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 587 }
 588
 589 #define FEATURE_MASK(feature) (1ULL << feature)
 590 static int
 591 vega20_get_allowed_feature_mask(struct smu_context *smu,
 592                                   uint32_t *feature_mask, uint32_t num)
 593 {
 594         if (num > 2)
 595                 return -EINVAL;
 596
 597         memset(feature_mask, 0, sizeof(uint32_t) * num);
 598
 599         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 600                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 601                                 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 602                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 603                                 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
 604                                 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
 605                                 | FEATURE_MASK(FEATURE_ULV_BIT)
 606                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 607                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 608                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
 609                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 610                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 611                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 612                                 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
 613                                 | FEATURE_MASK(FEATURE_RM_BIT)
 614                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 615                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 616                                 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
 617                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 618                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 619                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 620                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 621                                 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
 622                                 | FEATURE_MASK(FEATURE_CG_BIT)
 623                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 624                                 | FEATURE_MASK(FEATURE_XGMI_BIT);
 625         return 0;
 626 }
 627
 628 static enum
 629 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
 630 {
 631         enum amd_pm_state_type pm_type;
 632         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 633
 634         if (!smu_dpm_ctx->dpm_context ||
 635             !smu_dpm_ctx->dpm_current_power_state)
 636                 return -EINVAL;
 637
 638         mutex_lock(&(smu->mutex));
 639         switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
 640         case SMU_STATE_UI_LABEL_BATTERY:
 641                 pm_type = POWER_STATE_TYPE_BATTERY;
 642                 break;
 643         case SMU_STATE_UI_LABEL_BALLANCED:
 644                 pm_type = POWER_STATE_TYPE_BALANCED;
 645                 break;
 646         case SMU_STATE_UI_LABEL_PERFORMANCE:
 647                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
 648                 break;
 649         default:
 650                 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
 651                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 652                 else
 653                         pm_type = POWER_STATE_TYPE_DEFAULT;
 654                 break;
 655         }
 656         mutex_unlock(&(smu->mutex));
 657
 658         return pm_type;
 659 }
 660
 661 static int
 662 vega20_set_single_dpm_table(struct smu_context *smu,
 663                             struct vega20_single_dpm_table *single_dpm_table,
 664                             PPCLK_e clk_id)
 665 {
 666         int ret = 0;
 667         uint32_t i, num_of_levels = 0, clk;
 668
 669         ret = smu_send_smc_msg_with_param(smu,
 670                         SMU_MSG_GetDpmFreqByIndex,
 671                         (clk_id << 16 | 0xFF));
 672         if (ret) {
 673                 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
 674                 return ret;
 675         }
 676
 677         smu_read_smc_arg(smu, &num_of_levels);
 678         if (!num_of_levels) {
 679                 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
 680                 return -EINVAL;
 681         }
 682
 683         single_dpm_table->count = num_of_levels;
 684
 685         for (i = 0; i < num_of_levels; i++) {
 686                 ret = smu_send_smc_msg_with_param(smu,
 687                                 SMU_MSG_GetDpmFreqByIndex,
 688                                 (clk_id << 16 | i));
 689                 if (ret) {
 690                         pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
 691                         return ret;
 692                 }
 693                 smu_read_smc_arg(smu, &clk);
 694                 if (!clk) {
 695                         pr_err("[GetDpmFreqByIndex] clk value is invalid!");
 696                         return -EINVAL;
 697                 }
 698                 single_dpm_table->dpm_levels[i].value = clk;
 699                 single_dpm_table->dpm_levels[i].enabled = true;
 700         }
 701         return 0;
 702 }
 703
 704 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
 705 {
 706         dpm_state->soft_min_level = 0x0;
 707         dpm_state->soft_max_level = 0xffff;
 708         dpm_state->hard_min_level = 0x0;
 709         dpm_state->hard_max_level = 0xffff;
 710 }
 711
 712 static int vega20_set_default_dpm_table(struct smu_context *smu)
 713 {
 714         int ret;
 715
 716         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 717         struct vega20_dpm_table *dpm_table = NULL;
 718         struct vega20_single_dpm_table *single_dpm_table;
 719
 720         dpm_table = smu_dpm->dpm_context;
 721
 722         /* socclk */
 723         single_dpm_table = &(dpm_table->soc_table);
 724
 725         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 726                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 727                                                   PPCLK_SOCCLK);
 728                 if (ret) {
 729                         pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
 730                         return ret;
 731                 }
 732         } else {
 733                 single_dpm_table->count = 1;
 734                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 735         }
 736         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 737
 738         /* gfxclk */
 739         single_dpm_table = &(dpm_table->gfx_table);
 740
 741         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 742                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 743                                                   PPCLK_GFXCLK);
 744                 if (ret) {
 745                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 746                         return ret;
 747                 }
 748         } else {
 749                 single_dpm_table->count = 1;
 750                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 751         }
 752         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 753
 754         /* memclk */
 755         single_dpm_table = &(dpm_table->mem_table);
 756
 757         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 758                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 759                                                   PPCLK_UCLK);
 760                 if (ret) {
 761                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 762                         return ret;
 763                 }
 764         } else {
 765                 single_dpm_table->count = 1;
 766                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 767         }
 768         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 769
 770         /* eclk */
 771         single_dpm_table = &(dpm_table->eclk_table);
 772
 773         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
 774                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
 775                 if (ret) {
 776                         pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
 777                         return ret;
 778                 }
 779         } else {
 780                 single_dpm_table->count = 1;
 781                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
 782         }
 783         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 784
 785         /* vclk */
 786         single_dpm_table = &(dpm_table->vclk_table);
 787
 788         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 789                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
 790                 if (ret) {
 791                         pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
 792                         return ret;
 793                 }
 794         } else {
 795                 single_dpm_table->count = 1;
 796                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 797         }
 798         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 799
 800         /* dclk */
 801         single_dpm_table = &(dpm_table->dclk_table);
 802
 803         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 804                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
 805                 if (ret) {
 806                         pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
 807                         return ret;
 808                 }
 809         } else {
 810                 single_dpm_table->count = 1;
 811                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 812         }
 813         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 814
 815         /* dcefclk */
 816         single_dpm_table = &(dpm_table->dcef_table);
 817
 818         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 819                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 820                                                   PPCLK_DCEFCLK);
 821                 if (ret) {
 822                         pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
 823                         return ret;
 824                 }
 825         } else {
 826                 single_dpm_table->count = 1;
 827                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 828         }
 829         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 830
 831         /* pixclk */
 832         single_dpm_table = &(dpm_table->pixel_table);
 833
 834         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 835                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 836                                                   PPCLK_PIXCLK);
 837                 if (ret) {
 838                         pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
 839                         return ret;
 840                 }
 841         } else {
 842                 single_dpm_table->count = 0;
 843         }
 844         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 845
 846         /* dispclk */
 847         single_dpm_table = &(dpm_table->display_table);
 848
 849         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 850                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 851                                                   PPCLK_DISPCLK);
 852                 if (ret) {
 853                         pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
 854                         return ret;
 855                 }
 856         } else {
 857                 single_dpm_table->count = 0;
 858         }
 859         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 860
 861         /* phyclk */
 862         single_dpm_table = &(dpm_table->phy_table);
 863
 864         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 865                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 866                                                   PPCLK_PHYCLK);
 867                 if (ret) {
 868                         pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
 869                         return ret;
 870                 }
 871         } else {
 872                 single_dpm_table->count = 0;
 873         }
 874         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 875
 876         /* fclk */
 877         single_dpm_table = &(dpm_table->fclk_table);
 878
 879         if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
 880                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 881                                                   PPCLK_FCLK);
 882                 if (ret) {
 883                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 884                         return ret;
 885                 }
 886         } else {
 887                 single_dpm_table->count = 0;
 888         }
 889         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 890
 891         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 892                sizeof(struct vega20_dpm_table));
 893
 894         return 0;
 895 }
 896
 897 static int vega20_populate_umd_state_clk(struct smu_context *smu)
 898 {
 899         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 900         struct vega20_dpm_table *dpm_table = NULL;
 901         struct vega20_single_dpm_table *gfx_table = NULL;
 902         struct vega20_single_dpm_table *mem_table = NULL;
 903
 904         dpm_table = smu_dpm->dpm_context;
 905         gfx_table = &(dpm_table->gfx_table);
 906         mem_table = &(dpm_table->mem_table);
 907
 908         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 909         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 910
 911         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
 912             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
 913                 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
 914                 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
 915         }
 916
 917         smu->pstate_sclk = smu->pstate_sclk * 100;
 918         smu->pstate_mclk = smu->pstate_mclk * 100;
 919
 920         return 0;
 921 }
 922
 923 static int vega20_get_clk_table(struct smu_context *smu,
 924                         struct pp_clock_levels_with_latency *clocks,
 925                         struct vega20_single_dpm_table *dpm_table)
 926 {
 927         int i, count;
 928
 929         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 930         clocks->num_levels = count;
 931
 932         for (i = 0; i < count; i++) {
 933                 clocks->data[i].clocks_in_khz =
 934                         dpm_table->dpm_levels[i].value * 1000;
 935                 clocks->data[i].latency_in_us = 0;
 936         }
 937
 938         return 0;
 939 }
 940
 941 static int vega20_print_clk_levels(struct smu_context *smu,
 942                         enum smu_clk_type type, char *buf)
 943 {
 944         int i, now, size = 0;
 945         int ret = 0;
 946         uint32_t gen_speed, lane_width;
 947         struct amdgpu_device *adev = smu->adev;
 948         struct pp_clock_levels_with_latency clocks;
 949         struct vega20_single_dpm_table *single_dpm_table;
 950         struct smu_table_context *table_context = &smu->smu_table;
 951         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 952         struct vega20_dpm_table *dpm_table = NULL;
 953         struct vega20_od8_settings *od8_settings =
 954                 (struct vega20_od8_settings *)smu->od_settings;
 955         OverDriveTable_t *od_table =
 956                 (OverDriveTable_t *)(table_context->overdrive_table);
 957         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 958
 959         dpm_table = smu_dpm->dpm_context;
 960
 961         switch (type) {
 962         case SMU_SCLK:
 963                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 964                 if (ret) {
 965                         pr_err("Attempt to get current gfx clk Failed!");
 966                         return ret;
 967                 }
 968
 969                 single_dpm_table = &(dpm_table->gfx_table);
 970                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 971                 if (ret) {
 972                         pr_err("Attempt to get gfx clk levels Failed!");
 973                         return ret;
 974                 }
 975
 976                 for (i = 0; i < clocks.num_levels; i++)
 977                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 978                                         clocks.data[i].clocks_in_khz / 1000,
 979                                         (clocks.data[i].clocks_in_khz == now * 10)
 980                                         ? "*" : "");
 981                 break;
 982
 983         case SMU_MCLK:
 984                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 985                 if (ret) {
 986                         pr_err("Attempt to get current mclk Failed!");
 987                         return ret;
 988                 }
 989
 990                 single_dpm_table = &(dpm_table->mem_table);
 991                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 992                 if (ret) {
 993                         pr_err("Attempt to get memory clk levels Failed!");
 994                         return ret;
 995                 }
 996
 997                 for (i = 0; i < clocks.num_levels; i++)
 998                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 999                                 i, clocks.data[i].clocks_in_khz / 1000,
1000                                 (clocks.data[i].clocks_in_khz == now * 10)
1001                                 ? "*" : "");
1002                 break;
1003
1004         case SMU_SOCCLK:
1005                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
1006                 if (ret) {
1007                         pr_err("Attempt to get current socclk Failed!");
1008                         return ret;
1009                 }
1010
1011                 single_dpm_table = &(dpm_table->soc_table);
1012                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1013                 if (ret) {
1014                         pr_err("Attempt to get socclk levels Failed!");
1015                         return ret;
1016                 }
1017
1018                 for (i = 0; i < clocks.num_levels; i++)
1019                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1020                                 i, clocks.data[i].clocks_in_khz / 1000,
1021                                 (clocks.data[i].clocks_in_khz == now * 10)
1022                                 ? "*" : "");
1023                 break;
1024
1025         case SMU_FCLK:
1026                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1027                 if (ret) {
1028                         pr_err("Attempt to get current fclk Failed!");
1029                         return ret;
1030                 }
1031
1032                 single_dpm_table = &(dpm_table->fclk_table);
1033                 for (i = 0; i < single_dpm_table->count; i++)
1034                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1035                                 i, single_dpm_table->dpm_levels[i].value,
1036                                 (single_dpm_table->dpm_levels[i].value == now / 100)
1037                                 ? "*" : "");
1038                 break;
1039
1040         case SMU_DCEFCLK:
1041                 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1042                 if (ret) {
1043                         pr_err("Attempt to get current dcefclk Failed!");
1044                         return ret;
1045                 }
1046
1047                 single_dpm_table = &(dpm_table->dcef_table);
1048                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1049                 if (ret) {
1050                         pr_err("Attempt to get dcefclk levels Failed!");
1051                         return ret;
1052                 }
1053
1054                 for (i = 0; i < clocks.num_levels; i++)
1055                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1056                                 i, clocks.data[i].clocks_in_khz / 1000,
1057                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1058                 break;
1059
1060         case SMU_PCIE:
1061                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1062                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1063                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1064                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1065                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1066                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1067                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1068                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1069                                         (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1070                                         (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1071                                         (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1072                                         (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1073                                         (pptable->PcieLaneCount[i] == 1) ? "x1" :
1074                                         (pptable->PcieLaneCount[i] == 2) ? "x2" :
1075                                         (pptable->PcieLaneCount[i] == 3) ? "x4" :
1076                                         (pptable->PcieLaneCount[i] == 4) ? "x8" :
1077                                         (pptable->PcieLaneCount[i] == 5) ? "x12" :
1078                                         (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1079                                         pptable->LclkFreq[i],
1080                                         (gen_speed == pptable->PcieGenSpeed[i]) &&
1081                                         (lane_width == pptable->PcieLaneCount[i]) ?
1082                                         "*" : "");
1083                 break;
1084
1085         case SMU_OD_SCLK:
1086                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1087                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1088                         size = sprintf(buf, "%s:\n", "OD_SCLK");
1089                         size += sprintf(buf + size, "0: %10uMhz\n",
1090                                         od_table->GfxclkFmin);
1091                         size += sprintf(buf + size, "1: %10uMhz\n",
1092                                         od_table->GfxclkFmax);
1093                 }
1094
1095                 break;
1096
1097         case SMU_OD_MCLK:
1098                 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1099                         size = sprintf(buf, "%s:\n", "OD_MCLK");
1100                         size += sprintf(buf + size, "1: %10uMhz\n",
1101                                          od_table->UclkFmax);
1102                 }
1103
1104                 break;
1105
1106         case SMU_OD_VDDC_CURVE:
1107                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1108                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1109                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1110                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1111                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1112                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1113                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1114                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1115                                         od_table->GfxclkFreq1,
1116                                         od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1117                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1118                                         od_table->GfxclkFreq2,
1119                                         od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1120                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1121                                         od_table->GfxclkFreq3,
1122                                         od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1123                 }
1124
1125                 break;
1126
1127         case SMU_OD_RANGE:
1128                 size = sprintf(buf, "%s:\n", "OD_RANGE");
1129
1130                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1131                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1132                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1133                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1134                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1135                 }
1136
1137                 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1138                         single_dpm_table = &(dpm_table->mem_table);
1139                         ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1140                         if (ret) {
1141                                 pr_err("Attempt to get memory clk levels Failed!");
1142                                 return ret;
1143                         }
1144
1145                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1146                                         clocks.data[0].clocks_in_khz / 1000,
1147                                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1148                 }
1149
1150                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1151                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1152                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1153                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1154                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1155                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1156                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1157                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1158                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1159                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1160                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1161                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1162                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1163                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1164                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1165                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1166                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1167                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1168                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1169                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1170                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1171                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1172                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1173                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1174                 }
1175
1176                 break;
1177
1178         default:
1179                 break;
1180         }
1181         return size;
1182 }
1183
1184 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1185                                    uint32_t feature_mask)
1186 {
1187         struct vega20_dpm_table *dpm_table;
1188         struct vega20_single_dpm_table *single_dpm_table;
1189         uint32_t freq;
1190         int ret = 0;
1191
1192         dpm_table = smu->smu_dpm.dpm_context;
1193
1194         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1195             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1196                 single_dpm_table = &(dpm_table->gfx_table);
1197                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1198                         single_dpm_table->dpm_state.soft_min_level;
1199                 ret = smu_send_smc_msg_with_param(smu,
1200                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1201                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1202                 if (ret) {
1203                         pr_err("Failed to set soft %s gfxclk !\n",
1204                                                 max ? "max" : "min");
1205                         return ret;
1206                 }
1207         }
1208
1209         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1210             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1211                 single_dpm_table = &(dpm_table->mem_table);
1212                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1213                         single_dpm_table->dpm_state.soft_min_level;
1214                 ret = smu_send_smc_msg_with_param(smu,
1215                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1216                         (PPCLK_UCLK << 16) | (freq & 0xffff));
1217                 if (ret) {
1218                         pr_err("Failed to set soft %s memclk !\n",
1219                                                 max ? "max" : "min");
1220                         return ret;
1221                 }
1222         }
1223
1224         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1225             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1226                 single_dpm_table = &(dpm_table->soc_table);
1227                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1228                         single_dpm_table->dpm_state.soft_min_level;
1229                 ret = smu_send_smc_msg_with_param(smu,
1230                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1231                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1232                 if (ret) {
1233                         pr_err("Failed to set soft %s socclk !\n",
1234                                                 max ? "max" : "min");
1235                         return ret;
1236                 }
1237         }
1238
1239         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1240             (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1241                 single_dpm_table = &(dpm_table->fclk_table);
1242                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1243                         single_dpm_table->dpm_state.soft_min_level;
1244                 ret = smu_send_smc_msg_with_param(smu,
1245                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1246                         (PPCLK_FCLK << 16) | (freq & 0xffff));
1247                 if (ret) {
1248                         pr_err("Failed to set soft %s fclk !\n",
1249                                                 max ? "max" : "min");
1250                         return ret;
1251                 }
1252         }
1253
1254         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1255             (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1256                 single_dpm_table = &(dpm_table->dcef_table);
1257                 freq = single_dpm_table->dpm_state.hard_min_level;
1258                 if (!max) {
1259                         ret = smu_send_smc_msg_with_param(smu,
1260                                 SMU_MSG_SetHardMinByFreq,
1261                                 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1262                         if (ret) {
1263                                 pr_err("Failed to set hard min dcefclk !\n");
1264                                 return ret;
1265                         }
1266                 }
1267         }
1268
1269         return ret;
1270 }
1271
1272 static int vega20_force_clk_levels(struct smu_context *smu,
1273                         enum  smu_clk_type clk_type, uint32_t mask)
1274 {
1275         struct vega20_dpm_table *dpm_table;
1276         struct vega20_single_dpm_table *single_dpm_table;
1277         uint32_t soft_min_level, soft_max_level, hard_min_level;
1278         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1279         int ret = 0;
1280
1281         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1282                 pr_info("force clock level is for dpm manual mode only.\n");
1283                 return -EINVAL;
1284         }
1285
1286         mutex_lock(&(smu->mutex));
1287
1288         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1289         soft_max_level = mask ? (fls(mask) - 1) : 0;
1290
1291         dpm_table = smu->smu_dpm.dpm_context;
1292
1293         switch (clk_type) {
1294         case SMU_SCLK:
1295                 single_dpm_table = &(dpm_table->gfx_table);
1296
1297                 if (soft_max_level >= single_dpm_table->count) {
1298                         pr_err("Clock level specified %d is over max allowed %d\n",
1299                                         soft_max_level, single_dpm_table->count - 1);
1300                         ret = -EINVAL;
1301                         break;
1302                 }
1303
1304                 single_dpm_table->dpm_state.soft_min_level =
1305                         single_dpm_table->dpm_levels[soft_min_level].value;
1306                 single_dpm_table->dpm_state.soft_max_level =
1307                         single_dpm_table->dpm_levels[soft_max_level].value;
1308
1309                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1310                 if (ret) {
1311                         pr_err("Failed to upload boot level to lowest!\n");
1312                         break;
1313                 }
1314
1315                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1316                 if (ret)
1317                         pr_err("Failed to upload dpm max level to highest!\n");
1318
1319                 break;
1320
1321         case SMU_MCLK:
1322                 single_dpm_table = &(dpm_table->mem_table);
1323
1324                 if (soft_max_level >= single_dpm_table->count) {
1325                         pr_err("Clock level specified %d is over max allowed %d\n",
1326                                         soft_max_level, single_dpm_table->count - 1);
1327                         ret = -EINVAL;
1328                         break;
1329                 }
1330
1331                 single_dpm_table->dpm_state.soft_min_level =
1332                         single_dpm_table->dpm_levels[soft_min_level].value;
1333                 single_dpm_table->dpm_state.soft_max_level =
1334                         single_dpm_table->dpm_levels[soft_max_level].value;
1335
1336                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1337                 if (ret) {
1338                         pr_err("Failed to upload boot level to lowest!\n");
1339                         break;
1340                 }
1341
1342                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1343                 if (ret)
1344                         pr_err("Failed to upload dpm max level to highest!\n");
1345
1346                 break;
1347
1348         case SMU_SOCCLK:
1349                 single_dpm_table = &(dpm_table->soc_table);
1350
1351                 if (soft_max_level >= single_dpm_table->count) {
1352                         pr_err("Clock level specified %d is over max allowed %d\n",
1353                                         soft_max_level, single_dpm_table->count - 1);
1354                         ret = -EINVAL;
1355                         break;
1356                 }
1357
1358                 single_dpm_table->dpm_state.soft_min_level =
1359                         single_dpm_table->dpm_levels[soft_min_level].value;
1360                 single_dpm_table->dpm_state.soft_max_level =
1361                         single_dpm_table->dpm_levels[soft_max_level].value;
1362
1363                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1364                 if (ret) {
1365                         pr_err("Failed to upload boot level to lowest!\n");
1366                         break;
1367                 }
1368
1369                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1370                 if (ret)
1371                         pr_err("Failed to upload dpm max level to highest!\n");
1372
1373                 break;
1374
1375         case SMU_FCLK:
1376                 single_dpm_table = &(dpm_table->fclk_table);
1377
1378                 if (soft_max_level >= single_dpm_table->count) {
1379                         pr_err("Clock level specified %d is over max allowed %d\n",
1380                                         soft_max_level, single_dpm_table->count - 1);
1381                         ret = -EINVAL;
1382                         break;
1383                 }
1384
1385                 single_dpm_table->dpm_state.soft_min_level =
1386                         single_dpm_table->dpm_levels[soft_min_level].value;
1387                 single_dpm_table->dpm_state.soft_max_level =
1388                         single_dpm_table->dpm_levels[soft_max_level].value;
1389
1390                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1391                 if (ret) {
1392                         pr_err("Failed to upload boot level to lowest!\n");
1393                         break;
1394                 }
1395
1396                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1397                 if (ret)
1398                         pr_err("Failed to upload dpm max level to highest!\n");
1399
1400                 break;
1401
1402         case SMU_DCEFCLK:
1403                 hard_min_level = soft_min_level;
1404                 single_dpm_table = &(dpm_table->dcef_table);
1405
1406                 if (hard_min_level >= single_dpm_table->count) {
1407                         pr_err("Clock level specified %d is over max allowed %d\n",
1408                                         hard_min_level, single_dpm_table->count - 1);
1409                         ret = -EINVAL;
1410                         break;
1411                 }
1412
1413                 single_dpm_table->dpm_state.hard_min_level =
1414                         single_dpm_table->dpm_levels[hard_min_level].value;
1415
1416                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1417                 if (ret)
1418                         pr_err("Failed to upload boot level to lowest!\n");
1419
1420                 break;
1421
1422         case SMU_PCIE:
1423                 if (soft_min_level >= NUM_LINK_LEVELS ||
1424                     soft_max_level >= NUM_LINK_LEVELS) {
1425                         ret = -EINVAL;
1426                         break;
1427                 }
1428
1429                 ret = smu_send_smc_msg_with_param(smu,
1430                                 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1431                 if (ret)
1432                         pr_err("Failed to set min link dpm level!\n");
1433
1434                 break;
1435
1436         default:
1437                 break;
1438         }
1439
1440         mutex_unlock(&(smu->mutex));
1441         return ret;
1442 }
1443
1444 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1445                                                  enum smu_clk_type clk_type,
1446                                                  struct pp_clock_levels_with_latency *clocks)
1447 {
1448         int ret;
1449         struct vega20_single_dpm_table *single_dpm_table;
1450         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1451         struct vega20_dpm_table *dpm_table = NULL;
1452
1453         dpm_table = smu_dpm->dpm_context;
1454
1455         mutex_lock(&smu->mutex);
1456
1457         switch (clk_type) {
1458         case SMU_GFXCLK:
1459                 single_dpm_table = &(dpm_table->gfx_table);
1460                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1461                 break;
1462         case SMU_MCLK:
1463                 single_dpm_table = &(dpm_table->mem_table);
1464                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1465                 break;
1466         case SMU_DCEFCLK:
1467                 single_dpm_table = &(dpm_table->dcef_table);
1468                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1469                 break;
1470         case SMU_SOCCLK:
1471                 single_dpm_table = &(dpm_table->soc_table);
1472                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1473                 break;
1474         default:
1475                 ret = -EINVAL;
1476         }
1477
1478         mutex_unlock(&smu->mutex);
1479         return ret;
1480 }
1481
1482 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1483                                                      uint32_t *voltage,
1484                                                      uint32_t freq)
1485 {
1486         int ret;
1487
1488         ret = smu_send_smc_msg_with_param(smu,
1489                         SMU_MSG_GetAVFSVoltageByDpm,
1490                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1491         if (ret) {
1492                 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1493                 return ret;
1494         }
1495
1496         smu_read_smc_arg(smu, voltage);
1497         *voltage = *voltage / VOLTAGE_SCALE;
1498
1499         return 0;
1500 }
1501
1502 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1503 {
1504         struct smu_table_context *table_context = &smu->smu_table;
1505         OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1506         struct vega20_od8_settings *od8_settings = NULL;
1507         PPTable_t *smc_pptable = table_context->driver_pptable;
1508         int i, ret;
1509
1510         if (smu->od_settings)
1511                 return -EINVAL;
1512
1513         od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1514
1515         if (!od8_settings)
1516                 return -ENOMEM;
1517
1518         smu->od_settings = (void *)od8_settings;
1519
1520         ret = vega20_setup_od8_information(smu);
1521         if (ret) {
1522                 pr_err("Retrieve board OD limits failed!\n");
1523                 return ret;
1524         }
1525
1526         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1527                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1528                     od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1529                     od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1530                     (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1531                      od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1532                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1533                                 OD8_GFXCLK_LIMITS;
1534                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1535                                 OD8_GFXCLK_LIMITS;
1536                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1537                                 od_table->GfxclkFmin;
1538                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1539                                 od_table->GfxclkFmax;
1540                 }
1541
1542                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1543                     (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1544                      smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1545                     (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1546                      smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1547                     (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1548                      od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1549                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1550                                 OD8_GFXCLK_CURVE;
1551                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1552                                 OD8_GFXCLK_CURVE;
1553                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1554                                 OD8_GFXCLK_CURVE;
1555                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1556                                 OD8_GFXCLK_CURVE;
1557                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1558                                 OD8_GFXCLK_CURVE;
1559                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1560                                 OD8_GFXCLK_CURVE;
1561
1562                         od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1563                         od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1564                         od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1565                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1566                                 od_table->GfxclkFreq1;
1567                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1568                                 od_table->GfxclkFreq2;
1569                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1570                                 od_table->GfxclkFreq3;
1571
1572                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1573                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1574                                 od_table->GfxclkFreq1);
1575                         if (ret)
1576                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1577                         od_table->GfxclkVolt1 =
1578                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1579                                 * VOLTAGE_SCALE;
1580                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1581                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1582                                 od_table->GfxclkFreq2);
1583                         if (ret)
1584                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1585                         od_table->GfxclkVolt2 =
1586                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1587                                 * VOLTAGE_SCALE;
1588                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1589                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1590                                 od_table->GfxclkFreq3);
1591                         if (ret)
1592                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1593                         od_table->GfxclkVolt3 =
1594                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1595                                 * VOLTAGE_SCALE;
1596                 }
1597         }
1598
1599         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1600                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1601                     od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1602                     od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1603                     (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1604                      od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1605                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1606                                 OD8_UCLK_MAX;
1607                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1608                                 od_table->UclkFmax;
1609                 }
1610         }
1611
1612         if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1613             od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1614             od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1615             od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1616             od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1617                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1618                         OD8_POWER_LIMIT;
1619                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1620                         od_table->OverDrivePct;
1621         }
1622
1623         if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1624                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1625                     od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1626                     od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1627                     (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1628                      od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1629                         od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1630                                 OD8_ACOUSTIC_LIMIT_SCLK;
1631                         od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1632                                 od_table->FanMaximumRpm;
1633                 }
1634
1635                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1636                     od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1637                     od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1638                     (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1639                      od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1640                         od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1641                                 OD8_FAN_SPEED_MIN;
1642                         od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1643                                 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1644                 }
1645         }
1646
1647         if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1648                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1649                     od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1650                     od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1651                     (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1652                      od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1653                         od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1654                                 OD8_TEMPERATURE_FAN;
1655                         od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1656                                 od_table->FanTargetTemperature;
1657                 }
1658
1659                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1660                     od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1661                     od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1662                     (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1663                      od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1664                         od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1665                                 OD8_TEMPERATURE_SYSTEM;
1666                         od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1667                                 od_table->MaxOpTemp;
1668                 }
1669         }
1670
1671         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1672                 if (od8_settings->od8_settings_array[i].feature_id) {
1673                         od8_settings->od8_settings_array[i].min_value =
1674                                 od8_settings->od_settings_min[i];
1675                         od8_settings->od8_settings_array[i].max_value =
1676                                 od8_settings->od_settings_max[i];
1677                         od8_settings->od8_settings_array[i].current_value =
1678                                 od8_settings->od8_settings_array[i].default_value;
1679                 } else {
1680                         od8_settings->od8_settings_array[i].min_value = 0;
1681                         od8_settings->od8_settings_array[i].max_value = 0;
1682                         od8_settings->od8_settings_array[i].current_value = 0;
1683                 }
1684         }
1685
1686         return 0;
1687 }
1688
1689 static int vega20_get_metrics_table(struct smu_context *smu,
1690                                     SmuMetrics_t *metrics_table)
1691 {
1692         struct smu_table_context *smu_table= &smu->smu_table;
1693         int ret = 0;
1694
1695         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1696                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1697                                 (void *)smu_table->metrics_table, false);
1698                 if (ret) {
1699                         pr_info("Failed to export SMU metrics table!\n");
1700                         return ret;
1701                 }
1702                 smu_table->metrics_time = jiffies;
1703         }
1704
1705         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1706
1707         return ret;
1708 }
1709
1710 static int vega20_set_default_od_settings(struct smu_context *smu,
1711                                           bool initialize)
1712 {
1713         struct smu_table_context *table_context = &smu->smu_table;
1714         int ret;
1715
1716         if (initialize) {
1717                 if (table_context->overdrive_table)
1718                         return -EINVAL;
1719
1720                 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1721
1722                 if (!table_context->overdrive_table)
1723                         return -ENOMEM;
1724
1725                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1726                                        table_context->overdrive_table, false);
1727                 if (ret) {
1728                         pr_err("Failed to export over drive table!\n");
1729                         return ret;
1730                 }
1731
1732                 ret = vega20_set_default_od8_setttings(smu);
1733                 if (ret)
1734                         return ret;
1735         }
1736
1737         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1738                                table_context->overdrive_table, true);
1739         if (ret) {
1740                 pr_err("Failed to import over drive table!\n");
1741                 return ret;
1742         }
1743
1744         return 0;
1745 }
1746
1747 static int vega20_get_od_percentage(struct smu_context *smu,
1748                                     enum smu_clk_type clk_type)
1749 {
1750         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1751         struct vega20_dpm_table *dpm_table = NULL;
1752         struct vega20_dpm_table *golden_table = NULL;
1753         struct vega20_single_dpm_table *single_dpm_table;
1754         struct vega20_single_dpm_table *golden_dpm_table;
1755         int value, golden_value;
1756
1757         dpm_table = smu_dpm->dpm_context;
1758         golden_table = smu_dpm->golden_dpm_context;
1759
1760         switch (clk_type) {
1761         case SMU_OD_SCLK:
1762                 single_dpm_table = &(dpm_table->gfx_table);
1763                 golden_dpm_table = &(golden_table->gfx_table);
1764                 break;
1765         case SMU_OD_MCLK:
1766                 single_dpm_table = &(dpm_table->mem_table);
1767                 golden_dpm_table = &(golden_table->mem_table);
1768                 break;
1769         default:
1770                 return -EINVAL;
1771                 break;
1772         }
1773
1774         value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1775         golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1776
1777         value -= golden_value;
1778         value = DIV_ROUND_UP(value * 100, golden_value);
1779
1780         return value;
1781 }
1782
1783 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1784 {
1785         DpmActivityMonitorCoeffInt_t activity_monitor;
1786         uint32_t i, size = 0;
1787         int16_t workload_type = 0;
1788         static const char *profile_name[] = {
1789                                         "BOOTUP_DEFAULT",
1790                                         "3D_FULL_SCREEN",
1791                                         "POWER_SAVING",
1792                                         "VIDEO",
1793                                         "VR",
1794                                         "COMPUTE",
1795                                         "CUSTOM"};
1796         static const char *title[] = {
1797                         "PROFILE_INDEX(NAME)",
1798                         "CLOCK_TYPE(NAME)",
1799                         "FPS",
1800                         "UseRlcBusy",
1801                         "MinActiveFreqType",
1802                         "MinActiveFreq",
1803                         "BoosterFreqType",
1804                         "BoosterFreq",
1805                         "PD_Data_limit_c",
1806                         "PD_Data_error_coeff",
1807                         "PD_Data_error_rate_coeff"};
1808         int result = 0;
1809
1810         if (!smu->pm_enabled || !buf)
1811                 return -EINVAL;
1812
1813         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1814                         title[0], title[1], title[2], title[3], title[4], title[5],
1815                         title[6], title[7], title[8], title[9], title[10]);
1816
1817         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1818                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1819                 workload_type = smu_workload_get_type(smu, i);
1820                 if (workload_type < 0)
1821                         return -EINVAL;
1822
1823                 result = smu_update_table(smu,
1824                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1825                                           (void *)(&activity_monitor), false);
1826                 if (result) {
1827                         pr_err("[%s] Failed to get activity monitor!", __func__);
1828                         return result;
1829                 }
1830
1831                 size += sprintf(buf + size, "%2d %14s%s:\n",
1832                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1833
1834                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1835                         " ",
1836                         0,
1837                         "GFXCLK",
1838                         activity_monitor.Gfx_FPS,
1839                         activity_monitor.Gfx_UseRlcBusy,
1840                         activity_monitor.Gfx_MinActiveFreqType,
1841                         activity_monitor.Gfx_MinActiveFreq,
1842                         activity_monitor.Gfx_BoosterFreqType,
1843                         activity_monitor.Gfx_BoosterFreq,
1844                         activity_monitor.Gfx_PD_Data_limit_c,
1845                         activity_monitor.Gfx_PD_Data_error_coeff,
1846                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1847
1848                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1849                         " ",
1850                         1,
1851                         "SOCCLK",
1852                         activity_monitor.Soc_FPS,
1853                         activity_monitor.Soc_UseRlcBusy,
1854                         activity_monitor.Soc_MinActiveFreqType,
1855                         activity_monitor.Soc_MinActiveFreq,
1856                         activity_monitor.Soc_BoosterFreqType,
1857                         activity_monitor.Soc_BoosterFreq,
1858                         activity_monitor.Soc_PD_Data_limit_c,
1859                         activity_monitor.Soc_PD_Data_error_coeff,
1860                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1861
1862                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1863                         " ",
1864                         2,
1865                         "UCLK",
1866                         activity_monitor.Mem_FPS,
1867                         activity_monitor.Mem_UseRlcBusy,
1868                         activity_monitor.Mem_MinActiveFreqType,
1869                         activity_monitor.Mem_MinActiveFreq,
1870                         activity_monitor.Mem_BoosterFreqType,
1871                         activity_monitor.Mem_BoosterFreq,
1872                         activity_monitor.Mem_PD_Data_limit_c,
1873                         activity_monitor.Mem_PD_Data_error_coeff,
1874                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1875
1876                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1877                         " ",
1878                         3,
1879                         "FCLK",
1880                         activity_monitor.Fclk_FPS,
1881                         activity_monitor.Fclk_UseRlcBusy,
1882                         activity_monitor.Fclk_MinActiveFreqType,
1883                         activity_monitor.Fclk_MinActiveFreq,
1884                         activity_monitor.Fclk_BoosterFreqType,
1885                         activity_monitor.Fclk_BoosterFreq,
1886                         activity_monitor.Fclk_PD_Data_limit_c,
1887                         activity_monitor.Fclk_PD_Data_error_coeff,
1888                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1889         }
1890
1891         return size;
1892 }
1893
1894 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1895 {
1896         DpmActivityMonitorCoeffInt_t activity_monitor;
1897         int workload_type = 0, ret = 0;
1898
1899         smu->power_profile_mode = input[size];
1900
1901         if (!smu->pm_enabled)
1902                 return ret;
1903         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1904                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1905                 return -EINVAL;
1906         }
1907
1908         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1909                 ret = smu_update_table(smu,
1910                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1911                                        (void *)(&activity_monitor), false);
1912                 if (ret) {
1913                         pr_err("[%s] Failed to get activity monitor!", __func__);
1914                         return ret;
1915                 }
1916
1917                 switch (input[0]) {
1918                 case 0: /* Gfxclk */
1919                         activity_monitor.Gfx_FPS = input[1];
1920                         activity_monitor.Gfx_UseRlcBusy = input[2];
1921                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1922                         activity_monitor.Gfx_MinActiveFreq = input[4];
1923                         activity_monitor.Gfx_BoosterFreqType = input[5];
1924                         activity_monitor.Gfx_BoosterFreq = input[6];
1925                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1926                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1927                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1928                         break;
1929                 case 1: /* Socclk */
1930                         activity_monitor.Soc_FPS = input[1];
1931                         activity_monitor.Soc_UseRlcBusy = input[2];
1932                         activity_monitor.Soc_MinActiveFreqType = input[3];
1933                         activity_monitor.Soc_MinActiveFreq = input[4];
1934                         activity_monitor.Soc_BoosterFreqType = input[5];
1935                         activity_monitor.Soc_BoosterFreq = input[6];
1936                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1937                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1938                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1939                         break;
1940                 case 2: /* Uclk */
1941                         activity_monitor.Mem_FPS = input[1];
1942                         activity_monitor.Mem_UseRlcBusy = input[2];
1943                         activity_monitor.Mem_MinActiveFreqType = input[3];
1944                         activity_monitor.Mem_MinActiveFreq = input[4];
1945                         activity_monitor.Mem_BoosterFreqType = input[5];
1946                         activity_monitor.Mem_BoosterFreq = input[6];
1947                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1948                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1949                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1950                         break;
1951                 case 3: /* Fclk */
1952                         activity_monitor.Fclk_FPS = input[1];
1953                         activity_monitor.Fclk_UseRlcBusy = input[2];
1954                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1955                         activity_monitor.Fclk_MinActiveFreq = input[4];
1956                         activity_monitor.Fclk_BoosterFreqType = input[5];
1957                         activity_monitor.Fclk_BoosterFreq = input[6];
1958                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1959                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1960                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1961                         break;
1962                 }
1963
1964                 ret = smu_update_table(smu,
1965                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1966                                        (void *)(&activity_monitor), true);
1967                 if (ret) {
1968                         pr_err("[%s] Failed to set activity monitor!", __func__);
1969                         return ret;
1970                 }
1971         }
1972
1973         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1974         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1975         if (workload_type < 0)
1976                 return -EINVAL;
1977         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1978                                     1 << workload_type);
1979
1980         return ret;
1981 }
1982
1983 static int
1984 vega20_get_profiling_clk_mask(struct smu_context *smu,
1985                               enum amd_dpm_forced_level level,
1986                               uint32_t *sclk_mask,
1987                               uint32_t *mclk_mask,
1988                               uint32_t *soc_mask)
1989 {
1990         struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1991         struct vega20_single_dpm_table *gfx_dpm_table;
1992         struct vega20_single_dpm_table *mem_dpm_table;
1993         struct vega20_single_dpm_table *soc_dpm_table;
1994
1995         if (!smu->smu_dpm.dpm_context)
1996                 return -EINVAL;
1997
1998         gfx_dpm_table = &dpm_table->gfx_table;
1999         mem_dpm_table = &dpm_table->mem_table;
2000         soc_dpm_table = &dpm_table->soc_table;
2001
2002         *sclk_mask = 0;
2003         *mclk_mask = 0;
2004         *soc_mask  = 0;
2005
2006         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2007             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2008             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2009                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2010                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2011                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2012         }
2013
2014         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2015                 *sclk_mask = 0;
2016         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2017                 *mclk_mask = 0;
2018         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2019                 *sclk_mask = gfx_dpm_table->count - 1;
2020                 *mclk_mask = mem_dpm_table->count - 1;
2021                 *soc_mask  = soc_dpm_table->count - 1;
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int
2028 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2029                                      struct vega20_single_dpm_table *dpm_table)
2030 {
2031         int ret = 0;
2032         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2033         if (!smu_dpm_ctx->dpm_context)
2034                 return -EINVAL;
2035
2036         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2037                 if (dpm_table->count <= 0) {
2038                         pr_err("[%s] Dpm table has no entry!", __func__);
2039                                 return -EINVAL;
2040                 }
2041
2042                 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2043                         pr_err("[%s] Dpm table has too many entries!", __func__);
2044                                 return -EINVAL;
2045                 }
2046
2047                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2048                 ret = smu_send_smc_msg_with_param(smu,
2049                                 SMU_MSG_SetHardMinByFreq,
2050                                 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2051                 if (ret) {
2052                         pr_err("[%s] Set hard min uclk failed!", __func__);
2053                                 return ret;
2054                 }
2055         }
2056
2057         return ret;
2058 }
2059
2060 static int vega20_pre_display_config_changed(struct smu_context *smu)
2061 {
2062         int ret = 0;
2063         struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2064
2065         if (!smu->smu_dpm.dpm_context)
2066                 return -EINVAL;
2067
2068         smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2069         ret = vega20_set_uclk_to_highest_dpm_level(smu,
2070                                                    &dpm_table->mem_table);
2071         if (ret)
2072                 pr_err("Failed to set uclk to highest dpm level");
2073         return ret;
2074 }
2075
2076 static int vega20_display_config_changed(struct smu_context *smu)
2077 {
2078         int ret = 0;
2079
2080         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2081             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2082                 ret = smu_write_watermarks_table(smu);
2083                 if (ret) {
2084                         pr_err("Failed to update WMTABLE!");
2085                         return ret;
2086                 }
2087                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2088         }
2089
2090         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2091             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2092             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2093                 smu_send_smc_msg_with_param(smu,
2094                                             SMU_MSG_NumOfDisplays,
2095                                             smu->display_config->num_display);
2096         }
2097
2098         return ret;
2099 }
2100
2101 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2102 {
2103         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2104         struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2105         struct vega20_single_dpm_table *dpm_table;
2106         bool vblank_too_short = false;
2107         bool disable_mclk_switching;
2108         uint32_t i, latency;
2109
2110         disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2111                                   !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2112         latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2113
2114         /* gfxclk */
2115         dpm_table = &(dpm_ctx->gfx_table);
2116         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2117         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2118         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2119         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2120
2121                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2122                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2123                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2124                 }
2125
2126                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2127                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2128                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2129                 }
2130
2131                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2132                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2133                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2134                 }
2135
2136         /* memclk */
2137         dpm_table = &(dpm_ctx->mem_table);
2138         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2139         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2140         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2141         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2142
2143                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2144                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2145                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2146                 }
2147
2148                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2149                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2150                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2151                 }
2152
2153                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2154                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2155                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2156                 }
2157
2158         /* honour DAL's UCLK Hardmin */
2159         if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2160                 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2161
2162         /* Hardmin is dependent on displayconfig */
2163         if (disable_mclk_switching) {
2164                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2165                 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2166                         if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2167                                 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2168                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2169                                         break;
2170                                 }
2171                         }
2172                 }
2173         }
2174
2175         if (smu->display_config->nb_pstate_switch_disable)
2176                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2177
2178         /* vclk */
2179         dpm_table = &(dpm_ctx->vclk_table);
2180         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2181         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2182         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2183         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2184
2185                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2186                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2187                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2188                 }
2189
2190                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2191                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2192                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2193                 }
2194
2195         /* dclk */
2196         dpm_table = &(dpm_ctx->dclk_table);
2197         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2198         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2199         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2200         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2201
2202                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2203                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2204                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2205                 }
2206
2207                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2208                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2209                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2210                 }
2211
2212         /* socclk */
2213         dpm_table = &(dpm_ctx->soc_table);
2214         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2215         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2216         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2217         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2218
2219                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2220                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2221                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2222                 }
2223
2224                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2225                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2226                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2227                 }
2228
2229         /* eclk */
2230         dpm_table = &(dpm_ctx->eclk_table);
2231         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2232         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2233         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2234         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2235
2236                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2237                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2238                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2239                 }
2240
2241                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2242                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2243                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2244                 }
2245         return 0;
2246 }
2247
2248 static int
2249 vega20_notify_smc_dispaly_config(struct smu_context *smu)
2250 {
2251         struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2252         struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2253         struct smu_clocks min_clocks = {0};
2254         struct pp_display_clock_request clock_req;
2255         int ret = 0;
2256
2257         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2258         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2259         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2260
2261         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2262                 clock_req.clock_type = amd_pp_dcef_clock;
2263                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2264                 if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
2265                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2266                                 ret = smu_send_smc_msg_with_param(smu,
2267                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
2268                                                                   min_clocks.dcef_clock_in_sr/100);
2269                                 if (ret) {
2270                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
2271                                         return ret;
2272                                 }
2273                         }
2274                 } else {
2275                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2276                 }
2277         }
2278
2279         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2280                 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2281                 ret = smu_send_smc_msg_with_param(smu,
2282                                                   SMU_MSG_SetHardMinByFreq,
2283                                                   (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2284                 if (ret) {
2285                         pr_err("[%s] Set hard min uclk failed!", __func__);
2286                         return ret;
2287                 }
2288         }
2289
2290         return 0;
2291 }
2292
2293 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2294 {
2295         uint32_t i;
2296
2297         for (i = 0; i < table->count; i++) {
2298                 if (table->dpm_levels[i].enabled)
2299                         break;
2300         }
2301         if (i >= table->count) {
2302                 i = 0;
2303                 table->dpm_levels[i].enabled = true;
2304         }
2305
2306         return i;
2307 }
2308
2309 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2310 {
2311         int i = 0;
2312
2313         if (!table) {
2314                 pr_err("[%s] DPM Table does not exist!", __func__);
2315                 return 0;
2316         }
2317         if (table->count <= 0) {
2318                 pr_err("[%s] DPM Table has no entry!", __func__);
2319                 return 0;
2320         }
2321         if (table->count > MAX_REGULAR_DPM_NUMBER) {
2322                 pr_err("[%s] DPM Table has too many entries!", __func__);
2323                 return MAX_REGULAR_DPM_NUMBER - 1;
2324         }
2325
2326         for (i = table->count - 1; i >= 0; i--) {
2327                 if (table->dpm_levels[i].enabled)
2328                         break;
2329         }
2330         if (i < 0) {
2331                 i = 0;
2332                 table->dpm_levels[i].enabled = true;
2333         }
2334
2335         return i;
2336 }
2337
2338 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2339 {
2340         uint32_t soft_level;
2341         int ret = 0;
2342         struct vega20_dpm_table *dpm_table =
2343                 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2344
2345         if (highest)
2346                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2347         else
2348                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2349
2350         dpm_table->gfx_table.dpm_state.soft_min_level =
2351                 dpm_table->gfx_table.dpm_state.soft_max_level =
2352                 dpm_table->gfx_table.dpm_levels[soft_level].value;
2353
2354         if (highest)
2355                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2356         else
2357                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2358
2359         dpm_table->mem_table.dpm_state.soft_min_level =
2360                 dpm_table->mem_table.dpm_state.soft_max_level =
2361                 dpm_table->mem_table.dpm_levels[soft_level].value;
2362
2363         if (highest)
2364                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2365         else
2366                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2367
2368         dpm_table->soc_table.dpm_state.soft_min_level =
2369                 dpm_table->soc_table.dpm_state.soft_max_level =
2370                 dpm_table->soc_table.dpm_levels[soft_level].value;
2371
2372         ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2373         if (ret) {
2374                 pr_err("Failed to upload boot level to %s!\n",
2375                                 highest ? "highest" : "lowest");
2376                 return ret;
2377         }
2378
2379         ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2380         if (ret) {
2381                 pr_err("Failed to upload dpm max level to %s!\n!",
2382                                 highest ? "highest" : "lowest");
2383                 return ret;
2384         }
2385
2386         return ret;
2387 }
2388
2389 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2390 {
2391         uint32_t soft_min_level, soft_max_level;
2392         int ret = 0;
2393         struct vega20_dpm_table *dpm_table =
2394                 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2395
2396         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2397         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2398         dpm_table->gfx_table.dpm_state.soft_min_level =
2399                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2400         dpm_table->gfx_table.dpm_state.soft_max_level =
2401                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2402
2403         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2404         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2405         dpm_table->mem_table.dpm_state.soft_min_level =
2406                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2407         dpm_table->mem_table.dpm_state.soft_max_level =
2408                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2409
2410         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2411         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2412         dpm_table->soc_table.dpm_state.soft_min_level =
2413                 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2414         dpm_table->soc_table.dpm_state.soft_max_level =
2415                 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2416
2417         ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2418         if (ret) {
2419                 pr_err("Failed to upload DPM Bootup Levels!");
2420                 return ret;
2421         }
2422
2423         ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2424         if (ret) {
2425                 pr_err("Failed to upload DPM Max Levels!");
2426                 return ret;
2427         }
2428
2429         return ret;
2430 }
2431
2432 static int vega20_update_specified_od8_value(struct smu_context *smu,
2433                                              uint32_t index,
2434                                              uint32_t value)
2435 {
2436         struct smu_table_context *table_context = &smu->smu_table;
2437         OverDriveTable_t *od_table =
2438                 (OverDriveTable_t *)(table_context->overdrive_table);
2439         struct vega20_od8_settings *od8_settings =
2440                 (struct vega20_od8_settings *)smu->od_settings;
2441
2442         switch (index) {
2443         case OD8_SETTING_GFXCLK_FMIN:
2444                 od_table->GfxclkFmin = (uint16_t)value;
2445                 break;
2446
2447         case OD8_SETTING_GFXCLK_FMAX:
2448                 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2449                     value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2450                         return -EINVAL;
2451                 od_table->GfxclkFmax = (uint16_t)value;
2452                 break;
2453
2454         case OD8_SETTING_GFXCLK_FREQ1:
2455                 od_table->GfxclkFreq1 = (uint16_t)value;
2456                 break;
2457
2458         case OD8_SETTING_GFXCLK_VOLTAGE1:
2459                 od_table->GfxclkVolt1 = (uint16_t)value;
2460                 break;
2461
2462         case OD8_SETTING_GFXCLK_FREQ2:
2463                 od_table->GfxclkFreq2 = (uint16_t)value;
2464                 break;
2465
2466         case OD8_SETTING_GFXCLK_VOLTAGE2:
2467                 od_table->GfxclkVolt2 = (uint16_t)value;
2468                 break;
2469
2470         case OD8_SETTING_GFXCLK_FREQ3:
2471                 od_table->GfxclkFreq3 = (uint16_t)value;
2472                 break;
2473
2474         case OD8_SETTING_GFXCLK_VOLTAGE3:
2475                 od_table->GfxclkVolt3 = (uint16_t)value;
2476                 break;
2477
2478         case OD8_SETTING_UCLK_FMAX:
2479                 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2480                     value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2481                         return -EINVAL;
2482                 od_table->UclkFmax = (uint16_t)value;
2483                 break;
2484
2485         case OD8_SETTING_POWER_PERCENTAGE:
2486                 od_table->OverDrivePct = (int16_t)value;
2487                 break;
2488
2489         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2490                 od_table->FanMaximumRpm = (uint16_t)value;
2491                 break;
2492
2493         case OD8_SETTING_FAN_MIN_SPEED:
2494                 od_table->FanMinimumPwm = (uint16_t)value;
2495                 break;
2496
2497         case OD8_SETTING_FAN_TARGET_TEMP:
2498                 od_table->FanTargetTemperature = (uint16_t)value;
2499                 break;
2500
2501         case OD8_SETTING_OPERATING_TEMP_MAX:
2502                 od_table->MaxOpTemp = (uint16_t)value;
2503                 break;
2504         }
2505
2506         return 0;
2507 }
2508
2509 static int vega20_update_od8_settings(struct smu_context *smu,
2510                                       uint32_t index,
2511                                       uint32_t value)
2512 {
2513         struct smu_table_context *table_context = &smu->smu_table;
2514         int ret;
2515
2516         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2517                                table_context->overdrive_table, false);
2518         if (ret) {
2519                 pr_err("Failed to export over drive table!\n");
2520                 return ret;
2521         }
2522
2523         ret = vega20_update_specified_od8_value(smu, index, value);
2524         if (ret)
2525                 return ret;
2526
2527         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2528                                table_context->overdrive_table, true);
2529         if (ret) {
2530                 pr_err("Failed to import over drive table!\n");
2531                 return ret;
2532         }
2533
2534         return 0;
2535 }
2536
2537 static int vega20_set_od_percentage(struct smu_context *smu,
2538                                     enum smu_clk_type clk_type,
2539                                     uint32_t value)
2540 {
2541         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2542         struct vega20_dpm_table *dpm_table = NULL;
2543         struct vega20_dpm_table *golden_table = NULL;
2544         struct vega20_single_dpm_table *single_dpm_table;
2545         struct vega20_single_dpm_table *golden_dpm_table;
2546         uint32_t od_clk, index;
2547         int ret = 0;
2548         int feature_enabled;
2549         PPCLK_e clk_id;
2550
2551         mutex_lock(&(smu->mutex));
2552
2553         dpm_table = smu_dpm->dpm_context;
2554         golden_table = smu_dpm->golden_dpm_context;
2555
2556         switch (clk_type) {
2557         case SMU_OD_SCLK:
2558                 single_dpm_table = &(dpm_table->gfx_table);
2559                 golden_dpm_table = &(golden_table->gfx_table);
2560                 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2561                 clk_id = PPCLK_GFXCLK;
2562                 index = OD8_SETTING_GFXCLK_FMAX;
2563                 break;
2564         case SMU_OD_MCLK:
2565                 single_dpm_table = &(dpm_table->mem_table);
2566                 golden_dpm_table = &(golden_table->mem_table);
2567                 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2568                 clk_id = PPCLK_UCLK;
2569                 index = OD8_SETTING_UCLK_FMAX;
2570                 break;
2571         default:
2572                 ret = -EINVAL;
2573                 break;
2574         }
2575
2576         if (ret)
2577                 goto set_od_failed;
2578
2579         od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2580         od_clk /= 100;
2581         od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2582
2583         ret = vega20_update_od8_settings(smu, index, od_clk);
2584         if (ret) {
2585                 pr_err("[Setoverdrive] failed to set od clk!\n");
2586                 goto set_od_failed;
2587         }
2588
2589         if (feature_enabled) {
2590                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2591                                                   clk_id);
2592                 if (ret) {
2593                         pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2594                         goto set_od_failed;
2595                 }
2596         } else {
2597                 single_dpm_table->count = 1;
2598                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2599         }
2600
2601         ret = smu_handle_task(smu, smu_dpm->dpm_level,
2602                               AMD_PP_TASK_READJUST_POWER_STATE);
2603
2604 set_od_failed:
2605         mutex_unlock(&(smu->mutex));
2606
2607         return ret;
2608 }
2609
2610 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2611                                      enum PP_OD_DPM_TABLE_COMMAND type,
2612                                      long *input, uint32_t size)
2613 {
2614         struct smu_table_context *table_context = &smu->smu_table;
2615         OverDriveTable_t *od_table =
2616                 (OverDriveTable_t *)(table_context->overdrive_table);
2617         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2618         struct vega20_dpm_table *dpm_table = NULL;
2619         struct vega20_single_dpm_table *single_dpm_table;
2620         struct vega20_od8_settings *od8_settings =
2621                 (struct vega20_od8_settings *)smu->od_settings;
2622         struct pp_clock_levels_with_latency clocks;
2623         int32_t input_index, input_clk, input_vol, i;
2624         int od8_id;
2625         int ret = 0;
2626
2627         dpm_table = smu_dpm->dpm_context;
2628
2629         if (!input) {
2630                 pr_warn("NULL user input for clock and voltage\n");
2631                 return -EINVAL;
2632         }
2633
2634         switch (type) {
2635         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2636                 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2637                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2638                         pr_info("Sclk min/max frequency overdrive not supported\n");
2639                         return -EOPNOTSUPP;
2640                 }
2641
2642                 for (i = 0; i < size; i += 2) {
2643                         if (i + 2 > size) {
2644                                 pr_info("invalid number of input parameters %d\n", size);
2645                                 return -EINVAL;
2646                         }
2647
2648                         input_index = input[i];
2649                         input_clk = input[i + 1];
2650
2651                         if (input_index != 0 && input_index != 1) {
2652                                 pr_info("Invalid index %d\n", input_index);
2653                                 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2654                                 return -EINVAL;
2655                         }
2656
2657                         if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2658                             input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2659                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2660                                         input_clk,
2661                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2662                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2663                                 return -EINVAL;
2664                         }
2665
2666                         if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2667                                 od_table->GfxclkFmin = input_clk;
2668                                 od8_settings->od_gfxclk_update = true;
2669                         } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2670                                 od_table->GfxclkFmax = input_clk;
2671                                 od8_settings->od_gfxclk_update = true;
2672                         }
2673                 }
2674
2675                 break;
2676
2677         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2678                 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2679                         pr_info("Mclk max frequency overdrive not supported\n");
2680                         return -EOPNOTSUPP;
2681                 }
2682
2683                 single_dpm_table = &(dpm_table->mem_table);
2684                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2685                 if (ret) {
2686                         pr_err("Attempt to get memory clk levels Failed!");
2687                         return ret;
2688                 }
2689
2690                 for (i = 0; i < size; i += 2) {
2691                         if (i + 2 > size) {
2692                                 pr_info("invalid number of input parameters %d\n",
2693                                          size);
2694                                 return -EINVAL;
2695                         }
2696
2697                         input_index = input[i];
2698                         input_clk = input[i + 1];
2699
2700                         if (input_index != 1) {
2701                                 pr_info("Invalid index %d\n", input_index);
2702                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2703                                 return -EINVAL;
2704                         }
2705
2706                         if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2707                             input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2708                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2709                                         input_clk,
2710                                         clocks.data[0].clocks_in_khz / 1000,
2711                                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2712                                 return -EINVAL;
2713                         }
2714
2715                         if (input_index == 1 && od_table->UclkFmax != input_clk) {
2716                                 od8_settings->od_gfxclk_update = true;
2717                                 od_table->UclkFmax = input_clk;
2718                         }
2719                 }
2720
2721                 break;
2722
2723         case PP_OD_EDIT_VDDC_CURVE:
2724                 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2725                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2726                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2727                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2728                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2729                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2730                         pr_info("Voltage curve calibrate not supported\n");
2731                         return -EOPNOTSUPP;
2732                 }
2733
2734                 for (i = 0; i < size; i += 3) {
2735                         if (i + 3 > size) {
2736                                 pr_info("invalid number of input parameters %d\n",
2737                                         size);
2738                                 return -EINVAL;
2739                         }
2740
2741                         input_index = input[i];
2742                         input_clk = input[i + 1];
2743                         input_vol = input[i + 2];
2744
2745                         if (input_index > 2) {
2746                                 pr_info("Setting for point %d is not supported\n",
2747                                         input_index + 1);
2748                                 pr_info("Three supported points index by 0, 1, 2\n");
2749                                 return -EINVAL;
2750                         }
2751
2752                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2753                         if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2754                             input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2755                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2756                                         input_clk,
2757                                         od8_settings->od8_settings_array[od8_id].min_value,
2758                                         od8_settings->od8_settings_array[od8_id].max_value);
2759                                 return -EINVAL;
2760                         }
2761
2762                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2763                         if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2764                             input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2765                                 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2766                                         input_vol,
2767                                         od8_settings->od8_settings_array[od8_id].min_value,
2768                                         od8_settings->od8_settings_array[od8_id].max_value);
2769                                 return -EINVAL;
2770                         }
2771
2772                         switch (input_index) {
2773                         case 0:
2774                                 od_table->GfxclkFreq1 = input_clk;
2775                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2776                                 break;
2777                         case 1:
2778                                 od_table->GfxclkFreq2 = input_clk;
2779                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2780                                 break;
2781                         case 2:
2782                                 od_table->GfxclkFreq3 = input_clk;
2783                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2784                                 break;
2785                         }
2786                 }
2787
2788                 break;
2789
2790         case PP_OD_RESTORE_DEFAULT_TABLE:
2791                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
2792                 if (ret) {
2793                         pr_err("Failed to export over drive table!\n");
2794                         return ret;
2795                 }
2796
2797                 break;
2798
2799         case PP_OD_COMMIT_DPM_TABLE:
2800                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
2801                 if (ret) {
2802                         pr_err("Failed to import over drive table!\n");
2803                         return ret;
2804                 }
2805
2806                 /* retrieve updated gfxclk table */
2807                 if (od8_settings->od_gfxclk_update) {
2808                         od8_settings->od_gfxclk_update = false;
2809                         single_dpm_table = &(dpm_table->gfx_table);
2810
2811                         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2812                                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2813                                                                   PPCLK_GFXCLK);
2814                                 if (ret) {
2815                                         pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2816                                         return ret;
2817                                 }
2818                         } else {
2819                                 single_dpm_table->count = 1;
2820                                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2821                         }
2822                 }
2823
2824                 break;
2825
2826         default:
2827                 return -EINVAL;
2828         }
2829
2830         if (type == PP_OD_COMMIT_DPM_TABLE) {
2831                 mutex_lock(&(smu->mutex));
2832                 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2833                                       AMD_PP_TASK_READJUST_POWER_STATE);
2834                 mutex_unlock(&(smu->mutex));
2835         }
2836
2837         return ret;
2838 }
2839
2840 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2841 {
2842         if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2843                 return 0;
2844
2845         if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2846                 return 0;
2847
2848         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2849 }
2850
2851 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2852 {
2853         if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2854                 return 0;
2855
2856         if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2857                 return 0;
2858
2859         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2860 }
2861
2862 static int vega20_get_enabled_smc_features(struct smu_context *smu,
2863                 uint64_t *features_enabled)
2864 {
2865         uint32_t feature_mask[2] = {0, 0};
2866         int ret = 0;
2867
2868         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2869         if (ret)
2870                 return ret;
2871
2872         *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
2873                         (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
2874
2875         return ret;
2876 }
2877
2878 static int vega20_enable_smc_features(struct smu_context *smu,
2879                 bool enable, uint64_t feature_mask)
2880 {
2881         uint32_t smu_features_low, smu_features_high;
2882         int ret = 0;
2883
2884         smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
2885         smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
2886
2887         if (enable) {
2888                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
2889                                                   smu_features_low);
2890                 if (ret)
2891                         return ret;
2892                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
2893                                                   smu_features_high);
2894                 if (ret)
2895                         return ret;
2896         } else {
2897                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
2898                                                   smu_features_low);
2899                 if (ret)
2900                         return ret;
2901                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
2902                                                   smu_features_high);
2903                 if (ret)
2904                         return ret;
2905         }
2906
2907         return 0;
2908
2909 }
2910
2911 static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
2912 {
2913         static const char *ppfeature_name[] = {
2914                                 "DPM_PREFETCHER",
2915                                 "GFXCLK_DPM",
2916                                 "UCLK_DPM",
2917                                 "SOCCLK_DPM",
2918                                 "UVD_DPM",
2919                                 "VCE_DPM",
2920                                 "ULV",
2921                                 "MP0CLK_DPM",
2922                                 "LINK_DPM",
2923                                 "DCEFCLK_DPM",
2924                                 "GFXCLK_DS",
2925                                 "SOCCLK_DS",
2926                                 "LCLK_DS",
2927                                 "PPT",
2928                                 "TDC",
2929                                 "THERMAL",
2930                                 "GFX_PER_CU_CG",
2931                                 "RM",
2932                                 "DCEFCLK_DS",
2933                                 "ACDC",
2934                                 "VR0HOT",
2935                                 "VR1HOT",
2936                                 "FW_CTF",
2937                                 "LED_DISPLAY",
2938                                 "FAN_CONTROL",
2939                                 "GFX_EDC",
2940                                 "GFXOFF",
2941                                 "CG",
2942                                 "FCLK_DPM",
2943                                 "FCLK_DS",
2944                                 "MP1CLK_DS",
2945                                 "MP0CLK_DS",
2946                                 "XGMI",
2947                                 "ECC"};
2948         static const char *output_title[] = {
2949                                 "FEATURES",
2950                                 "BITMASK",
2951                                 "ENABLEMENT"};
2952         uint64_t features_enabled;
2953         int i;
2954         int ret = 0;
2955         int size = 0;
2956
2957         ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2958         if (ret)
2959                 return ret;
2960
2961         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2962         size += sprintf(buf + size, "%-19s %-22s %s\n",
2963                                 output_title[0],
2964                                 output_title[1],
2965                                 output_title[2]);
2966         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2967                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
2968                                         ppfeature_name[i],
2969                                         1ULL << i,
2970                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
2971         }
2972
2973         return size;
2974 }
2975
2976 static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
2977 {
2978         uint64_t features_enabled;
2979         uint64_t features_to_enable;
2980         uint64_t features_to_disable;
2981         int ret = 0;
2982
2983         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2984                 return -EINVAL;
2985
2986         ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2987         if (ret)
2988                 return ret;
2989
2990         features_to_disable =
2991                 features_enabled & ~new_ppfeature_masks;
2992         features_to_enable =
2993                 ~features_enabled & new_ppfeature_masks;
2994
2995         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2996         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2997
2998         if (features_to_disable) {
2999                 ret = vega20_enable_smc_features(smu, false, features_to_disable);
3000                 if (ret)
3001                         return ret;
3002         }
3003
3004         if (features_to_enable) {
3005                 ret = vega20_enable_smc_features(smu, true, features_to_enable);
3006                 if (ret)
3007                         return ret;
3008         }
3009
3010         return 0;
3011 }
3012
3013 static bool vega20_is_dpm_running(struct smu_context *smu)
3014 {
3015         int ret = 0;
3016         uint32_t feature_mask[2];
3017         unsigned long feature_enabled;
3018         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
3019         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
3020                            ((uint64_t)feature_mask[1] << 32));
3021         return !!(feature_enabled & SMC_DPM_FEATURE);
3022 }
3023
3024 static int vega20_set_thermal_fan_table(struct smu_context *smu)
3025 {
3026         int ret;
3027         struct smu_table_context *table_context = &smu->smu_table;
3028         PPTable_t *pptable = table_context->driver_pptable;
3029
3030         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
3031                         (uint32_t)pptable->FanTargetTemperature);
3032
3033         return ret;
3034 }
3035
3036 static int vega20_get_fan_speed_rpm(struct smu_context *smu,
3037                                     uint32_t *speed)
3038 {
3039         int ret;
3040
3041         ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
3042
3043         if (ret) {
3044                 pr_err("Attempt to get current RPM from SMC Failed!\n");
3045                 return ret;
3046         }
3047
3048         smu_read_smc_arg(smu, speed);
3049
3050         return 0;
3051 }
3052
3053 static int vega20_get_fan_speed_percent(struct smu_context *smu,
3054                                         uint32_t *speed)
3055 {
3056         int ret = 0;
3057         uint32_t current_rpm = 0, percent = 0;
3058         PPTable_t *pptable = smu->smu_table.driver_pptable;
3059
3060         ret = vega20_get_fan_speed_rpm(smu, &current_rpm);
3061         if (ret)
3062                 return ret;
3063
3064         percent = current_rpm * 100 / pptable->FanMaximumRpm;
3065         *speed = percent > 100 ? 100 : percent;
3066
3067         return 0;
3068 }
3069
3070 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
3071 {
3072         int ret = 0;
3073         SmuMetrics_t metrics;
3074
3075         if (!value)
3076                 return -EINVAL;
3077
3078         ret = vega20_get_metrics_table(smu, &metrics);
3079         if (ret)
3080                 return ret;
3081
3082         *value = metrics.CurrSocketPower << 8;
3083
3084         return 0;
3085 }
3086
3087 static int vega20_get_current_activity_percent(struct smu_context *smu,
3088                                                enum amd_pp_sensors sensor,
3089                                                uint32_t *value)
3090 {
3091         int ret = 0;
3092         SmuMetrics_t metrics;
3093
3094         if (!value)
3095                 return -EINVAL;
3096
3097         ret = vega20_get_metrics_table(smu, &metrics);
3098         if (ret)
3099                 return ret;
3100
3101         switch (sensor) {
3102         case AMDGPU_PP_SENSOR_GPU_LOAD:
3103                 *value = metrics.AverageGfxActivity;
3104                 break;
3105         case AMDGPU_PP_SENSOR_MEM_LOAD:
3106                 *value = metrics.AverageUclkActivity;
3107                 break;
3108         default:
3109                 pr_err("Invalid sensor for retrieving clock activity\n");
3110                 return -EINVAL;
3111         }
3112
3113         return 0;
3114 }
3115
3116 static int vega20_thermal_get_temperature(struct smu_context *smu,
3117                                              enum amd_pp_sensors sensor,
3118                                              uint32_t *value)
3119 {
3120         struct amdgpu_device *adev = smu->adev;
3121         SmuMetrics_t metrics;
3122         uint32_t temp = 0;
3123         int ret = 0;
3124
3125         if (!value)
3126                 return -EINVAL;
3127
3128         ret = vega20_get_metrics_table(smu, &metrics);
3129         if (ret)
3130                 return ret;
3131
3132         switch (sensor) {
3133         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3134                 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
3135                 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
3136                                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
3137
3138                 temp = temp & 0x1ff;
3139                 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3140
3141                 *value = temp;
3142                 break;
3143         case AMDGPU_PP_SENSOR_EDGE_TEMP:
3144                 *value = metrics.TemperatureEdge *
3145                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3146                 break;
3147         case AMDGPU_PP_SENSOR_MEM_TEMP:
3148                 *value = metrics.TemperatureHBM *
3149                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3150                 break;
3151         default:
3152                 pr_err("Invalid sensor for retrieving temp\n");
3153                 return -EINVAL;
3154         }
3155
3156         return 0;
3157 }
3158 static int vega20_read_sensor(struct smu_context *smu,
3159                                  enum amd_pp_sensors sensor,
3160                                  void *data, uint32_t *size)
3161 {
3162         int ret = 0;
3163         struct smu_table_context *table_context = &smu->smu_table;
3164         PPTable_t *pptable = table_context->driver_pptable;
3165
3166         switch (sensor) {
3167         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3168                 *(uint32_t *)data = pptable->FanMaximumRpm;
3169                 *size = 4;
3170                 break;
3171         case AMDGPU_PP_SENSOR_MEM_LOAD:
3172         case AMDGPU_PP_SENSOR_GPU_LOAD:
3173                 ret = vega20_get_current_activity_percent(smu,
3174                                                 sensor,
3175                                                 (uint32_t *)data);
3176                 *size = 4;
3177                 break;
3178         case AMDGPU_PP_SENSOR_GPU_POWER:
3179                 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3180                 *size = 4;
3181                 break;
3182         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3183         case AMDGPU_PP_SENSOR_EDGE_TEMP:
3184         case AMDGPU_PP_SENSOR_MEM_TEMP:
3185                 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3186                 *size = 4;
3187                 break;
3188         default:
3189                 return -EINVAL;
3190         }
3191
3192         return ret;
3193 }
3194
3195 static int vega20_set_watermarks_table(struct smu_context *smu,
3196                                        void *watermarks, struct
3197                                        dm_pp_wm_sets_with_clock_ranges_soc15
3198                                        *clock_ranges)
3199 {
3200         int i;
3201         Watermarks_t *table = watermarks;
3202
3203         if (!table || !clock_ranges)
3204                 return -EINVAL;
3205
3206         if (clock_ranges->num_wm_dmif_sets > 4 ||
3207             clock_ranges->num_wm_mcif_sets > 4)
3208                 return -EINVAL;
3209
3210         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3211                 table->WatermarkRow[1][i].MinClock =
3212                         cpu_to_le16((uint16_t)
3213                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3214                         1000));
3215                 table->WatermarkRow[1][i].MaxClock =
3216                         cpu_to_le16((uint16_t)
3217                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3218                         1000));
3219                 table->WatermarkRow[1][i].MinUclk =
3220                         cpu_to_le16((uint16_t)
3221                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3222                         1000));
3223                 table->WatermarkRow[1][i].MaxUclk =
3224                         cpu_to_le16((uint16_t)
3225                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3226                         1000));
3227                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3228                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3229         }
3230
3231         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3232                 table->WatermarkRow[0][i].MinClock =
3233                         cpu_to_le16((uint16_t)
3234                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3235                         1000));
3236                 table->WatermarkRow[0][i].MaxClock =
3237                         cpu_to_le16((uint16_t)
3238                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3239                         1000));
3240                 table->WatermarkRow[0][i].MinUclk =
3241                         cpu_to_le16((uint16_t)
3242                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3243                         1000));
3244                 table->WatermarkRow[0][i].MaxUclk =
3245                         cpu_to_le16((uint16_t)
3246                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3247                         1000));
3248                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3249                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3250         }
3251
3252         return 0;
3253 }
3254
3255 static const struct smu_temperature_range vega20_thermal_policy[] =
3256 {
3257         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
3258         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
3259 };
3260
3261 static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3262                                                 struct smu_temperature_range *range)
3263 {
3264
3265         PPTable_t *pptable = smu->smu_table.driver_pptable;
3266
3267         if (!range)
3268                 return -EINVAL;
3269
3270         memcpy(range, &vega20_thermal_policy[0], sizeof(struct smu_temperature_range));
3271
3272         range->max = pptable->TedgeLimit *
3273                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3274         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
3275                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3276         range->hotspot_crit_max = pptable->ThotspotLimit *
3277                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3278         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
3279                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3280         range->mem_crit_max = pptable->ThbmLimit *
3281                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3282         range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
3283                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3284
3285
3286         return 0;
3287 }
3288
3289 static const struct pptable_funcs vega20_ppt_funcs = {
3290         .tables_init = vega20_tables_init,
3291         .alloc_dpm_context = vega20_allocate_dpm_context,
3292         .store_powerplay_table = vega20_store_powerplay_table,
3293         .check_powerplay_table = vega20_check_powerplay_table,
3294         .append_powerplay_table = vega20_append_powerplay_table,
3295         .get_smu_msg_index = vega20_get_smu_msg_index,
3296         .get_smu_clk_index = vega20_get_smu_clk_index,
3297         .get_smu_feature_index = vega20_get_smu_feature_index,
3298         .get_smu_table_index = vega20_get_smu_table_index,
3299         .get_smu_power_index = vega20_get_pwr_src_index,
3300         .get_workload_type = vega20_get_workload_type,
3301         .run_afll_btc = vega20_run_btc_afll,
3302         .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3303         .get_current_power_state = vega20_get_current_power_state,
3304         .set_default_dpm_table = vega20_set_default_dpm_table,
3305         .set_power_state = NULL,
3306         .populate_umd_state_clk = vega20_populate_umd_state_clk,
3307         .print_clk_levels = vega20_print_clk_levels,
3308         .force_clk_levels = vega20_force_clk_levels,
3309         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3310         .get_od_percentage = vega20_get_od_percentage,
3311         .get_power_profile_mode = vega20_get_power_profile_mode,
3312         .set_power_profile_mode = vega20_set_power_profile_mode,
3313         .set_od_percentage = vega20_set_od_percentage,
3314         .set_default_od_settings = vega20_set_default_od_settings,
3315         .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3316         .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3317         .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3318         .read_sensor = vega20_read_sensor,
3319         .pre_display_config_changed = vega20_pre_display_config_changed,
3320         .display_config_changed = vega20_display_config_changed,
3321         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3322         .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
3323         .force_dpm_limit_value = vega20_force_dpm_limit_value,
3324         .unforce_dpm_levels = vega20_unforce_dpm_levels,
3325         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3326         .set_ppfeature_status = vega20_set_ppfeature_status,
3327         .get_ppfeature_status = vega20_get_ppfeature_status,
3328         .is_dpm_running = vega20_is_dpm_running,
3329         .set_thermal_fan_table = vega20_set_thermal_fan_table,
3330         .get_fan_speed_percent = vega20_get_fan_speed_percent,
3331         .get_fan_speed_rpm = vega20_get_fan_speed_rpm,
3332         .set_watermarks_table = vega20_set_watermarks_table,
3333         .get_thermal_temperature_range = vega20_get_thermal_temperature_range
3334 };
3335
3336 void vega20_set_ppt_funcs(struct smu_context *smu)
3337 {
3338         struct smu_table_context *smu_table = &smu->smu_table;
3339
3340         smu->ppt_funcs = &vega20_ppt_funcs;
3341         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
3342         smu_table->table_count = TABLE_COUNT;
3343 }