2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "smu_internal.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "smu_v11_0.h"
32 #include "smu11_driver_if.h"
33 #include "soc15_common.h"
35 #include "power_state.h"
36 #include "vega20_ppt.h"
37 #include "vega20_pptable.h"
38 #include "vega20_ppsmc.h"
39 #include "nbio/nbio_7_4_sh_mask.h"
40 #include "asic_reg/thm/thm_11_0_2_offset.h"
41 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
43 #define smnPCIE_LC_SPEED_CNTL 0x11140290
44 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
46 #define CTF_OFFSET_EDGE 5
47 #define CTF_OFFSET_HOTSPOT 5
48 #define CTF_OFFSET_HBM 5
50 #define MSG_MAP(msg) \
51 [SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
53 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
54 FEATURE_DPM_GFXCLK_MASK | \
55 FEATURE_DPM_UCLK_MASK | \
56 FEATURE_DPM_SOCCLK_MASK | \
57 FEATURE_DPM_UVD_MASK | \
58 FEATURE_DPM_VCE_MASK | \
59 FEATURE_DPM_MP0CLK_MASK | \
60 FEATURE_DPM_LINK_MASK | \
61 FEATURE_DPM_DCEFCLK_MASK)
63 static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
65 MSG_MAP(GetSmuVersion),
66 MSG_MAP(GetDriverIfVersion),
67 MSG_MAP(SetAllowedFeaturesMaskLow),
68 MSG_MAP(SetAllowedFeaturesMaskHigh),
69 MSG_MAP(EnableAllSmuFeatures),
70 MSG_MAP(DisableAllSmuFeatures),
71 MSG_MAP(EnableSmuFeaturesLow),
72 MSG_MAP(EnableSmuFeaturesHigh),
73 MSG_MAP(DisableSmuFeaturesLow),
74 MSG_MAP(DisableSmuFeaturesHigh),
75 MSG_MAP(GetEnabledSmuFeaturesLow),
76 MSG_MAP(GetEnabledSmuFeaturesHigh),
77 MSG_MAP(SetWorkloadMask),
79 MSG_MAP(SetDriverDramAddrHigh),
80 MSG_MAP(SetDriverDramAddrLow),
81 MSG_MAP(SetToolsDramAddrHigh),
82 MSG_MAP(SetToolsDramAddrLow),
83 MSG_MAP(TransferTableSmu2Dram),
84 MSG_MAP(TransferTableDram2Smu),
85 MSG_MAP(UseDefaultPPTable),
86 MSG_MAP(UseBackupPPTable),
88 MSG_MAP(RequestI2CBus),
89 MSG_MAP(ReleaseI2CBus),
90 MSG_MAP(SetFloorSocVoltage),
92 MSG_MAP(StartBacoMonitor),
93 MSG_MAP(CancelBacoMonitor),
95 MSG_MAP(SetSoftMinByFreq),
96 MSG_MAP(SetSoftMaxByFreq),
97 MSG_MAP(SetHardMinByFreq),
98 MSG_MAP(SetHardMaxByFreq),
99 MSG_MAP(GetMinDpmFreq),
100 MSG_MAP(GetMaxDpmFreq),
101 MSG_MAP(GetDpmFreqByIndex),
102 MSG_MAP(GetDpmClockFreq),
103 MSG_MAP(GetSsVoltageByDpm),
104 MSG_MAP(SetMemoryChannelConfig),
105 MSG_MAP(SetGeminiMode),
106 MSG_MAP(SetGeminiApertureHigh),
107 MSG_MAP(SetGeminiApertureLow),
108 MSG_MAP(SetMinLinkDpmByIndex),
109 MSG_MAP(OverridePcieParameters),
110 MSG_MAP(OverDriveSetPercentage),
111 MSG_MAP(SetMinDeepSleepDcefclk),
112 MSG_MAP(ReenableAcDcInterrupt),
113 MSG_MAP(NotifyPowerSource),
114 MSG_MAP(SetUclkFastSwitch),
115 MSG_MAP(SetUclkDownHyst),
116 MSG_MAP(GetCurrentRpm),
117 MSG_MAP(SetVideoFps),
119 MSG_MAP(SetFanTemperatureTarget),
120 MSG_MAP(PrepareMp1ForUnload),
121 MSG_MAP(DramLogSetDramAddrHigh),
122 MSG_MAP(DramLogSetDramAddrLow),
123 MSG_MAP(DramLogSetDramSize),
124 MSG_MAP(SetFanMaxRpm),
125 MSG_MAP(SetFanMinPwm),
126 MSG_MAP(ConfigureGfxDidt),
127 MSG_MAP(NumOfDisplays),
128 MSG_MAP(RemoveMargins),
129 MSG_MAP(ReadSerialNumTop32),
130 MSG_MAP(ReadSerialNumBottom32),
131 MSG_MAP(SetSystemVirtualDramAddrHigh),
132 MSG_MAP(SetSystemVirtualDramAddrLow),
134 MSG_MAP(SetFclkGfxClkRatio),
135 MSG_MAP(AllowGfxOff),
136 MSG_MAP(DisallowGfxOff),
137 MSG_MAP(GetPptLimit),
138 MSG_MAP(GetDcModeMaxDpmFreq),
139 MSG_MAP(GetDebugData),
140 MSG_MAP(SetXgmiMode),
143 MSG_MAP(PrepareMp1ForReset),
144 MSG_MAP(PrepareMp1ForShutdown),
145 MSG_MAP(SetMGpuFanBoostLimitRpm),
146 MSG_MAP(GetAVFSVoltageByDpm),
147 MSG_MAP(DFCstateControl),
150 static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(VCLK, PPCLK_VCLK),
153 CLK_MAP(DCLK, PPCLK_DCLK),
154 CLK_MAP(ECLK, PPCLK_ECLK),
155 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
156 CLK_MAP(UCLK, PPCLK_UCLK),
157 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
158 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
159 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
160 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
161 CLK_MAP(FCLK, PPCLK_FCLK),
164 static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
165 FEA_MAP(DPM_PREFETCHER),
174 FEA_MAP(DPM_DCEFCLK),
181 FEA_MAP(GFX_PER_CU_CG),
188 FEA_MAP(LED_DISPLAY),
189 FEA_MAP(FAN_CONTROL),
200 static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
204 TAB_MAP(AVFS_PSM_DEBUG),
205 TAB_MAP(AVFS_FUSE_OVERRIDE),
206 TAB_MAP(PMSTATUSLOG),
207 TAB_MAP(SMU_METRICS),
208 TAB_MAP(DRIVER_SMU_CONFIG),
209 TAB_MAP(ACTIVITY_MONITOR_COEFF),
213 static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
218 static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
224 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
228 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
230 struct smu_11_0_cmn2aisc_mapping mapping;
232 if (index >= SMU_TABLE_COUNT)
235 mapping = vega20_table_map[index];
236 if (!(mapping.valid_mapping)) {
240 return mapping.map_to;
243 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
245 struct smu_11_0_cmn2aisc_mapping mapping;
247 if (index >= SMU_POWER_SOURCE_COUNT)
250 mapping = vega20_pwr_src_map[index];
251 if (!(mapping.valid_mapping)) {
255 return mapping.map_to;
258 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
260 struct smu_11_0_cmn2aisc_mapping mapping;
262 if (index >= SMU_FEATURE_COUNT)
265 mapping = vega20_feature_mask_map[index];
266 if (!(mapping.valid_mapping)) {
270 return mapping.map_to;
273 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
275 struct smu_11_0_cmn2aisc_mapping mapping;
277 if (index >= SMU_CLK_COUNT)
280 mapping = vega20_clk_map[index];
281 if (!(mapping.valid_mapping)) {
285 return mapping.map_to;
288 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
290 struct smu_11_0_cmn2aisc_mapping mapping;
292 if (index >= SMU_MSG_MAX_COUNT)
295 mapping = vega20_message_map[index];
296 if (!(mapping.valid_mapping)) {
300 return mapping.map_to;
303 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
305 struct smu_11_0_cmn2aisc_mapping mapping;
307 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
310 mapping = vega20_workload_map[profile];
311 if (!(mapping.valid_mapping)) {
315 return mapping.map_to;
318 static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
320 struct smu_table_context *smu_table = &smu->smu_table;
322 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
323 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
324 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
325 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
326 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
327 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
328 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
329 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
330 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
331 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
332 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
333 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
334 AMDGPU_GEM_DOMAIN_VRAM);
336 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
337 if (!smu_table->metrics_table)
339 smu_table->metrics_time = 0;
341 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
342 if (!smu_table->watermarks_table)
348 static int vega20_allocate_dpm_context(struct smu_context *smu)
350 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
352 if (smu_dpm->dpm_context)
355 smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
357 if (!smu_dpm->dpm_context)
360 if (smu_dpm->golden_dpm_context)
363 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
365 if (!smu_dpm->golden_dpm_context)
368 smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
370 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
372 if (!smu_dpm->dpm_current_power_state)
375 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
377 if (!smu_dpm->dpm_request_power_state)
383 static int vega20_setup_od8_information(struct smu_context *smu)
385 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
386 struct smu_table_context *table_context = &smu->smu_table;
387 struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
389 uint32_t od_feature_count, od_feature_array_size,
390 od_setting_count, od_setting_array_size;
392 if (!table_context->power_play_table)
395 powerplay_table = table_context->power_play_table;
397 if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
398 /* Setup correct ODFeatureCount, and store ODFeatureArray from
399 * powerplay table to od_feature_capabilities */
401 (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
402 ATOM_VEGA20_ODFEATURE_COUNT) ?
403 ATOM_VEGA20_ODFEATURE_COUNT :
404 le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
406 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
408 if (od8_settings->od_feature_capabilities)
411 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
412 od_feature_array_size,
414 if (!od8_settings->od_feature_capabilities)
417 /* Setup correct ODSettingCount, and store ODSettingArray from
418 * powerplay table to od_settings_max and od_setting_min */
420 (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
421 ATOM_VEGA20_ODSETTING_COUNT) ?
422 ATOM_VEGA20_ODSETTING_COUNT :
423 le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
425 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
427 if (od8_settings->od_settings_max)
430 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
431 od_setting_array_size,
434 if (!od8_settings->od_settings_max) {
435 kfree(od8_settings->od_feature_capabilities);
436 od8_settings->od_feature_capabilities = NULL;
440 if (od8_settings->od_settings_min)
443 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
444 od_setting_array_size,
447 if (!od8_settings->od_settings_min) {
448 kfree(od8_settings->od_feature_capabilities);
449 od8_settings->od_feature_capabilities = NULL;
450 kfree(od8_settings->od_settings_max);
451 od8_settings->od_settings_max = NULL;
459 static int vega20_store_powerplay_table(struct smu_context *smu)
461 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
462 struct smu_table_context *table_context = &smu->smu_table;
464 if (!table_context->power_play_table)
467 powerplay_table = table_context->power_play_table;
469 memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
472 table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
477 static int vega20_append_powerplay_table(struct smu_context *smu)
479 struct smu_table_context *table_context = &smu->smu_table;
480 PPTable_t *smc_pptable = table_context->driver_pptable;
481 struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
484 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
487 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
488 (uint8_t **)&smc_dpm_table);
492 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
493 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
495 smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
496 smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
497 smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
498 smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
500 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
501 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
502 smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
504 smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
505 smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
506 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
508 smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
509 smc_pptable->SocOffset = smc_dpm_table->socoffset;
510 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
512 smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
513 smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
514 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
516 smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
517 smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
518 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
520 smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
521 smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
522 smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
523 smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
525 smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
526 smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
527 smc_pptable->Padding1 = smc_dpm_table->padding1;
528 smc_pptable->Padding2 = smc_dpm_table->padding2;
530 smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
531 smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
532 smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
534 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
535 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
536 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
538 smc_pptable->UclkSpreadEnabled = 0;
539 smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
540 smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
542 smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
543 smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
544 smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
546 smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
547 smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
548 smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
550 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
551 smc_pptable->I2cControllers[i].Enabled =
552 smc_dpm_table->i2ccontrollers[i].enabled;
553 smc_pptable->I2cControllers[i].SlaveAddress =
554 smc_dpm_table->i2ccontrollers[i].slaveaddress;
555 smc_pptable->I2cControllers[i].ControllerPort =
556 smc_dpm_table->i2ccontrollers[i].controllerport;
557 smc_pptable->I2cControllers[i].ThermalThrottler =
558 smc_dpm_table->i2ccontrollers[i].thermalthrottler;
559 smc_pptable->I2cControllers[i].I2cProtocol =
560 smc_dpm_table->i2ccontrollers[i].i2cprotocol;
561 smc_pptable->I2cControllers[i].I2cSpeed =
562 smc_dpm_table->i2ccontrollers[i].i2cspeed;
568 static int vega20_check_powerplay_table(struct smu_context *smu)
570 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
571 struct smu_table_context *table_context = &smu->smu_table;
573 powerplay_table = table_context->power_play_table;
575 if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
576 pr_err("Unsupported PPTable format!");
580 if (!powerplay_table->sHeader.structuresize) {
581 pr_err("Invalid PowerPlay Table!");
588 static int vega20_run_btc_afll(struct smu_context *smu)
590 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
593 #define FEATURE_MASK(feature) (1ULL << feature)
595 vega20_get_allowed_feature_mask(struct smu_context *smu,
596 uint32_t *feature_mask, uint32_t num)
601 memset(feature_mask, 0, sizeof(uint32_t) * num);
603 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
604 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
605 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
606 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
607 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
608 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
609 | FEATURE_MASK(FEATURE_ULV_BIT)
610 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
611 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
612 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
613 | FEATURE_MASK(FEATURE_PPT_BIT)
614 | FEATURE_MASK(FEATURE_TDC_BIT)
615 | FEATURE_MASK(FEATURE_THERMAL_BIT)
616 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
617 | FEATURE_MASK(FEATURE_RM_BIT)
618 | FEATURE_MASK(FEATURE_ACDC_BIT)
619 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
620 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
621 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
622 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
623 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
624 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
625 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
626 | FEATURE_MASK(FEATURE_CG_BIT)
627 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
628 | FEATURE_MASK(FEATURE_XGMI_BIT);
633 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
635 enum amd_pm_state_type pm_type;
636 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
638 if (!smu_dpm_ctx->dpm_context ||
639 !smu_dpm_ctx->dpm_current_power_state)
642 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
643 case SMU_STATE_UI_LABEL_BATTERY:
644 pm_type = POWER_STATE_TYPE_BATTERY;
646 case SMU_STATE_UI_LABEL_BALLANCED:
647 pm_type = POWER_STATE_TYPE_BALANCED;
649 case SMU_STATE_UI_LABEL_PERFORMANCE:
650 pm_type = POWER_STATE_TYPE_PERFORMANCE;
653 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
654 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
656 pm_type = POWER_STATE_TYPE_DEFAULT;
664 vega20_set_single_dpm_table(struct smu_context *smu,
665 struct vega20_single_dpm_table *single_dpm_table,
669 uint32_t i, num_of_levels = 0, clk;
671 ret = smu_send_smc_msg_with_param(smu,
672 SMU_MSG_GetDpmFreqByIndex,
673 (clk_id << 16 | 0xFF));
675 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
679 smu_read_smc_arg(smu, &num_of_levels);
680 if (!num_of_levels) {
681 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
685 single_dpm_table->count = num_of_levels;
687 for (i = 0; i < num_of_levels; i++) {
688 ret = smu_send_smc_msg_with_param(smu,
689 SMU_MSG_GetDpmFreqByIndex,
692 pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
695 smu_read_smc_arg(smu, &clk);
697 pr_err("[GetDpmFreqByIndex] clk value is invalid!");
700 single_dpm_table->dpm_levels[i].value = clk;
701 single_dpm_table->dpm_levels[i].enabled = true;
706 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
708 dpm_state->soft_min_level = 0x0;
709 dpm_state->soft_max_level = 0xffff;
710 dpm_state->hard_min_level = 0x0;
711 dpm_state->hard_max_level = 0xffff;
714 static int vega20_set_default_dpm_table(struct smu_context *smu)
718 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
719 struct vega20_dpm_table *dpm_table = NULL;
720 struct vega20_single_dpm_table *single_dpm_table;
722 dpm_table = smu_dpm->dpm_context;
725 single_dpm_table = &(dpm_table->soc_table);
727 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
728 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
731 pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
735 single_dpm_table->count = 1;
736 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
738 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
741 single_dpm_table = &(dpm_table->gfx_table);
743 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
744 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
747 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
751 single_dpm_table->count = 1;
752 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
754 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
757 single_dpm_table = &(dpm_table->mem_table);
759 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
760 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
763 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
767 single_dpm_table->count = 1;
768 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
770 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
773 single_dpm_table = &(dpm_table->eclk_table);
775 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
776 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
778 pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
782 single_dpm_table->count = 1;
783 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
785 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
788 single_dpm_table = &(dpm_table->vclk_table);
790 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
791 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
793 pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
797 single_dpm_table->count = 1;
798 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
800 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
803 single_dpm_table = &(dpm_table->dclk_table);
805 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
806 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
808 pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
812 single_dpm_table->count = 1;
813 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
815 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
818 single_dpm_table = &(dpm_table->dcef_table);
820 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
821 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
824 pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
828 single_dpm_table->count = 1;
829 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
831 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
834 single_dpm_table = &(dpm_table->pixel_table);
836 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
837 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
840 pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
844 single_dpm_table->count = 0;
846 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
849 single_dpm_table = &(dpm_table->display_table);
851 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
852 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
855 pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
859 single_dpm_table->count = 0;
861 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
864 single_dpm_table = &(dpm_table->phy_table);
866 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
867 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
870 pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
874 single_dpm_table->count = 0;
876 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
879 single_dpm_table = &(dpm_table->fclk_table);
881 if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
882 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
885 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
889 single_dpm_table->count = 0;
891 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
893 memcpy(smu_dpm->golden_dpm_context, dpm_table,
894 sizeof(struct vega20_dpm_table));
899 static int vega20_populate_umd_state_clk(struct smu_context *smu)
901 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
902 struct vega20_dpm_table *dpm_table = NULL;
903 struct vega20_single_dpm_table *gfx_table = NULL;
904 struct vega20_single_dpm_table *mem_table = NULL;
906 dpm_table = smu_dpm->dpm_context;
907 gfx_table = &(dpm_table->gfx_table);
908 mem_table = &(dpm_table->mem_table);
910 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
911 smu->pstate_mclk = mem_table->dpm_levels[0].value;
913 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
914 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
915 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
916 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
919 smu->pstate_sclk = smu->pstate_sclk * 100;
920 smu->pstate_mclk = smu->pstate_mclk * 100;
925 static int vega20_get_clk_table(struct smu_context *smu,
926 struct pp_clock_levels_with_latency *clocks,
927 struct vega20_single_dpm_table *dpm_table)
931 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
932 clocks->num_levels = count;
934 for (i = 0; i < count; i++) {
935 clocks->data[i].clocks_in_khz =
936 dpm_table->dpm_levels[i].value * 1000;
937 clocks->data[i].latency_in_us = 0;
943 static int vega20_print_clk_levels(struct smu_context *smu,
944 enum smu_clk_type type, char *buf)
946 int i, now, size = 0;
948 uint32_t gen_speed, lane_width;
949 struct amdgpu_device *adev = smu->adev;
950 struct pp_clock_levels_with_latency clocks;
951 struct vega20_single_dpm_table *single_dpm_table;
952 struct smu_table_context *table_context = &smu->smu_table;
953 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
954 struct vega20_dpm_table *dpm_table = NULL;
955 struct vega20_od8_settings *od8_settings =
956 (struct vega20_od8_settings *)smu->od_settings;
957 OverDriveTable_t *od_table =
958 (OverDriveTable_t *)(table_context->overdrive_table);
959 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
961 dpm_table = smu_dpm->dpm_context;
965 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
967 pr_err("Attempt to get current gfx clk Failed!");
971 single_dpm_table = &(dpm_table->gfx_table);
972 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
974 pr_err("Attempt to get gfx clk levels Failed!");
978 for (i = 0; i < clocks.num_levels; i++)
979 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
980 clocks.data[i].clocks_in_khz / 1000,
981 (clocks.data[i].clocks_in_khz == now * 10)
986 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
988 pr_err("Attempt to get current mclk Failed!");
992 single_dpm_table = &(dpm_table->mem_table);
993 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
995 pr_err("Attempt to get memory clk levels Failed!");
999 for (i = 0; i < clocks.num_levels; i++)
1000 size += sprintf(buf + size, "%d: %uMhz %s\n",
1001 i, clocks.data[i].clocks_in_khz / 1000,
1002 (clocks.data[i].clocks_in_khz == now * 10)
1007 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
1009 pr_err("Attempt to get current socclk Failed!");
1013 single_dpm_table = &(dpm_table->soc_table);
1014 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1016 pr_err("Attempt to get socclk levels Failed!");
1020 for (i = 0; i < clocks.num_levels; i++)
1021 size += sprintf(buf + size, "%d: %uMhz %s\n",
1022 i, clocks.data[i].clocks_in_khz / 1000,
1023 (clocks.data[i].clocks_in_khz == now * 10)
1028 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1030 pr_err("Attempt to get current fclk Failed!");
1034 single_dpm_table = &(dpm_table->fclk_table);
1035 for (i = 0; i < single_dpm_table->count; i++)
1036 size += sprintf(buf + size, "%d: %uMhz %s\n",
1037 i, single_dpm_table->dpm_levels[i].value,
1038 (single_dpm_table->dpm_levels[i].value == now / 100)
1043 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1045 pr_err("Attempt to get current dcefclk Failed!");
1049 single_dpm_table = &(dpm_table->dcef_table);
1050 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1052 pr_err("Attempt to get dcefclk levels Failed!");
1056 for (i = 0; i < clocks.num_levels; i++)
1057 size += sprintf(buf + size, "%d: %uMhz %s\n",
1058 i, clocks.data[i].clocks_in_khz / 1000,
1059 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1063 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1064 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1065 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1066 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1067 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1068 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1069 for (i = 0; i < NUM_LINK_LEVELS; i++)
1070 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1071 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1072 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1073 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1074 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1075 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1076 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1077 (pptable->PcieLaneCount[i] == 3) ? "x4" :
1078 (pptable->PcieLaneCount[i] == 4) ? "x8" :
1079 (pptable->PcieLaneCount[i] == 5) ? "x12" :
1080 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1081 pptable->LclkFreq[i],
1082 (gen_speed == pptable->PcieGenSpeed[i]) &&
1083 (lane_width == pptable->PcieLaneCount[i]) ?
1088 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1089 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1090 size = sprintf(buf, "%s:\n", "OD_SCLK");
1091 size += sprintf(buf + size, "0: %10uMhz\n",
1092 od_table->GfxclkFmin);
1093 size += sprintf(buf + size, "1: %10uMhz\n",
1094 od_table->GfxclkFmax);
1100 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1101 size = sprintf(buf, "%s:\n", "OD_MCLK");
1102 size += sprintf(buf + size, "1: %10uMhz\n",
1103 od_table->UclkFmax);
1108 case SMU_OD_VDDC_CURVE:
1109 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1110 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1111 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1112 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1113 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1114 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1115 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1116 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1117 od_table->GfxclkFreq1,
1118 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1119 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1120 od_table->GfxclkFreq2,
1121 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1122 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1123 od_table->GfxclkFreq3,
1124 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1130 size = sprintf(buf, "%s:\n", "OD_RANGE");
1132 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1133 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1134 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1135 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1136 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1139 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1140 single_dpm_table = &(dpm_table->mem_table);
1141 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1143 pr_err("Attempt to get memory clk levels Failed!");
1147 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1148 clocks.data[0].clocks_in_khz / 1000,
1149 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1152 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1153 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1154 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1155 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1156 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1157 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1158 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1159 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1160 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1161 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1162 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1163 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1164 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1165 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1166 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1167 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1168 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1169 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1170 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1171 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1172 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1173 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1174 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1175 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1186 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1187 uint32_t feature_mask)
1189 struct vega20_dpm_table *dpm_table;
1190 struct vega20_single_dpm_table *single_dpm_table;
1194 dpm_table = smu->smu_dpm.dpm_context;
1196 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1197 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1198 single_dpm_table = &(dpm_table->gfx_table);
1199 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1200 single_dpm_table->dpm_state.soft_min_level;
1201 ret = smu_send_smc_msg_with_param(smu,
1202 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1203 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1205 pr_err("Failed to set soft %s gfxclk !\n",
1206 max ? "max" : "min");
1211 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1212 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1213 single_dpm_table = &(dpm_table->mem_table);
1214 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1215 single_dpm_table->dpm_state.soft_min_level;
1216 ret = smu_send_smc_msg_with_param(smu,
1217 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1218 (PPCLK_UCLK << 16) | (freq & 0xffff));
1220 pr_err("Failed to set soft %s memclk !\n",
1221 max ? "max" : "min");
1226 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1227 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1228 single_dpm_table = &(dpm_table->soc_table);
1229 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1230 single_dpm_table->dpm_state.soft_min_level;
1231 ret = smu_send_smc_msg_with_param(smu,
1232 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1233 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1235 pr_err("Failed to set soft %s socclk !\n",
1236 max ? "max" : "min");
1241 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1242 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1243 single_dpm_table = &(dpm_table->fclk_table);
1244 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1245 single_dpm_table->dpm_state.soft_min_level;
1246 ret = smu_send_smc_msg_with_param(smu,
1247 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1248 (PPCLK_FCLK << 16) | (freq & 0xffff));
1250 pr_err("Failed to set soft %s fclk !\n",
1251 max ? "max" : "min");
1256 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1257 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1258 single_dpm_table = &(dpm_table->dcef_table);
1259 freq = single_dpm_table->dpm_state.hard_min_level;
1261 ret = smu_send_smc_msg_with_param(smu,
1262 SMU_MSG_SetHardMinByFreq,
1263 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1265 pr_err("Failed to set hard min dcefclk !\n");
1274 static int vega20_force_clk_levels(struct smu_context *smu,
1275 enum smu_clk_type clk_type, uint32_t mask)
1277 struct vega20_dpm_table *dpm_table;
1278 struct vega20_single_dpm_table *single_dpm_table;
1279 uint32_t soft_min_level, soft_max_level, hard_min_level;
1282 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1283 soft_max_level = mask ? (fls(mask) - 1) : 0;
1285 dpm_table = smu->smu_dpm.dpm_context;
1289 single_dpm_table = &(dpm_table->gfx_table);
1291 if (soft_max_level >= single_dpm_table->count) {
1292 pr_err("Clock level specified %d is over max allowed %d\n",
1293 soft_max_level, single_dpm_table->count - 1);
1298 single_dpm_table->dpm_state.soft_min_level =
1299 single_dpm_table->dpm_levels[soft_min_level].value;
1300 single_dpm_table->dpm_state.soft_max_level =
1301 single_dpm_table->dpm_levels[soft_max_level].value;
1303 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1305 pr_err("Failed to upload boot level to lowest!\n");
1309 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1311 pr_err("Failed to upload dpm max level to highest!\n");
1316 single_dpm_table = &(dpm_table->mem_table);
1318 if (soft_max_level >= single_dpm_table->count) {
1319 pr_err("Clock level specified %d is over max allowed %d\n",
1320 soft_max_level, single_dpm_table->count - 1);
1325 single_dpm_table->dpm_state.soft_min_level =
1326 single_dpm_table->dpm_levels[soft_min_level].value;
1327 single_dpm_table->dpm_state.soft_max_level =
1328 single_dpm_table->dpm_levels[soft_max_level].value;
1330 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1332 pr_err("Failed to upload boot level to lowest!\n");
1336 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1338 pr_err("Failed to upload dpm max level to highest!\n");
1343 single_dpm_table = &(dpm_table->soc_table);
1345 if (soft_max_level >= single_dpm_table->count) {
1346 pr_err("Clock level specified %d is over max allowed %d\n",
1347 soft_max_level, single_dpm_table->count - 1);
1352 single_dpm_table->dpm_state.soft_min_level =
1353 single_dpm_table->dpm_levels[soft_min_level].value;
1354 single_dpm_table->dpm_state.soft_max_level =
1355 single_dpm_table->dpm_levels[soft_max_level].value;
1357 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1359 pr_err("Failed to upload boot level to lowest!\n");
1363 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1365 pr_err("Failed to upload dpm max level to highest!\n");
1370 single_dpm_table = &(dpm_table->fclk_table);
1372 if (soft_max_level >= single_dpm_table->count) {
1373 pr_err("Clock level specified %d is over max allowed %d\n",
1374 soft_max_level, single_dpm_table->count - 1);
1379 single_dpm_table->dpm_state.soft_min_level =
1380 single_dpm_table->dpm_levels[soft_min_level].value;
1381 single_dpm_table->dpm_state.soft_max_level =
1382 single_dpm_table->dpm_levels[soft_max_level].value;
1384 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1386 pr_err("Failed to upload boot level to lowest!\n");
1390 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1392 pr_err("Failed to upload dpm max level to highest!\n");
1397 hard_min_level = soft_min_level;
1398 single_dpm_table = &(dpm_table->dcef_table);
1400 if (hard_min_level >= single_dpm_table->count) {
1401 pr_err("Clock level specified %d is over max allowed %d\n",
1402 hard_min_level, single_dpm_table->count - 1);
1407 single_dpm_table->dpm_state.hard_min_level =
1408 single_dpm_table->dpm_levels[hard_min_level].value;
1410 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1412 pr_err("Failed to upload boot level to lowest!\n");
1417 if (soft_min_level >= NUM_LINK_LEVELS ||
1418 soft_max_level >= NUM_LINK_LEVELS) {
1423 ret = smu_send_smc_msg_with_param(smu,
1424 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1426 pr_err("Failed to set min link dpm level!\n");
1437 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1438 enum smu_clk_type clk_type,
1439 struct pp_clock_levels_with_latency *clocks)
1442 struct vega20_single_dpm_table *single_dpm_table;
1443 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1444 struct vega20_dpm_table *dpm_table = NULL;
1446 dpm_table = smu_dpm->dpm_context;
1450 single_dpm_table = &(dpm_table->gfx_table);
1451 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1454 single_dpm_table = &(dpm_table->mem_table);
1455 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1458 single_dpm_table = &(dpm_table->dcef_table);
1459 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1462 single_dpm_table = &(dpm_table->soc_table);
1463 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1472 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1478 ret = smu_send_smc_msg_with_param(smu,
1479 SMU_MSG_GetAVFSVoltageByDpm,
1480 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1482 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1486 smu_read_smc_arg(smu, voltage);
1487 *voltage = *voltage / VOLTAGE_SCALE;
1492 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1494 struct smu_table_context *table_context = &smu->smu_table;
1495 OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1496 struct vega20_od8_settings *od8_settings = NULL;
1497 PPTable_t *smc_pptable = table_context->driver_pptable;
1500 if (smu->od_settings)
1503 od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1508 smu->od_settings = (void *)od8_settings;
1510 ret = vega20_setup_od8_information(smu);
1512 pr_err("Retrieve board OD limits failed!\n");
1516 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1517 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1518 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1519 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1520 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1521 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1522 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1524 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1526 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1527 od_table->GfxclkFmin;
1528 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1529 od_table->GfxclkFmax;
1532 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1533 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1534 smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1535 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1536 smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1537 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1538 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1539 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1541 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1543 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1545 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1547 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1549 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1552 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1553 od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1554 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1555 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1556 od_table->GfxclkFreq1;
1557 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1558 od_table->GfxclkFreq2;
1559 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1560 od_table->GfxclkFreq3;
1562 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1563 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1564 od_table->GfxclkFreq1);
1566 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1567 od_table->GfxclkVolt1 =
1568 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1570 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1571 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1572 od_table->GfxclkFreq2);
1574 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1575 od_table->GfxclkVolt2 =
1576 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1578 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1579 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1580 od_table->GfxclkFreq3);
1582 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1583 od_table->GfxclkVolt3 =
1584 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1589 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1590 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1591 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1592 od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1593 (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1594 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1595 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1597 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1602 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1603 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1604 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1605 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1606 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1607 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1609 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1610 od_table->OverDrivePct;
1613 if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1614 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1615 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1616 od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1617 (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1618 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1619 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1620 OD8_ACOUSTIC_LIMIT_SCLK;
1621 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1622 od_table->FanMaximumRpm;
1625 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1626 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1627 od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1628 (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1629 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1630 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1632 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1633 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1637 if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1638 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1639 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1640 od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1641 (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1642 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1643 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1644 OD8_TEMPERATURE_FAN;
1645 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1646 od_table->FanTargetTemperature;
1649 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1650 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1651 od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1652 (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1653 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1654 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1655 OD8_TEMPERATURE_SYSTEM;
1656 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1657 od_table->MaxOpTemp;
1661 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1662 if (od8_settings->od8_settings_array[i].feature_id) {
1663 od8_settings->od8_settings_array[i].min_value =
1664 od8_settings->od_settings_min[i];
1665 od8_settings->od8_settings_array[i].max_value =
1666 od8_settings->od_settings_max[i];
1667 od8_settings->od8_settings_array[i].current_value =
1668 od8_settings->od8_settings_array[i].default_value;
1670 od8_settings->od8_settings_array[i].min_value = 0;
1671 od8_settings->od8_settings_array[i].max_value = 0;
1672 od8_settings->od8_settings_array[i].current_value = 0;
1679 static int vega20_get_metrics_table(struct smu_context *smu,
1680 SmuMetrics_t *metrics_table)
1682 struct smu_table_context *smu_table= &smu->smu_table;
1685 mutex_lock(&smu->metrics_lock);
1686 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1687 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1688 (void *)smu_table->metrics_table, false);
1690 pr_info("Failed to export SMU metrics table!\n");
1691 mutex_unlock(&smu->metrics_lock);
1694 smu_table->metrics_time = jiffies;
1697 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1698 mutex_unlock(&smu->metrics_lock);
1703 static int vega20_set_default_od_settings(struct smu_context *smu,
1706 struct smu_table_context *table_context = &smu->smu_table;
1710 if (table_context->overdrive_table)
1713 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1715 if (!table_context->overdrive_table)
1718 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1719 table_context->overdrive_table, false);
1721 pr_err("Failed to export over drive table!\n");
1725 ret = vega20_set_default_od8_setttings(smu);
1730 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1731 table_context->overdrive_table, true);
1733 pr_err("Failed to import over drive table!\n");
1740 static int vega20_get_od_percentage(struct smu_context *smu,
1741 enum smu_clk_type clk_type)
1743 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1744 struct vega20_dpm_table *dpm_table = NULL;
1745 struct vega20_dpm_table *golden_table = NULL;
1746 struct vega20_single_dpm_table *single_dpm_table;
1747 struct vega20_single_dpm_table *golden_dpm_table;
1748 int value, golden_value;
1750 dpm_table = smu_dpm->dpm_context;
1751 golden_table = smu_dpm->golden_dpm_context;
1755 single_dpm_table = &(dpm_table->gfx_table);
1756 golden_dpm_table = &(golden_table->gfx_table);
1759 single_dpm_table = &(dpm_table->mem_table);
1760 golden_dpm_table = &(golden_table->mem_table);
1767 value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1768 golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1770 value -= golden_value;
1771 value = DIV_ROUND_UP(value * 100, golden_value);
1776 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1778 DpmActivityMonitorCoeffInt_t activity_monitor;
1779 uint32_t i, size = 0;
1780 int16_t workload_type = 0;
1781 static const char *profile_name[] = {
1789 static const char *title[] = {
1790 "PROFILE_INDEX(NAME)",
1794 "MinActiveFreqType",
1799 "PD_Data_error_coeff",
1800 "PD_Data_error_rate_coeff"};
1803 if (!smu->pm_enabled || !buf)
1806 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1807 title[0], title[1], title[2], title[3], title[4], title[5],
1808 title[6], title[7], title[8], title[9], title[10]);
1810 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1811 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1812 workload_type = smu_workload_get_type(smu, i);
1813 if (workload_type < 0)
1816 result = smu_update_table(smu,
1817 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1818 (void *)(&activity_monitor), false);
1820 pr_err("[%s] Failed to get activity monitor!", __func__);
1824 size += sprintf(buf + size, "%2d %14s%s:\n",
1825 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1827 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1831 activity_monitor.Gfx_FPS,
1832 activity_monitor.Gfx_UseRlcBusy,
1833 activity_monitor.Gfx_MinActiveFreqType,
1834 activity_monitor.Gfx_MinActiveFreq,
1835 activity_monitor.Gfx_BoosterFreqType,
1836 activity_monitor.Gfx_BoosterFreq,
1837 activity_monitor.Gfx_PD_Data_limit_c,
1838 activity_monitor.Gfx_PD_Data_error_coeff,
1839 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1841 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1845 activity_monitor.Soc_FPS,
1846 activity_monitor.Soc_UseRlcBusy,
1847 activity_monitor.Soc_MinActiveFreqType,
1848 activity_monitor.Soc_MinActiveFreq,
1849 activity_monitor.Soc_BoosterFreqType,
1850 activity_monitor.Soc_BoosterFreq,
1851 activity_monitor.Soc_PD_Data_limit_c,
1852 activity_monitor.Soc_PD_Data_error_coeff,
1853 activity_monitor.Soc_PD_Data_error_rate_coeff);
1855 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1859 activity_monitor.Mem_FPS,
1860 activity_monitor.Mem_UseRlcBusy,
1861 activity_monitor.Mem_MinActiveFreqType,
1862 activity_monitor.Mem_MinActiveFreq,
1863 activity_monitor.Mem_BoosterFreqType,
1864 activity_monitor.Mem_BoosterFreq,
1865 activity_monitor.Mem_PD_Data_limit_c,
1866 activity_monitor.Mem_PD_Data_error_coeff,
1867 activity_monitor.Mem_PD_Data_error_rate_coeff);
1869 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1873 activity_monitor.Fclk_FPS,
1874 activity_monitor.Fclk_UseRlcBusy,
1875 activity_monitor.Fclk_MinActiveFreqType,
1876 activity_monitor.Fclk_MinActiveFreq,
1877 activity_monitor.Fclk_BoosterFreqType,
1878 activity_monitor.Fclk_BoosterFreq,
1879 activity_monitor.Fclk_PD_Data_limit_c,
1880 activity_monitor.Fclk_PD_Data_error_coeff,
1881 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1887 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1889 DpmActivityMonitorCoeffInt_t activity_monitor;
1890 int workload_type = 0, ret = 0;
1892 smu->power_profile_mode = input[size];
1894 if (!smu->pm_enabled)
1896 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1897 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1901 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1902 ret = smu_update_table(smu,
1903 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1904 (void *)(&activity_monitor), false);
1906 pr_err("[%s] Failed to get activity monitor!", __func__);
1911 case 0: /* Gfxclk */
1912 activity_monitor.Gfx_FPS = input[1];
1913 activity_monitor.Gfx_UseRlcBusy = input[2];
1914 activity_monitor.Gfx_MinActiveFreqType = input[3];
1915 activity_monitor.Gfx_MinActiveFreq = input[4];
1916 activity_monitor.Gfx_BoosterFreqType = input[5];
1917 activity_monitor.Gfx_BoosterFreq = input[6];
1918 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1919 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1920 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1922 case 1: /* Socclk */
1923 activity_monitor.Soc_FPS = input[1];
1924 activity_monitor.Soc_UseRlcBusy = input[2];
1925 activity_monitor.Soc_MinActiveFreqType = input[3];
1926 activity_monitor.Soc_MinActiveFreq = input[4];
1927 activity_monitor.Soc_BoosterFreqType = input[5];
1928 activity_monitor.Soc_BoosterFreq = input[6];
1929 activity_monitor.Soc_PD_Data_limit_c = input[7];
1930 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1931 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1934 activity_monitor.Mem_FPS = input[1];
1935 activity_monitor.Mem_UseRlcBusy = input[2];
1936 activity_monitor.Mem_MinActiveFreqType = input[3];
1937 activity_monitor.Mem_MinActiveFreq = input[4];
1938 activity_monitor.Mem_BoosterFreqType = input[5];
1939 activity_monitor.Mem_BoosterFreq = input[6];
1940 activity_monitor.Mem_PD_Data_limit_c = input[7];
1941 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1942 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1945 activity_monitor.Fclk_FPS = input[1];
1946 activity_monitor.Fclk_UseRlcBusy = input[2];
1947 activity_monitor.Fclk_MinActiveFreqType = input[3];
1948 activity_monitor.Fclk_MinActiveFreq = input[4];
1949 activity_monitor.Fclk_BoosterFreqType = input[5];
1950 activity_monitor.Fclk_BoosterFreq = input[6];
1951 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1952 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1953 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1957 ret = smu_update_table(smu,
1958 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1959 (void *)(&activity_monitor), true);
1961 pr_err("[%s] Failed to set activity monitor!", __func__);
1966 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1967 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1968 if (workload_type < 0)
1970 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1971 1 << workload_type);
1977 vega20_get_profiling_clk_mask(struct smu_context *smu,
1978 enum amd_dpm_forced_level level,
1979 uint32_t *sclk_mask,
1980 uint32_t *mclk_mask,
1983 struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1984 struct vega20_single_dpm_table *gfx_dpm_table;
1985 struct vega20_single_dpm_table *mem_dpm_table;
1986 struct vega20_single_dpm_table *soc_dpm_table;
1988 if (!smu->smu_dpm.dpm_context)
1991 gfx_dpm_table = &dpm_table->gfx_table;
1992 mem_dpm_table = &dpm_table->mem_table;
1993 soc_dpm_table = &dpm_table->soc_table;
1999 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2000 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2001 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2002 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2003 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2004 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2007 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2009 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2011 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2012 *sclk_mask = gfx_dpm_table->count - 1;
2013 *mclk_mask = mem_dpm_table->count - 1;
2014 *soc_mask = soc_dpm_table->count - 1;
2021 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2022 struct vega20_single_dpm_table *dpm_table)
2025 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2026 if (!smu_dpm_ctx->dpm_context)
2029 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2030 if (dpm_table->count <= 0) {
2031 pr_err("[%s] Dpm table has no entry!", __func__);
2035 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2036 pr_err("[%s] Dpm table has too many entries!", __func__);
2040 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2041 ret = smu_send_smc_msg_with_param(smu,
2042 SMU_MSG_SetHardMinByFreq,
2043 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2045 pr_err("[%s] Set hard min uclk failed!", __func__);
2053 static int vega20_pre_display_config_changed(struct smu_context *smu)
2056 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2058 if (!smu->smu_dpm.dpm_context)
2061 smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2062 ret = vega20_set_uclk_to_highest_dpm_level(smu,
2063 &dpm_table->mem_table);
2065 pr_err("Failed to set uclk to highest dpm level");
2069 static int vega20_display_config_changed(struct smu_context *smu)
2073 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2074 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2075 ret = smu_write_watermarks_table(smu);
2077 pr_err("Failed to update WMTABLE!");
2080 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2083 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2084 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2085 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2086 smu_send_smc_msg_with_param(smu,
2087 SMU_MSG_NumOfDisplays,
2088 smu->display_config->num_display);
2094 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2096 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2097 struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2098 struct vega20_single_dpm_table *dpm_table;
2099 bool vblank_too_short = false;
2100 bool disable_mclk_switching;
2101 uint32_t i, latency;
2103 disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2104 !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2105 latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2108 dpm_table = &(dpm_ctx->gfx_table);
2109 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2110 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2111 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2112 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2114 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2115 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2116 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2119 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2120 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2121 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2124 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2125 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2126 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2130 dpm_table = &(dpm_ctx->mem_table);
2131 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2132 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2133 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2134 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2136 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2137 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2138 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2141 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2142 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2143 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2146 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2147 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2148 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2151 /* honour DAL's UCLK Hardmin */
2152 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2153 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2155 /* Hardmin is dependent on displayconfig */
2156 if (disable_mclk_switching) {
2157 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2158 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2159 if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2160 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2161 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2168 if (smu->display_config->nb_pstate_switch_disable)
2169 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2172 dpm_table = &(dpm_ctx->vclk_table);
2173 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2174 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2175 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2176 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2178 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2179 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2180 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2183 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2184 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2185 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2189 dpm_table = &(dpm_ctx->dclk_table);
2190 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2191 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2192 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2193 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2195 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2196 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2197 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2200 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2201 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2202 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2206 dpm_table = &(dpm_ctx->soc_table);
2207 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2208 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2209 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2210 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2212 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2213 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2214 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2217 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2218 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2219 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2223 dpm_table = &(dpm_ctx->eclk_table);
2224 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2225 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2226 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2227 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2229 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2230 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2231 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2234 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2235 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2236 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2242 vega20_notify_smc_display_config(struct smu_context *smu)
2244 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2245 struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2246 struct smu_clocks min_clocks = {0};
2247 struct pp_display_clock_request clock_req;
2250 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2251 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2252 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2254 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2255 clock_req.clock_type = amd_pp_dcef_clock;
2256 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2257 if (!smu_v11_0_display_clock_voltage_request(smu, &clock_req)) {
2258 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2259 ret = smu_send_smc_msg_with_param(smu,
2260 SMU_MSG_SetMinDeepSleepDcefclk,
2261 min_clocks.dcef_clock_in_sr/100);
2263 pr_err("Attempt to set divider for DCEFCLK Failed!");
2268 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2272 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2273 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2274 ret = smu_send_smc_msg_with_param(smu,
2275 SMU_MSG_SetHardMinByFreq,
2276 (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2278 pr_err("[%s] Set hard min uclk failed!", __func__);
2286 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2290 for (i = 0; i < table->count; i++) {
2291 if (table->dpm_levels[i].enabled)
2294 if (i >= table->count) {
2296 table->dpm_levels[i].enabled = true;
2302 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2307 pr_err("[%s] DPM Table does not exist!", __func__);
2310 if (table->count <= 0) {
2311 pr_err("[%s] DPM Table has no entry!", __func__);
2314 if (table->count > MAX_REGULAR_DPM_NUMBER) {
2315 pr_err("[%s] DPM Table has too many entries!", __func__);
2316 return MAX_REGULAR_DPM_NUMBER - 1;
2319 for (i = table->count - 1; i >= 0; i--) {
2320 if (table->dpm_levels[i].enabled)
2325 table->dpm_levels[i].enabled = true;
2331 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2333 uint32_t soft_level;
2335 struct vega20_dpm_table *dpm_table =
2336 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2339 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2341 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2343 dpm_table->gfx_table.dpm_state.soft_min_level =
2344 dpm_table->gfx_table.dpm_state.soft_max_level =
2345 dpm_table->gfx_table.dpm_levels[soft_level].value;
2348 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2350 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2352 dpm_table->mem_table.dpm_state.soft_min_level =
2353 dpm_table->mem_table.dpm_state.soft_max_level =
2354 dpm_table->mem_table.dpm_levels[soft_level].value;
2357 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2359 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2361 dpm_table->soc_table.dpm_state.soft_min_level =
2362 dpm_table->soc_table.dpm_state.soft_max_level =
2363 dpm_table->soc_table.dpm_levels[soft_level].value;
2365 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2367 pr_err("Failed to upload boot level to %s!\n",
2368 highest ? "highest" : "lowest");
2372 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2374 pr_err("Failed to upload dpm max level to %s!\n!",
2375 highest ? "highest" : "lowest");
2382 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2384 uint32_t soft_min_level, soft_max_level;
2386 struct vega20_dpm_table *dpm_table =
2387 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2389 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2390 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2391 dpm_table->gfx_table.dpm_state.soft_min_level =
2392 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2393 dpm_table->gfx_table.dpm_state.soft_max_level =
2394 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2396 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2397 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2398 dpm_table->mem_table.dpm_state.soft_min_level =
2399 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2400 dpm_table->mem_table.dpm_state.soft_max_level =
2401 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2403 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2404 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2405 dpm_table->soc_table.dpm_state.soft_min_level =
2406 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2407 dpm_table->soc_table.dpm_state.soft_max_level =
2408 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2410 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2412 pr_err("Failed to upload DPM Bootup Levels!");
2416 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2418 pr_err("Failed to upload DPM Max Levels!");
2425 static int vega20_update_specified_od8_value(struct smu_context *smu,
2429 struct smu_table_context *table_context = &smu->smu_table;
2430 OverDriveTable_t *od_table =
2431 (OverDriveTable_t *)(table_context->overdrive_table);
2432 struct vega20_od8_settings *od8_settings =
2433 (struct vega20_od8_settings *)smu->od_settings;
2436 case OD8_SETTING_GFXCLK_FMIN:
2437 od_table->GfxclkFmin = (uint16_t)value;
2440 case OD8_SETTING_GFXCLK_FMAX:
2441 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2442 value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2444 od_table->GfxclkFmax = (uint16_t)value;
2447 case OD8_SETTING_GFXCLK_FREQ1:
2448 od_table->GfxclkFreq1 = (uint16_t)value;
2451 case OD8_SETTING_GFXCLK_VOLTAGE1:
2452 od_table->GfxclkVolt1 = (uint16_t)value;
2455 case OD8_SETTING_GFXCLK_FREQ2:
2456 od_table->GfxclkFreq2 = (uint16_t)value;
2459 case OD8_SETTING_GFXCLK_VOLTAGE2:
2460 od_table->GfxclkVolt2 = (uint16_t)value;
2463 case OD8_SETTING_GFXCLK_FREQ3:
2464 od_table->GfxclkFreq3 = (uint16_t)value;
2467 case OD8_SETTING_GFXCLK_VOLTAGE3:
2468 od_table->GfxclkVolt3 = (uint16_t)value;
2471 case OD8_SETTING_UCLK_FMAX:
2472 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2473 value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2475 od_table->UclkFmax = (uint16_t)value;
2478 case OD8_SETTING_POWER_PERCENTAGE:
2479 od_table->OverDrivePct = (int16_t)value;
2482 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2483 od_table->FanMaximumRpm = (uint16_t)value;
2486 case OD8_SETTING_FAN_MIN_SPEED:
2487 od_table->FanMinimumPwm = (uint16_t)value;
2490 case OD8_SETTING_FAN_TARGET_TEMP:
2491 od_table->FanTargetTemperature = (uint16_t)value;
2494 case OD8_SETTING_OPERATING_TEMP_MAX:
2495 od_table->MaxOpTemp = (uint16_t)value;
2502 static int vega20_update_od8_settings(struct smu_context *smu,
2506 struct smu_table_context *table_context = &smu->smu_table;
2509 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2510 table_context->overdrive_table, false);
2512 pr_err("Failed to export over drive table!\n");
2516 ret = vega20_update_specified_od8_value(smu, index, value);
2520 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2521 table_context->overdrive_table, true);
2523 pr_err("Failed to import over drive table!\n");
2530 static int vega20_set_od_percentage(struct smu_context *smu,
2531 enum smu_clk_type clk_type,
2534 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2535 struct vega20_dpm_table *dpm_table = NULL;
2536 struct vega20_dpm_table *golden_table = NULL;
2537 struct vega20_single_dpm_table *single_dpm_table;
2538 struct vega20_single_dpm_table *golden_dpm_table;
2539 uint32_t od_clk, index;
2541 int feature_enabled;
2544 dpm_table = smu_dpm->dpm_context;
2545 golden_table = smu_dpm->golden_dpm_context;
2549 single_dpm_table = &(dpm_table->gfx_table);
2550 golden_dpm_table = &(golden_table->gfx_table);
2551 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2552 clk_id = PPCLK_GFXCLK;
2553 index = OD8_SETTING_GFXCLK_FMAX;
2556 single_dpm_table = &(dpm_table->mem_table);
2557 golden_dpm_table = &(golden_table->mem_table);
2558 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2559 clk_id = PPCLK_UCLK;
2560 index = OD8_SETTING_UCLK_FMAX;
2570 od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2572 od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2574 ret = vega20_update_od8_settings(smu, index, od_clk);
2576 pr_err("[Setoverdrive] failed to set od clk!\n");
2580 if (feature_enabled) {
2581 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2584 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2588 single_dpm_table->count = 1;
2589 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2592 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2593 AMD_PP_TASK_READJUST_POWER_STATE,
2600 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2601 enum PP_OD_DPM_TABLE_COMMAND type,
2602 long *input, uint32_t size)
2604 struct smu_table_context *table_context = &smu->smu_table;
2605 OverDriveTable_t *od_table =
2606 (OverDriveTable_t *)(table_context->overdrive_table);
2607 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2608 struct vega20_dpm_table *dpm_table = NULL;
2609 struct vega20_single_dpm_table *single_dpm_table;
2610 struct vega20_od8_settings *od8_settings =
2611 (struct vega20_od8_settings *)smu->od_settings;
2612 struct pp_clock_levels_with_latency clocks;
2613 int32_t input_index, input_clk, input_vol, i;
2617 dpm_table = smu_dpm->dpm_context;
2620 pr_warn("NULL user input for clock and voltage\n");
2625 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2626 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2627 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2628 pr_info("Sclk min/max frequency overdrive not supported\n");
2632 for (i = 0; i < size; i += 2) {
2634 pr_info("invalid number of input parameters %d\n", size);
2638 input_index = input[i];
2639 input_clk = input[i + 1];
2641 if (input_index != 0 && input_index != 1) {
2642 pr_info("Invalid index %d\n", input_index);
2643 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2647 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2648 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2649 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2651 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2652 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2656 if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2657 od_table->GfxclkFmin = input_clk;
2658 od8_settings->od_gfxclk_update = true;
2659 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2660 od_table->GfxclkFmax = input_clk;
2661 od8_settings->od_gfxclk_update = true;
2667 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2668 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2669 pr_info("Mclk max frequency overdrive not supported\n");
2673 single_dpm_table = &(dpm_table->mem_table);
2674 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2676 pr_err("Attempt to get memory clk levels Failed!");
2680 for (i = 0; i < size; i += 2) {
2682 pr_info("invalid number of input parameters %d\n",
2687 input_index = input[i];
2688 input_clk = input[i + 1];
2690 if (input_index != 1) {
2691 pr_info("Invalid index %d\n", input_index);
2692 pr_info("Support max Mclk frequency setting only which index by 1\n");
2696 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2697 input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2698 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2700 clocks.data[0].clocks_in_khz / 1000,
2701 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2705 if (input_index == 1 && od_table->UclkFmax != input_clk) {
2706 od8_settings->od_gfxclk_update = true;
2707 od_table->UclkFmax = input_clk;
2713 case PP_OD_EDIT_VDDC_CURVE:
2714 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2715 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2716 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2717 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2718 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2719 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2720 pr_info("Voltage curve calibrate not supported\n");
2724 for (i = 0; i < size; i += 3) {
2726 pr_info("invalid number of input parameters %d\n",
2731 input_index = input[i];
2732 input_clk = input[i + 1];
2733 input_vol = input[i + 2];
2735 if (input_index > 2) {
2736 pr_info("Setting for point %d is not supported\n",
2738 pr_info("Three supported points index by 0, 1, 2\n");
2742 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2743 if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2744 input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2745 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2747 od8_settings->od8_settings_array[od8_id].min_value,
2748 od8_settings->od8_settings_array[od8_id].max_value);
2752 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2753 if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2754 input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2755 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2757 od8_settings->od8_settings_array[od8_id].min_value,
2758 od8_settings->od8_settings_array[od8_id].max_value);
2762 switch (input_index) {
2764 od_table->GfxclkFreq1 = input_clk;
2765 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2768 od_table->GfxclkFreq2 = input_clk;
2769 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2772 od_table->GfxclkFreq3 = input_clk;
2773 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2780 case PP_OD_RESTORE_DEFAULT_TABLE:
2781 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
2783 pr_err("Failed to export over drive table!\n");
2789 case PP_OD_COMMIT_DPM_TABLE:
2790 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
2792 pr_err("Failed to import over drive table!\n");
2796 /* retrieve updated gfxclk table */
2797 if (od8_settings->od_gfxclk_update) {
2798 od8_settings->od_gfxclk_update = false;
2799 single_dpm_table = &(dpm_table->gfx_table);
2801 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2802 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2805 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2809 single_dpm_table->count = 1;
2810 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2820 if (type == PP_OD_COMMIT_DPM_TABLE) {
2821 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2822 AMD_PP_TASK_READJUST_POWER_STATE,
2829 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2831 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2834 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2837 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2840 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2842 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2845 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2848 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2851 static bool vega20_is_dpm_running(struct smu_context *smu)
2854 uint32_t feature_mask[2];
2855 unsigned long feature_enabled;
2856 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2857 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
2858 ((uint64_t)feature_mask[1] << 32));
2859 return !!(feature_enabled & SMC_DPM_FEATURE);
2862 static int vega20_set_thermal_fan_table(struct smu_context *smu)
2865 struct smu_table_context *table_context = &smu->smu_table;
2866 PPTable_t *pptable = table_context->driver_pptable;
2868 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
2869 (uint32_t)pptable->FanTargetTemperature);
2874 static int vega20_get_fan_speed_rpm(struct smu_context *smu,
2879 ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
2882 pr_err("Attempt to get current RPM from SMC Failed!\n");
2886 smu_read_smc_arg(smu, speed);
2891 static int vega20_get_fan_speed_percent(struct smu_context *smu,
2895 uint32_t current_rpm = 0, percent = 0;
2896 PPTable_t *pptable = smu->smu_table.driver_pptable;
2898 ret = vega20_get_fan_speed_rpm(smu, ¤t_rpm);
2902 percent = current_rpm * 100 / pptable->FanMaximumRpm;
2903 *speed = percent > 100 ? 100 : percent;
2908 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
2910 uint32_t smu_version;
2912 SmuMetrics_t metrics;
2917 ret = vega20_get_metrics_table(smu, &metrics);
2921 ret = smu_get_smc_version(smu, NULL, &smu_version);
2925 /* For the 40.46 release, they changed the value name */
2926 if (smu_version == 0x282e00)
2927 *value = metrics.AverageSocketPower << 8;
2929 *value = metrics.CurrSocketPower << 8;
2934 static int vega20_get_current_activity_percent(struct smu_context *smu,
2935 enum amd_pp_sensors sensor,
2939 SmuMetrics_t metrics;
2944 ret = vega20_get_metrics_table(smu, &metrics);
2949 case AMDGPU_PP_SENSOR_GPU_LOAD:
2950 *value = metrics.AverageGfxActivity;
2952 case AMDGPU_PP_SENSOR_MEM_LOAD:
2953 *value = metrics.AverageUclkActivity;
2956 pr_err("Invalid sensor for retrieving clock activity\n");
2963 static int vega20_thermal_get_temperature(struct smu_context *smu,
2964 enum amd_pp_sensors sensor,
2967 struct amdgpu_device *adev = smu->adev;
2968 SmuMetrics_t metrics;
2975 ret = vega20_get_metrics_table(smu, &metrics);
2980 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2981 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
2982 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
2983 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
2985 temp = temp & 0x1ff;
2986 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2990 case AMDGPU_PP_SENSOR_EDGE_TEMP:
2991 *value = metrics.TemperatureEdge *
2992 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2994 case AMDGPU_PP_SENSOR_MEM_TEMP:
2995 *value = metrics.TemperatureHBM *
2996 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2999 pr_err("Invalid sensor for retrieving temp\n");
3005 static int vega20_read_sensor(struct smu_context *smu,
3006 enum amd_pp_sensors sensor,
3007 void *data, uint32_t *size)
3010 struct smu_table_context *table_context = &smu->smu_table;
3011 PPTable_t *pptable = table_context->driver_pptable;
3016 mutex_lock(&smu->sensor_lock);
3018 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3019 *(uint32_t *)data = pptable->FanMaximumRpm;
3022 case AMDGPU_PP_SENSOR_MEM_LOAD:
3023 case AMDGPU_PP_SENSOR_GPU_LOAD:
3024 ret = vega20_get_current_activity_percent(smu,
3029 case AMDGPU_PP_SENSOR_GPU_POWER:
3030 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3033 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3034 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3035 case AMDGPU_PP_SENSOR_MEM_TEMP:
3036 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3040 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
3042 mutex_unlock(&smu->sensor_lock);
3047 static int vega20_set_watermarks_table(struct smu_context *smu,
3048 void *watermarks, struct
3049 dm_pp_wm_sets_with_clock_ranges_soc15
3053 Watermarks_t *table = watermarks;
3055 if (!table || !clock_ranges)
3058 if (clock_ranges->num_wm_dmif_sets > 4 ||
3059 clock_ranges->num_wm_mcif_sets > 4)
3062 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3063 table->WatermarkRow[1][i].MinClock =
3064 cpu_to_le16((uint16_t)
3065 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3067 table->WatermarkRow[1][i].MaxClock =
3068 cpu_to_le16((uint16_t)
3069 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3071 table->WatermarkRow[1][i].MinUclk =
3072 cpu_to_le16((uint16_t)
3073 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3075 table->WatermarkRow[1][i].MaxUclk =
3076 cpu_to_le16((uint16_t)
3077 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3079 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3080 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3083 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3084 table->WatermarkRow[0][i].MinClock =
3085 cpu_to_le16((uint16_t)
3086 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3088 table->WatermarkRow[0][i].MaxClock =
3089 cpu_to_le16((uint16_t)
3090 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3092 table->WatermarkRow[0][i].MinUclk =
3093 cpu_to_le16((uint16_t)
3094 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3096 table->WatermarkRow[0][i].MaxUclk =
3097 cpu_to_le16((uint16_t)
3098 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3100 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3101 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3107 static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3108 struct smu_temperature_range *range)
3110 struct smu_table_context *table_context = &smu->smu_table;
3111 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = table_context->power_play_table;
3112 PPTable_t *pptable = smu->smu_table.driver_pptable;
3114 if (!range || !powerplay_table)
3117 range->max = powerplay_table->usSoftwareShutdownTemp *
3118 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3119 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
3120 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3121 range->hotspot_crit_max = pptable->ThotspotLimit *
3122 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3123 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
3124 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3125 range->mem_crit_max = pptable->ThbmLimit *
3126 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3127 range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM) *
3128 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3134 static int vega20_set_df_cstate(struct smu_context *smu,
3135 enum pp_df_cstate state)
3137 uint32_t smu_version;
3140 ret = smu_get_smc_version(smu, NULL, &smu_version);
3142 pr_err("Failed to get smu version!\n");
3146 /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
3147 if (smu_version < 0x283200) {
3148 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
3152 return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
3155 static int vega20_update_pcie_parameters(struct smu_context *smu,
3156 uint32_t pcie_gen_cap,
3157 uint32_t pcie_width_cap)
3159 PPTable_t *pptable = smu->smu_table.driver_pptable;
3161 uint32_t smu_pcie_arg;
3163 for (i = 0; i < NUM_LINK_LEVELS; i++) {
3164 smu_pcie_arg = (i << 16) |
3165 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
3166 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
3167 pptable->PcieLaneCount[i] : pcie_width_cap);
3168 ret = smu_send_smc_msg_with_param(smu,
3169 SMU_MSG_OverridePcieParameters,
3177 static const struct pptable_funcs vega20_ppt_funcs = {
3178 .tables_init = vega20_tables_init,
3179 .alloc_dpm_context = vega20_allocate_dpm_context,
3180 .store_powerplay_table = vega20_store_powerplay_table,
3181 .check_powerplay_table = vega20_check_powerplay_table,
3182 .append_powerplay_table = vega20_append_powerplay_table,
3183 .get_smu_msg_index = vega20_get_smu_msg_index,
3184 .get_smu_clk_index = vega20_get_smu_clk_index,
3185 .get_smu_feature_index = vega20_get_smu_feature_index,
3186 .get_smu_table_index = vega20_get_smu_table_index,
3187 .get_smu_power_index = vega20_get_pwr_src_index,
3188 .get_workload_type = vega20_get_workload_type,
3189 .run_btc = vega20_run_btc_afll,
3190 .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3191 .get_current_power_state = vega20_get_current_power_state,
3192 .set_default_dpm_table = vega20_set_default_dpm_table,
3193 .set_power_state = NULL,
3194 .populate_umd_state_clk = vega20_populate_umd_state_clk,
3195 .print_clk_levels = vega20_print_clk_levels,
3196 .force_clk_levels = vega20_force_clk_levels,
3197 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3198 .get_od_percentage = vega20_get_od_percentage,
3199 .get_power_profile_mode = vega20_get_power_profile_mode,
3200 .set_power_profile_mode = vega20_set_power_profile_mode,
3201 .set_performance_level = smu_v11_0_set_performance_level,
3202 .set_od_percentage = vega20_set_od_percentage,
3203 .set_default_od_settings = vega20_set_default_od_settings,
3204 .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3205 .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3206 .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3207 .read_sensor = vega20_read_sensor,
3208 .pre_display_config_changed = vega20_pre_display_config_changed,
3209 .display_config_changed = vega20_display_config_changed,
3210 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3211 .notify_smc_display_config = vega20_notify_smc_display_config,
3212 .force_dpm_limit_value = vega20_force_dpm_limit_value,
3213 .unforce_dpm_levels = vega20_unforce_dpm_levels,
3214 .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3215 .is_dpm_running = vega20_is_dpm_running,
3216 .set_thermal_fan_table = vega20_set_thermal_fan_table,
3217 .get_fan_speed_percent = vega20_get_fan_speed_percent,
3218 .get_fan_speed_rpm = vega20_get_fan_speed_rpm,
3219 .set_watermarks_table = vega20_set_watermarks_table,
3220 .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3221 .set_df_cstate = vega20_set_df_cstate,
3222 .update_pcie_parameters = vega20_update_pcie_parameters,
3223 .init_microcode = smu_v11_0_init_microcode,
3224 .load_microcode = smu_v11_0_load_microcode,
3225 .init_smc_tables = smu_v11_0_init_smc_tables,
3226 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3227 .init_power = smu_v11_0_init_power,
3228 .fini_power = smu_v11_0_fini_power,
3229 .check_fw_status = smu_v11_0_check_fw_status,
3230 .setup_pptable = smu_v11_0_setup_pptable,
3231 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3232 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
3233 .check_pptable = smu_v11_0_check_pptable,
3234 .parse_pptable = smu_v11_0_parse_pptable,
3235 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
3236 .check_fw_version = smu_v11_0_check_fw_version,
3237 .write_pptable = smu_v11_0_write_pptable,
3238 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
3239 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3240 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3241 .system_features_control = smu_v11_0_system_features_control,
3242 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
3243 .read_smc_arg = smu_v11_0_read_arg,
3244 .init_display_count = smu_v11_0_init_display_count,
3245 .set_allowed_mask = smu_v11_0_set_allowed_mask,
3246 .get_enabled_mask = smu_v11_0_get_enabled_mask,
3247 .notify_display_change = smu_v11_0_notify_display_change,
3248 .set_power_limit = smu_v11_0_set_power_limit,
3249 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
3250 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3251 .start_thermal_control = smu_v11_0_start_thermal_control,
3252 .stop_thermal_control = smu_v11_0_stop_thermal_control,
3253 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
3254 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3255 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3256 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3257 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
3258 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3259 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3260 .gfx_off_control = smu_v11_0_gfx_off_control,
3261 .register_irq_handler = smu_v11_0_register_irq_handler,
3262 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3263 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3264 .baco_is_support= smu_v11_0_baco_is_support,
3265 .baco_get_state = smu_v11_0_baco_get_state,
3266 .baco_set_state = smu_v11_0_baco_set_state,
3267 .baco_enter = smu_v11_0_baco_enter,
3268 .baco_exit = smu_v11_0_baco_exit,
3269 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3270 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3271 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
3274 void vega20_set_ppt_funcs(struct smu_context *smu)
3276 smu->ppt_funcs = &vega20_ppt_funcs;