2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "atomfirmware.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "smu_v11_0.h"
31 #include "smu11_driver_if.h"
32 #include "soc15_common.h"
34 #include "power_state.h"
35 #include "vega20_ppt.h"
36 #include "vega20_pptable.h"
37 #include "vega20_ppsmc.h"
38 #include "nbio/nbio_7_4_sh_mask.h"
40 #define smnPCIE_LC_SPEED_CNTL 0x11140290
41 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
43 #define MSG_MAP(msg) \
44 [SMU_MSG_##msg] = PPSMC_MSG_##msg
46 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
47 FEATURE_DPM_GFXCLK_MASK | \
48 FEATURE_DPM_UCLK_MASK | \
49 FEATURE_DPM_SOCCLK_MASK | \
50 FEATURE_DPM_UVD_MASK | \
51 FEATURE_DPM_VCE_MASK | \
52 FEATURE_DPM_MP0CLK_MASK | \
53 FEATURE_DPM_LINK_MASK | \
54 FEATURE_DPM_DCEFCLK_MASK)
56 static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
58 MSG_MAP(GetSmuVersion),
59 MSG_MAP(GetDriverIfVersion),
60 MSG_MAP(SetAllowedFeaturesMaskLow),
61 MSG_MAP(SetAllowedFeaturesMaskHigh),
62 MSG_MAP(EnableAllSmuFeatures),
63 MSG_MAP(DisableAllSmuFeatures),
64 MSG_MAP(EnableSmuFeaturesLow),
65 MSG_MAP(EnableSmuFeaturesHigh),
66 MSG_MAP(DisableSmuFeaturesLow),
67 MSG_MAP(DisableSmuFeaturesHigh),
68 MSG_MAP(GetEnabledSmuFeaturesLow),
69 MSG_MAP(GetEnabledSmuFeaturesHigh),
70 MSG_MAP(SetWorkloadMask),
72 MSG_MAP(SetDriverDramAddrHigh),
73 MSG_MAP(SetDriverDramAddrLow),
74 MSG_MAP(SetToolsDramAddrHigh),
75 MSG_MAP(SetToolsDramAddrLow),
76 MSG_MAP(TransferTableSmu2Dram),
77 MSG_MAP(TransferTableDram2Smu),
78 MSG_MAP(UseDefaultPPTable),
79 MSG_MAP(UseBackupPPTable),
81 MSG_MAP(RequestI2CBus),
82 MSG_MAP(ReleaseI2CBus),
83 MSG_MAP(SetFloorSocVoltage),
85 MSG_MAP(StartBacoMonitor),
86 MSG_MAP(CancelBacoMonitor),
88 MSG_MAP(SetSoftMinByFreq),
89 MSG_MAP(SetSoftMaxByFreq),
90 MSG_MAP(SetHardMinByFreq),
91 MSG_MAP(SetHardMaxByFreq),
92 MSG_MAP(GetMinDpmFreq),
93 MSG_MAP(GetMaxDpmFreq),
94 MSG_MAP(GetDpmFreqByIndex),
95 MSG_MAP(GetDpmClockFreq),
96 MSG_MAP(GetSsVoltageByDpm),
97 MSG_MAP(SetMemoryChannelConfig),
98 MSG_MAP(SetGeminiMode),
99 MSG_MAP(SetGeminiApertureHigh),
100 MSG_MAP(SetGeminiApertureLow),
101 MSG_MAP(SetMinLinkDpmByIndex),
102 MSG_MAP(OverridePcieParameters),
103 MSG_MAP(OverDriveSetPercentage),
104 MSG_MAP(SetMinDeepSleepDcefclk),
105 MSG_MAP(ReenableAcDcInterrupt),
106 MSG_MAP(NotifyPowerSource),
107 MSG_MAP(SetUclkFastSwitch),
108 MSG_MAP(SetUclkDownHyst),
109 MSG_MAP(GetCurrentRpm),
110 MSG_MAP(SetVideoFps),
112 MSG_MAP(SetFanTemperatureTarget),
113 MSG_MAP(PrepareMp1ForUnload),
114 MSG_MAP(DramLogSetDramAddrHigh),
115 MSG_MAP(DramLogSetDramAddrLow),
116 MSG_MAP(DramLogSetDramSize),
117 MSG_MAP(SetFanMaxRpm),
118 MSG_MAP(SetFanMinPwm),
119 MSG_MAP(ConfigureGfxDidt),
120 MSG_MAP(NumOfDisplays),
121 MSG_MAP(RemoveMargins),
122 MSG_MAP(ReadSerialNumTop32),
123 MSG_MAP(ReadSerialNumBottom32),
124 MSG_MAP(SetSystemVirtualDramAddrHigh),
125 MSG_MAP(SetSystemVirtualDramAddrLow),
127 MSG_MAP(SetFclkGfxClkRatio),
128 MSG_MAP(AllowGfxOff),
129 MSG_MAP(DisallowGfxOff),
130 MSG_MAP(GetPptLimit),
131 MSG_MAP(GetDcModeMaxDpmFreq),
132 MSG_MAP(GetDebugData),
133 MSG_MAP(SetXgmiMode),
136 MSG_MAP(PrepareMp1ForReset),
137 MSG_MAP(PrepareMp1ForShutdown),
138 MSG_MAP(SetMGpuFanBoostLimitRpm),
139 MSG_MAP(GetAVFSVoltageByDpm),
142 static int vega20_clk_map[SMU_CLK_COUNT] = {
143 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
144 CLK_MAP(VCLK, PPCLK_VCLK),
145 CLK_MAP(DCLK, PPCLK_DCLK),
146 CLK_MAP(ECLK, PPCLK_ECLK),
147 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
148 CLK_MAP(UCLK, PPCLK_UCLK),
149 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
150 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
151 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
152 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
153 CLK_MAP(FCLK, PPCLK_FCLK),
156 static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
157 FEA_MAP(DPM_PREFETCHER),
166 FEA_MAP(DPM_DCEFCLK),
173 FEA_MAP(GFX_PER_CU_CG),
180 FEA_MAP(LED_DISPLAY),
181 FEA_MAP(FAN_CONTROL),
192 static int vega20_table_map[SMU_TABLE_COUNT] = {
196 TAB_MAP(AVFS_PSM_DEBUG),
197 TAB_MAP(AVFS_FUSE_OVERRIDE),
198 TAB_MAP(PMSTATUSLOG),
199 TAB_MAP(SMU_METRICS),
200 TAB_MAP(DRIVER_SMU_CONFIG),
201 TAB_MAP(ACTIVITY_MONITOR_COEFF),
205 static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
210 static int vega20_workload_map[] = {
211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
213 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
214 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
215 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
216 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
220 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
223 if (index >= SMU_TABLE_COUNT)
226 val = vega20_table_map[index];
227 if (val >= TABLE_COUNT)
233 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
236 if (index >= SMU_POWER_SOURCE_COUNT)
239 val = vega20_pwr_src_map[index];
240 if (val >= POWER_SOURCE_COUNT)
246 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
249 if (index >= SMU_FEATURE_COUNT)
252 val = vega20_feature_mask_map[index];
259 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
262 if (index >= SMU_CLK_COUNT)
265 val = vega20_clk_map[index];
266 if (val >= PPCLK_COUNT)
272 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
276 if (index >= SMU_MSG_MAX_COUNT)
279 val = vega20_message_map[index];
280 if (val > PPSMC_Message_Count)
286 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
289 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
292 val = vega20_workload_map[profile];
297 static void vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
299 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
300 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
301 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
302 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
303 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
304 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
305 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
306 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
307 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
308 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
309 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
310 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
311 AMDGPU_GEM_DOMAIN_VRAM);
314 static int vega20_allocate_dpm_context(struct smu_context *smu)
316 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
318 if (smu_dpm->dpm_context)
321 smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
323 if (!smu_dpm->dpm_context)
326 if (smu_dpm->golden_dpm_context)
329 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
331 if (!smu_dpm->golden_dpm_context)
334 smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
336 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
338 if (!smu_dpm->dpm_current_power_state)
341 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
343 if (!smu_dpm->dpm_request_power_state)
349 static int vega20_setup_od8_information(struct smu_context *smu)
351 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
352 struct smu_table_context *table_context = &smu->smu_table;
354 uint32_t od_feature_count, od_feature_array_size,
355 od_setting_count, od_setting_array_size;
357 if (!table_context->power_play_table)
360 powerplay_table = table_context->power_play_table;
362 if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
363 /* Setup correct ODFeatureCount, and store ODFeatureArray from
364 * powerplay table to od_feature_capabilities */
366 (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
367 ATOM_VEGA20_ODFEATURE_COUNT) ?
368 ATOM_VEGA20_ODFEATURE_COUNT :
369 le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
371 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
373 if (table_context->od_feature_capabilities)
376 table_context->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
377 od_feature_array_size,
379 if (!table_context->od_feature_capabilities)
382 /* Setup correct ODSettingCount, and store ODSettingArray from
383 * powerplay table to od_settings_max and od_setting_min */
385 (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
386 ATOM_VEGA20_ODSETTING_COUNT) ?
387 ATOM_VEGA20_ODSETTING_COUNT :
388 le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
390 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
392 if (table_context->od_settings_max)
395 table_context->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
396 od_setting_array_size,
399 if (!table_context->od_settings_max) {
400 kfree(table_context->od_feature_capabilities);
401 table_context->od_feature_capabilities = NULL;
405 if (table_context->od_settings_min)
408 table_context->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
409 od_setting_array_size,
412 if (!table_context->od_settings_min) {
413 kfree(table_context->od_feature_capabilities);
414 table_context->od_feature_capabilities = NULL;
415 kfree(table_context->od_settings_max);
416 table_context->od_settings_max = NULL;
424 static int vega20_store_powerplay_table(struct smu_context *smu)
426 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
427 struct smu_table_context *table_context = &smu->smu_table;
430 if (!table_context->power_play_table)
433 powerplay_table = table_context->power_play_table;
435 memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
438 table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
439 table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
440 table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
442 ret = vega20_setup_od8_information(smu);
447 static int vega20_append_powerplay_table(struct smu_context *smu)
449 struct smu_table_context *table_context = &smu->smu_table;
450 PPTable_t *smc_pptable = table_context->driver_pptable;
451 struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
454 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
457 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
458 (uint8_t **)&smc_dpm_table);
462 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
463 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
465 smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
466 smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
467 smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
468 smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
470 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
471 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
472 smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
474 smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
475 smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
476 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
478 smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
479 smc_pptable->SocOffset = smc_dpm_table->socoffset;
480 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
482 smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
483 smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
484 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
486 smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
487 smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
488 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
490 smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
491 smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
492 smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
493 smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
495 smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
496 smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
497 smc_pptable->Padding1 = smc_dpm_table->padding1;
498 smc_pptable->Padding2 = smc_dpm_table->padding2;
500 smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
501 smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
502 smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
504 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
505 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
506 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
508 smc_pptable->UclkSpreadEnabled = 0;
509 smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
510 smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
512 smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
513 smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
514 smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
516 smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
517 smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
518 smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
520 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
521 smc_pptable->I2cControllers[i].Enabled =
522 smc_dpm_table->i2ccontrollers[i].enabled;
523 smc_pptable->I2cControllers[i].SlaveAddress =
524 smc_dpm_table->i2ccontrollers[i].slaveaddress;
525 smc_pptable->I2cControllers[i].ControllerPort =
526 smc_dpm_table->i2ccontrollers[i].controllerport;
527 smc_pptable->I2cControllers[i].ThermalThrottler =
528 smc_dpm_table->i2ccontrollers[i].thermalthrottler;
529 smc_pptable->I2cControllers[i].I2cProtocol =
530 smc_dpm_table->i2ccontrollers[i].i2cprotocol;
531 smc_pptable->I2cControllers[i].I2cSpeed =
532 smc_dpm_table->i2ccontrollers[i].i2cspeed;
538 static int vega20_check_powerplay_table(struct smu_context *smu)
540 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
541 struct smu_table_context *table_context = &smu->smu_table;
543 powerplay_table = table_context->power_play_table;
545 if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
546 pr_err("Unsupported PPTable format!");
550 if (!powerplay_table->sHeader.structuresize) {
551 pr_err("Invalid PowerPlay Table!");
558 static int vega20_run_btc_afll(struct smu_context *smu)
560 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
563 #define FEATURE_MASK(feature) (1UL << feature)
565 vega20_get_allowed_feature_mask(struct smu_context *smu,
566 uint32_t *feature_mask, uint32_t num)
571 memset(feature_mask, 0, sizeof(uint32_t) * num);
573 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
574 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
575 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
576 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
577 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
578 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
579 | FEATURE_MASK(FEATURE_ULV_BIT)
580 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
581 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
582 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
583 | FEATURE_MASK(FEATURE_PPT_BIT)
584 | FEATURE_MASK(FEATURE_TDC_BIT)
585 | FEATURE_MASK(FEATURE_THERMAL_BIT)
586 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
587 | FEATURE_MASK(FEATURE_RM_BIT)
588 | FEATURE_MASK(FEATURE_ACDC_BIT)
589 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
590 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
591 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
592 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
593 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
594 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
595 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
596 | FEATURE_MASK(FEATURE_CG_BIT)
597 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
598 | FEATURE_MASK(FEATURE_XGMI_BIT);
603 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
605 enum amd_pm_state_type pm_type;
606 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
608 if (!smu_dpm_ctx->dpm_context ||
609 !smu_dpm_ctx->dpm_current_power_state)
612 mutex_lock(&(smu->mutex));
613 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
614 case SMU_STATE_UI_LABEL_BATTERY:
615 pm_type = POWER_STATE_TYPE_BATTERY;
617 case SMU_STATE_UI_LABEL_BALLANCED:
618 pm_type = POWER_STATE_TYPE_BALANCED;
620 case SMU_STATE_UI_LABEL_PERFORMANCE:
621 pm_type = POWER_STATE_TYPE_PERFORMANCE;
624 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
625 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
627 pm_type = POWER_STATE_TYPE_DEFAULT;
630 mutex_unlock(&(smu->mutex));
636 vega20_set_single_dpm_table(struct smu_context *smu,
637 struct vega20_single_dpm_table *single_dpm_table,
641 uint32_t i, num_of_levels = 0, clk;
643 ret = smu_send_smc_msg_with_param(smu,
644 SMU_MSG_GetDpmFreqByIndex,
645 (clk_id << 16 | 0xFF));
647 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
651 smu_read_smc_arg(smu, &num_of_levels);
652 if (!num_of_levels) {
653 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
657 single_dpm_table->count = num_of_levels;
659 for (i = 0; i < num_of_levels; i++) {
660 ret = smu_send_smc_msg_with_param(smu,
661 SMU_MSG_GetDpmFreqByIndex,
664 pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
667 smu_read_smc_arg(smu, &clk);
669 pr_err("[GetDpmFreqByIndex] clk value is invalid!");
672 single_dpm_table->dpm_levels[i].value = clk;
673 single_dpm_table->dpm_levels[i].enabled = true;
678 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
680 dpm_state->soft_min_level = 0x0;
681 dpm_state->soft_max_level = 0xffff;
682 dpm_state->hard_min_level = 0x0;
683 dpm_state->hard_max_level = 0xffff;
686 static int vega20_set_default_dpm_table(struct smu_context *smu)
690 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
691 struct vega20_dpm_table *dpm_table = NULL;
692 struct vega20_single_dpm_table *single_dpm_table;
694 dpm_table = smu_dpm->dpm_context;
697 single_dpm_table = &(dpm_table->soc_table);
699 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
700 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
703 pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
707 single_dpm_table->count = 1;
708 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
710 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
713 single_dpm_table = &(dpm_table->gfx_table);
715 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
716 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
719 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
723 single_dpm_table->count = 1;
724 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
726 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
729 single_dpm_table = &(dpm_table->mem_table);
731 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
732 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
735 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
739 single_dpm_table->count = 1;
740 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
742 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
745 single_dpm_table = &(dpm_table->eclk_table);
747 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
748 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
750 pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
754 single_dpm_table->count = 1;
755 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
757 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
760 single_dpm_table = &(dpm_table->vclk_table);
762 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
763 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
765 pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
769 single_dpm_table->count = 1;
770 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
772 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
775 single_dpm_table = &(dpm_table->dclk_table);
777 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
778 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
780 pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
784 single_dpm_table->count = 1;
785 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
787 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
790 single_dpm_table = &(dpm_table->dcef_table);
792 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
793 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
796 pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
800 single_dpm_table->count = 1;
801 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
803 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
806 single_dpm_table = &(dpm_table->pixel_table);
808 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
809 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
812 pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
816 single_dpm_table->count = 0;
818 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
821 single_dpm_table = &(dpm_table->display_table);
823 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
824 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
827 pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
831 single_dpm_table->count = 0;
833 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
836 single_dpm_table = &(dpm_table->phy_table);
838 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
839 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
842 pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
846 single_dpm_table->count = 0;
848 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
851 single_dpm_table = &(dpm_table->fclk_table);
853 if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
854 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
857 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
861 single_dpm_table->count = 0;
863 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
865 memcpy(smu_dpm->golden_dpm_context, dpm_table,
866 sizeof(struct vega20_dpm_table));
871 static int vega20_populate_umd_state_clk(struct smu_context *smu)
873 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
874 struct vega20_dpm_table *dpm_table = NULL;
875 struct vega20_single_dpm_table *gfx_table = NULL;
876 struct vega20_single_dpm_table *mem_table = NULL;
878 dpm_table = smu_dpm->dpm_context;
879 gfx_table = &(dpm_table->gfx_table);
880 mem_table = &(dpm_table->mem_table);
882 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
883 smu->pstate_mclk = mem_table->dpm_levels[0].value;
885 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
886 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
887 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
888 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
891 smu->pstate_sclk = smu->pstate_sclk * 100;
892 smu->pstate_mclk = smu->pstate_mclk * 100;
897 static int vega20_get_clk_table(struct smu_context *smu,
898 struct pp_clock_levels_with_latency *clocks,
899 struct vega20_single_dpm_table *dpm_table)
903 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
904 clocks->num_levels = count;
906 for (i = 0; i < count; i++) {
907 clocks->data[i].clocks_in_khz =
908 dpm_table->dpm_levels[i].value * 1000;
909 clocks->data[i].latency_in_us = 0;
915 static int vega20_print_clk_levels(struct smu_context *smu,
916 enum smu_clk_type type, char *buf)
918 int i, now, size = 0;
920 uint32_t gen_speed, lane_width;
921 struct amdgpu_device *adev = smu->adev;
922 struct pp_clock_levels_with_latency clocks;
923 struct vega20_single_dpm_table *single_dpm_table;
924 struct smu_table_context *table_context = &smu->smu_table;
925 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
926 struct vega20_dpm_table *dpm_table = NULL;
927 struct vega20_od8_settings *od8_settings =
928 (struct vega20_od8_settings *)table_context->od8_settings;
929 OverDriveTable_t *od_table =
930 (OverDriveTable_t *)(table_context->overdrive_table);
931 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
933 dpm_table = smu_dpm->dpm_context;
937 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
939 pr_err("Attempt to get current gfx clk Failed!");
943 single_dpm_table = &(dpm_table->gfx_table);
944 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
946 pr_err("Attempt to get gfx clk levels Failed!");
950 for (i = 0; i < clocks.num_levels; i++)
951 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
952 clocks.data[i].clocks_in_khz / 1000,
953 (clocks.data[i].clocks_in_khz == now * 10)
958 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
960 pr_err("Attempt to get current mclk Failed!");
964 single_dpm_table = &(dpm_table->mem_table);
965 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
967 pr_err("Attempt to get memory clk levels Failed!");
971 for (i = 0; i < clocks.num_levels; i++)
972 size += sprintf(buf + size, "%d: %uMhz %s\n",
973 i, clocks.data[i].clocks_in_khz / 1000,
974 (clocks.data[i].clocks_in_khz == now * 10)
979 ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now);
981 pr_err("Attempt to get current socclk Failed!");
985 single_dpm_table = &(dpm_table->soc_table);
986 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
988 pr_err("Attempt to get socclk levels Failed!");
992 for (i = 0; i < clocks.num_levels; i++)
993 size += sprintf(buf + size, "%d: %uMhz %s\n",
994 i, clocks.data[i].clocks_in_khz / 1000,
995 (clocks.data[i].clocks_in_khz == now * 10)
1000 ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now);
1002 pr_err("Attempt to get current fclk Failed!");
1006 single_dpm_table = &(dpm_table->fclk_table);
1007 for (i = 0; i < single_dpm_table->count; i++)
1008 size += sprintf(buf + size, "%d: %uMhz %s\n",
1009 i, single_dpm_table->dpm_levels[i].value,
1010 (single_dpm_table->dpm_levels[i].value == now / 100)
1015 ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now);
1017 pr_err("Attempt to get current dcefclk Failed!");
1021 single_dpm_table = &(dpm_table->dcef_table);
1022 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1024 pr_err("Attempt to get dcefclk levels Failed!");
1028 for (i = 0; i < clocks.num_levels; i++)
1029 size += sprintf(buf + size, "%d: %uMhz %s\n",
1030 i, clocks.data[i].clocks_in_khz / 1000,
1031 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1035 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1036 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1037 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1038 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1039 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1040 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1041 for (i = 0; i < NUM_LINK_LEVELS; i++)
1042 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1043 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1044 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1045 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1046 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1047 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1048 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1049 (pptable->PcieLaneCount[i] == 3) ? "x4" :
1050 (pptable->PcieLaneCount[i] == 4) ? "x8" :
1051 (pptable->PcieLaneCount[i] == 5) ? "x12" :
1052 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1053 pptable->LclkFreq[i],
1054 (gen_speed == pptable->PcieGenSpeed[i]) &&
1055 (lane_width == pptable->PcieLaneCount[i]) ?
1060 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1061 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1062 size = sprintf(buf, "%s:\n", "OD_SCLK");
1063 size += sprintf(buf + size, "0: %10uMhz\n",
1064 od_table->GfxclkFmin);
1065 size += sprintf(buf + size, "1: %10uMhz\n",
1066 od_table->GfxclkFmax);
1072 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1073 size = sprintf(buf, "%s:\n", "OD_MCLK");
1074 size += sprintf(buf + size, "1: %10uMhz\n",
1075 od_table->UclkFmax);
1080 case SMU_OD_VDDC_CURVE:
1081 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1082 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1083 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1084 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1085 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1086 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1087 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1088 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1089 od_table->GfxclkFreq1,
1090 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1091 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1092 od_table->GfxclkFreq2,
1093 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1094 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1095 od_table->GfxclkFreq3,
1096 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1102 size = sprintf(buf, "%s:\n", "OD_RANGE");
1104 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1105 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1106 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1107 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1108 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1111 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1112 single_dpm_table = &(dpm_table->mem_table);
1113 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1115 pr_err("Attempt to get memory clk levels Failed!");
1119 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1120 clocks.data[0].clocks_in_khz / 1000,
1121 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1124 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1125 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1126 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1127 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1128 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1129 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1130 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1131 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1132 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1133 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1134 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1135 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1136 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1137 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1138 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1139 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1140 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1141 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1142 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1143 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1144 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1145 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1146 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1147 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1158 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1159 uint32_t feature_mask)
1161 struct vega20_dpm_table *dpm_table;
1162 struct vega20_single_dpm_table *single_dpm_table;
1166 dpm_table = smu->smu_dpm.dpm_context;
1168 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1169 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1170 single_dpm_table = &(dpm_table->gfx_table);
1171 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1172 single_dpm_table->dpm_state.soft_min_level;
1173 ret = smu_send_smc_msg_with_param(smu,
1174 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1175 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1177 pr_err("Failed to set soft %s gfxclk !\n",
1178 max ? "max" : "min");
1183 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1184 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1185 single_dpm_table = &(dpm_table->mem_table);
1186 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1187 single_dpm_table->dpm_state.soft_min_level;
1188 ret = smu_send_smc_msg_with_param(smu,
1189 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1190 (PPCLK_UCLK << 16) | (freq & 0xffff));
1192 pr_err("Failed to set soft %s memclk !\n",
1193 max ? "max" : "min");
1198 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1199 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1200 single_dpm_table = &(dpm_table->soc_table);
1201 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1202 single_dpm_table->dpm_state.soft_min_level;
1203 ret = smu_send_smc_msg_with_param(smu,
1204 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1205 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1207 pr_err("Failed to set soft %s socclk !\n",
1208 max ? "max" : "min");
1213 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1214 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1215 single_dpm_table = &(dpm_table->fclk_table);
1216 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1217 single_dpm_table->dpm_state.soft_min_level;
1218 ret = smu_send_smc_msg_with_param(smu,
1219 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1220 (PPCLK_FCLK << 16) | (freq & 0xffff));
1222 pr_err("Failed to set soft %s fclk !\n",
1223 max ? "max" : "min");
1228 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1229 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1230 single_dpm_table = &(dpm_table->dcef_table);
1231 freq = single_dpm_table->dpm_state.hard_min_level;
1233 ret = smu_send_smc_msg_with_param(smu,
1234 SMU_MSG_SetHardMinByFreq,
1235 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1237 pr_err("Failed to set hard min dcefclk !\n");
1246 static int vega20_force_clk_levels(struct smu_context *smu,
1247 enum smu_clk_type clk_type, uint32_t mask)
1249 struct vega20_dpm_table *dpm_table;
1250 struct vega20_single_dpm_table *single_dpm_table;
1251 uint32_t soft_min_level, soft_max_level, hard_min_level;
1252 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1255 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1256 pr_info("force clock level is for dpm manual mode only.\n");
1260 mutex_lock(&(smu->mutex));
1262 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1263 soft_max_level = mask ? (fls(mask) - 1) : 0;
1265 dpm_table = smu->smu_dpm.dpm_context;
1269 single_dpm_table = &(dpm_table->gfx_table);
1271 if (soft_max_level >= single_dpm_table->count) {
1272 pr_err("Clock level specified %d is over max allowed %d\n",
1273 soft_max_level, single_dpm_table->count - 1);
1278 single_dpm_table->dpm_state.soft_min_level =
1279 single_dpm_table->dpm_levels[soft_min_level].value;
1280 single_dpm_table->dpm_state.soft_max_level =
1281 single_dpm_table->dpm_levels[soft_max_level].value;
1283 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1285 pr_err("Failed to upload boot level to lowest!\n");
1289 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1291 pr_err("Failed to upload dpm max level to highest!\n");
1296 single_dpm_table = &(dpm_table->mem_table);
1298 if (soft_max_level >= single_dpm_table->count) {
1299 pr_err("Clock level specified %d is over max allowed %d\n",
1300 soft_max_level, single_dpm_table->count - 1);
1305 single_dpm_table->dpm_state.soft_min_level =
1306 single_dpm_table->dpm_levels[soft_min_level].value;
1307 single_dpm_table->dpm_state.soft_max_level =
1308 single_dpm_table->dpm_levels[soft_max_level].value;
1310 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1312 pr_err("Failed to upload boot level to lowest!\n");
1316 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1318 pr_err("Failed to upload dpm max level to highest!\n");
1323 single_dpm_table = &(dpm_table->soc_table);
1325 if (soft_max_level >= single_dpm_table->count) {
1326 pr_err("Clock level specified %d is over max allowed %d\n",
1327 soft_max_level, single_dpm_table->count - 1);
1332 single_dpm_table->dpm_state.soft_min_level =
1333 single_dpm_table->dpm_levels[soft_min_level].value;
1334 single_dpm_table->dpm_state.soft_max_level =
1335 single_dpm_table->dpm_levels[soft_max_level].value;
1337 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1339 pr_err("Failed to upload boot level to lowest!\n");
1343 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1345 pr_err("Failed to upload dpm max level to highest!\n");
1350 single_dpm_table = &(dpm_table->fclk_table);
1352 if (soft_max_level >= single_dpm_table->count) {
1353 pr_err("Clock level specified %d is over max allowed %d\n",
1354 soft_max_level, single_dpm_table->count - 1);
1359 single_dpm_table->dpm_state.soft_min_level =
1360 single_dpm_table->dpm_levels[soft_min_level].value;
1361 single_dpm_table->dpm_state.soft_max_level =
1362 single_dpm_table->dpm_levels[soft_max_level].value;
1364 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1366 pr_err("Failed to upload boot level to lowest!\n");
1370 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1372 pr_err("Failed to upload dpm max level to highest!\n");
1377 hard_min_level = soft_min_level;
1378 single_dpm_table = &(dpm_table->dcef_table);
1380 if (hard_min_level >= single_dpm_table->count) {
1381 pr_err("Clock level specified %d is over max allowed %d\n",
1382 hard_min_level, single_dpm_table->count - 1);
1387 single_dpm_table->dpm_state.hard_min_level =
1388 single_dpm_table->dpm_levels[hard_min_level].value;
1390 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1392 pr_err("Failed to upload boot level to lowest!\n");
1397 if (soft_min_level >= NUM_LINK_LEVELS ||
1398 soft_max_level >= NUM_LINK_LEVELS) {
1403 ret = smu_send_smc_msg_with_param(smu,
1404 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1406 pr_err("Failed to set min link dpm level!\n");
1414 mutex_unlock(&(smu->mutex));
1418 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1419 enum smu_clk_type clk_type,
1420 struct pp_clock_levels_with_latency *clocks)
1423 struct vega20_single_dpm_table *single_dpm_table;
1424 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1425 struct vega20_dpm_table *dpm_table = NULL;
1427 dpm_table = smu_dpm->dpm_context;
1429 mutex_lock(&smu->mutex);
1433 single_dpm_table = &(dpm_table->gfx_table);
1434 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1437 single_dpm_table = &(dpm_table->mem_table);
1438 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1441 single_dpm_table = &(dpm_table->dcef_table);
1442 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1445 single_dpm_table = &(dpm_table->soc_table);
1446 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1452 mutex_unlock(&smu->mutex);
1456 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1462 ret = smu_send_smc_msg_with_param(smu,
1463 SMU_MSG_GetAVFSVoltageByDpm,
1464 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1466 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1470 smu_read_smc_arg(smu, voltage);
1471 *voltage = *voltage / VOLTAGE_SCALE;
1476 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1478 struct smu_table_context *table_context = &smu->smu_table;
1479 OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1480 struct vega20_od8_settings *od8_settings = NULL;
1481 PPTable_t *smc_pptable = table_context->driver_pptable;
1484 if (table_context->od8_settings)
1487 table_context->od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1489 if (!table_context->od8_settings)
1492 od8_settings = (struct vega20_od8_settings *)table_context->od8_settings;
1494 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1495 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1496 table_context->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1497 table_context->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1498 (table_context->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1499 table_context->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1500 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1502 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1504 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1505 od_table->GfxclkFmin;
1506 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1507 od_table->GfxclkFmax;
1510 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1511 (table_context->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1512 smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1513 (table_context->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1514 smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1515 (table_context->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1516 table_context->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1517 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1519 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1521 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1523 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1525 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1527 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1530 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1531 od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1532 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1533 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1534 od_table->GfxclkFreq1;
1535 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1536 od_table->GfxclkFreq2;
1537 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1538 od_table->GfxclkFreq3;
1540 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1541 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1542 od_table->GfxclkFreq1);
1544 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1545 od_table->GfxclkVolt1 =
1546 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1548 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1549 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1550 od_table->GfxclkFreq2);
1552 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1553 od_table->GfxclkVolt2 =
1554 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1556 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1557 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1558 od_table->GfxclkFreq3);
1560 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1561 od_table->GfxclkVolt3 =
1562 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1567 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1568 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1569 table_context->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1570 table_context->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1571 (table_context->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1572 table_context->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1573 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1575 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1580 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1581 table_context->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1582 table_context->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1583 table_context->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1584 table_context->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1585 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1587 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1588 od_table->OverDrivePct;
1591 if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1592 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1593 table_context->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1594 table_context->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1595 (table_context->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1596 table_context->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1597 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1598 OD8_ACOUSTIC_LIMIT_SCLK;
1599 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1600 od_table->FanMaximumRpm;
1603 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1604 table_context->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1605 table_context->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1606 (table_context->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1607 table_context->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1608 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1610 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1611 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1615 if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1616 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1617 table_context->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1618 table_context->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1619 (table_context->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1620 table_context->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1621 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1622 OD8_TEMPERATURE_FAN;
1623 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1624 od_table->FanTargetTemperature;
1627 if (table_context->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1628 table_context->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1629 table_context->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1630 (table_context->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1631 table_context->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1632 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1633 OD8_TEMPERATURE_SYSTEM;
1634 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1635 od_table->MaxOpTemp;
1639 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1640 if (od8_settings->od8_settings_array[i].feature_id) {
1641 od8_settings->od8_settings_array[i].min_value =
1642 table_context->od_settings_min[i];
1643 od8_settings->od8_settings_array[i].max_value =
1644 table_context->od_settings_max[i];
1645 od8_settings->od8_settings_array[i].current_value =
1646 od8_settings->od8_settings_array[i].default_value;
1648 od8_settings->od8_settings_array[i].min_value = 0;
1649 od8_settings->od8_settings_array[i].max_value = 0;
1650 od8_settings->od8_settings_array[i].current_value = 0;
1657 static int vega20_get_od_percentage(struct smu_context *smu,
1658 enum pp_clock_type type)
1660 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1661 struct vega20_dpm_table *dpm_table = NULL;
1662 struct vega20_dpm_table *golden_table = NULL;
1663 struct vega20_single_dpm_table *single_dpm_table;
1664 struct vega20_single_dpm_table *golden_dpm_table;
1665 int value, golden_value;
1667 dpm_table = smu_dpm->dpm_context;
1668 golden_table = smu_dpm->golden_dpm_context;
1672 single_dpm_table = &(dpm_table->gfx_table);
1673 golden_dpm_table = &(golden_table->gfx_table);
1676 single_dpm_table = &(dpm_table->mem_table);
1677 golden_dpm_table = &(golden_table->mem_table);
1684 value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1685 golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1687 value -= golden_value;
1688 value = DIV_ROUND_UP(value * 100, golden_value);
1693 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1695 DpmActivityMonitorCoeffInt_t activity_monitor;
1696 uint32_t i, size = 0;
1697 uint16_t workload_type = 0;
1698 static const char *profile_name[] = {
1706 static const char *title[] = {
1707 "PROFILE_INDEX(NAME)",
1711 "MinActiveFreqType",
1716 "PD_Data_error_coeff",
1717 "PD_Data_error_rate_coeff"};
1720 if (!smu->pm_enabled || !buf)
1723 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1724 title[0], title[1], title[2], title[3], title[4], title[5],
1725 title[6], title[7], title[8], title[9], title[10]);
1727 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1728 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1729 workload_type = smu_workload_get_type(smu, i);
1730 result = smu_update_table(smu,
1731 TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
1732 (void *)(&activity_monitor), false);
1734 pr_err("[%s] Failed to get activity monitor!", __func__);
1738 size += sprintf(buf + size, "%2d %14s%s:\n",
1739 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1741 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1745 activity_monitor.Gfx_FPS,
1746 activity_monitor.Gfx_UseRlcBusy,
1747 activity_monitor.Gfx_MinActiveFreqType,
1748 activity_monitor.Gfx_MinActiveFreq,
1749 activity_monitor.Gfx_BoosterFreqType,
1750 activity_monitor.Gfx_BoosterFreq,
1751 activity_monitor.Gfx_PD_Data_limit_c,
1752 activity_monitor.Gfx_PD_Data_error_coeff,
1753 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1755 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1759 activity_monitor.Soc_FPS,
1760 activity_monitor.Soc_UseRlcBusy,
1761 activity_monitor.Soc_MinActiveFreqType,
1762 activity_monitor.Soc_MinActiveFreq,
1763 activity_monitor.Soc_BoosterFreqType,
1764 activity_monitor.Soc_BoosterFreq,
1765 activity_monitor.Soc_PD_Data_limit_c,
1766 activity_monitor.Soc_PD_Data_error_coeff,
1767 activity_monitor.Soc_PD_Data_error_rate_coeff);
1769 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1773 activity_monitor.Mem_FPS,
1774 activity_monitor.Mem_UseRlcBusy,
1775 activity_monitor.Mem_MinActiveFreqType,
1776 activity_monitor.Mem_MinActiveFreq,
1777 activity_monitor.Mem_BoosterFreqType,
1778 activity_monitor.Mem_BoosterFreq,
1779 activity_monitor.Mem_PD_Data_limit_c,
1780 activity_monitor.Mem_PD_Data_error_coeff,
1781 activity_monitor.Mem_PD_Data_error_rate_coeff);
1783 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1787 activity_monitor.Fclk_FPS,
1788 activity_monitor.Fclk_UseRlcBusy,
1789 activity_monitor.Fclk_MinActiveFreqType,
1790 activity_monitor.Fclk_MinActiveFreq,
1791 activity_monitor.Fclk_BoosterFreqType,
1792 activity_monitor.Fclk_BoosterFreq,
1793 activity_monitor.Fclk_PD_Data_limit_c,
1794 activity_monitor.Fclk_PD_Data_error_coeff,
1795 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1801 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1803 DpmActivityMonitorCoeffInt_t activity_monitor;
1804 int workload_type = 0, ret = 0;
1806 smu->power_profile_mode = input[size];
1808 if (!smu->pm_enabled)
1810 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1811 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1815 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1816 ret = smu_update_table(smu,
1817 TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
1818 (void *)(&activity_monitor), false);
1820 pr_err("[%s] Failed to get activity monitor!", __func__);
1825 case 0: /* Gfxclk */
1826 activity_monitor.Gfx_FPS = input[1];
1827 activity_monitor.Gfx_UseRlcBusy = input[2];
1828 activity_monitor.Gfx_MinActiveFreqType = input[3];
1829 activity_monitor.Gfx_MinActiveFreq = input[4];
1830 activity_monitor.Gfx_BoosterFreqType = input[5];
1831 activity_monitor.Gfx_BoosterFreq = input[6];
1832 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1833 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1834 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1836 case 1: /* Socclk */
1837 activity_monitor.Soc_FPS = input[1];
1838 activity_monitor.Soc_UseRlcBusy = input[2];
1839 activity_monitor.Soc_MinActiveFreqType = input[3];
1840 activity_monitor.Soc_MinActiveFreq = input[4];
1841 activity_monitor.Soc_BoosterFreqType = input[5];
1842 activity_monitor.Soc_BoosterFreq = input[6];
1843 activity_monitor.Soc_PD_Data_limit_c = input[7];
1844 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1845 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1848 activity_monitor.Mem_FPS = input[1];
1849 activity_monitor.Mem_UseRlcBusy = input[2];
1850 activity_monitor.Mem_MinActiveFreqType = input[3];
1851 activity_monitor.Mem_MinActiveFreq = input[4];
1852 activity_monitor.Mem_BoosterFreqType = input[5];
1853 activity_monitor.Mem_BoosterFreq = input[6];
1854 activity_monitor.Mem_PD_Data_limit_c = input[7];
1855 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1856 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1859 activity_monitor.Fclk_FPS = input[1];
1860 activity_monitor.Fclk_UseRlcBusy = input[2];
1861 activity_monitor.Fclk_MinActiveFreqType = input[3];
1862 activity_monitor.Fclk_MinActiveFreq = input[4];
1863 activity_monitor.Fclk_BoosterFreqType = input[5];
1864 activity_monitor.Fclk_BoosterFreq = input[6];
1865 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1866 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1867 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1871 ret = smu_update_table(smu,
1872 TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
1873 (void *)(&activity_monitor), true);
1875 pr_err("[%s] Failed to set activity monitor!", __func__);
1880 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1881 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1882 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1883 1 << workload_type);
1889 vega20_get_profiling_clk_mask(struct smu_context *smu,
1890 enum amd_dpm_forced_level level,
1891 uint32_t *sclk_mask,
1892 uint32_t *mclk_mask,
1895 struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1896 struct vega20_single_dpm_table *gfx_dpm_table;
1897 struct vega20_single_dpm_table *mem_dpm_table;
1898 struct vega20_single_dpm_table *soc_dpm_table;
1900 if (!smu->smu_dpm.dpm_context)
1903 gfx_dpm_table = &dpm_table->gfx_table;
1904 mem_dpm_table = &dpm_table->mem_table;
1905 soc_dpm_table = &dpm_table->soc_table;
1911 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1912 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
1913 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
1914 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
1915 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
1916 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
1919 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1921 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1923 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1924 *sclk_mask = gfx_dpm_table->count - 1;
1925 *mclk_mask = mem_dpm_table->count - 1;
1926 *soc_mask = soc_dpm_table->count - 1;
1933 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
1934 struct vega20_single_dpm_table *dpm_table)
1937 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1938 if (!smu_dpm_ctx->dpm_context)
1941 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1942 if (dpm_table->count <= 0) {
1943 pr_err("[%s] Dpm table has no entry!", __func__);
1947 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
1948 pr_err("[%s] Dpm table has too many entries!", __func__);
1952 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
1953 ret = smu_send_smc_msg_with_param(smu,
1954 SMU_MSG_SetHardMinByFreq,
1955 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
1957 pr_err("[%s] Set hard min uclk failed!", __func__);
1965 static int vega20_pre_display_config_changed(struct smu_context *smu)
1968 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
1970 if (!smu->smu_dpm.dpm_context)
1973 smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
1974 ret = vega20_set_uclk_to_highest_dpm_level(smu,
1975 &dpm_table->mem_table);
1977 pr_err("Failed to set uclk to highest dpm level");
1981 static int vega20_display_config_changed(struct smu_context *smu)
1985 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1986 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1987 ret = smu_write_watermarks_table(smu);
1989 pr_err("Failed to update WMTABLE!");
1992 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1995 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1996 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1997 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1998 smu_send_smc_msg_with_param(smu,
1999 SMU_MSG_NumOfDisplays,
2000 smu->display_config->num_display);
2006 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2008 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2009 struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2010 struct vega20_single_dpm_table *dpm_table;
2011 bool vblank_too_short = false;
2012 bool disable_mclk_switching;
2013 uint32_t i, latency;
2015 disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2016 !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2017 latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2020 dpm_table = &(dpm_ctx->gfx_table);
2021 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2022 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2023 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2024 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2026 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2027 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2028 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2031 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2032 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2033 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2036 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2037 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2038 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2042 dpm_table = &(dpm_ctx->mem_table);
2043 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2044 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2045 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2046 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2048 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2049 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2050 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2053 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2054 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2055 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2058 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2059 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2060 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2063 /* honour DAL's UCLK Hardmin */
2064 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2065 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2067 /* Hardmin is dependent on displayconfig */
2068 if (disable_mclk_switching) {
2069 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2070 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2071 if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2072 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2073 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2080 if (smu->display_config->nb_pstate_switch_disable)
2081 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2084 dpm_table = &(dpm_ctx->vclk_table);
2085 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2086 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2087 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2088 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2090 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2091 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2092 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2095 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2096 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2097 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2101 dpm_table = &(dpm_ctx->dclk_table);
2102 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2103 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2104 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2105 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2107 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2108 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2109 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2112 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2113 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2114 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2118 dpm_table = &(dpm_ctx->soc_table);
2119 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2120 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2121 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2122 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2124 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2125 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2126 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2129 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2130 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2131 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2135 dpm_table = &(dpm_ctx->eclk_table);
2136 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2137 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2138 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2139 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2141 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2142 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2143 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2146 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2147 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2148 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2154 vega20_notify_smc_dispaly_config(struct smu_context *smu)
2156 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2157 struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2158 struct smu_clocks min_clocks = {0};
2159 struct pp_display_clock_request clock_req;
2162 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2163 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2164 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2166 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2167 clock_req.clock_type = amd_pp_dcef_clock;
2168 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2169 if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
2170 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2171 ret = smu_send_smc_msg_with_param(smu,
2172 SMU_MSG_SetMinDeepSleepDcefclk,
2173 min_clocks.dcef_clock_in_sr/100);
2175 pr_err("Attempt to set divider for DCEFCLK Failed!");
2180 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2184 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2185 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2186 ret = smu_send_smc_msg_with_param(smu,
2187 SMU_MSG_SetHardMinByFreq,
2188 (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2190 pr_err("[%s] Set hard min uclk failed!", __func__);
2198 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2202 for (i = 0; i < table->count; i++) {
2203 if (table->dpm_levels[i].enabled)
2206 if (i >= table->count) {
2208 table->dpm_levels[i].enabled = true;
2214 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2219 pr_err("[%s] DPM Table does not exist!", __func__);
2222 if (table->count <= 0) {
2223 pr_err("[%s] DPM Table has no entry!", __func__);
2226 if (table->count > MAX_REGULAR_DPM_NUMBER) {
2227 pr_err("[%s] DPM Table has too many entries!", __func__);
2228 return MAX_REGULAR_DPM_NUMBER - 1;
2231 for (i = table->count - 1; i >= 0; i--) {
2232 if (table->dpm_levels[i].enabled)
2237 table->dpm_levels[i].enabled = true;
2243 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2245 uint32_t soft_level;
2247 struct vega20_dpm_table *dpm_table =
2248 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2251 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2253 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2255 dpm_table->gfx_table.dpm_state.soft_min_level =
2256 dpm_table->gfx_table.dpm_state.soft_max_level =
2257 dpm_table->gfx_table.dpm_levels[soft_level].value;
2260 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2262 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2264 dpm_table->mem_table.dpm_state.soft_min_level =
2265 dpm_table->mem_table.dpm_state.soft_max_level =
2266 dpm_table->mem_table.dpm_levels[soft_level].value;
2269 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2271 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2273 dpm_table->soc_table.dpm_state.soft_min_level =
2274 dpm_table->soc_table.dpm_state.soft_max_level =
2275 dpm_table->soc_table.dpm_levels[soft_level].value;
2277 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2279 pr_err("Failed to upload boot level to %s!\n",
2280 highest ? "highest" : "lowest");
2284 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2286 pr_err("Failed to upload dpm max level to %s!\n!",
2287 highest ? "highest" : "lowest");
2294 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2296 uint32_t soft_min_level, soft_max_level;
2298 struct vega20_dpm_table *dpm_table =
2299 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2301 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2302 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2303 dpm_table->gfx_table.dpm_state.soft_min_level =
2304 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2305 dpm_table->gfx_table.dpm_state.soft_max_level =
2306 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2308 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2309 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2310 dpm_table->mem_table.dpm_state.soft_min_level =
2311 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2312 dpm_table->mem_table.dpm_state.soft_max_level =
2313 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2315 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2316 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2317 dpm_table->soc_table.dpm_state.soft_min_level =
2318 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2319 dpm_table->soc_table.dpm_state.soft_max_level =
2320 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2322 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2324 pr_err("Failed to upload DPM Bootup Levels!");
2328 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2330 pr_err("Failed to upload DPM Max Levels!");
2337 static enum amd_dpm_forced_level vega20_get_performance_level(struct smu_context *smu)
2339 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2340 if (!smu_dpm_ctx->dpm_context)
2343 if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
2344 mutex_lock(&(smu->mutex));
2345 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
2346 mutex_unlock(&(smu->mutex));
2348 return smu_dpm_ctx->dpm_level;
2352 vega20_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
2356 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2358 if (!smu_dpm_ctx->dpm_context)
2361 for (i = 0; i < smu->adev->num_ip_blocks; i++) {
2362 if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
2366 mutex_lock(&smu->mutex);
2368 smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
2369 ret = smu_handle_task(smu, level,
2370 AMD_PP_TASK_READJUST_POWER_STATE);
2372 mutex_unlock(&smu->mutex);
2377 static int vega20_update_specified_od8_value(struct smu_context *smu,
2381 struct smu_table_context *table_context = &smu->smu_table;
2382 OverDriveTable_t *od_table =
2383 (OverDriveTable_t *)(table_context->overdrive_table);
2384 struct vega20_od8_settings *od8_settings =
2385 (struct vega20_od8_settings *)table_context->od8_settings;
2388 case OD8_SETTING_GFXCLK_FMIN:
2389 od_table->GfxclkFmin = (uint16_t)value;
2392 case OD8_SETTING_GFXCLK_FMAX:
2393 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2394 value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2396 od_table->GfxclkFmax = (uint16_t)value;
2399 case OD8_SETTING_GFXCLK_FREQ1:
2400 od_table->GfxclkFreq1 = (uint16_t)value;
2403 case OD8_SETTING_GFXCLK_VOLTAGE1:
2404 od_table->GfxclkVolt1 = (uint16_t)value;
2407 case OD8_SETTING_GFXCLK_FREQ2:
2408 od_table->GfxclkFreq2 = (uint16_t)value;
2411 case OD8_SETTING_GFXCLK_VOLTAGE2:
2412 od_table->GfxclkVolt2 = (uint16_t)value;
2415 case OD8_SETTING_GFXCLK_FREQ3:
2416 od_table->GfxclkFreq3 = (uint16_t)value;
2419 case OD8_SETTING_GFXCLK_VOLTAGE3:
2420 od_table->GfxclkVolt3 = (uint16_t)value;
2423 case OD8_SETTING_UCLK_FMAX:
2424 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2425 value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2427 od_table->UclkFmax = (uint16_t)value;
2430 case OD8_SETTING_POWER_PERCENTAGE:
2431 od_table->OverDrivePct = (int16_t)value;
2434 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2435 od_table->FanMaximumRpm = (uint16_t)value;
2438 case OD8_SETTING_FAN_MIN_SPEED:
2439 od_table->FanMinimumPwm = (uint16_t)value;
2442 case OD8_SETTING_FAN_TARGET_TEMP:
2443 od_table->FanTargetTemperature = (uint16_t)value;
2446 case OD8_SETTING_OPERATING_TEMP_MAX:
2447 od_table->MaxOpTemp = (uint16_t)value;
2454 static int vega20_set_od_percentage(struct smu_context *smu,
2455 enum pp_clock_type type,
2458 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2459 struct vega20_dpm_table *dpm_table = NULL;
2460 struct vega20_dpm_table *golden_table = NULL;
2461 struct vega20_single_dpm_table *single_dpm_table;
2462 struct vega20_single_dpm_table *golden_dpm_table;
2463 uint32_t od_clk, index;
2465 int feature_enabled;
2468 mutex_lock(&(smu->mutex));
2470 dpm_table = smu_dpm->dpm_context;
2471 golden_table = smu_dpm->golden_dpm_context;
2475 single_dpm_table = &(dpm_table->gfx_table);
2476 golden_dpm_table = &(golden_table->gfx_table);
2477 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2478 clk_id = PPCLK_GFXCLK;
2479 index = OD8_SETTING_GFXCLK_FMAX;
2482 single_dpm_table = &(dpm_table->mem_table);
2483 golden_dpm_table = &(golden_table->mem_table);
2484 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2485 clk_id = PPCLK_UCLK;
2486 index = OD8_SETTING_UCLK_FMAX;
2496 od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2498 od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2500 ret = smu_update_od8_settings(smu, index, od_clk);
2502 pr_err("[Setoverdrive] failed to set od clk!\n");
2506 if (feature_enabled) {
2507 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2510 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2514 single_dpm_table->count = 1;
2515 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2518 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2519 AMD_PP_TASK_READJUST_POWER_STATE);
2522 mutex_unlock(&(smu->mutex));
2527 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2528 enum PP_OD_DPM_TABLE_COMMAND type,
2529 long *input, uint32_t size)
2531 struct smu_table_context *table_context = &smu->smu_table;
2532 OverDriveTable_t *od_table =
2533 (OverDriveTable_t *)(table_context->overdrive_table);
2534 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2535 struct vega20_dpm_table *dpm_table = NULL;
2536 struct vega20_single_dpm_table *single_dpm_table;
2537 struct vega20_od8_settings *od8_settings =
2538 (struct vega20_od8_settings *)table_context->od8_settings;
2539 struct pp_clock_levels_with_latency clocks;
2540 int32_t input_index, input_clk, input_vol, i;
2544 dpm_table = smu_dpm->dpm_context;
2547 pr_warn("NULL user input for clock and voltage\n");
2552 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2553 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2554 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2555 pr_info("Sclk min/max frequency overdrive not supported\n");
2559 for (i = 0; i < size; i += 2) {
2561 pr_info("invalid number of input parameters %d\n", size);
2565 input_index = input[i];
2566 input_clk = input[i + 1];
2568 if (input_index != 0 && input_index != 1) {
2569 pr_info("Invalid index %d\n", input_index);
2570 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2574 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2575 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2576 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2578 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2579 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2583 if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2584 od_table->GfxclkFmin = input_clk;
2585 table_context->od_gfxclk_update = true;
2586 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2587 od_table->GfxclkFmax = input_clk;
2588 table_context->od_gfxclk_update = true;
2594 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2595 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2596 pr_info("Mclk max frequency overdrive not supported\n");
2600 single_dpm_table = &(dpm_table->mem_table);
2601 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2603 pr_err("Attempt to get memory clk levels Failed!");
2607 for (i = 0; i < size; i += 2) {
2609 pr_info("invalid number of input parameters %d\n",
2614 input_index = input[i];
2615 input_clk = input[i + 1];
2617 if (input_index != 1) {
2618 pr_info("Invalid index %d\n", input_index);
2619 pr_info("Support max Mclk frequency setting only which index by 1\n");
2623 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2624 input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2625 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2627 clocks.data[0].clocks_in_khz / 1000,
2628 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2632 if (input_index == 1 && od_table->UclkFmax != input_clk) {
2633 table_context->od_gfxclk_update = true;
2634 od_table->UclkFmax = input_clk;
2640 case PP_OD_EDIT_VDDC_CURVE:
2641 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2642 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2643 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2644 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2645 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2646 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2647 pr_info("Voltage curve calibrate not supported\n");
2651 for (i = 0; i < size; i += 3) {
2653 pr_info("invalid number of input parameters %d\n",
2658 input_index = input[i];
2659 input_clk = input[i + 1];
2660 input_vol = input[i + 2];
2662 if (input_index > 2) {
2663 pr_info("Setting for point %d is not supported\n",
2665 pr_info("Three supported points index by 0, 1, 2\n");
2669 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2670 if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2671 input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2672 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2674 od8_settings->od8_settings_array[od8_id].min_value,
2675 od8_settings->od8_settings_array[od8_id].max_value);
2679 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2680 if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2681 input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2682 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2684 od8_settings->od8_settings_array[od8_id].min_value,
2685 od8_settings->od8_settings_array[od8_id].max_value);
2689 switch (input_index) {
2691 od_table->GfxclkFreq1 = input_clk;
2692 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2695 od_table->GfxclkFreq2 = input_clk;
2696 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2699 od_table->GfxclkFreq3 = input_clk;
2700 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2707 case PP_OD_RESTORE_DEFAULT_TABLE:
2708 ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, false);
2710 pr_err("Failed to export over drive table!\n");
2716 case PP_OD_COMMIT_DPM_TABLE:
2717 ret = smu_update_table(smu, TABLE_OVERDRIVE, table_context->overdrive_table, true);
2719 pr_err("Failed to import over drive table!\n");
2723 /* retrieve updated gfxclk table */
2724 if (table_context->od_gfxclk_update) {
2725 table_context->od_gfxclk_update = false;
2726 single_dpm_table = &(dpm_table->gfx_table);
2728 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2729 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2732 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2736 single_dpm_table->count = 1;
2737 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2747 if (type == PP_OD_COMMIT_DPM_TABLE) {
2748 mutex_lock(&(smu->mutex));
2749 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2750 AMD_PP_TASK_READJUST_POWER_STATE);
2751 mutex_unlock(&(smu->mutex));
2757 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2759 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2762 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2765 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2768 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2770 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2773 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2776 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2779 static int vega20_get_enabled_smc_features(struct smu_context *smu,
2780 uint64_t *features_enabled)
2782 uint32_t feature_mask[2] = {0, 0};
2785 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2789 *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
2790 (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
2795 static int vega20_enable_smc_features(struct smu_context *smu,
2796 bool enable, uint64_t feature_mask)
2798 uint32_t smu_features_low, smu_features_high;
2801 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
2802 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
2805 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
2809 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
2814 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
2818 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
2828 static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
2830 static const char *ppfeature_name[] = {
2865 static const char *output_title[] = {
2869 uint64_t features_enabled;
2874 ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2878 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2879 size += sprintf(buf + size, "%-19s %-22s %s\n",
2883 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2884 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
2887 (features_enabled & (1ULL << i)) ? "Y" : "N");
2893 static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
2895 uint64_t features_enabled;
2896 uint64_t features_to_enable;
2897 uint64_t features_to_disable;
2900 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2903 ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2907 features_to_disable =
2908 features_enabled & ~new_ppfeature_masks;
2909 features_to_enable =
2910 ~features_enabled & new_ppfeature_masks;
2912 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2913 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2915 if (features_to_disable) {
2916 ret = vega20_enable_smc_features(smu, false, features_to_disable);
2921 if (features_to_enable) {
2922 ret = vega20_enable_smc_features(smu, true, features_to_enable);
2930 static bool vega20_is_dpm_running(struct smu_context *smu)
2933 uint32_t feature_mask[2];
2934 unsigned long feature_enabled;
2935 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2936 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
2937 ((uint64_t)feature_mask[1] << 32));
2938 return !!(feature_enabled & SMC_DPM_FEATURE);
2941 static int vega20_set_thermal_fan_table(struct smu_context *smu)
2944 struct smu_table_context *table_context = &smu->smu_table;
2945 PPTable_t *pptable = table_context->driver_pptable;
2947 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
2948 (uint32_t)pptable->FanTargetTemperature);
2953 static int vega20_get_fan_speed_percent(struct smu_context *smu,
2957 uint32_t percent = 0;
2958 uint32_t current_rpm;
2959 PPTable_t *pptable = smu->smu_table.driver_pptable;
2961 ret = smu_get_current_rpm(smu, ¤t_rpm);
2962 percent = current_rpm * 100 / pptable->FanMaximumRpm;
2963 *speed = percent > 100 ? 100 : percent;
2968 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
2971 SmuMetrics_t metrics;
2976 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics,
2981 *value = metrics.CurrSocketPower << 8;
2986 static int vega20_get_current_activity_percent(struct smu_context *smu,
2987 enum amd_pp_sensors sensor,
2991 SmuMetrics_t metrics;
2996 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
2997 (void *)&metrics, false);
3002 case AMDGPU_PP_SENSOR_GPU_LOAD:
3003 *value = metrics.AverageGfxActivity;
3005 case AMDGPU_PP_SENSOR_MEM_LOAD:
3006 *value = metrics.AverageUclkActivity;
3009 pr_err("Invalid sensor for retrieving clock activity\n");
3016 static int vega20_read_sensor(struct smu_context *smu,
3017 enum amd_pp_sensors sensor,
3018 void *data, uint32_t *size)
3021 struct smu_table_context *table_context = &smu->smu_table;
3022 PPTable_t *pptable = table_context->driver_pptable;
3025 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3026 *(uint32_t *)data = pptable->FanMaximumRpm;
3029 case AMDGPU_PP_SENSOR_MEM_LOAD:
3030 case AMDGPU_PP_SENSOR_GPU_LOAD:
3031 ret = vega20_get_current_activity_percent(smu,
3036 case AMDGPU_PP_SENSOR_GPU_POWER:
3037 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3047 static int vega20_set_watermarks_table(struct smu_context *smu,
3048 void *watermarks, struct
3049 dm_pp_wm_sets_with_clock_ranges_soc15
3053 Watermarks_t *table = watermarks;
3055 if (!table || !clock_ranges)
3058 if (clock_ranges->num_wm_dmif_sets > 4 ||
3059 clock_ranges->num_wm_mcif_sets > 4)
3062 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3063 table->WatermarkRow[1][i].MinClock =
3064 cpu_to_le16((uint16_t)
3065 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3067 table->WatermarkRow[1][i].MaxClock =
3068 cpu_to_le16((uint16_t)
3069 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3071 table->WatermarkRow[1][i].MinUclk =
3072 cpu_to_le16((uint16_t)
3073 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3075 table->WatermarkRow[1][i].MaxUclk =
3076 cpu_to_le16((uint16_t)
3077 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3079 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3080 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3083 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3084 table->WatermarkRow[0][i].MinClock =
3085 cpu_to_le16((uint16_t)
3086 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3088 table->WatermarkRow[0][i].MaxClock =
3089 cpu_to_le16((uint16_t)
3090 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3092 table->WatermarkRow[0][i].MinUclk =
3093 cpu_to_le16((uint16_t)
3094 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3096 table->WatermarkRow[0][i].MaxUclk =
3097 cpu_to_le16((uint16_t)
3098 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3100 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3101 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3107 static const struct pptable_funcs vega20_ppt_funcs = {
3108 .tables_init = vega20_tables_init,
3109 .alloc_dpm_context = vega20_allocate_dpm_context,
3110 .store_powerplay_table = vega20_store_powerplay_table,
3111 .check_powerplay_table = vega20_check_powerplay_table,
3112 .append_powerplay_table = vega20_append_powerplay_table,
3113 .get_smu_msg_index = vega20_get_smu_msg_index,
3114 .get_smu_clk_index = vega20_get_smu_clk_index,
3115 .get_smu_feature_index = vega20_get_smu_feature_index,
3116 .get_smu_table_index = vega20_get_smu_table_index,
3117 .get_smu_power_index = vega20_get_pwr_src_index,
3118 .get_workload_type = vega20_get_workload_type,
3119 .run_afll_btc = vega20_run_btc_afll,
3120 .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3121 .get_current_power_state = vega20_get_current_power_state,
3122 .set_default_dpm_table = vega20_set_default_dpm_table,
3123 .set_power_state = NULL,
3124 .populate_umd_state_clk = vega20_populate_umd_state_clk,
3125 .print_clk_levels = vega20_print_clk_levels,
3126 .force_clk_levels = vega20_force_clk_levels,
3127 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3128 .set_default_od8_settings = vega20_set_default_od8_setttings,
3129 .get_od_percentage = vega20_get_od_percentage,
3130 .get_power_profile_mode = vega20_get_power_profile_mode,
3131 .set_power_profile_mode = vega20_set_power_profile_mode,
3132 .get_performance_level = vega20_get_performance_level,
3133 .force_performance_level = vega20_force_performance_level,
3134 .update_specified_od8_value = vega20_update_specified_od8_value,
3135 .set_od_percentage = vega20_set_od_percentage,
3136 .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3137 .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3138 .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3139 .read_sensor = vega20_read_sensor,
3140 .pre_display_config_changed = vega20_pre_display_config_changed,
3141 .display_config_changed = vega20_display_config_changed,
3142 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3143 .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
3144 .force_dpm_limit_value = vega20_force_dpm_limit_value,
3145 .unforce_dpm_levels = vega20_unforce_dpm_levels,
3146 .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3147 .set_ppfeature_status = vega20_set_ppfeature_status,
3148 .get_ppfeature_status = vega20_get_ppfeature_status,
3149 .is_dpm_running = vega20_is_dpm_running,
3150 .set_thermal_fan_table = vega20_set_thermal_fan_table,
3151 .get_fan_speed_percent = vega20_get_fan_speed_percent,
3152 .set_watermarks_table = vega20_set_watermarks_table,
3155 void vega20_set_ppt_funcs(struct smu_context *smu)
3157 struct smu_table_context *smu_table = &smu->smu_table;
3159 smu->ppt_funcs = &vega20_ppt_funcs;
3160 smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
3161 smu_table->table_count = TABLE_COUNT;