drivers/gpu/drm/amd/powerplay/vega20_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "smu_v11_0.h"
  32 #include "smu11_driver_if.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "power_state.h"
  36 #include "vega20_ppt.h"
  37 #include "vega20_pptable.h"
  38 #include "vega20_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40 #include "asic_reg/thm/thm_11_0_2_offset.h"
  41 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  42
  43 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  44 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  45
  46 #define CTF_OFFSET_EDGE                 5
  47 #define CTF_OFFSET_HOTSPOT              5
  48 #define CTF_OFFSET_HBM                  5
  49
  50 #define MSG_MAP(msg) \
  51         [SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
  52
  53 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
  54                          FEATURE_DPM_GFXCLK_MASK | \
  55                          FEATURE_DPM_UCLK_MASK | \
  56                          FEATURE_DPM_SOCCLK_MASK | \
  57                          FEATURE_DPM_UVD_MASK | \
  58                          FEATURE_DPM_VCE_MASK | \
  59                          FEATURE_DPM_MP0CLK_MASK | \
  60                          FEATURE_DPM_LINK_MASK | \
  61                          FEATURE_DPM_DCEFCLK_MASK)
  62
  63 static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
  64         MSG_MAP(TestMessage),
  65         MSG_MAP(GetSmuVersion),
  66         MSG_MAP(GetDriverIfVersion),
  67         MSG_MAP(SetAllowedFeaturesMaskLow),
  68         MSG_MAP(SetAllowedFeaturesMaskHigh),
  69         MSG_MAP(EnableAllSmuFeatures),
  70         MSG_MAP(DisableAllSmuFeatures),
  71         MSG_MAP(EnableSmuFeaturesLow),
  72         MSG_MAP(EnableSmuFeaturesHigh),
  73         MSG_MAP(DisableSmuFeaturesLow),
  74         MSG_MAP(DisableSmuFeaturesHigh),
  75         MSG_MAP(GetEnabledSmuFeaturesLow),
  76         MSG_MAP(GetEnabledSmuFeaturesHigh),
  77         MSG_MAP(SetWorkloadMask),
  78         MSG_MAP(SetPptLimit),
  79         MSG_MAP(SetDriverDramAddrHigh),
  80         MSG_MAP(SetDriverDramAddrLow),
  81         MSG_MAP(SetToolsDramAddrHigh),
  82         MSG_MAP(SetToolsDramAddrLow),
  83         MSG_MAP(TransferTableSmu2Dram),
  84         MSG_MAP(TransferTableDram2Smu),
  85         MSG_MAP(UseDefaultPPTable),
  86         MSG_MAP(UseBackupPPTable),
  87         MSG_MAP(RunBtc),
  88         MSG_MAP(RequestI2CBus),
  89         MSG_MAP(ReleaseI2CBus),
  90         MSG_MAP(SetFloorSocVoltage),
  91         MSG_MAP(SoftReset),
  92         MSG_MAP(StartBacoMonitor),
  93         MSG_MAP(CancelBacoMonitor),
  94         MSG_MAP(EnterBaco),
  95         MSG_MAP(SetSoftMinByFreq),
  96         MSG_MAP(SetSoftMaxByFreq),
  97         MSG_MAP(SetHardMinByFreq),
  98         MSG_MAP(SetHardMaxByFreq),
  99         MSG_MAP(GetMinDpmFreq),
 100         MSG_MAP(GetMaxDpmFreq),
 101         MSG_MAP(GetDpmFreqByIndex),
 102         MSG_MAP(GetDpmClockFreq),
 103         MSG_MAP(GetSsVoltageByDpm),
 104         MSG_MAP(SetMemoryChannelConfig),
 105         MSG_MAP(SetGeminiMode),
 106         MSG_MAP(SetGeminiApertureHigh),
 107         MSG_MAP(SetGeminiApertureLow),
 108         MSG_MAP(SetMinLinkDpmByIndex),
 109         MSG_MAP(OverridePcieParameters),
 110         MSG_MAP(OverDriveSetPercentage),
 111         MSG_MAP(SetMinDeepSleepDcefclk),
 112         MSG_MAP(ReenableAcDcInterrupt),
 113         MSG_MAP(NotifyPowerSource),
 114         MSG_MAP(SetUclkFastSwitch),
 115         MSG_MAP(SetUclkDownHyst),
 116         MSG_MAP(GetCurrentRpm),
 117         MSG_MAP(SetVideoFps),
 118         MSG_MAP(SetTjMax),
 119         MSG_MAP(SetFanTemperatureTarget),
 120         MSG_MAP(PrepareMp1ForUnload),
 121         MSG_MAP(DramLogSetDramAddrHigh),
 122         MSG_MAP(DramLogSetDramAddrLow),
 123         MSG_MAP(DramLogSetDramSize),
 124         MSG_MAP(SetFanMaxRpm),
 125         MSG_MAP(SetFanMinPwm),
 126         MSG_MAP(ConfigureGfxDidt),
 127         MSG_MAP(NumOfDisplays),
 128         MSG_MAP(RemoveMargins),
 129         MSG_MAP(ReadSerialNumTop32),
 130         MSG_MAP(ReadSerialNumBottom32),
 131         MSG_MAP(SetSystemVirtualDramAddrHigh),
 132         MSG_MAP(SetSystemVirtualDramAddrLow),
 133         MSG_MAP(WaflTest),
 134         MSG_MAP(SetFclkGfxClkRatio),
 135         MSG_MAP(AllowGfxOff),
 136         MSG_MAP(DisallowGfxOff),
 137         MSG_MAP(GetPptLimit),
 138         MSG_MAP(GetDcModeMaxDpmFreq),
 139         MSG_MAP(GetDebugData),
 140         MSG_MAP(SetXgmiMode),
 141         MSG_MAP(RunAfllBtc),
 142         MSG_MAP(ExitBaco),
 143         MSG_MAP(PrepareMp1ForReset),
 144         MSG_MAP(PrepareMp1ForShutdown),
 145         MSG_MAP(SetMGpuFanBoostLimitRpm),
 146         MSG_MAP(GetAVFSVoltageByDpm),
 147         MSG_MAP(DFCstateControl),
 148 };
 149
 150 static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
 151         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 152         CLK_MAP(VCLK, PPCLK_VCLK),
 153         CLK_MAP(DCLK, PPCLK_DCLK),
 154         CLK_MAP(ECLK, PPCLK_ECLK),
 155         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 156         CLK_MAP(UCLK, PPCLK_UCLK),
 157         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 158         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 159         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 160         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 161         CLK_MAP(FCLK, PPCLK_FCLK),
 162 };
 163
 164 static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
 165         FEA_MAP(DPM_PREFETCHER),
 166         FEA_MAP(DPM_GFXCLK),
 167         FEA_MAP(DPM_UCLK),
 168         FEA_MAP(DPM_SOCCLK),
 169         FEA_MAP(DPM_UVD),
 170         FEA_MAP(DPM_VCE),
 171         FEA_MAP(ULV),
 172         FEA_MAP(DPM_MP0CLK),
 173         FEA_MAP(DPM_LINK),
 174         FEA_MAP(DPM_DCEFCLK),
 175         FEA_MAP(DS_GFXCLK),
 176         FEA_MAP(DS_SOCCLK),
 177         FEA_MAP(DS_LCLK),
 178         FEA_MAP(PPT),
 179         FEA_MAP(TDC),
 180         FEA_MAP(THERMAL),
 181         FEA_MAP(GFX_PER_CU_CG),
 182         FEA_MAP(RM),
 183         FEA_MAP(DS_DCEFCLK),
 184         FEA_MAP(ACDC),
 185         FEA_MAP(VR0HOT),
 186         FEA_MAP(VR1HOT),
 187         FEA_MAP(FW_CTF),
 188         FEA_MAP(LED_DISPLAY),
 189         FEA_MAP(FAN_CONTROL),
 190         FEA_MAP(GFX_EDC),
 191         FEA_MAP(GFXOFF),
 192         FEA_MAP(CG),
 193         FEA_MAP(DPM_FCLK),
 194         FEA_MAP(DS_FCLK),
 195         FEA_MAP(DS_MP1CLK),
 196         FEA_MAP(DS_MP0CLK),
 197         FEA_MAP(XGMI),
 198 };
 199
 200 static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
 201         TAB_MAP(PPTABLE),
 202         TAB_MAP(WATERMARKS),
 203         TAB_MAP(AVFS),
 204         TAB_MAP(AVFS_PSM_DEBUG),
 205         TAB_MAP(AVFS_FUSE_OVERRIDE),
 206         TAB_MAP(PMSTATUSLOG),
 207         TAB_MAP(SMU_METRICS),
 208         TAB_MAP(DRIVER_SMU_CONFIG),
 209         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 210         TAB_MAP(OVERDRIVE),
 211 };
 212
 213 static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 214         PWR_MAP(AC),
 215         PWR_MAP(DC),
 216 };
 217
 218 static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_DEFAULT_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 223         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 224         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 225         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 226 };
 227
 228 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
 229 {
 230         struct smu_11_0_cmn2aisc_mapping mapping;
 231
 232         if (index >= SMU_TABLE_COUNT)
 233                 return -EINVAL;
 234
 235         mapping = vega20_table_map[index];
 236         if (!(mapping.valid_mapping)) {
 237                 return -EINVAL;
 238         }
 239
 240         return mapping.map_to;
 241 }
 242
 243 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 244 {
 245         struct smu_11_0_cmn2aisc_mapping mapping;
 246
 247         if (index >= SMU_POWER_SOURCE_COUNT)
 248                 return -EINVAL;
 249
 250         mapping = vega20_pwr_src_map[index];
 251         if (!(mapping.valid_mapping)) {
 252                 return -EINVAL;
 253         }
 254
 255         return mapping.map_to;
 256 }
 257
 258 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 259 {
 260         struct smu_11_0_cmn2aisc_mapping mapping;
 261
 262         if (index >= SMU_FEATURE_COUNT)
 263                 return -EINVAL;
 264
 265         mapping = vega20_feature_mask_map[index];
 266         if (!(mapping.valid_mapping)) {
 267                 return -EINVAL;
 268         }
 269
 270         return mapping.map_to;
 271 }
 272
 273 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 274 {
 275         struct smu_11_0_cmn2aisc_mapping mapping;
 276
 277         if (index >= SMU_CLK_COUNT)
 278                 return -EINVAL;
 279
 280         mapping = vega20_clk_map[index];
 281         if (!(mapping.valid_mapping)) {
 282                 return -EINVAL;
 283         }
 284
 285         return mapping.map_to;
 286 }
 287
 288 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 289 {
 290         struct smu_11_0_cmn2aisc_mapping mapping;
 291
 292         if (index >= SMU_MSG_MAX_COUNT)
 293                 return -EINVAL;
 294
 295         mapping = vega20_message_map[index];
 296         if (!(mapping.valid_mapping)) {
 297                 return -EINVAL;
 298         }
 299
 300         return mapping.map_to;
 301 }
 302
 303 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 304 {
 305         struct smu_11_0_cmn2aisc_mapping mapping;
 306
 307         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 308                 return -EINVAL;
 309
 310         mapping = vega20_workload_map[profile];
 311         if (!(mapping.valid_mapping)) {
 312                 return -EINVAL;
 313         }
 314
 315         return mapping.map_to;
 316 }
 317
 318 static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
 319 {
 320         struct smu_table_context *smu_table = &smu->smu_table;
 321
 322         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 323                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 324         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 325                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 326         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 327                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 328         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 329                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 330         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 331                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 332         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 333                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 334                        AMDGPU_GEM_DOMAIN_VRAM);
 335
 336         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 337         if (!smu_table->metrics_table)
 338                 return -ENOMEM;
 339         smu_table->metrics_time = 0;
 340
 341         return 0;
 342 }
 343
 344 static int vega20_allocate_dpm_context(struct smu_context *smu)
 345 {
 346         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 347
 348         if (smu_dpm->dpm_context)
 349                 return -EINVAL;
 350
 351         smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
 352                                        GFP_KERNEL);
 353         if (!smu_dpm->dpm_context)
 354                 return -ENOMEM;
 355
 356         if (smu_dpm->golden_dpm_context)
 357                 return -EINVAL;
 358
 359         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
 360                                               GFP_KERNEL);
 361         if (!smu_dpm->golden_dpm_context)
 362                 return -ENOMEM;
 363
 364         smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
 365
 366         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 367                                        GFP_KERNEL);
 368         if (!smu_dpm->dpm_current_power_state)
 369                 return -ENOMEM;
 370
 371         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 372                                        GFP_KERNEL);
 373         if (!smu_dpm->dpm_request_power_state)
 374                 return -ENOMEM;
 375
 376         return 0;
 377 }
 378
 379 static int vega20_setup_od8_information(struct smu_context *smu)
 380 {
 381         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 382         struct smu_table_context *table_context = &smu->smu_table;
 383         struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
 384
 385         uint32_t od_feature_count, od_feature_array_size,
 386                  od_setting_count, od_setting_array_size;
 387
 388         if (!table_context->power_play_table)
 389                 return -EINVAL;
 390
 391         powerplay_table = table_context->power_play_table;
 392
 393         if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
 394                 /* Setup correct ODFeatureCount, and store ODFeatureArray from
 395                  * powerplay table to od_feature_capabilities */
 396                 od_feature_count =
 397                         (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
 398                          ATOM_VEGA20_ODFEATURE_COUNT) ?
 399                         ATOM_VEGA20_ODFEATURE_COUNT :
 400                         le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
 401
 402                 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
 403
 404                 if (od8_settings->od_feature_capabilities)
 405                         return -EINVAL;
 406
 407                 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
 408                                                                  od_feature_array_size,
 409                                                                  GFP_KERNEL);
 410                 if (!od8_settings->od_feature_capabilities)
 411                         return -ENOMEM;
 412
 413                 /* Setup correct ODSettingCount, and store ODSettingArray from
 414                  * powerplay table to od_settings_max and od_setting_min */
 415                 od_setting_count =
 416                         (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
 417                          ATOM_VEGA20_ODSETTING_COUNT) ?
 418                         ATOM_VEGA20_ODSETTING_COUNT :
 419                         le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
 420
 421                 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
 422
 423                 if (od8_settings->od_settings_max)
 424                         return -EINVAL;
 425
 426                 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
 427                                                          od_setting_array_size,
 428                                                          GFP_KERNEL);
 429
 430                 if (!od8_settings->od_settings_max) {
 431                         kfree(od8_settings->od_feature_capabilities);
 432                         od8_settings->od_feature_capabilities = NULL;
 433                         return -ENOMEM;
 434                 }
 435
 436                 if (od8_settings->od_settings_min)
 437                         return -EINVAL;
 438
 439                 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
 440                                                          od_setting_array_size,
 441                                                          GFP_KERNEL);
 442
 443                 if (!od8_settings->od_settings_min) {
 444                         kfree(od8_settings->od_feature_capabilities);
 445                         od8_settings->od_feature_capabilities = NULL;
 446                         kfree(od8_settings->od_settings_max);
 447                         od8_settings->od_settings_max = NULL;
 448                         return -ENOMEM;
 449                 }
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int vega20_store_powerplay_table(struct smu_context *smu)
 456 {
 457         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 458         struct smu_table_context *table_context = &smu->smu_table;
 459
 460         if (!table_context->power_play_table)
 461                 return -EINVAL;
 462
 463         powerplay_table = table_context->power_play_table;
 464
 465         memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
 466                sizeof(PPTable_t));
 467
 468         table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
 469         table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
 470
 471         return 0;
 472 }
 473
 474 static int vega20_append_powerplay_table(struct smu_context *smu)
 475 {
 476         struct smu_table_context *table_context = &smu->smu_table;
 477         PPTable_t *smc_pptable = table_context->driver_pptable;
 478         struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
 479         int index, i, ret;
 480
 481         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 482                                            smc_dpm_info);
 483
 484         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 485                                       (uint8_t **)&smc_dpm_table);
 486         if (ret)
 487                 return ret;
 488
 489         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
 490         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
 491
 492         smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
 493         smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
 494         smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
 495         smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
 496
 497         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
 498         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
 499         smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
 500
 501         smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
 502         smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
 503         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
 504
 505         smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
 506         smc_pptable->SocOffset = smc_dpm_table->socoffset;
 507         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
 508
 509         smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
 510         smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
 511         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
 512
 513         smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
 514         smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
 515         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
 516
 517         smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
 518         smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
 519         smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
 520         smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
 521
 522         smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
 523         smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
 524         smc_pptable->Padding1 = smc_dpm_table->padding1;
 525         smc_pptable->Padding2 = smc_dpm_table->padding2;
 526
 527         smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
 528         smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
 529         smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
 530
 531         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
 532         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
 533         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
 534
 535         smc_pptable->UclkSpreadEnabled = 0;
 536         smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
 537         smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
 538
 539         smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
 540         smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
 541         smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
 542
 543         smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
 544         smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
 545         smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
 546
 547         for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
 548                 smc_pptable->I2cControllers[i].Enabled =
 549                         smc_dpm_table->i2ccontrollers[i].enabled;
 550                 smc_pptable->I2cControllers[i].SlaveAddress =
 551                         smc_dpm_table->i2ccontrollers[i].slaveaddress;
 552                 smc_pptable->I2cControllers[i].ControllerPort =
 553                         smc_dpm_table->i2ccontrollers[i].controllerport;
 554                 smc_pptable->I2cControllers[i].ThermalThrottler =
 555                         smc_dpm_table->i2ccontrollers[i].thermalthrottler;
 556                 smc_pptable->I2cControllers[i].I2cProtocol =
 557                         smc_dpm_table->i2ccontrollers[i].i2cprotocol;
 558                 smc_pptable->I2cControllers[i].I2cSpeed =
 559                         smc_dpm_table->i2ccontrollers[i].i2cspeed;
 560         }
 561
 562         return 0;
 563 }
 564
 565 static int vega20_check_powerplay_table(struct smu_context *smu)
 566 {
 567         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 568         struct smu_table_context *table_context = &smu->smu_table;
 569
 570         powerplay_table = table_context->power_play_table;
 571
 572         if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
 573                 pr_err("Unsupported PPTable format!");
 574                 return -EINVAL;
 575         }
 576
 577         if (!powerplay_table->sHeader.structuresize) {
 578                 pr_err("Invalid PowerPlay Table!");
 579                 return -EINVAL;
 580         }
 581
 582         return 0;
 583 }
 584
 585 static int vega20_run_btc_afll(struct smu_context *smu)
 586 {
 587         return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 588 }
 589
 590 #define FEATURE_MASK(feature) (1ULL << feature)
 591 static int
 592 vega20_get_allowed_feature_mask(struct smu_context *smu,
 593                                   uint32_t *feature_mask, uint32_t num)
 594 {
 595         if (num > 2)
 596                 return -EINVAL;
 597
 598         memset(feature_mask, 0, sizeof(uint32_t) * num);
 599
 600         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 601                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 602                                 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 603                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 604                                 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
 605                                 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
 606                                 | FEATURE_MASK(FEATURE_ULV_BIT)
 607                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 608                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 609                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
 610                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 611                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 612                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 613                                 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
 614                                 | FEATURE_MASK(FEATURE_RM_BIT)
 615                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 616                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 617                                 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
 618                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 619                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 620                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 621                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 622                                 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
 623                                 | FEATURE_MASK(FEATURE_CG_BIT)
 624                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 625                                 | FEATURE_MASK(FEATURE_XGMI_BIT);
 626         return 0;
 627 }
 628
 629 static enum
 630 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
 631 {
 632         enum amd_pm_state_type pm_type;
 633         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 634
 635         if (!smu_dpm_ctx->dpm_context ||
 636             !smu_dpm_ctx->dpm_current_power_state)
 637                 return -EINVAL;
 638
 639         switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
 640         case SMU_STATE_UI_LABEL_BATTERY:
 641                 pm_type = POWER_STATE_TYPE_BATTERY;
 642                 break;
 643         case SMU_STATE_UI_LABEL_BALLANCED:
 644                 pm_type = POWER_STATE_TYPE_BALANCED;
 645                 break;
 646         case SMU_STATE_UI_LABEL_PERFORMANCE:
 647                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
 648                 break;
 649         default:
 650                 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
 651                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 652                 else
 653                         pm_type = POWER_STATE_TYPE_DEFAULT;
 654                 break;
 655         }
 656
 657         return pm_type;
 658 }
 659
 660 static int
 661 vega20_set_single_dpm_table(struct smu_context *smu,
 662                             struct vega20_single_dpm_table *single_dpm_table,
 663                             PPCLK_e clk_id)
 664 {
 665         int ret = 0;
 666         uint32_t i, num_of_levels = 0, clk;
 667
 668         ret = smu_send_smc_msg_with_param(smu,
 669                         SMU_MSG_GetDpmFreqByIndex,
 670                         (clk_id << 16 | 0xFF));
 671         if (ret) {
 672                 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
 673                 return ret;
 674         }
 675
 676         smu_read_smc_arg(smu, &num_of_levels);
 677         if (!num_of_levels) {
 678                 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
 679                 return -EINVAL;
 680         }
 681
 682         single_dpm_table->count = num_of_levels;
 683
 684         for (i = 0; i < num_of_levels; i++) {
 685                 ret = smu_send_smc_msg_with_param(smu,
 686                                 SMU_MSG_GetDpmFreqByIndex,
 687                                 (clk_id << 16 | i));
 688                 if (ret) {
 689                         pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
 690                         return ret;
 691                 }
 692                 smu_read_smc_arg(smu, &clk);
 693                 if (!clk) {
 694                         pr_err("[GetDpmFreqByIndex] clk value is invalid!");
 695                         return -EINVAL;
 696                 }
 697                 single_dpm_table->dpm_levels[i].value = clk;
 698                 single_dpm_table->dpm_levels[i].enabled = true;
 699         }
 700         return 0;
 701 }
 702
 703 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
 704 {
 705         dpm_state->soft_min_level = 0x0;
 706         dpm_state->soft_max_level = 0xffff;
 707         dpm_state->hard_min_level = 0x0;
 708         dpm_state->hard_max_level = 0xffff;
 709 }
 710
 711 static int vega20_set_default_dpm_table(struct smu_context *smu)
 712 {
 713         int ret;
 714
 715         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 716         struct vega20_dpm_table *dpm_table = NULL;
 717         struct vega20_single_dpm_table *single_dpm_table;
 718
 719         dpm_table = smu_dpm->dpm_context;
 720
 721         /* socclk */
 722         single_dpm_table = &(dpm_table->soc_table);
 723
 724         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 725                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 726                                                   PPCLK_SOCCLK);
 727                 if (ret) {
 728                         pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
 729                         return ret;
 730                 }
 731         } else {
 732                 single_dpm_table->count = 1;
 733                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 734         }
 735         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 736
 737         /* gfxclk */
 738         single_dpm_table = &(dpm_table->gfx_table);
 739
 740         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 741                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 742                                                   PPCLK_GFXCLK);
 743                 if (ret) {
 744                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 745                         return ret;
 746                 }
 747         } else {
 748                 single_dpm_table->count = 1;
 749                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 750         }
 751         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 752
 753         /* memclk */
 754         single_dpm_table = &(dpm_table->mem_table);
 755
 756         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 757                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 758                                                   PPCLK_UCLK);
 759                 if (ret) {
 760                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 761                         return ret;
 762                 }
 763         } else {
 764                 single_dpm_table->count = 1;
 765                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 766         }
 767         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 768
 769         /* eclk */
 770         single_dpm_table = &(dpm_table->eclk_table);
 771
 772         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
 773                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
 774                 if (ret) {
 775                         pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
 776                         return ret;
 777                 }
 778         } else {
 779                 single_dpm_table->count = 1;
 780                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
 781         }
 782         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 783
 784         /* vclk */
 785         single_dpm_table = &(dpm_table->vclk_table);
 786
 787         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 788                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
 789                 if (ret) {
 790                         pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
 791                         return ret;
 792                 }
 793         } else {
 794                 single_dpm_table->count = 1;
 795                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 796         }
 797         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 798
 799         /* dclk */
 800         single_dpm_table = &(dpm_table->dclk_table);
 801
 802         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 803                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
 804                 if (ret) {
 805                         pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
 806                         return ret;
 807                 }
 808         } else {
 809                 single_dpm_table->count = 1;
 810                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 811         }
 812         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 813
 814         /* dcefclk */
 815         single_dpm_table = &(dpm_table->dcef_table);
 816
 817         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 818                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 819                                                   PPCLK_DCEFCLK);
 820                 if (ret) {
 821                         pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
 822                         return ret;
 823                 }
 824         } else {
 825                 single_dpm_table->count = 1;
 826                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 827         }
 828         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 829
 830         /* pixclk */
 831         single_dpm_table = &(dpm_table->pixel_table);
 832
 833         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 834                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 835                                                   PPCLK_PIXCLK);
 836                 if (ret) {
 837                         pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
 838                         return ret;
 839                 }
 840         } else {
 841                 single_dpm_table->count = 0;
 842         }
 843         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 844
 845         /* dispclk */
 846         single_dpm_table = &(dpm_table->display_table);
 847
 848         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 849                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 850                                                   PPCLK_DISPCLK);
 851                 if (ret) {
 852                         pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
 853                         return ret;
 854                 }
 855         } else {
 856                 single_dpm_table->count = 0;
 857         }
 858         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 859
 860         /* phyclk */
 861         single_dpm_table = &(dpm_table->phy_table);
 862
 863         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 864                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 865                                                   PPCLK_PHYCLK);
 866                 if (ret) {
 867                         pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
 868                         return ret;
 869                 }
 870         } else {
 871                 single_dpm_table->count = 0;
 872         }
 873         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 874
 875         /* fclk */
 876         single_dpm_table = &(dpm_table->fclk_table);
 877
 878         if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
 879                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 880                                                   PPCLK_FCLK);
 881                 if (ret) {
 882                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 883                         return ret;
 884                 }
 885         } else {
 886                 single_dpm_table->count = 0;
 887         }
 888         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 889
 890         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 891                sizeof(struct vega20_dpm_table));
 892
 893         return 0;
 894 }
 895
 896 static int vega20_populate_umd_state_clk(struct smu_context *smu)
 897 {
 898         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 899         struct vega20_dpm_table *dpm_table = NULL;
 900         struct vega20_single_dpm_table *gfx_table = NULL;
 901         struct vega20_single_dpm_table *mem_table = NULL;
 902
 903         dpm_table = smu_dpm->dpm_context;
 904         gfx_table = &(dpm_table->gfx_table);
 905         mem_table = &(dpm_table->mem_table);
 906
 907         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 908         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 909
 910         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
 911             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
 912                 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
 913                 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
 914         }
 915
 916         smu->pstate_sclk = smu->pstate_sclk * 100;
 917         smu->pstate_mclk = smu->pstate_mclk * 100;
 918
 919         return 0;
 920 }
 921
 922 static int vega20_get_clk_table(struct smu_context *smu,
 923                         struct pp_clock_levels_with_latency *clocks,
 924                         struct vega20_single_dpm_table *dpm_table)
 925 {
 926         int i, count;
 927
 928         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 929         clocks->num_levels = count;
 930
 931         for (i = 0; i < count; i++) {
 932                 clocks->data[i].clocks_in_khz =
 933                         dpm_table->dpm_levels[i].value * 1000;
 934                 clocks->data[i].latency_in_us = 0;
 935         }
 936
 937         return 0;
 938 }
 939
 940 static int vega20_print_clk_levels(struct smu_context *smu,
 941                         enum smu_clk_type type, char *buf)
 942 {
 943         int i, now, size = 0;
 944         int ret = 0;
 945         uint32_t gen_speed, lane_width;
 946         struct amdgpu_device *adev = smu->adev;
 947         struct pp_clock_levels_with_latency clocks;
 948         struct vega20_single_dpm_table *single_dpm_table;
 949         struct smu_table_context *table_context = &smu->smu_table;
 950         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 951         struct vega20_dpm_table *dpm_table = NULL;
 952         struct vega20_od8_settings *od8_settings =
 953                 (struct vega20_od8_settings *)smu->od_settings;
 954         OverDriveTable_t *od_table =
 955                 (OverDriveTable_t *)(table_context->overdrive_table);
 956         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 957
 958         dpm_table = smu_dpm->dpm_context;
 959
 960         switch (type) {
 961         case SMU_SCLK:
 962                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 963                 if (ret) {
 964                         pr_err("Attempt to get current gfx clk Failed!");
 965                         return ret;
 966                 }
 967
 968                 single_dpm_table = &(dpm_table->gfx_table);
 969                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 970                 if (ret) {
 971                         pr_err("Attempt to get gfx clk levels Failed!");
 972                         return ret;
 973                 }
 974
 975                 for (i = 0; i < clocks.num_levels; i++)
 976                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 977                                         clocks.data[i].clocks_in_khz / 1000,
 978                                         (clocks.data[i].clocks_in_khz == now * 10)
 979                                         ? "*" : "");
 980                 break;
 981
 982         case SMU_MCLK:
 983                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 984                 if (ret) {
 985                         pr_err("Attempt to get current mclk Failed!");
 986                         return ret;
 987                 }
 988
 989                 single_dpm_table = &(dpm_table->mem_table);
 990                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 991                 if (ret) {
 992                         pr_err("Attempt to get memory clk levels Failed!");
 993                         return ret;
 994                 }
 995
 996                 for (i = 0; i < clocks.num_levels; i++)
 997                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 998                                 i, clocks.data[i].clocks_in_khz / 1000,
 999                                 (clocks.data[i].clocks_in_khz == now * 10)
1000                                 ? "*" : "");
1001                 break;
1002
1003         case SMU_SOCCLK:
1004                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
1005                 if (ret) {
1006                         pr_err("Attempt to get current socclk Failed!");
1007                         return ret;
1008                 }
1009
1010                 single_dpm_table = &(dpm_table->soc_table);
1011                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1012                 if (ret) {
1013                         pr_err("Attempt to get socclk levels Failed!");
1014                         return ret;
1015                 }
1016
1017                 for (i = 0; i < clocks.num_levels; i++)
1018                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1019                                 i, clocks.data[i].clocks_in_khz / 1000,
1020                                 (clocks.data[i].clocks_in_khz == now * 10)
1021                                 ? "*" : "");
1022                 break;
1023
1024         case SMU_FCLK:
1025                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1026                 if (ret) {
1027                         pr_err("Attempt to get current fclk Failed!");
1028                         return ret;
1029                 }
1030
1031                 single_dpm_table = &(dpm_table->fclk_table);
1032                 for (i = 0; i < single_dpm_table->count; i++)
1033                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1034                                 i, single_dpm_table->dpm_levels[i].value,
1035                                 (single_dpm_table->dpm_levels[i].value == now / 100)
1036                                 ? "*" : "");
1037                 break;
1038
1039         case SMU_DCEFCLK:
1040                 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1041                 if (ret) {
1042                         pr_err("Attempt to get current dcefclk Failed!");
1043                         return ret;
1044                 }
1045
1046                 single_dpm_table = &(dpm_table->dcef_table);
1047                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1048                 if (ret) {
1049                         pr_err("Attempt to get dcefclk levels Failed!");
1050                         return ret;
1051                 }
1052
1053                 for (i = 0; i < clocks.num_levels; i++)
1054                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1055                                 i, clocks.data[i].clocks_in_khz / 1000,
1056                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1057                 break;
1058
1059         case SMU_PCIE:
1060                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1061                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1062                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1063                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1064                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1065                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1066                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1067                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1068                                         (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1069                                         (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1070                                         (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1071                                         (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1072                                         (pptable->PcieLaneCount[i] == 1) ? "x1" :
1073                                         (pptable->PcieLaneCount[i] == 2) ? "x2" :
1074                                         (pptable->PcieLaneCount[i] == 3) ? "x4" :
1075                                         (pptable->PcieLaneCount[i] == 4) ? "x8" :
1076                                         (pptable->PcieLaneCount[i] == 5) ? "x12" :
1077                                         (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1078                                         pptable->LclkFreq[i],
1079                                         (gen_speed == pptable->PcieGenSpeed[i]) &&
1080                                         (lane_width == pptable->PcieLaneCount[i]) ?
1081                                         "*" : "");
1082                 break;
1083
1084         case SMU_OD_SCLK:
1085                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1086                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1087                         size = sprintf(buf, "%s:\n", "OD_SCLK");
1088                         size += sprintf(buf + size, "0: %10uMhz\n",
1089                                         od_table->GfxclkFmin);
1090                         size += sprintf(buf + size, "1: %10uMhz\n",
1091                                         od_table->GfxclkFmax);
1092                 }
1093
1094                 break;
1095
1096         case SMU_OD_MCLK:
1097                 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1098                         size = sprintf(buf, "%s:\n", "OD_MCLK");
1099                         size += sprintf(buf + size, "1: %10uMhz\n",
1100                                          od_table->UclkFmax);
1101                 }
1102
1103                 break;
1104
1105         case SMU_OD_VDDC_CURVE:
1106                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1107                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1108                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1109                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1110                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1111                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1112                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1113                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1114                                         od_table->GfxclkFreq1,
1115                                         od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1116                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1117                                         od_table->GfxclkFreq2,
1118                                         od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1119                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1120                                         od_table->GfxclkFreq3,
1121                                         od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1122                 }
1123
1124                 break;
1125
1126         case SMU_OD_RANGE:
1127                 size = sprintf(buf, "%s:\n", "OD_RANGE");
1128
1129                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1130                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1131                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1132                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1133                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1134                 }
1135
1136                 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1137                         single_dpm_table = &(dpm_table->mem_table);
1138                         ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1139                         if (ret) {
1140                                 pr_err("Attempt to get memory clk levels Failed!");
1141                                 return ret;
1142                         }
1143
1144                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1145                                         clocks.data[0].clocks_in_khz / 1000,
1146                                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1147                 }
1148
1149                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1150                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1151                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1152                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1153                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1154                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1155                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1156                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1157                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1158                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1159                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1160                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1161                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1162                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1163                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1164                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1165                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1166                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1167                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1168                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1169                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1170                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1171                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1172                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1173                 }
1174
1175                 break;
1176
1177         default:
1178                 break;
1179         }
1180         return size;
1181 }
1182
1183 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1184                                    uint32_t feature_mask)
1185 {
1186         struct vega20_dpm_table *dpm_table;
1187         struct vega20_single_dpm_table *single_dpm_table;
1188         uint32_t freq;
1189         int ret = 0;
1190
1191         dpm_table = smu->smu_dpm.dpm_context;
1192
1193         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1194             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1195                 single_dpm_table = &(dpm_table->gfx_table);
1196                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1197                         single_dpm_table->dpm_state.soft_min_level;
1198                 ret = smu_send_smc_msg_with_param(smu,
1199                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1200                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1201                 if (ret) {
1202                         pr_err("Failed to set soft %s gfxclk !\n",
1203                                                 max ? "max" : "min");
1204                         return ret;
1205                 }
1206         }
1207
1208         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1209             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1210                 single_dpm_table = &(dpm_table->mem_table);
1211                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1212                         single_dpm_table->dpm_state.soft_min_level;
1213                 ret = smu_send_smc_msg_with_param(smu,
1214                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1215                         (PPCLK_UCLK << 16) | (freq & 0xffff));
1216                 if (ret) {
1217                         pr_err("Failed to set soft %s memclk !\n",
1218                                                 max ? "max" : "min");
1219                         return ret;
1220                 }
1221         }
1222
1223         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1224             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1225                 single_dpm_table = &(dpm_table->soc_table);
1226                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1227                         single_dpm_table->dpm_state.soft_min_level;
1228                 ret = smu_send_smc_msg_with_param(smu,
1229                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1230                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1231                 if (ret) {
1232                         pr_err("Failed to set soft %s socclk !\n",
1233                                                 max ? "max" : "min");
1234                         return ret;
1235                 }
1236         }
1237
1238         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1239             (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1240                 single_dpm_table = &(dpm_table->fclk_table);
1241                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1242                         single_dpm_table->dpm_state.soft_min_level;
1243                 ret = smu_send_smc_msg_with_param(smu,
1244                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1245                         (PPCLK_FCLK << 16) | (freq & 0xffff));
1246                 if (ret) {
1247                         pr_err("Failed to set soft %s fclk !\n",
1248                                                 max ? "max" : "min");
1249                         return ret;
1250                 }
1251         }
1252
1253         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1254             (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1255                 single_dpm_table = &(dpm_table->dcef_table);
1256                 freq = single_dpm_table->dpm_state.hard_min_level;
1257                 if (!max) {
1258                         ret = smu_send_smc_msg_with_param(smu,
1259                                 SMU_MSG_SetHardMinByFreq,
1260                                 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1261                         if (ret) {
1262                                 pr_err("Failed to set hard min dcefclk !\n");
1263                                 return ret;
1264                         }
1265                 }
1266         }
1267
1268         return ret;
1269 }
1270
1271 static int vega20_force_clk_levels(struct smu_context *smu,
1272                         enum  smu_clk_type clk_type, uint32_t mask)
1273 {
1274         struct vega20_dpm_table *dpm_table;
1275         struct vega20_single_dpm_table *single_dpm_table;
1276         uint32_t soft_min_level, soft_max_level, hard_min_level;
1277         int ret = 0;
1278
1279         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1280         soft_max_level = mask ? (fls(mask) - 1) : 0;
1281
1282         dpm_table = smu->smu_dpm.dpm_context;
1283
1284         switch (clk_type) {
1285         case SMU_SCLK:
1286                 single_dpm_table = &(dpm_table->gfx_table);
1287
1288                 if (soft_max_level >= single_dpm_table->count) {
1289                         pr_err("Clock level specified %d is over max allowed %d\n",
1290                                         soft_max_level, single_dpm_table->count - 1);
1291                         ret = -EINVAL;
1292                         break;
1293                 }
1294
1295                 single_dpm_table->dpm_state.soft_min_level =
1296                         single_dpm_table->dpm_levels[soft_min_level].value;
1297                 single_dpm_table->dpm_state.soft_max_level =
1298                         single_dpm_table->dpm_levels[soft_max_level].value;
1299
1300                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1301                 if (ret) {
1302                         pr_err("Failed to upload boot level to lowest!\n");
1303                         break;
1304                 }
1305
1306                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1307                 if (ret)
1308                         pr_err("Failed to upload dpm max level to highest!\n");
1309
1310                 break;
1311
1312         case SMU_MCLK:
1313                 single_dpm_table = &(dpm_table->mem_table);
1314
1315                 if (soft_max_level >= single_dpm_table->count) {
1316                         pr_err("Clock level specified %d is over max allowed %d\n",
1317                                         soft_max_level, single_dpm_table->count - 1);
1318                         ret = -EINVAL;
1319                         break;
1320                 }
1321
1322                 single_dpm_table->dpm_state.soft_min_level =
1323                         single_dpm_table->dpm_levels[soft_min_level].value;
1324                 single_dpm_table->dpm_state.soft_max_level =
1325                         single_dpm_table->dpm_levels[soft_max_level].value;
1326
1327                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1328                 if (ret) {
1329                         pr_err("Failed to upload boot level to lowest!\n");
1330                         break;
1331                 }
1332
1333                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1334                 if (ret)
1335                         pr_err("Failed to upload dpm max level to highest!\n");
1336
1337                 break;
1338
1339         case SMU_SOCCLK:
1340                 single_dpm_table = &(dpm_table->soc_table);
1341
1342                 if (soft_max_level >= single_dpm_table->count) {
1343                         pr_err("Clock level specified %d is over max allowed %d\n",
1344                                         soft_max_level, single_dpm_table->count - 1);
1345                         ret = -EINVAL;
1346                         break;
1347                 }
1348
1349                 single_dpm_table->dpm_state.soft_min_level =
1350                         single_dpm_table->dpm_levels[soft_min_level].value;
1351                 single_dpm_table->dpm_state.soft_max_level =
1352                         single_dpm_table->dpm_levels[soft_max_level].value;
1353
1354                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1355                 if (ret) {
1356                         pr_err("Failed to upload boot level to lowest!\n");
1357                         break;
1358                 }
1359
1360                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1361                 if (ret)
1362                         pr_err("Failed to upload dpm max level to highest!\n");
1363
1364                 break;
1365
1366         case SMU_FCLK:
1367                 single_dpm_table = &(dpm_table->fclk_table);
1368
1369                 if (soft_max_level >= single_dpm_table->count) {
1370                         pr_err("Clock level specified %d is over max allowed %d\n",
1371                                         soft_max_level, single_dpm_table->count - 1);
1372                         ret = -EINVAL;
1373                         break;
1374                 }
1375
1376                 single_dpm_table->dpm_state.soft_min_level =
1377                         single_dpm_table->dpm_levels[soft_min_level].value;
1378                 single_dpm_table->dpm_state.soft_max_level =
1379                         single_dpm_table->dpm_levels[soft_max_level].value;
1380
1381                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1382                 if (ret) {
1383                         pr_err("Failed to upload boot level to lowest!\n");
1384                         break;
1385                 }
1386
1387                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1388                 if (ret)
1389                         pr_err("Failed to upload dpm max level to highest!\n");
1390
1391                 break;
1392
1393         case SMU_DCEFCLK:
1394                 hard_min_level = soft_min_level;
1395                 single_dpm_table = &(dpm_table->dcef_table);
1396
1397                 if (hard_min_level >= single_dpm_table->count) {
1398                         pr_err("Clock level specified %d is over max allowed %d\n",
1399                                         hard_min_level, single_dpm_table->count - 1);
1400                         ret = -EINVAL;
1401                         break;
1402                 }
1403
1404                 single_dpm_table->dpm_state.hard_min_level =
1405                         single_dpm_table->dpm_levels[hard_min_level].value;
1406
1407                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1408                 if (ret)
1409                         pr_err("Failed to upload boot level to lowest!\n");
1410
1411                 break;
1412
1413         case SMU_PCIE:
1414                 if (soft_min_level >= NUM_LINK_LEVELS ||
1415                     soft_max_level >= NUM_LINK_LEVELS) {
1416                         ret = -EINVAL;
1417                         break;
1418                 }
1419
1420                 ret = smu_send_smc_msg_with_param(smu,
1421                                 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1422                 if (ret)
1423                         pr_err("Failed to set min link dpm level!\n");
1424
1425                 break;
1426
1427         default:
1428                 break;
1429         }
1430
1431         return ret;
1432 }
1433
1434 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1435                                                  enum smu_clk_type clk_type,
1436                                                  struct pp_clock_levels_with_latency *clocks)
1437 {
1438         int ret;
1439         struct vega20_single_dpm_table *single_dpm_table;
1440         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1441         struct vega20_dpm_table *dpm_table = NULL;
1442
1443         dpm_table = smu_dpm->dpm_context;
1444
1445         switch (clk_type) {
1446         case SMU_GFXCLK:
1447                 single_dpm_table = &(dpm_table->gfx_table);
1448                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1449                 break;
1450         case SMU_MCLK:
1451                 single_dpm_table = &(dpm_table->mem_table);
1452                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1453                 break;
1454         case SMU_DCEFCLK:
1455                 single_dpm_table = &(dpm_table->dcef_table);
1456                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1457                 break;
1458         case SMU_SOCCLK:
1459                 single_dpm_table = &(dpm_table->soc_table);
1460                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1461                 break;
1462         default:
1463                 ret = -EINVAL;
1464         }
1465
1466         return ret;
1467 }
1468
1469 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1470                                                      uint32_t *voltage,
1471                                                      uint32_t freq)
1472 {
1473         int ret;
1474
1475         ret = smu_send_smc_msg_with_param(smu,
1476                         SMU_MSG_GetAVFSVoltageByDpm,
1477                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1478         if (ret) {
1479                 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1480                 return ret;
1481         }
1482
1483         smu_read_smc_arg(smu, voltage);
1484         *voltage = *voltage / VOLTAGE_SCALE;
1485
1486         return 0;
1487 }
1488
1489 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1490 {
1491         struct smu_table_context *table_context = &smu->smu_table;
1492         OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1493         struct vega20_od8_settings *od8_settings = NULL;
1494         PPTable_t *smc_pptable = table_context->driver_pptable;
1495         int i, ret;
1496
1497         if (smu->od_settings)
1498                 return -EINVAL;
1499
1500         od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1501
1502         if (!od8_settings)
1503                 return -ENOMEM;
1504
1505         smu->od_settings = (void *)od8_settings;
1506
1507         ret = vega20_setup_od8_information(smu);
1508         if (ret) {
1509                 pr_err("Retrieve board OD limits failed!\n");
1510                 return ret;
1511         }
1512
1513         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1514                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1515                     od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1516                     od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1517                     (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1518                      od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1519                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1520                                 OD8_GFXCLK_LIMITS;
1521                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1522                                 OD8_GFXCLK_LIMITS;
1523                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1524                                 od_table->GfxclkFmin;
1525                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1526                                 od_table->GfxclkFmax;
1527                 }
1528
1529                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1530                     (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1531                      smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1532                     (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1533                      smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1534                     (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1535                      od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1536                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1537                                 OD8_GFXCLK_CURVE;
1538                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1539                                 OD8_GFXCLK_CURVE;
1540                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1541                                 OD8_GFXCLK_CURVE;
1542                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1543                                 OD8_GFXCLK_CURVE;
1544                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1545                                 OD8_GFXCLK_CURVE;
1546                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1547                                 OD8_GFXCLK_CURVE;
1548
1549                         od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1550                         od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1551                         od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1552                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1553                                 od_table->GfxclkFreq1;
1554                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1555                                 od_table->GfxclkFreq2;
1556                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1557                                 od_table->GfxclkFreq3;
1558
1559                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1560                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1561                                 od_table->GfxclkFreq1);
1562                         if (ret)
1563                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1564                         od_table->GfxclkVolt1 =
1565                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1566                                 * VOLTAGE_SCALE;
1567                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1568                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1569                                 od_table->GfxclkFreq2);
1570                         if (ret)
1571                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1572                         od_table->GfxclkVolt2 =
1573                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1574                                 * VOLTAGE_SCALE;
1575                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1576                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1577                                 od_table->GfxclkFreq3);
1578                         if (ret)
1579                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1580                         od_table->GfxclkVolt3 =
1581                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1582                                 * VOLTAGE_SCALE;
1583                 }
1584         }
1585
1586         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1587                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1588                     od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1589                     od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1590                     (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1591                      od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1592                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1593                                 OD8_UCLK_MAX;
1594                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1595                                 od_table->UclkFmax;
1596                 }
1597         }
1598
1599         if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1600             od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1601             od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1602             od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1603             od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1604                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1605                         OD8_POWER_LIMIT;
1606                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1607                         od_table->OverDrivePct;
1608         }
1609
1610         if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1611                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1612                     od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1613                     od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1614                     (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1615                      od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1616                         od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1617                                 OD8_ACOUSTIC_LIMIT_SCLK;
1618                         od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1619                                 od_table->FanMaximumRpm;
1620                 }
1621
1622                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1623                     od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1624                     od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1625                     (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1626                      od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1627                         od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1628                                 OD8_FAN_SPEED_MIN;
1629                         od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1630                                 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1631                 }
1632         }
1633
1634         if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1635                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1636                     od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1637                     od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1638                     (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1639                      od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1640                         od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1641                                 OD8_TEMPERATURE_FAN;
1642                         od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1643                                 od_table->FanTargetTemperature;
1644                 }
1645
1646                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1647                     od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1648                     od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1649                     (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1650                      od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1651                         od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1652                                 OD8_TEMPERATURE_SYSTEM;
1653                         od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1654                                 od_table->MaxOpTemp;
1655                 }
1656         }
1657
1658         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1659                 if (od8_settings->od8_settings_array[i].feature_id) {
1660                         od8_settings->od8_settings_array[i].min_value =
1661                                 od8_settings->od_settings_min[i];
1662                         od8_settings->od8_settings_array[i].max_value =
1663                                 od8_settings->od_settings_max[i];
1664                         od8_settings->od8_settings_array[i].current_value =
1665                                 od8_settings->od8_settings_array[i].default_value;
1666                 } else {
1667                         od8_settings->od8_settings_array[i].min_value = 0;
1668                         od8_settings->od8_settings_array[i].max_value = 0;
1669                         od8_settings->od8_settings_array[i].current_value = 0;
1670                 }
1671         }
1672
1673         return 0;
1674 }
1675
1676 static int vega20_get_metrics_table(struct smu_context *smu,
1677                                     SmuMetrics_t *metrics_table)
1678 {
1679         struct smu_table_context *smu_table= &smu->smu_table;
1680         int ret = 0;
1681
1682         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1683                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1684                                 (void *)smu_table->metrics_table, false);
1685                 if (ret) {
1686                         pr_info("Failed to export SMU metrics table!\n");
1687                         return ret;
1688                 }
1689                 smu_table->metrics_time = jiffies;
1690         }
1691
1692         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1693
1694         return ret;
1695 }
1696
1697 static int vega20_set_default_od_settings(struct smu_context *smu,
1698                                           bool initialize)
1699 {
1700         struct smu_table_context *table_context = &smu->smu_table;
1701         int ret;
1702
1703         if (initialize) {
1704                 if (table_context->overdrive_table)
1705                         return -EINVAL;
1706
1707                 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1708
1709                 if (!table_context->overdrive_table)
1710                         return -ENOMEM;
1711
1712                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1713                                        table_context->overdrive_table, false);
1714                 if (ret) {
1715                         pr_err("Failed to export over drive table!\n");
1716                         return ret;
1717                 }
1718
1719                 ret = vega20_set_default_od8_setttings(smu);
1720                 if (ret)
1721                         return ret;
1722         }
1723
1724         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1725                                table_context->overdrive_table, true);
1726         if (ret) {
1727                 pr_err("Failed to import over drive table!\n");
1728                 return ret;
1729         }
1730
1731         return 0;
1732 }
1733
1734 static int vega20_get_od_percentage(struct smu_context *smu,
1735                                     enum smu_clk_type clk_type)
1736 {
1737         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1738         struct vega20_dpm_table *dpm_table = NULL;
1739         struct vega20_dpm_table *golden_table = NULL;
1740         struct vega20_single_dpm_table *single_dpm_table;
1741         struct vega20_single_dpm_table *golden_dpm_table;
1742         int value, golden_value;
1743
1744         dpm_table = smu_dpm->dpm_context;
1745         golden_table = smu_dpm->golden_dpm_context;
1746
1747         switch (clk_type) {
1748         case SMU_OD_SCLK:
1749                 single_dpm_table = &(dpm_table->gfx_table);
1750                 golden_dpm_table = &(golden_table->gfx_table);
1751                 break;
1752         case SMU_OD_MCLK:
1753                 single_dpm_table = &(dpm_table->mem_table);
1754                 golden_dpm_table = &(golden_table->mem_table);
1755                 break;
1756         default:
1757                 return -EINVAL;
1758                 break;
1759         }
1760
1761         value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1762         golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1763
1764         value -= golden_value;
1765         value = DIV_ROUND_UP(value * 100, golden_value);
1766
1767         return value;
1768 }
1769
1770 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1771 {
1772         DpmActivityMonitorCoeffInt_t activity_monitor;
1773         uint32_t i, size = 0;
1774         int16_t workload_type = 0;
1775         static const char *profile_name[] = {
1776                                         "BOOTUP_DEFAULT",
1777                                         "3D_FULL_SCREEN",
1778                                         "POWER_SAVING",
1779                                         "VIDEO",
1780                                         "VR",
1781                                         "COMPUTE",
1782                                         "CUSTOM"};
1783         static const char *title[] = {
1784                         "PROFILE_INDEX(NAME)",
1785                         "CLOCK_TYPE(NAME)",
1786                         "FPS",
1787                         "UseRlcBusy",
1788                         "MinActiveFreqType",
1789                         "MinActiveFreq",
1790                         "BoosterFreqType",
1791                         "BoosterFreq",
1792                         "PD_Data_limit_c",
1793                         "PD_Data_error_coeff",
1794                         "PD_Data_error_rate_coeff"};
1795         int result = 0;
1796
1797         if (!smu->pm_enabled || !buf)
1798                 return -EINVAL;
1799
1800         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1801                         title[0], title[1], title[2], title[3], title[4], title[5],
1802                         title[6], title[7], title[8], title[9], title[10]);
1803
1804         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1805                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1806                 workload_type = smu_workload_get_type(smu, i);
1807                 if (workload_type < 0)
1808                         return -EINVAL;
1809
1810                 result = smu_update_table(smu,
1811                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1812                                           (void *)(&activity_monitor), false);
1813                 if (result) {
1814                         pr_err("[%s] Failed to get activity monitor!", __func__);
1815                         return result;
1816                 }
1817
1818                 size += sprintf(buf + size, "%2d %14s%s:\n",
1819                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1820
1821                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1822                         " ",
1823                         0,
1824                         "GFXCLK",
1825                         activity_monitor.Gfx_FPS,
1826                         activity_monitor.Gfx_UseRlcBusy,
1827                         activity_monitor.Gfx_MinActiveFreqType,
1828                         activity_monitor.Gfx_MinActiveFreq,
1829                         activity_monitor.Gfx_BoosterFreqType,
1830                         activity_monitor.Gfx_BoosterFreq,
1831                         activity_monitor.Gfx_PD_Data_limit_c,
1832                         activity_monitor.Gfx_PD_Data_error_coeff,
1833                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1834
1835                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1836                         " ",
1837                         1,
1838                         "SOCCLK",
1839                         activity_monitor.Soc_FPS,
1840                         activity_monitor.Soc_UseRlcBusy,
1841                         activity_monitor.Soc_MinActiveFreqType,
1842                         activity_monitor.Soc_MinActiveFreq,
1843                         activity_monitor.Soc_BoosterFreqType,
1844                         activity_monitor.Soc_BoosterFreq,
1845                         activity_monitor.Soc_PD_Data_limit_c,
1846                         activity_monitor.Soc_PD_Data_error_coeff,
1847                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1848
1849                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1850                         " ",
1851                         2,
1852                         "UCLK",
1853                         activity_monitor.Mem_FPS,
1854                         activity_monitor.Mem_UseRlcBusy,
1855                         activity_monitor.Mem_MinActiveFreqType,
1856                         activity_monitor.Mem_MinActiveFreq,
1857                         activity_monitor.Mem_BoosterFreqType,
1858                         activity_monitor.Mem_BoosterFreq,
1859                         activity_monitor.Mem_PD_Data_limit_c,
1860                         activity_monitor.Mem_PD_Data_error_coeff,
1861                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1862
1863                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1864                         " ",
1865                         3,
1866                         "FCLK",
1867                         activity_monitor.Fclk_FPS,
1868                         activity_monitor.Fclk_UseRlcBusy,
1869                         activity_monitor.Fclk_MinActiveFreqType,
1870                         activity_monitor.Fclk_MinActiveFreq,
1871                         activity_monitor.Fclk_BoosterFreqType,
1872                         activity_monitor.Fclk_BoosterFreq,
1873                         activity_monitor.Fclk_PD_Data_limit_c,
1874                         activity_monitor.Fclk_PD_Data_error_coeff,
1875                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1876         }
1877
1878         return size;
1879 }
1880
1881 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1882 {
1883         DpmActivityMonitorCoeffInt_t activity_monitor;
1884         int workload_type = 0, ret = 0;
1885
1886         smu->power_profile_mode = input[size];
1887
1888         if (!smu->pm_enabled)
1889                 return ret;
1890         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1891                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1892                 return -EINVAL;
1893         }
1894
1895         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1896                 ret = smu_update_table(smu,
1897                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1898                                        (void *)(&activity_monitor), false);
1899                 if (ret) {
1900                         pr_err("[%s] Failed to get activity monitor!", __func__);
1901                         return ret;
1902                 }
1903
1904                 switch (input[0]) {
1905                 case 0: /* Gfxclk */
1906                         activity_monitor.Gfx_FPS = input[1];
1907                         activity_monitor.Gfx_UseRlcBusy = input[2];
1908                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1909                         activity_monitor.Gfx_MinActiveFreq = input[4];
1910                         activity_monitor.Gfx_BoosterFreqType = input[5];
1911                         activity_monitor.Gfx_BoosterFreq = input[6];
1912                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1913                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1914                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1915                         break;
1916                 case 1: /* Socclk */
1917                         activity_monitor.Soc_FPS = input[1];
1918                         activity_monitor.Soc_UseRlcBusy = input[2];
1919                         activity_monitor.Soc_MinActiveFreqType = input[3];
1920                         activity_monitor.Soc_MinActiveFreq = input[4];
1921                         activity_monitor.Soc_BoosterFreqType = input[5];
1922                         activity_monitor.Soc_BoosterFreq = input[6];
1923                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1924                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1925                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1926                         break;
1927                 case 2: /* Uclk */
1928                         activity_monitor.Mem_FPS = input[1];
1929                         activity_monitor.Mem_UseRlcBusy = input[2];
1930                         activity_monitor.Mem_MinActiveFreqType = input[3];
1931                         activity_monitor.Mem_MinActiveFreq = input[4];
1932                         activity_monitor.Mem_BoosterFreqType = input[5];
1933                         activity_monitor.Mem_BoosterFreq = input[6];
1934                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1935                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1936                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1937                         break;
1938                 case 3: /* Fclk */
1939                         activity_monitor.Fclk_FPS = input[1];
1940                         activity_monitor.Fclk_UseRlcBusy = input[2];
1941                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1942                         activity_monitor.Fclk_MinActiveFreq = input[4];
1943                         activity_monitor.Fclk_BoosterFreqType = input[5];
1944                         activity_monitor.Fclk_BoosterFreq = input[6];
1945                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1946                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1947                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1948                         break;
1949                 }
1950
1951                 ret = smu_update_table(smu,
1952                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1953                                        (void *)(&activity_monitor), true);
1954                 if (ret) {
1955                         pr_err("[%s] Failed to set activity monitor!", __func__);
1956                         return ret;
1957                 }
1958         }
1959
1960         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1961         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1962         if (workload_type < 0)
1963                 return -EINVAL;
1964         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1965                                     1 << workload_type);
1966
1967         return ret;
1968 }
1969
1970 static int
1971 vega20_get_profiling_clk_mask(struct smu_context *smu,
1972                               enum amd_dpm_forced_level level,
1973                               uint32_t *sclk_mask,
1974                               uint32_t *mclk_mask,
1975                               uint32_t *soc_mask)
1976 {
1977         struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1978         struct vega20_single_dpm_table *gfx_dpm_table;
1979         struct vega20_single_dpm_table *mem_dpm_table;
1980         struct vega20_single_dpm_table *soc_dpm_table;
1981
1982         if (!smu->smu_dpm.dpm_context)
1983                 return -EINVAL;
1984
1985         gfx_dpm_table = &dpm_table->gfx_table;
1986         mem_dpm_table = &dpm_table->mem_table;
1987         soc_dpm_table = &dpm_table->soc_table;
1988
1989         *sclk_mask = 0;
1990         *mclk_mask = 0;
1991         *soc_mask  = 0;
1992
1993         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1994             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
1995             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
1996                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
1997                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
1998                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
1999         }
2000
2001         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2002                 *sclk_mask = 0;
2003         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2004                 *mclk_mask = 0;
2005         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2006                 *sclk_mask = gfx_dpm_table->count - 1;
2007                 *mclk_mask = mem_dpm_table->count - 1;
2008                 *soc_mask  = soc_dpm_table->count - 1;
2009         }
2010
2011         return 0;
2012 }
2013
2014 static int
2015 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2016                                      struct vega20_single_dpm_table *dpm_table)
2017 {
2018         int ret = 0;
2019         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2020         if (!smu_dpm_ctx->dpm_context)
2021                 return -EINVAL;
2022
2023         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2024                 if (dpm_table->count <= 0) {
2025                         pr_err("[%s] Dpm table has no entry!", __func__);
2026                                 return -EINVAL;
2027                 }
2028
2029                 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2030                         pr_err("[%s] Dpm table has too many entries!", __func__);
2031                                 return -EINVAL;
2032                 }
2033
2034                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2035                 ret = smu_send_smc_msg_with_param(smu,
2036                                 SMU_MSG_SetHardMinByFreq,
2037                                 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2038                 if (ret) {
2039                         pr_err("[%s] Set hard min uclk failed!", __func__);
2040                                 return ret;
2041                 }
2042         }
2043
2044         return ret;
2045 }
2046
2047 static int vega20_pre_display_config_changed(struct smu_context *smu)
2048 {
2049         int ret = 0;
2050         struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2051
2052         if (!smu->smu_dpm.dpm_context)
2053                 return -EINVAL;
2054
2055         smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2056         ret = vega20_set_uclk_to_highest_dpm_level(smu,
2057                                                    &dpm_table->mem_table);
2058         if (ret)
2059                 pr_err("Failed to set uclk to highest dpm level");
2060         return ret;
2061 }
2062
2063 static int vega20_display_config_changed(struct smu_context *smu)
2064 {
2065         int ret = 0;
2066
2067         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2068             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2069                 ret = smu_write_watermarks_table(smu);
2070                 if (ret) {
2071                         pr_err("Failed to update WMTABLE!");
2072                         return ret;
2073                 }
2074                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2075         }
2076
2077         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2078             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2079             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2080                 smu_send_smc_msg_with_param(smu,
2081                                             SMU_MSG_NumOfDisplays,
2082                                             smu->display_config->num_display);
2083         }
2084
2085         return ret;
2086 }
2087
2088 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2089 {
2090         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2091         struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2092         struct vega20_single_dpm_table *dpm_table;
2093         bool vblank_too_short = false;
2094         bool disable_mclk_switching;
2095         uint32_t i, latency;
2096
2097         disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2098                                   !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2099         latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2100
2101         /* gfxclk */
2102         dpm_table = &(dpm_ctx->gfx_table);
2103         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2104         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2105         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2106         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2107
2108                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2109                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2110                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2111                 }
2112
2113                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2114                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2115                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2116                 }
2117
2118                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2119                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2120                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2121                 }
2122
2123         /* memclk */
2124         dpm_table = &(dpm_ctx->mem_table);
2125         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2126         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2127         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2128         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2129
2130                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2131                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2132                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2133                 }
2134
2135                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2136                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2137                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2138                 }
2139
2140                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2141                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2142                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2143                 }
2144
2145         /* honour DAL's UCLK Hardmin */
2146         if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2147                 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2148
2149         /* Hardmin is dependent on displayconfig */
2150         if (disable_mclk_switching) {
2151                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2152                 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2153                         if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2154                                 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2155                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2156                                         break;
2157                                 }
2158                         }
2159                 }
2160         }
2161
2162         if (smu->display_config->nb_pstate_switch_disable)
2163                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2164
2165         /* vclk */
2166         dpm_table = &(dpm_ctx->vclk_table);
2167         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2168         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2169         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2170         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2171
2172                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2173                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2174                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2175                 }
2176
2177                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2178                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2179                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2180                 }
2181
2182         /* dclk */
2183         dpm_table = &(dpm_ctx->dclk_table);
2184         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2185         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2186         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2187         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2188
2189                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2190                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2191                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2192                 }
2193
2194                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2195                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2196                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2197                 }
2198
2199         /* socclk */
2200         dpm_table = &(dpm_ctx->soc_table);
2201         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2202         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2203         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2204         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2205
2206                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2207                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2208                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2209                 }
2210
2211                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2212                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2213                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2214                 }
2215
2216         /* eclk */
2217         dpm_table = &(dpm_ctx->eclk_table);
2218         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2219         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2220         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2221         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2222
2223                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2224                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2225                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2226                 }
2227
2228                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2229                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2230                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2231                 }
2232         return 0;
2233 }
2234
2235 static int
2236 vega20_notify_smc_dispaly_config(struct smu_context *smu)
2237 {
2238         struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2239         struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2240         struct smu_clocks min_clocks = {0};
2241         struct pp_display_clock_request clock_req;
2242         int ret = 0;
2243
2244         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2245         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2246         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2247
2248         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2249                 clock_req.clock_type = amd_pp_dcef_clock;
2250                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2251                 if (!smu_v11_0_display_clock_voltage_request(smu, &clock_req)) {
2252                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2253                                 ret = smu_send_smc_msg_with_param(smu,
2254                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
2255                                                                   min_clocks.dcef_clock_in_sr/100);
2256                                 if (ret) {
2257                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
2258                                         return ret;
2259                                 }
2260                         }
2261                 } else {
2262                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2263                 }
2264         }
2265
2266         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2267                 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2268                 ret = smu_send_smc_msg_with_param(smu,
2269                                                   SMU_MSG_SetHardMinByFreq,
2270                                                   (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2271                 if (ret) {
2272                         pr_err("[%s] Set hard min uclk failed!", __func__);
2273                         return ret;
2274                 }
2275         }
2276
2277         return 0;
2278 }
2279
2280 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2281 {
2282         uint32_t i;
2283
2284         for (i = 0; i < table->count; i++) {
2285                 if (table->dpm_levels[i].enabled)
2286                         break;
2287         }
2288         if (i >= table->count) {
2289                 i = 0;
2290                 table->dpm_levels[i].enabled = true;
2291         }
2292
2293         return i;
2294 }
2295
2296 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2297 {
2298         int i = 0;
2299
2300         if (!table) {
2301                 pr_err("[%s] DPM Table does not exist!", __func__);
2302                 return 0;
2303         }
2304         if (table->count <= 0) {
2305                 pr_err("[%s] DPM Table has no entry!", __func__);
2306                 return 0;
2307         }
2308         if (table->count > MAX_REGULAR_DPM_NUMBER) {
2309                 pr_err("[%s] DPM Table has too many entries!", __func__);
2310                 return MAX_REGULAR_DPM_NUMBER - 1;
2311         }
2312
2313         for (i = table->count - 1; i >= 0; i--) {
2314                 if (table->dpm_levels[i].enabled)
2315                         break;
2316         }
2317         if (i < 0) {
2318                 i = 0;
2319                 table->dpm_levels[i].enabled = true;
2320         }
2321
2322         return i;
2323 }
2324
2325 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2326 {
2327         uint32_t soft_level;
2328         int ret = 0;
2329         struct vega20_dpm_table *dpm_table =
2330                 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2331
2332         if (highest)
2333                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2334         else
2335                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2336
2337         dpm_table->gfx_table.dpm_state.soft_min_level =
2338                 dpm_table->gfx_table.dpm_state.soft_max_level =
2339                 dpm_table->gfx_table.dpm_levels[soft_level].value;
2340
2341         if (highest)
2342                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2343         else
2344                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2345
2346         dpm_table->mem_table.dpm_state.soft_min_level =
2347                 dpm_table->mem_table.dpm_state.soft_max_level =
2348                 dpm_table->mem_table.dpm_levels[soft_level].value;
2349
2350         if (highest)
2351                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2352         else
2353                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2354
2355         dpm_table->soc_table.dpm_state.soft_min_level =
2356                 dpm_table->soc_table.dpm_state.soft_max_level =
2357                 dpm_table->soc_table.dpm_levels[soft_level].value;
2358
2359         ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2360         if (ret) {
2361                 pr_err("Failed to upload boot level to %s!\n",
2362                                 highest ? "highest" : "lowest");
2363                 return ret;
2364         }
2365
2366         ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2367         if (ret) {
2368                 pr_err("Failed to upload dpm max level to %s!\n!",
2369                                 highest ? "highest" : "lowest");
2370                 return ret;
2371         }
2372
2373         return ret;
2374 }
2375
2376 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2377 {
2378         uint32_t soft_min_level, soft_max_level;
2379         int ret = 0;
2380         struct vega20_dpm_table *dpm_table =
2381                 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2382
2383         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2384         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2385         dpm_table->gfx_table.dpm_state.soft_min_level =
2386                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2387         dpm_table->gfx_table.dpm_state.soft_max_level =
2388                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2389
2390         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2391         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2392         dpm_table->mem_table.dpm_state.soft_min_level =
2393                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2394         dpm_table->mem_table.dpm_state.soft_max_level =
2395                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2396
2397         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2398         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2399         dpm_table->soc_table.dpm_state.soft_min_level =
2400                 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2401         dpm_table->soc_table.dpm_state.soft_max_level =
2402                 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2403
2404         ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2405         if (ret) {
2406                 pr_err("Failed to upload DPM Bootup Levels!");
2407                 return ret;
2408         }
2409
2410         ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2411         if (ret) {
2412                 pr_err("Failed to upload DPM Max Levels!");
2413                 return ret;
2414         }
2415
2416         return ret;
2417 }
2418
2419 static int vega20_update_specified_od8_value(struct smu_context *smu,
2420                                              uint32_t index,
2421                                              uint32_t value)
2422 {
2423         struct smu_table_context *table_context = &smu->smu_table;
2424         OverDriveTable_t *od_table =
2425                 (OverDriveTable_t *)(table_context->overdrive_table);
2426         struct vega20_od8_settings *od8_settings =
2427                 (struct vega20_od8_settings *)smu->od_settings;
2428
2429         switch (index) {
2430         case OD8_SETTING_GFXCLK_FMIN:
2431                 od_table->GfxclkFmin = (uint16_t)value;
2432                 break;
2433
2434         case OD8_SETTING_GFXCLK_FMAX:
2435                 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2436                     value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2437                         return -EINVAL;
2438                 od_table->GfxclkFmax = (uint16_t)value;
2439                 break;
2440
2441         case OD8_SETTING_GFXCLK_FREQ1:
2442                 od_table->GfxclkFreq1 = (uint16_t)value;
2443                 break;
2444
2445         case OD8_SETTING_GFXCLK_VOLTAGE1:
2446                 od_table->GfxclkVolt1 = (uint16_t)value;
2447                 break;
2448
2449         case OD8_SETTING_GFXCLK_FREQ2:
2450                 od_table->GfxclkFreq2 = (uint16_t)value;
2451                 break;
2452
2453         case OD8_SETTING_GFXCLK_VOLTAGE2:
2454                 od_table->GfxclkVolt2 = (uint16_t)value;
2455                 break;
2456
2457         case OD8_SETTING_GFXCLK_FREQ3:
2458                 od_table->GfxclkFreq3 = (uint16_t)value;
2459                 break;
2460
2461         case OD8_SETTING_GFXCLK_VOLTAGE3:
2462                 od_table->GfxclkVolt3 = (uint16_t)value;
2463                 break;
2464
2465         case OD8_SETTING_UCLK_FMAX:
2466                 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2467                     value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2468                         return -EINVAL;
2469                 od_table->UclkFmax = (uint16_t)value;
2470                 break;
2471
2472         case OD8_SETTING_POWER_PERCENTAGE:
2473                 od_table->OverDrivePct = (int16_t)value;
2474                 break;
2475
2476         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2477                 od_table->FanMaximumRpm = (uint16_t)value;
2478                 break;
2479
2480         case OD8_SETTING_FAN_MIN_SPEED:
2481                 od_table->FanMinimumPwm = (uint16_t)value;
2482                 break;
2483
2484         case OD8_SETTING_FAN_TARGET_TEMP:
2485                 od_table->FanTargetTemperature = (uint16_t)value;
2486                 break;
2487
2488         case OD8_SETTING_OPERATING_TEMP_MAX:
2489                 od_table->MaxOpTemp = (uint16_t)value;
2490                 break;
2491         }
2492
2493         return 0;
2494 }
2495
2496 static int vega20_update_od8_settings(struct smu_context *smu,
2497                                       uint32_t index,
2498                                       uint32_t value)
2499 {
2500         struct smu_table_context *table_context = &smu->smu_table;
2501         int ret;
2502
2503         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2504                                table_context->overdrive_table, false);
2505         if (ret) {
2506                 pr_err("Failed to export over drive table!\n");
2507                 return ret;
2508         }
2509
2510         ret = vega20_update_specified_od8_value(smu, index, value);
2511         if (ret)
2512                 return ret;
2513
2514         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2515                                table_context->overdrive_table, true);
2516         if (ret) {
2517                 pr_err("Failed to import over drive table!\n");
2518                 return ret;
2519         }
2520
2521         return 0;
2522 }
2523
2524 static int vega20_set_od_percentage(struct smu_context *smu,
2525                                     enum smu_clk_type clk_type,
2526                                     uint32_t value)
2527 {
2528         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2529         struct vega20_dpm_table *dpm_table = NULL;
2530         struct vega20_dpm_table *golden_table = NULL;
2531         struct vega20_single_dpm_table *single_dpm_table;
2532         struct vega20_single_dpm_table *golden_dpm_table;
2533         uint32_t od_clk, index;
2534         int ret = 0;
2535         int feature_enabled;
2536         PPCLK_e clk_id;
2537
2538         dpm_table = smu_dpm->dpm_context;
2539         golden_table = smu_dpm->golden_dpm_context;
2540
2541         switch (clk_type) {
2542         case SMU_OD_SCLK:
2543                 single_dpm_table = &(dpm_table->gfx_table);
2544                 golden_dpm_table = &(golden_table->gfx_table);
2545                 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2546                 clk_id = PPCLK_GFXCLK;
2547                 index = OD8_SETTING_GFXCLK_FMAX;
2548                 break;
2549         case SMU_OD_MCLK:
2550                 single_dpm_table = &(dpm_table->mem_table);
2551                 golden_dpm_table = &(golden_table->mem_table);
2552                 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2553                 clk_id = PPCLK_UCLK;
2554                 index = OD8_SETTING_UCLK_FMAX;
2555                 break;
2556         default:
2557                 ret = -EINVAL;
2558                 break;
2559         }
2560
2561         if (ret)
2562                 goto set_od_failed;
2563
2564         od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2565         od_clk /= 100;
2566         od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2567
2568         ret = vega20_update_od8_settings(smu, index, od_clk);
2569         if (ret) {
2570                 pr_err("[Setoverdrive] failed to set od clk!\n");
2571                 goto set_od_failed;
2572         }
2573
2574         if (feature_enabled) {
2575                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2576                                                   clk_id);
2577                 if (ret) {
2578                         pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2579                         goto set_od_failed;
2580                 }
2581         } else {
2582                 single_dpm_table->count = 1;
2583                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2584         }
2585
2586         ret = smu_handle_task(smu, smu_dpm->dpm_level,
2587                               AMD_PP_TASK_READJUST_POWER_STATE,
2588                               false);
2589
2590 set_od_failed:
2591         return ret;
2592 }
2593
2594 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2595                                      enum PP_OD_DPM_TABLE_COMMAND type,
2596                                      long *input, uint32_t size)
2597 {
2598         struct smu_table_context *table_context = &smu->smu_table;
2599         OverDriveTable_t *od_table =
2600                 (OverDriveTable_t *)(table_context->overdrive_table);
2601         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2602         struct vega20_dpm_table *dpm_table = NULL;
2603         struct vega20_single_dpm_table *single_dpm_table;
2604         struct vega20_od8_settings *od8_settings =
2605                 (struct vega20_od8_settings *)smu->od_settings;
2606         struct pp_clock_levels_with_latency clocks;
2607         int32_t input_index, input_clk, input_vol, i;
2608         int od8_id;
2609         int ret = 0;
2610
2611         dpm_table = smu_dpm->dpm_context;
2612
2613         if (!input) {
2614                 pr_warn("NULL user input for clock and voltage\n");
2615                 return -EINVAL;
2616         }
2617
2618         switch (type) {
2619         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2620                 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2621                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2622                         pr_info("Sclk min/max frequency overdrive not supported\n");
2623                         return -EOPNOTSUPP;
2624                 }
2625
2626                 for (i = 0; i < size; i += 2) {
2627                         if (i + 2 > size) {
2628                                 pr_info("invalid number of input parameters %d\n", size);
2629                                 return -EINVAL;
2630                         }
2631
2632                         input_index = input[i];
2633                         input_clk = input[i + 1];
2634
2635                         if (input_index != 0 && input_index != 1) {
2636                                 pr_info("Invalid index %d\n", input_index);
2637                                 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2638                                 return -EINVAL;
2639                         }
2640
2641                         if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2642                             input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2643                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2644                                         input_clk,
2645                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2646                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2647                                 return -EINVAL;
2648                         }
2649
2650                         if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2651                                 od_table->GfxclkFmin = input_clk;
2652                                 od8_settings->od_gfxclk_update = true;
2653                         } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2654                                 od_table->GfxclkFmax = input_clk;
2655                                 od8_settings->od_gfxclk_update = true;
2656                         }
2657                 }
2658
2659                 break;
2660
2661         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2662                 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2663                         pr_info("Mclk max frequency overdrive not supported\n");
2664                         return -EOPNOTSUPP;
2665                 }
2666
2667                 single_dpm_table = &(dpm_table->mem_table);
2668                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2669                 if (ret) {
2670                         pr_err("Attempt to get memory clk levels Failed!");
2671                         return ret;
2672                 }
2673
2674                 for (i = 0; i < size; i += 2) {
2675                         if (i + 2 > size) {
2676                                 pr_info("invalid number of input parameters %d\n",
2677                                          size);
2678                                 return -EINVAL;
2679                         }
2680
2681                         input_index = input[i];
2682                         input_clk = input[i + 1];
2683
2684                         if (input_index != 1) {
2685                                 pr_info("Invalid index %d\n", input_index);
2686                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2687                                 return -EINVAL;
2688                         }
2689
2690                         if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2691                             input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2692                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2693                                         input_clk,
2694                                         clocks.data[0].clocks_in_khz / 1000,
2695                                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2696                                 return -EINVAL;
2697                         }
2698
2699                         if (input_index == 1 && od_table->UclkFmax != input_clk) {
2700                                 od8_settings->od_gfxclk_update = true;
2701                                 od_table->UclkFmax = input_clk;
2702                         }
2703                 }
2704
2705                 break;
2706
2707         case PP_OD_EDIT_VDDC_CURVE:
2708                 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2709                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2710                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2711                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2712                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2713                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2714                         pr_info("Voltage curve calibrate not supported\n");
2715                         return -EOPNOTSUPP;
2716                 }
2717
2718                 for (i = 0; i < size; i += 3) {
2719                         if (i + 3 > size) {
2720                                 pr_info("invalid number of input parameters %d\n",
2721                                         size);
2722                                 return -EINVAL;
2723                         }
2724
2725                         input_index = input[i];
2726                         input_clk = input[i + 1];
2727                         input_vol = input[i + 2];
2728
2729                         if (input_index > 2) {
2730                                 pr_info("Setting for point %d is not supported\n",
2731                                         input_index + 1);
2732                                 pr_info("Three supported points index by 0, 1, 2\n");
2733                                 return -EINVAL;
2734                         }
2735
2736                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2737                         if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2738                             input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2739                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2740                                         input_clk,
2741                                         od8_settings->od8_settings_array[od8_id].min_value,
2742                                         od8_settings->od8_settings_array[od8_id].max_value);
2743                                 return -EINVAL;
2744                         }
2745
2746                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2747                         if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2748                             input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2749                                 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2750                                         input_vol,
2751                                         od8_settings->od8_settings_array[od8_id].min_value,
2752                                         od8_settings->od8_settings_array[od8_id].max_value);
2753                                 return -EINVAL;
2754                         }
2755
2756                         switch (input_index) {
2757                         case 0:
2758                                 od_table->GfxclkFreq1 = input_clk;
2759                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2760                                 break;
2761                         case 1:
2762                                 od_table->GfxclkFreq2 = input_clk;
2763                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2764                                 break;
2765                         case 2:
2766                                 od_table->GfxclkFreq3 = input_clk;
2767                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2768                                 break;
2769                         }
2770                 }
2771
2772                 break;
2773
2774         case PP_OD_RESTORE_DEFAULT_TABLE:
2775                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
2776                 if (ret) {
2777                         pr_err("Failed to export over drive table!\n");
2778                         return ret;
2779                 }
2780
2781                 break;
2782
2783         case PP_OD_COMMIT_DPM_TABLE:
2784                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
2785                 if (ret) {
2786                         pr_err("Failed to import over drive table!\n");
2787                         return ret;
2788                 }
2789
2790                 /* retrieve updated gfxclk table */
2791                 if (od8_settings->od_gfxclk_update) {
2792                         od8_settings->od_gfxclk_update = false;
2793                         single_dpm_table = &(dpm_table->gfx_table);
2794
2795                         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2796                                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2797                                                                   PPCLK_GFXCLK);
2798                                 if (ret) {
2799                                         pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2800                                         return ret;
2801                                 }
2802                         } else {
2803                                 single_dpm_table->count = 1;
2804                                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2805                         }
2806                 }
2807
2808                 break;
2809
2810         default:
2811                 return -EINVAL;
2812         }
2813
2814         if (type == PP_OD_COMMIT_DPM_TABLE) {
2815                 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2816                                       AMD_PP_TASK_READJUST_POWER_STATE,
2817                                       false);
2818         }
2819
2820         return ret;
2821 }
2822
2823 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2824 {
2825         if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2826                 return 0;
2827
2828         if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2829                 return 0;
2830
2831         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2832 }
2833
2834 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2835 {
2836         if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2837                 return 0;
2838
2839         if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2840                 return 0;
2841
2842         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2843 }
2844
2845 static bool vega20_is_dpm_running(struct smu_context *smu)
2846 {
2847         int ret = 0;
2848         uint32_t feature_mask[2];
2849         unsigned long feature_enabled;
2850         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2851         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
2852                            ((uint64_t)feature_mask[1] << 32));
2853         return !!(feature_enabled & SMC_DPM_FEATURE);
2854 }
2855
2856 static int vega20_set_thermal_fan_table(struct smu_context *smu)
2857 {
2858         int ret;
2859         struct smu_table_context *table_context = &smu->smu_table;
2860         PPTable_t *pptable = table_context->driver_pptable;
2861
2862         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
2863                         (uint32_t)pptable->FanTargetTemperature);
2864
2865         return ret;
2866 }
2867
2868 static int vega20_get_fan_speed_rpm(struct smu_context *smu,
2869                                     uint32_t *speed)
2870 {
2871         int ret;
2872
2873         ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
2874
2875         if (ret) {
2876                 pr_err("Attempt to get current RPM from SMC Failed!\n");
2877                 return ret;
2878         }
2879
2880         smu_read_smc_arg(smu, speed);
2881
2882         return 0;
2883 }
2884
2885 static int vega20_get_fan_speed_percent(struct smu_context *smu,
2886                                         uint32_t *speed)
2887 {
2888         int ret = 0;
2889         uint32_t current_rpm = 0, percent = 0;
2890         PPTable_t *pptable = smu->smu_table.driver_pptable;
2891
2892         ret = vega20_get_fan_speed_rpm(smu, &current_rpm);
2893         if (ret)
2894                 return ret;
2895
2896         percent = current_rpm * 100 / pptable->FanMaximumRpm;
2897         *speed = percent > 100 ? 100 : percent;
2898
2899         return 0;
2900 }
2901
2902 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
2903 {
2904         uint32_t smu_version;
2905         int ret = 0;
2906         SmuMetrics_t metrics;
2907
2908         if (!value)
2909                 return -EINVAL;
2910
2911         ret = vega20_get_metrics_table(smu, &metrics);
2912         if (ret)
2913                 return ret;
2914
2915         ret = smu_get_smc_version(smu, NULL, &smu_version);
2916         if (ret)
2917                 return ret;
2918
2919         /* For the 40.46 release, they changed the value name */
2920         if (smu_version == 0x282e00)
2921                 *value = metrics.AverageSocketPower << 8;
2922         else
2923                 *value = metrics.CurrSocketPower << 8;
2924
2925         return 0;
2926 }
2927
2928 static int vega20_get_current_activity_percent(struct smu_context *smu,
2929                                                enum amd_pp_sensors sensor,
2930                                                uint32_t *value)
2931 {
2932         int ret = 0;
2933         SmuMetrics_t metrics;
2934
2935         if (!value)
2936                 return -EINVAL;
2937
2938         ret = vega20_get_metrics_table(smu, &metrics);
2939         if (ret)
2940                 return ret;
2941
2942         switch (sensor) {
2943         case AMDGPU_PP_SENSOR_GPU_LOAD:
2944                 *value = metrics.AverageGfxActivity;
2945                 break;
2946         case AMDGPU_PP_SENSOR_MEM_LOAD:
2947                 *value = metrics.AverageUclkActivity;
2948                 break;
2949         default:
2950                 pr_err("Invalid sensor for retrieving clock activity\n");
2951                 return -EINVAL;
2952         }
2953
2954         return 0;
2955 }
2956
2957 static int vega20_thermal_get_temperature(struct smu_context *smu,
2958                                              enum amd_pp_sensors sensor,
2959                                              uint32_t *value)
2960 {
2961         struct amdgpu_device *adev = smu->adev;
2962         SmuMetrics_t metrics;
2963         uint32_t temp = 0;
2964         int ret = 0;
2965
2966         if (!value)
2967                 return -EINVAL;
2968
2969         ret = vega20_get_metrics_table(smu, &metrics);
2970         if (ret)
2971                 return ret;
2972
2973         switch (sensor) {
2974         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2975                 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
2976                 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
2977                                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
2978
2979                 temp = temp & 0x1ff;
2980                 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2981
2982                 *value = temp;
2983                 break;
2984         case AMDGPU_PP_SENSOR_EDGE_TEMP:
2985                 *value = metrics.TemperatureEdge *
2986                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2987                 break;
2988         case AMDGPU_PP_SENSOR_MEM_TEMP:
2989                 *value = metrics.TemperatureHBM *
2990                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2991                 break;
2992         default:
2993                 pr_err("Invalid sensor for retrieving temp\n");
2994                 return -EINVAL;
2995         }
2996
2997         return 0;
2998 }
2999 static int vega20_read_sensor(struct smu_context *smu,
3000                                  enum amd_pp_sensors sensor,
3001                                  void *data, uint32_t *size)
3002 {
3003         int ret = 0;
3004         struct smu_table_context *table_context = &smu->smu_table;
3005         PPTable_t *pptable = table_context->driver_pptable;
3006
3007         if(!data || !size)
3008                 return -EINVAL;
3009
3010         mutex_lock(&smu->sensor_lock);
3011         switch (sensor) {
3012         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3013                 *(uint32_t *)data = pptable->FanMaximumRpm;
3014                 *size = 4;
3015                 break;
3016         case AMDGPU_PP_SENSOR_MEM_LOAD:
3017         case AMDGPU_PP_SENSOR_GPU_LOAD:
3018                 ret = vega20_get_current_activity_percent(smu,
3019                                                 sensor,
3020                                                 (uint32_t *)data);
3021                 *size = 4;
3022                 break;
3023         case AMDGPU_PP_SENSOR_GPU_POWER:
3024                 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3025                 *size = 4;
3026                 break;
3027         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3028         case AMDGPU_PP_SENSOR_EDGE_TEMP:
3029         case AMDGPU_PP_SENSOR_MEM_TEMP:
3030                 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3031                 *size = 4;
3032                 break;
3033         default:
3034                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
3035         }
3036         mutex_unlock(&smu->sensor_lock);
3037
3038         return ret;
3039 }
3040
3041 static int vega20_set_watermarks_table(struct smu_context *smu,
3042                                        void *watermarks, struct
3043                                        dm_pp_wm_sets_with_clock_ranges_soc15
3044                                        *clock_ranges)
3045 {
3046         int i;
3047         Watermarks_t *table = watermarks;
3048
3049         if (!table || !clock_ranges)
3050                 return -EINVAL;
3051
3052         if (clock_ranges->num_wm_dmif_sets > 4 ||
3053             clock_ranges->num_wm_mcif_sets > 4)
3054                 return -EINVAL;
3055
3056         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3057                 table->WatermarkRow[1][i].MinClock =
3058                         cpu_to_le16((uint16_t)
3059                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3060                         1000));
3061                 table->WatermarkRow[1][i].MaxClock =
3062                         cpu_to_le16((uint16_t)
3063                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3064                         1000));
3065                 table->WatermarkRow[1][i].MinUclk =
3066                         cpu_to_le16((uint16_t)
3067                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3068                         1000));
3069                 table->WatermarkRow[1][i].MaxUclk =
3070                         cpu_to_le16((uint16_t)
3071                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3072                         1000));
3073                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3074                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3075         }
3076
3077         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3078                 table->WatermarkRow[0][i].MinClock =
3079                         cpu_to_le16((uint16_t)
3080                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3081                         1000));
3082                 table->WatermarkRow[0][i].MaxClock =
3083                         cpu_to_le16((uint16_t)
3084                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3085                         1000));
3086                 table->WatermarkRow[0][i].MinUclk =
3087                         cpu_to_le16((uint16_t)
3088                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3089                         1000));
3090                 table->WatermarkRow[0][i].MaxUclk =
3091                         cpu_to_le16((uint16_t)
3092                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3093                         1000));
3094                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3095                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3096         }
3097
3098         return 0;
3099 }
3100
3101 static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3102                                                 struct smu_temperature_range *range)
3103 {
3104         struct smu_table_context *table_context = &smu->smu_table;
3105         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = table_context->power_play_table;
3106         PPTable_t *pptable = smu->smu_table.driver_pptable;
3107
3108         if (!range || !powerplay_table)
3109                 return -EINVAL;
3110
3111         range->max = powerplay_table->usSoftwareShutdownTemp *
3112                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3113         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
3114                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3115         range->hotspot_crit_max = pptable->ThotspotLimit *
3116                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3117         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
3118                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3119         range->mem_crit_max = pptable->ThbmLimit *
3120                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3121         range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM) *
3122                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3123
3124
3125         return 0;
3126 }
3127
3128 static int vega20_set_df_cstate(struct smu_context *smu,
3129                                 enum pp_df_cstate state)
3130 {
3131         uint32_t smu_version;
3132         int ret;
3133
3134         ret = smu_get_smc_version(smu, NULL, &smu_version);
3135         if (ret) {
3136                 pr_err("Failed to get smu version!\n");
3137                 return ret;
3138         }
3139
3140         /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
3141         if (smu_version < 0x283200) {
3142                 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
3143                 return -EINVAL;
3144         }
3145
3146         return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
3147 }
3148
3149 static int vega20_update_pcie_parameters(struct smu_context *smu,
3150                                      uint32_t pcie_gen_cap,
3151                                      uint32_t pcie_width_cap)
3152 {
3153         PPTable_t *pptable = smu->smu_table.driver_pptable;
3154         int ret, i;
3155         uint32_t smu_pcie_arg;
3156
3157         for (i = 0; i < NUM_LINK_LEVELS; i++) {
3158                 smu_pcie_arg = (i << 16) |
3159                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
3160                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
3161                                         pptable->PcieLaneCount[i] : pcie_width_cap);
3162                 ret = smu_send_smc_msg_with_param(smu,
3163                                           SMU_MSG_OverridePcieParameters,
3164                                           smu_pcie_arg);
3165         }
3166
3167         return ret;
3168 }
3169
3170
3171 static const struct pptable_funcs vega20_ppt_funcs = {
3172         .tables_init = vega20_tables_init,
3173         .alloc_dpm_context = vega20_allocate_dpm_context,
3174         .store_powerplay_table = vega20_store_powerplay_table,
3175         .check_powerplay_table = vega20_check_powerplay_table,
3176         .append_powerplay_table = vega20_append_powerplay_table,
3177         .get_smu_msg_index = vega20_get_smu_msg_index,
3178         .get_smu_clk_index = vega20_get_smu_clk_index,
3179         .get_smu_feature_index = vega20_get_smu_feature_index,
3180         .get_smu_table_index = vega20_get_smu_table_index,
3181         .get_smu_power_index = vega20_get_pwr_src_index,
3182         .get_workload_type = vega20_get_workload_type,
3183         .run_btc = vega20_run_btc_afll,
3184         .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3185         .get_current_power_state = vega20_get_current_power_state,
3186         .set_default_dpm_table = vega20_set_default_dpm_table,
3187         .set_power_state = NULL,
3188         .populate_umd_state_clk = vega20_populate_umd_state_clk,
3189         .print_clk_levels = vega20_print_clk_levels,
3190         .force_clk_levels = vega20_force_clk_levels,
3191         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3192         .get_od_percentage = vega20_get_od_percentage,
3193         .get_power_profile_mode = vega20_get_power_profile_mode,
3194         .set_power_profile_mode = vega20_set_power_profile_mode,
3195         .set_od_percentage = vega20_set_od_percentage,
3196         .set_default_od_settings = vega20_set_default_od_settings,
3197         .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3198         .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3199         .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3200         .read_sensor = vega20_read_sensor,
3201         .pre_display_config_changed = vega20_pre_display_config_changed,
3202         .display_config_changed = vega20_display_config_changed,
3203         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3204         .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
3205         .force_dpm_limit_value = vega20_force_dpm_limit_value,
3206         .unforce_dpm_levels = vega20_unforce_dpm_levels,
3207         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3208         .is_dpm_running = vega20_is_dpm_running,
3209         .set_thermal_fan_table = vega20_set_thermal_fan_table,
3210         .get_fan_speed_percent = vega20_get_fan_speed_percent,
3211         .get_fan_speed_rpm = vega20_get_fan_speed_rpm,
3212         .set_watermarks_table = vega20_set_watermarks_table,
3213         .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3214         .set_df_cstate = vega20_set_df_cstate,
3215         .update_pcie_parameters = vega20_update_pcie_parameters,
3216         .init_microcode = smu_v11_0_init_microcode,
3217         .load_microcode = smu_v11_0_load_microcode,
3218         .init_smc_tables = smu_v11_0_init_smc_tables,
3219         .fini_smc_tables = smu_v11_0_fini_smc_tables,
3220         .init_power = smu_v11_0_init_power,
3221         .fini_power = smu_v11_0_fini_power,
3222         .check_fw_status = smu_v11_0_check_fw_status,
3223         .setup_pptable = smu_v11_0_setup_pptable,
3224         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3225         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
3226         .check_pptable = smu_v11_0_check_pptable,
3227         .parse_pptable = smu_v11_0_parse_pptable,
3228         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
3229         .check_fw_version = smu_v11_0_check_fw_version,
3230         .write_pptable = smu_v11_0_write_pptable,
3231         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
3232         .set_tool_table_location = smu_v11_0_set_tool_table_location,
3233         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3234         .system_features_control = smu_v11_0_system_features_control,
3235         .send_smc_msg = smu_v11_0_send_msg,
3236         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
3237         .read_smc_arg = smu_v11_0_read_arg,
3238         .init_display_count = smu_v11_0_init_display_count,
3239         .set_allowed_mask = smu_v11_0_set_allowed_mask,
3240         .get_enabled_mask = smu_v11_0_get_enabled_mask,
3241         .notify_display_change = smu_v11_0_notify_display_change,
3242         .set_power_limit = smu_v11_0_set_power_limit,
3243         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
3244         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3245         .start_thermal_control = smu_v11_0_start_thermal_control,
3246         .stop_thermal_control = smu_v11_0_stop_thermal_control,
3247         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
3248         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3249         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3250         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3251         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
3252         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3253         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3254         .gfx_off_control = smu_v11_0_gfx_off_control,
3255         .register_irq_handler = smu_v11_0_register_irq_handler,
3256         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3257         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3258         .baco_is_support= smu_v11_0_baco_is_support,
3259         .baco_get_state = smu_v11_0_baco_get_state,
3260         .baco_set_state = smu_v11_0_baco_set_state,
3261         .baco_reset = smu_v11_0_baco_reset,
3262         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3263         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3264         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
3265 };
3266
3267 void vega20_set_ppt_funcs(struct smu_context *smu)
3268 {
3269         smu->ppt_funcs = &vega20_ppt_funcs;
3270 }