drivers/gpu/drm/amd/powerplay/vega20_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "vega20_ppt.h"
  36 #include "vega20_pptable.h"
  37 #include "vega20_ppsmc.h"
  38 #include "nbio/nbio_7_4_sh_mask.h"
  39 #include "asic_reg/thm/thm_11_0_2_offset.h"
  40 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  41
  42 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  43 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  44
  45 #define CTF_OFFSET_EDGE                 5
  46 #define CTF_OFFSET_HOTSPOT              5
  47 #define CTF_OFFSET_HBM                  5
  48
  49 #define MSG_MAP(msg) \
  50         [SMU_MSG_##msg] = PPSMC_MSG_##msg
  51
  52 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
  53                          FEATURE_DPM_GFXCLK_MASK | \
  54                          FEATURE_DPM_UCLK_MASK | \
  55                          FEATURE_DPM_SOCCLK_MASK | \
  56                          FEATURE_DPM_UVD_MASK | \
  57                          FEATURE_DPM_VCE_MASK | \
  58                          FEATURE_DPM_MP0CLK_MASK | \
  59                          FEATURE_DPM_LINK_MASK | \
  60                          FEATURE_DPM_DCEFCLK_MASK)
  61
  62 static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
  63         MSG_MAP(TestMessage),
  64         MSG_MAP(GetSmuVersion),
  65         MSG_MAP(GetDriverIfVersion),
  66         MSG_MAP(SetAllowedFeaturesMaskLow),
  67         MSG_MAP(SetAllowedFeaturesMaskHigh),
  68         MSG_MAP(EnableAllSmuFeatures),
  69         MSG_MAP(DisableAllSmuFeatures),
  70         MSG_MAP(EnableSmuFeaturesLow),
  71         MSG_MAP(EnableSmuFeaturesHigh),
  72         MSG_MAP(DisableSmuFeaturesLow),
  73         MSG_MAP(DisableSmuFeaturesHigh),
  74         MSG_MAP(GetEnabledSmuFeaturesLow),
  75         MSG_MAP(GetEnabledSmuFeaturesHigh),
  76         MSG_MAP(SetWorkloadMask),
  77         MSG_MAP(SetPptLimit),
  78         MSG_MAP(SetDriverDramAddrHigh),
  79         MSG_MAP(SetDriverDramAddrLow),
  80         MSG_MAP(SetToolsDramAddrHigh),
  81         MSG_MAP(SetToolsDramAddrLow),
  82         MSG_MAP(TransferTableSmu2Dram),
  83         MSG_MAP(TransferTableDram2Smu),
  84         MSG_MAP(UseDefaultPPTable),
  85         MSG_MAP(UseBackupPPTable),
  86         MSG_MAP(RunBtc),
  87         MSG_MAP(RequestI2CBus),
  88         MSG_MAP(ReleaseI2CBus),
  89         MSG_MAP(SetFloorSocVoltage),
  90         MSG_MAP(SoftReset),
  91         MSG_MAP(StartBacoMonitor),
  92         MSG_MAP(CancelBacoMonitor),
  93         MSG_MAP(EnterBaco),
  94         MSG_MAP(SetSoftMinByFreq),
  95         MSG_MAP(SetSoftMaxByFreq),
  96         MSG_MAP(SetHardMinByFreq),
  97         MSG_MAP(SetHardMaxByFreq),
  98         MSG_MAP(GetMinDpmFreq),
  99         MSG_MAP(GetMaxDpmFreq),
 100         MSG_MAP(GetDpmFreqByIndex),
 101         MSG_MAP(GetDpmClockFreq),
 102         MSG_MAP(GetSsVoltageByDpm),
 103         MSG_MAP(SetMemoryChannelConfig),
 104         MSG_MAP(SetGeminiMode),
 105         MSG_MAP(SetGeminiApertureHigh),
 106         MSG_MAP(SetGeminiApertureLow),
 107         MSG_MAP(SetMinLinkDpmByIndex),
 108         MSG_MAP(OverridePcieParameters),
 109         MSG_MAP(OverDriveSetPercentage),
 110         MSG_MAP(SetMinDeepSleepDcefclk),
 111         MSG_MAP(ReenableAcDcInterrupt),
 112         MSG_MAP(NotifyPowerSource),
 113         MSG_MAP(SetUclkFastSwitch),
 114         MSG_MAP(SetUclkDownHyst),
 115         MSG_MAP(GetCurrentRpm),
 116         MSG_MAP(SetVideoFps),
 117         MSG_MAP(SetTjMax),
 118         MSG_MAP(SetFanTemperatureTarget),
 119         MSG_MAP(PrepareMp1ForUnload),
 120         MSG_MAP(DramLogSetDramAddrHigh),
 121         MSG_MAP(DramLogSetDramAddrLow),
 122         MSG_MAP(DramLogSetDramSize),
 123         MSG_MAP(SetFanMaxRpm),
 124         MSG_MAP(SetFanMinPwm),
 125         MSG_MAP(ConfigureGfxDidt),
 126         MSG_MAP(NumOfDisplays),
 127         MSG_MAP(RemoveMargins),
 128         MSG_MAP(ReadSerialNumTop32),
 129         MSG_MAP(ReadSerialNumBottom32),
 130         MSG_MAP(SetSystemVirtualDramAddrHigh),
 131         MSG_MAP(SetSystemVirtualDramAddrLow),
 132         MSG_MAP(WaflTest),
 133         MSG_MAP(SetFclkGfxClkRatio),
 134         MSG_MAP(AllowGfxOff),
 135         MSG_MAP(DisallowGfxOff),
 136         MSG_MAP(GetPptLimit),
 137         MSG_MAP(GetDcModeMaxDpmFreq),
 138         MSG_MAP(GetDebugData),
 139         MSG_MAP(SetXgmiMode),
 140         MSG_MAP(RunAfllBtc),
 141         MSG_MAP(ExitBaco),
 142         MSG_MAP(PrepareMp1ForReset),
 143         MSG_MAP(PrepareMp1ForShutdown),
 144         MSG_MAP(SetMGpuFanBoostLimitRpm),
 145         MSG_MAP(GetAVFSVoltageByDpm),
 146 };
 147
 148 static int vega20_clk_map[SMU_CLK_COUNT] = {
 149         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 150         CLK_MAP(VCLK, PPCLK_VCLK),
 151         CLK_MAP(DCLK, PPCLK_DCLK),
 152         CLK_MAP(ECLK, PPCLK_ECLK),
 153         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 154         CLK_MAP(UCLK, PPCLK_UCLK),
 155         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 156         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 157         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 158         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 159         CLK_MAP(FCLK, PPCLK_FCLK),
 160 };
 161
 162 static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
 163         FEA_MAP(DPM_PREFETCHER),
 164         FEA_MAP(DPM_GFXCLK),
 165         FEA_MAP(DPM_UCLK),
 166         FEA_MAP(DPM_SOCCLK),
 167         FEA_MAP(DPM_UVD),
 168         FEA_MAP(DPM_VCE),
 169         FEA_MAP(ULV),
 170         FEA_MAP(DPM_MP0CLK),
 171         FEA_MAP(DPM_LINK),
 172         FEA_MAP(DPM_DCEFCLK),
 173         FEA_MAP(DS_GFXCLK),
 174         FEA_MAP(DS_SOCCLK),
 175         FEA_MAP(DS_LCLK),
 176         FEA_MAP(PPT),
 177         FEA_MAP(TDC),
 178         FEA_MAP(THERMAL),
 179         FEA_MAP(GFX_PER_CU_CG),
 180         FEA_MAP(RM),
 181         FEA_MAP(DS_DCEFCLK),
 182         FEA_MAP(ACDC),
 183         FEA_MAP(VR0HOT),
 184         FEA_MAP(VR1HOT),
 185         FEA_MAP(FW_CTF),
 186         FEA_MAP(LED_DISPLAY),
 187         FEA_MAP(FAN_CONTROL),
 188         FEA_MAP(GFX_EDC),
 189         FEA_MAP(GFXOFF),
 190         FEA_MAP(CG),
 191         FEA_MAP(DPM_FCLK),
 192         FEA_MAP(DS_FCLK),
 193         FEA_MAP(DS_MP1CLK),
 194         FEA_MAP(DS_MP0CLK),
 195         FEA_MAP(XGMI),
 196 };
 197
 198 static int vega20_table_map[SMU_TABLE_COUNT] = {
 199         TAB_MAP(PPTABLE),
 200         TAB_MAP(WATERMARKS),
 201         TAB_MAP(AVFS),
 202         TAB_MAP(AVFS_PSM_DEBUG),
 203         TAB_MAP(AVFS_FUSE_OVERRIDE),
 204         TAB_MAP(PMSTATUSLOG),
 205         TAB_MAP(SMU_METRICS),
 206         TAB_MAP(DRIVER_SMU_CONFIG),
 207         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 208         TAB_MAP(OVERDRIVE),
 209 };
 210
 211 static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 212         PWR_MAP(AC),
 213         PWR_MAP(DC),
 214 };
 215
 216 static int vega20_workload_map[] = {
 217         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_DEFAULT_BIT),
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 219         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 220         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 221         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 222         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 223         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 224 };
 225
 226 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
 227 {
 228         int val;
 229         if (index >= SMU_TABLE_COUNT)
 230                 return -EINVAL;
 231
 232         val = vega20_table_map[index];
 233         if (val >= TABLE_COUNT)
 234                 return -EINVAL;
 235
 236         return val;
 237 }
 238
 239 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 240 {
 241         int val;
 242         if (index >= SMU_POWER_SOURCE_COUNT)
 243                 return -EINVAL;
 244
 245         val = vega20_pwr_src_map[index];
 246         if (val >= POWER_SOURCE_COUNT)
 247                 return -EINVAL;
 248
 249         return val;
 250 }
 251
 252 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 253 {
 254         int val;
 255         if (index >= SMU_FEATURE_COUNT)
 256                 return -EINVAL;
 257
 258         val = vega20_feature_mask_map[index];
 259         if (val > 64)
 260                 return -EINVAL;
 261
 262         return val;
 263 }
 264
 265 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 266 {
 267         int val;
 268         if (index >= SMU_CLK_COUNT)
 269                 return -EINVAL;
 270
 271         val = vega20_clk_map[index];
 272         if (val >= PPCLK_COUNT)
 273                 return -EINVAL;
 274
 275         return val;
 276 }
 277
 278 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 279 {
 280         int val;
 281
 282         if (index >= SMU_MSG_MAX_COUNT)
 283                 return -EINVAL;
 284
 285         val = vega20_message_map[index];
 286         if (val > PPSMC_Message_Count)
 287                 return -EINVAL;
 288
 289         return val;
 290 }
 291
 292 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 293 {
 294         int val;
 295         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 296                 return -EINVAL;
 297
 298         val = vega20_workload_map[profile];
 299
 300         return val;
 301 }
 302
 303 static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
 304 {
 305         struct smu_table_context *smu_table = &smu->smu_table;
 306
 307         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 308                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 309         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 310                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 311         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 312                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 313         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 314                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 315         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 316                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 317         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 318                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 319                        AMDGPU_GEM_DOMAIN_VRAM);
 320
 321         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 322         if (!smu_table->metrics_table)
 323                 return -ENOMEM;
 324         smu_table->metrics_time = 0;
 325
 326         return 0;
 327 }
 328
 329 static int vega20_allocate_dpm_context(struct smu_context *smu)
 330 {
 331         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 332
 333         if (smu_dpm->dpm_context)
 334                 return -EINVAL;
 335
 336         smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
 337                                        GFP_KERNEL);
 338         if (!smu_dpm->dpm_context)
 339                 return -ENOMEM;
 340
 341         if (smu_dpm->golden_dpm_context)
 342                 return -EINVAL;
 343
 344         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
 345                                               GFP_KERNEL);
 346         if (!smu_dpm->golden_dpm_context)
 347                 return -ENOMEM;
 348
 349         smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
 350
 351         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 352                                        GFP_KERNEL);
 353         if (!smu_dpm->dpm_current_power_state)
 354                 return -ENOMEM;
 355
 356         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 357                                        GFP_KERNEL);
 358         if (!smu_dpm->dpm_request_power_state)
 359                 return -ENOMEM;
 360
 361         return 0;
 362 }
 363
 364 static int vega20_setup_od8_information(struct smu_context *smu)
 365 {
 366         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 367         struct smu_table_context *table_context = &smu->smu_table;
 368         struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
 369
 370         uint32_t od_feature_count, od_feature_array_size,
 371                  od_setting_count, od_setting_array_size;
 372
 373         if (!table_context->power_play_table)
 374                 return -EINVAL;
 375
 376         powerplay_table = table_context->power_play_table;
 377
 378         if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
 379                 /* Setup correct ODFeatureCount, and store ODFeatureArray from
 380                  * powerplay table to od_feature_capabilities */
 381                 od_feature_count =
 382                         (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
 383                          ATOM_VEGA20_ODFEATURE_COUNT) ?
 384                         ATOM_VEGA20_ODFEATURE_COUNT :
 385                         le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
 386
 387                 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
 388
 389                 if (od8_settings->od_feature_capabilities)
 390                         return -EINVAL;
 391
 392                 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
 393                                                                  od_feature_array_size,
 394                                                                  GFP_KERNEL);
 395                 if (!od8_settings->od_feature_capabilities)
 396                         return -ENOMEM;
 397
 398                 /* Setup correct ODSettingCount, and store ODSettingArray from
 399                  * powerplay table to od_settings_max and od_setting_min */
 400                 od_setting_count =
 401                         (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
 402                          ATOM_VEGA20_ODSETTING_COUNT) ?
 403                         ATOM_VEGA20_ODSETTING_COUNT :
 404                         le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
 405
 406                 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
 407
 408                 if (od8_settings->od_settings_max)
 409                         return -EINVAL;
 410
 411                 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
 412                                                          od_setting_array_size,
 413                                                          GFP_KERNEL);
 414
 415                 if (!od8_settings->od_settings_max) {
 416                         kfree(od8_settings->od_feature_capabilities);
 417                         od8_settings->od_feature_capabilities = NULL;
 418                         return -ENOMEM;
 419                 }
 420
 421                 if (od8_settings->od_settings_min)
 422                         return -EINVAL;
 423
 424                 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
 425                                                          od_setting_array_size,
 426                                                          GFP_KERNEL);
 427
 428                 if (!od8_settings->od_settings_min) {
 429                         kfree(od8_settings->od_feature_capabilities);
 430                         od8_settings->od_feature_capabilities = NULL;
 431                         kfree(od8_settings->od_settings_max);
 432                         od8_settings->od_settings_max = NULL;
 433                         return -ENOMEM;
 434                 }
 435         }
 436
 437         return 0;
 438 }
 439
 440 static int vega20_store_powerplay_table(struct smu_context *smu)
 441 {
 442         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 443         struct smu_table_context *table_context = &smu->smu_table;
 444
 445         if (!table_context->power_play_table)
 446                 return -EINVAL;
 447
 448         powerplay_table = table_context->power_play_table;
 449
 450         memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
 451                sizeof(PPTable_t));
 452
 453         table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
 454         table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
 455         table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
 456
 457         return 0;
 458 }
 459
 460 static int vega20_append_powerplay_table(struct smu_context *smu)
 461 {
 462         struct smu_table_context *table_context = &smu->smu_table;
 463         PPTable_t *smc_pptable = table_context->driver_pptable;
 464         struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
 465         int index, i, ret;
 466
 467         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 468                                            smc_dpm_info);
 469
 470         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 471                                       (uint8_t **)&smc_dpm_table);
 472         if (ret)
 473                 return ret;
 474
 475         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
 476         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
 477
 478         smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
 479         smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
 480         smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
 481         smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
 482
 483         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
 484         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
 485         smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
 486
 487         smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
 488         smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
 489         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
 490
 491         smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
 492         smc_pptable->SocOffset = smc_dpm_table->socoffset;
 493         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
 494
 495         smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
 496         smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
 497         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
 498
 499         smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
 500         smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
 501         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
 502
 503         smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
 504         smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
 505         smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
 506         smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
 507
 508         smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
 509         smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
 510         smc_pptable->Padding1 = smc_dpm_table->padding1;
 511         smc_pptable->Padding2 = smc_dpm_table->padding2;
 512
 513         smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
 514         smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
 515         smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
 516
 517         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
 518         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
 519         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
 520
 521         smc_pptable->UclkSpreadEnabled = 0;
 522         smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
 523         smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
 524
 525         smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
 526         smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
 527         smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
 528
 529         smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
 530         smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
 531         smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
 532
 533         for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
 534                 smc_pptable->I2cControllers[i].Enabled =
 535                         smc_dpm_table->i2ccontrollers[i].enabled;
 536                 smc_pptable->I2cControllers[i].SlaveAddress =
 537                         smc_dpm_table->i2ccontrollers[i].slaveaddress;
 538                 smc_pptable->I2cControllers[i].ControllerPort =
 539                         smc_dpm_table->i2ccontrollers[i].controllerport;
 540                 smc_pptable->I2cControllers[i].ThermalThrottler =
 541                         smc_dpm_table->i2ccontrollers[i].thermalthrottler;
 542                 smc_pptable->I2cControllers[i].I2cProtocol =
 543                         smc_dpm_table->i2ccontrollers[i].i2cprotocol;
 544                 smc_pptable->I2cControllers[i].I2cSpeed =
 545                         smc_dpm_table->i2ccontrollers[i].i2cspeed;
 546         }
 547
 548         return 0;
 549 }
 550
 551 static int vega20_check_powerplay_table(struct smu_context *smu)
 552 {
 553         ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
 554         struct smu_table_context *table_context = &smu->smu_table;
 555
 556         powerplay_table = table_context->power_play_table;
 557
 558         if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
 559                 pr_err("Unsupported PPTable format!");
 560                 return -EINVAL;
 561         }
 562
 563         if (!powerplay_table->sHeader.structuresize) {
 564                 pr_err("Invalid PowerPlay Table!");
 565                 return -EINVAL;
 566         }
 567
 568         return 0;
 569 }
 570
 571 static int vega20_run_btc_afll(struct smu_context *smu)
 572 {
 573         return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
 574 }
 575
 576 #define FEATURE_MASK(feature) (1ULL << feature)
 577 static int
 578 vega20_get_allowed_feature_mask(struct smu_context *smu,
 579                                   uint32_t *feature_mask, uint32_t num)
 580 {
 581         if (num > 2)
 582                 return -EINVAL;
 583
 584         memset(feature_mask, 0, sizeof(uint32_t) * num);
 585
 586         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 587                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 588                                 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 589                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 590                                 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
 591                                 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
 592                                 | FEATURE_MASK(FEATURE_ULV_BIT)
 593                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 594                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 595                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
 596                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 597                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 598                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 599                                 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
 600                                 | FEATURE_MASK(FEATURE_RM_BIT)
 601                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 602                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 603                                 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
 604                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 605                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 606                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 607                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 608                                 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
 609                                 | FEATURE_MASK(FEATURE_CG_BIT)
 610                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 611                                 | FEATURE_MASK(FEATURE_XGMI_BIT);
 612         return 0;
 613 }
 614
 615 static enum
 616 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
 617 {
 618         enum amd_pm_state_type pm_type;
 619         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 620
 621         if (!smu_dpm_ctx->dpm_context ||
 622             !smu_dpm_ctx->dpm_current_power_state)
 623                 return -EINVAL;
 624
 625         mutex_lock(&(smu->mutex));
 626         switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
 627         case SMU_STATE_UI_LABEL_BATTERY:
 628                 pm_type = POWER_STATE_TYPE_BATTERY;
 629                 break;
 630         case SMU_STATE_UI_LABEL_BALLANCED:
 631                 pm_type = POWER_STATE_TYPE_BALANCED;
 632                 break;
 633         case SMU_STATE_UI_LABEL_PERFORMANCE:
 634                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
 635                 break;
 636         default:
 637                 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
 638                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 639                 else
 640                         pm_type = POWER_STATE_TYPE_DEFAULT;
 641                 break;
 642         }
 643         mutex_unlock(&(smu->mutex));
 644
 645         return pm_type;
 646 }
 647
 648 static int
 649 vega20_set_single_dpm_table(struct smu_context *smu,
 650                             struct vega20_single_dpm_table *single_dpm_table,
 651                             PPCLK_e clk_id)
 652 {
 653         int ret = 0;
 654         uint32_t i, num_of_levels = 0, clk;
 655
 656         ret = smu_send_smc_msg_with_param(smu,
 657                         SMU_MSG_GetDpmFreqByIndex,
 658                         (clk_id << 16 | 0xFF));
 659         if (ret) {
 660                 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
 661                 return ret;
 662         }
 663
 664         smu_read_smc_arg(smu, &num_of_levels);
 665         if (!num_of_levels) {
 666                 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
 667                 return -EINVAL;
 668         }
 669
 670         single_dpm_table->count = num_of_levels;
 671
 672         for (i = 0; i < num_of_levels; i++) {
 673                 ret = smu_send_smc_msg_with_param(smu,
 674                                 SMU_MSG_GetDpmFreqByIndex,
 675                                 (clk_id << 16 | i));
 676                 if (ret) {
 677                         pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
 678                         return ret;
 679                 }
 680                 smu_read_smc_arg(smu, &clk);
 681                 if (!clk) {
 682                         pr_err("[GetDpmFreqByIndex] clk value is invalid!");
 683                         return -EINVAL;
 684                 }
 685                 single_dpm_table->dpm_levels[i].value = clk;
 686                 single_dpm_table->dpm_levels[i].enabled = true;
 687         }
 688         return 0;
 689 }
 690
 691 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
 692 {
 693         dpm_state->soft_min_level = 0x0;
 694         dpm_state->soft_max_level = 0xffff;
 695         dpm_state->hard_min_level = 0x0;
 696         dpm_state->hard_max_level = 0xffff;
 697 }
 698
 699 static int vega20_set_default_dpm_table(struct smu_context *smu)
 700 {
 701         int ret;
 702
 703         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 704         struct vega20_dpm_table *dpm_table = NULL;
 705         struct vega20_single_dpm_table *single_dpm_table;
 706
 707         dpm_table = smu_dpm->dpm_context;
 708
 709         /* socclk */
 710         single_dpm_table = &(dpm_table->soc_table);
 711
 712         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 713                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 714                                                   PPCLK_SOCCLK);
 715                 if (ret) {
 716                         pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
 717                         return ret;
 718                 }
 719         } else {
 720                 single_dpm_table->count = 1;
 721                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 722         }
 723         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 724
 725         /* gfxclk */
 726         single_dpm_table = &(dpm_table->gfx_table);
 727
 728         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 729                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 730                                                   PPCLK_GFXCLK);
 731                 if (ret) {
 732                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 733                         return ret;
 734                 }
 735         } else {
 736                 single_dpm_table->count = 1;
 737                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 738         }
 739         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 740
 741         /* memclk */
 742         single_dpm_table = &(dpm_table->mem_table);
 743
 744         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 745                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 746                                                   PPCLK_UCLK);
 747                 if (ret) {
 748                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 749                         return ret;
 750                 }
 751         } else {
 752                 single_dpm_table->count = 1;
 753                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 754         }
 755         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 756
 757         /* eclk */
 758         single_dpm_table = &(dpm_table->eclk_table);
 759
 760         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
 761                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
 762                 if (ret) {
 763                         pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
 764                         return ret;
 765                 }
 766         } else {
 767                 single_dpm_table->count = 1;
 768                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
 769         }
 770         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 771
 772         /* vclk */
 773         single_dpm_table = &(dpm_table->vclk_table);
 774
 775         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 776                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
 777                 if (ret) {
 778                         pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
 779                         return ret;
 780                 }
 781         } else {
 782                 single_dpm_table->count = 1;
 783                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 784         }
 785         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 786
 787         /* dclk */
 788         single_dpm_table = &(dpm_table->dclk_table);
 789
 790         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 791                 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
 792                 if (ret) {
 793                         pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
 794                         return ret;
 795                 }
 796         } else {
 797                 single_dpm_table->count = 1;
 798                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 799         }
 800         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 801
 802         /* dcefclk */
 803         single_dpm_table = &(dpm_table->dcef_table);
 804
 805         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 806                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 807                                                   PPCLK_DCEFCLK);
 808                 if (ret) {
 809                         pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
 810                         return ret;
 811                 }
 812         } else {
 813                 single_dpm_table->count = 1;
 814                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 815         }
 816         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 817
 818         /* pixclk */
 819         single_dpm_table = &(dpm_table->pixel_table);
 820
 821         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 822                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 823                                                   PPCLK_PIXCLK);
 824                 if (ret) {
 825                         pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
 826                         return ret;
 827                 }
 828         } else {
 829                 single_dpm_table->count = 0;
 830         }
 831         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 832
 833         /* dispclk */
 834         single_dpm_table = &(dpm_table->display_table);
 835
 836         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 837                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 838                                                   PPCLK_DISPCLK);
 839                 if (ret) {
 840                         pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
 841                         return ret;
 842                 }
 843         } else {
 844                 single_dpm_table->count = 0;
 845         }
 846         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 847
 848         /* phyclk */
 849         single_dpm_table = &(dpm_table->phy_table);
 850
 851         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 852                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 853                                                   PPCLK_PHYCLK);
 854                 if (ret) {
 855                         pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
 856                         return ret;
 857                 }
 858         } else {
 859                 single_dpm_table->count = 0;
 860         }
 861         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 862
 863         /* fclk */
 864         single_dpm_table = &(dpm_table->fclk_table);
 865
 866         if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
 867                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
 868                                                   PPCLK_FCLK);
 869                 if (ret) {
 870                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 871                         return ret;
 872                 }
 873         } else {
 874                 single_dpm_table->count = 0;
 875         }
 876         vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
 877
 878         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 879                sizeof(struct vega20_dpm_table));
 880
 881         return 0;
 882 }
 883
 884 static int vega20_populate_umd_state_clk(struct smu_context *smu)
 885 {
 886         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 887         struct vega20_dpm_table *dpm_table = NULL;
 888         struct vega20_single_dpm_table *gfx_table = NULL;
 889         struct vega20_single_dpm_table *mem_table = NULL;
 890
 891         dpm_table = smu_dpm->dpm_context;
 892         gfx_table = &(dpm_table->gfx_table);
 893         mem_table = &(dpm_table->mem_table);
 894
 895         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 896         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 897
 898         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
 899             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
 900                 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
 901                 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
 902         }
 903
 904         smu->pstate_sclk = smu->pstate_sclk * 100;
 905         smu->pstate_mclk = smu->pstate_mclk * 100;
 906
 907         return 0;
 908 }
 909
 910 static int vega20_get_clk_table(struct smu_context *smu,
 911                         struct pp_clock_levels_with_latency *clocks,
 912                         struct vega20_single_dpm_table *dpm_table)
 913 {
 914         int i, count;
 915
 916         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 917         clocks->num_levels = count;
 918
 919         for (i = 0; i < count; i++) {
 920                 clocks->data[i].clocks_in_khz =
 921                         dpm_table->dpm_levels[i].value * 1000;
 922                 clocks->data[i].latency_in_us = 0;
 923         }
 924
 925         return 0;
 926 }
 927
 928 static int vega20_print_clk_levels(struct smu_context *smu,
 929                         enum smu_clk_type type, char *buf)
 930 {
 931         int i, now, size = 0;
 932         int ret = 0;
 933         uint32_t gen_speed, lane_width;
 934         struct amdgpu_device *adev = smu->adev;
 935         struct pp_clock_levels_with_latency clocks;
 936         struct vega20_single_dpm_table *single_dpm_table;
 937         struct smu_table_context *table_context = &smu->smu_table;
 938         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 939         struct vega20_dpm_table *dpm_table = NULL;
 940         struct vega20_od8_settings *od8_settings =
 941                 (struct vega20_od8_settings *)smu->od_settings;
 942         OverDriveTable_t *od_table =
 943                 (OverDriveTable_t *)(table_context->overdrive_table);
 944         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 945
 946         dpm_table = smu_dpm->dpm_context;
 947
 948         switch (type) {
 949         case SMU_SCLK:
 950                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 951                 if (ret) {
 952                         pr_err("Attempt to get current gfx clk Failed!");
 953                         return ret;
 954                 }
 955
 956                 single_dpm_table = &(dpm_table->gfx_table);
 957                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 958                 if (ret) {
 959                         pr_err("Attempt to get gfx clk levels Failed!");
 960                         return ret;
 961                 }
 962
 963                 for (i = 0; i < clocks.num_levels; i++)
 964                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 965                                         clocks.data[i].clocks_in_khz / 1000,
 966                                         (clocks.data[i].clocks_in_khz == now * 10)
 967                                         ? "*" : "");
 968                 break;
 969
 970         case SMU_MCLK:
 971                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 972                 if (ret) {
 973                         pr_err("Attempt to get current mclk Failed!");
 974                         return ret;
 975                 }
 976
 977                 single_dpm_table = &(dpm_table->mem_table);
 978                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
 979                 if (ret) {
 980                         pr_err("Attempt to get memory clk levels Failed!");
 981                         return ret;
 982                 }
 983
 984                 for (i = 0; i < clocks.num_levels; i++)
 985                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 986                                 i, clocks.data[i].clocks_in_khz / 1000,
 987                                 (clocks.data[i].clocks_in_khz == now * 10)
 988                                 ? "*" : "");
 989                 break;
 990
 991         case SMU_SOCCLK:
 992                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 993                 if (ret) {
 994                         pr_err("Attempt to get current socclk Failed!");
 995                         return ret;
 996                 }
 997
 998                 single_dpm_table = &(dpm_table->soc_table);
 999                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1000                 if (ret) {
1001                         pr_err("Attempt to get socclk levels Failed!");
1002                         return ret;
1003                 }
1004
1005                 for (i = 0; i < clocks.num_levels; i++)
1006                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1007                                 i, clocks.data[i].clocks_in_khz / 1000,
1008                                 (clocks.data[i].clocks_in_khz == now * 10)
1009                                 ? "*" : "");
1010                 break;
1011
1012         case SMU_FCLK:
1013                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1014                 if (ret) {
1015                         pr_err("Attempt to get current fclk Failed!");
1016                         return ret;
1017                 }
1018
1019                 single_dpm_table = &(dpm_table->fclk_table);
1020                 for (i = 0; i < single_dpm_table->count; i++)
1021                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1022                                 i, single_dpm_table->dpm_levels[i].value,
1023                                 (single_dpm_table->dpm_levels[i].value == now / 100)
1024                                 ? "*" : "");
1025                 break;
1026
1027         case SMU_DCEFCLK:
1028                 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1029                 if (ret) {
1030                         pr_err("Attempt to get current dcefclk Failed!");
1031                         return ret;
1032                 }
1033
1034                 single_dpm_table = &(dpm_table->dcef_table);
1035                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1036                 if (ret) {
1037                         pr_err("Attempt to get dcefclk levels Failed!");
1038                         return ret;
1039                 }
1040
1041                 for (i = 0; i < clocks.num_levels; i++)
1042                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1043                                 i, clocks.data[i].clocks_in_khz / 1000,
1044                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1045                 break;
1046
1047         case SMU_PCIE:
1048                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1049                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1050                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1051                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1052                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1053                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1054                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1055                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1056                                         (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1057                                         (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1058                                         (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1059                                         (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1060                                         (pptable->PcieLaneCount[i] == 1) ? "x1" :
1061                                         (pptable->PcieLaneCount[i] == 2) ? "x2" :
1062                                         (pptable->PcieLaneCount[i] == 3) ? "x4" :
1063                                         (pptable->PcieLaneCount[i] == 4) ? "x8" :
1064                                         (pptable->PcieLaneCount[i] == 5) ? "x12" :
1065                                         (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1066                                         pptable->LclkFreq[i],
1067                                         (gen_speed == pptable->PcieGenSpeed[i]) &&
1068                                         (lane_width == pptable->PcieLaneCount[i]) ?
1069                                         "*" : "");
1070                 break;
1071
1072         case SMU_OD_SCLK:
1073                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1074                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1075                         size = sprintf(buf, "%s:\n", "OD_SCLK");
1076                         size += sprintf(buf + size, "0: %10uMhz\n",
1077                                         od_table->GfxclkFmin);
1078                         size += sprintf(buf + size, "1: %10uMhz\n",
1079                                         od_table->GfxclkFmax);
1080                 }
1081
1082                 break;
1083
1084         case SMU_OD_MCLK:
1085                 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1086                         size = sprintf(buf, "%s:\n", "OD_MCLK");
1087                         size += sprintf(buf + size, "1: %10uMhz\n",
1088                                          od_table->UclkFmax);
1089                 }
1090
1091                 break;
1092
1093         case SMU_OD_VDDC_CURVE:
1094                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1095                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1096                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1097                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1098                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1099                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1100                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1101                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1102                                         od_table->GfxclkFreq1,
1103                                         od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1104                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1105                                         od_table->GfxclkFreq2,
1106                                         od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1107                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1108                                         od_table->GfxclkFreq3,
1109                                         od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1110                 }
1111
1112                 break;
1113
1114         case SMU_OD_RANGE:
1115                 size = sprintf(buf, "%s:\n", "OD_RANGE");
1116
1117                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1118                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1119                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1120                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1121                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1122                 }
1123
1124                 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1125                         single_dpm_table = &(dpm_table->mem_table);
1126                         ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1127                         if (ret) {
1128                                 pr_err("Attempt to get memory clk levels Failed!");
1129                                 return ret;
1130                         }
1131
1132                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1133                                         clocks.data[0].clocks_in_khz / 1000,
1134                                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1135                 }
1136
1137                 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1138                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1139                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1140                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1141                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1142                     od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1143                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1144                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1145                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1146                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1147                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1148                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1149                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1150                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1151                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1152                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1153                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1154                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1155                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1156                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1157                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1158                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1159                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1160                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1161                 }
1162
1163                 break;
1164
1165         default:
1166                 break;
1167         }
1168         return size;
1169 }
1170
1171 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1172                                    uint32_t feature_mask)
1173 {
1174         struct vega20_dpm_table *dpm_table;
1175         struct vega20_single_dpm_table *single_dpm_table;
1176         uint32_t freq;
1177         int ret = 0;
1178
1179         dpm_table = smu->smu_dpm.dpm_context;
1180
1181         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1182             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1183                 single_dpm_table = &(dpm_table->gfx_table);
1184                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1185                         single_dpm_table->dpm_state.soft_min_level;
1186                 ret = smu_send_smc_msg_with_param(smu,
1187                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1188                         (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1189                 if (ret) {
1190                         pr_err("Failed to set soft %s gfxclk !\n",
1191                                                 max ? "max" : "min");
1192                         return ret;
1193                 }
1194         }
1195
1196         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1197             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1198                 single_dpm_table = &(dpm_table->mem_table);
1199                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1200                         single_dpm_table->dpm_state.soft_min_level;
1201                 ret = smu_send_smc_msg_with_param(smu,
1202                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1203                         (PPCLK_UCLK << 16) | (freq & 0xffff));
1204                 if (ret) {
1205                         pr_err("Failed to set soft %s memclk !\n",
1206                                                 max ? "max" : "min");
1207                         return ret;
1208                 }
1209         }
1210
1211         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1212             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1213                 single_dpm_table = &(dpm_table->soc_table);
1214                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1215                         single_dpm_table->dpm_state.soft_min_level;
1216                 ret = smu_send_smc_msg_with_param(smu,
1217                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1218                         (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1219                 if (ret) {
1220                         pr_err("Failed to set soft %s socclk !\n",
1221                                                 max ? "max" : "min");
1222                         return ret;
1223                 }
1224         }
1225
1226         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1227             (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1228                 single_dpm_table = &(dpm_table->fclk_table);
1229                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1230                         single_dpm_table->dpm_state.soft_min_level;
1231                 ret = smu_send_smc_msg_with_param(smu,
1232                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1233                         (PPCLK_FCLK << 16) | (freq & 0xffff));
1234                 if (ret) {
1235                         pr_err("Failed to set soft %s fclk !\n",
1236                                                 max ? "max" : "min");
1237                         return ret;
1238                 }
1239         }
1240
1241         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1242             (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1243                 single_dpm_table = &(dpm_table->dcef_table);
1244                 freq = single_dpm_table->dpm_state.hard_min_level;
1245                 if (!max) {
1246                         ret = smu_send_smc_msg_with_param(smu,
1247                                 SMU_MSG_SetHardMinByFreq,
1248                                 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1249                         if (ret) {
1250                                 pr_err("Failed to set hard min dcefclk !\n");
1251                                 return ret;
1252                         }
1253                 }
1254         }
1255
1256         return ret;
1257 }
1258
1259 static int vega20_force_clk_levels(struct smu_context *smu,
1260                         enum  smu_clk_type clk_type, uint32_t mask)
1261 {
1262         struct vega20_dpm_table *dpm_table;
1263         struct vega20_single_dpm_table *single_dpm_table;
1264         uint32_t soft_min_level, soft_max_level, hard_min_level;
1265         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1266         int ret = 0;
1267
1268         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1269                 pr_info("force clock level is for dpm manual mode only.\n");
1270                 return -EINVAL;
1271         }
1272
1273         mutex_lock(&(smu->mutex));
1274
1275         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1276         soft_max_level = mask ? (fls(mask) - 1) : 0;
1277
1278         dpm_table = smu->smu_dpm.dpm_context;
1279
1280         switch (clk_type) {
1281         case SMU_SCLK:
1282                 single_dpm_table = &(dpm_table->gfx_table);
1283
1284                 if (soft_max_level >= single_dpm_table->count) {
1285                         pr_err("Clock level specified %d is over max allowed %d\n",
1286                                         soft_max_level, single_dpm_table->count - 1);
1287                         ret = -EINVAL;
1288                         break;
1289                 }
1290
1291                 single_dpm_table->dpm_state.soft_min_level =
1292                         single_dpm_table->dpm_levels[soft_min_level].value;
1293                 single_dpm_table->dpm_state.soft_max_level =
1294                         single_dpm_table->dpm_levels[soft_max_level].value;
1295
1296                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1297                 if (ret) {
1298                         pr_err("Failed to upload boot level to lowest!\n");
1299                         break;
1300                 }
1301
1302                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1303                 if (ret)
1304                         pr_err("Failed to upload dpm max level to highest!\n");
1305
1306                 break;
1307
1308         case SMU_MCLK:
1309                 single_dpm_table = &(dpm_table->mem_table);
1310
1311                 if (soft_max_level >= single_dpm_table->count) {
1312                         pr_err("Clock level specified %d is over max allowed %d\n",
1313                                         soft_max_level, single_dpm_table->count - 1);
1314                         ret = -EINVAL;
1315                         break;
1316                 }
1317
1318                 single_dpm_table->dpm_state.soft_min_level =
1319                         single_dpm_table->dpm_levels[soft_min_level].value;
1320                 single_dpm_table->dpm_state.soft_max_level =
1321                         single_dpm_table->dpm_levels[soft_max_level].value;
1322
1323                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1324                 if (ret) {
1325                         pr_err("Failed to upload boot level to lowest!\n");
1326                         break;
1327                 }
1328
1329                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1330                 if (ret)
1331                         pr_err("Failed to upload dpm max level to highest!\n");
1332
1333                 break;
1334
1335         case SMU_SOCCLK:
1336                 single_dpm_table = &(dpm_table->soc_table);
1337
1338                 if (soft_max_level >= single_dpm_table->count) {
1339                         pr_err("Clock level specified %d is over max allowed %d\n",
1340                                         soft_max_level, single_dpm_table->count - 1);
1341                         ret = -EINVAL;
1342                         break;
1343                 }
1344
1345                 single_dpm_table->dpm_state.soft_min_level =
1346                         single_dpm_table->dpm_levels[soft_min_level].value;
1347                 single_dpm_table->dpm_state.soft_max_level =
1348                         single_dpm_table->dpm_levels[soft_max_level].value;
1349
1350                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1351                 if (ret) {
1352                         pr_err("Failed to upload boot level to lowest!\n");
1353                         break;
1354                 }
1355
1356                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1357                 if (ret)
1358                         pr_err("Failed to upload dpm max level to highest!\n");
1359
1360                 break;
1361
1362         case SMU_FCLK:
1363                 single_dpm_table = &(dpm_table->fclk_table);
1364
1365                 if (soft_max_level >= single_dpm_table->count) {
1366                         pr_err("Clock level specified %d is over max allowed %d\n",
1367                                         soft_max_level, single_dpm_table->count - 1);
1368                         ret = -EINVAL;
1369                         break;
1370                 }
1371
1372                 single_dpm_table->dpm_state.soft_min_level =
1373                         single_dpm_table->dpm_levels[soft_min_level].value;
1374                 single_dpm_table->dpm_state.soft_max_level =
1375                         single_dpm_table->dpm_levels[soft_max_level].value;
1376
1377                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1378                 if (ret) {
1379                         pr_err("Failed to upload boot level to lowest!\n");
1380                         break;
1381                 }
1382
1383                 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1384                 if (ret)
1385                         pr_err("Failed to upload dpm max level to highest!\n");
1386
1387                 break;
1388
1389         case SMU_DCEFCLK:
1390                 hard_min_level = soft_min_level;
1391                 single_dpm_table = &(dpm_table->dcef_table);
1392
1393                 if (hard_min_level >= single_dpm_table->count) {
1394                         pr_err("Clock level specified %d is over max allowed %d\n",
1395                                         hard_min_level, single_dpm_table->count - 1);
1396                         ret = -EINVAL;
1397                         break;
1398                 }
1399
1400                 single_dpm_table->dpm_state.hard_min_level =
1401                         single_dpm_table->dpm_levels[hard_min_level].value;
1402
1403                 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1404                 if (ret)
1405                         pr_err("Failed to upload boot level to lowest!\n");
1406
1407                 break;
1408
1409         case SMU_PCIE:
1410                 if (soft_min_level >= NUM_LINK_LEVELS ||
1411                     soft_max_level >= NUM_LINK_LEVELS) {
1412                         ret = -EINVAL;
1413                         break;
1414                 }
1415
1416                 ret = smu_send_smc_msg_with_param(smu,
1417                                 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1418                 if (ret)
1419                         pr_err("Failed to set min link dpm level!\n");
1420
1421                 break;
1422
1423         default:
1424                 break;
1425         }
1426
1427         mutex_unlock(&(smu->mutex));
1428         return ret;
1429 }
1430
1431 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1432                                                  enum smu_clk_type clk_type,
1433                                                  struct pp_clock_levels_with_latency *clocks)
1434 {
1435         int ret;
1436         struct vega20_single_dpm_table *single_dpm_table;
1437         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1438         struct vega20_dpm_table *dpm_table = NULL;
1439
1440         dpm_table = smu_dpm->dpm_context;
1441
1442         mutex_lock(&smu->mutex);
1443
1444         switch (clk_type) {
1445         case SMU_GFXCLK:
1446                 single_dpm_table = &(dpm_table->gfx_table);
1447                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1448                 break;
1449         case SMU_MCLK:
1450                 single_dpm_table = &(dpm_table->mem_table);
1451                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1452                 break;
1453         case SMU_DCEFCLK:
1454                 single_dpm_table = &(dpm_table->dcef_table);
1455                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1456                 break;
1457         case SMU_SOCCLK:
1458                 single_dpm_table = &(dpm_table->soc_table);
1459                 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1460                 break;
1461         default:
1462                 ret = -EINVAL;
1463         }
1464
1465         mutex_unlock(&smu->mutex);
1466         return ret;
1467 }
1468
1469 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1470                                                      uint32_t *voltage,
1471                                                      uint32_t freq)
1472 {
1473         int ret;
1474
1475         ret = smu_send_smc_msg_with_param(smu,
1476                         SMU_MSG_GetAVFSVoltageByDpm,
1477                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1478         if (ret) {
1479                 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1480                 return ret;
1481         }
1482
1483         smu_read_smc_arg(smu, voltage);
1484         *voltage = *voltage / VOLTAGE_SCALE;
1485
1486         return 0;
1487 }
1488
1489 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1490 {
1491         struct smu_table_context *table_context = &smu->smu_table;
1492         OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1493         struct vega20_od8_settings *od8_settings = NULL;
1494         PPTable_t *smc_pptable = table_context->driver_pptable;
1495         int i, ret;
1496
1497         if (smu->od_settings)
1498                 return -EINVAL;
1499
1500         od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1501
1502         if (!od8_settings)
1503                 return -ENOMEM;
1504
1505         smu->od_settings = (void *)od8_settings;
1506
1507         ret = vega20_setup_od8_information(smu);
1508         if (ret) {
1509                 pr_err("Retrieve board OD limits failed!\n");
1510                 return ret;
1511         }
1512
1513         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1514                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1515                     od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1516                     od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1517                     (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1518                      od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1519                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1520                                 OD8_GFXCLK_LIMITS;
1521                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1522                                 OD8_GFXCLK_LIMITS;
1523                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1524                                 od_table->GfxclkFmin;
1525                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1526                                 od_table->GfxclkFmax;
1527                 }
1528
1529                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1530                     (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1531                      smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1532                     (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1533                      smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1534                     (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1535                      od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1536                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1537                                 OD8_GFXCLK_CURVE;
1538                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1539                                 OD8_GFXCLK_CURVE;
1540                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1541                                 OD8_GFXCLK_CURVE;
1542                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1543                                 OD8_GFXCLK_CURVE;
1544                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1545                                 OD8_GFXCLK_CURVE;
1546                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1547                                 OD8_GFXCLK_CURVE;
1548
1549                         od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1550                         od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1551                         od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1552                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1553                                 od_table->GfxclkFreq1;
1554                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1555                                 od_table->GfxclkFreq2;
1556                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1557                                 od_table->GfxclkFreq3;
1558
1559                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1560                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1561                                 od_table->GfxclkFreq1);
1562                         if (ret)
1563                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1564                         od_table->GfxclkVolt1 =
1565                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1566                                 * VOLTAGE_SCALE;
1567                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1568                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1569                                 od_table->GfxclkFreq2);
1570                         if (ret)
1571                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1572                         od_table->GfxclkVolt2 =
1573                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1574                                 * VOLTAGE_SCALE;
1575                         ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1576                                 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1577                                 od_table->GfxclkFreq3);
1578                         if (ret)
1579                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1580                         od_table->GfxclkVolt3 =
1581                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1582                                 * VOLTAGE_SCALE;
1583                 }
1584         }
1585
1586         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1587                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1588                     od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1589                     od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1590                     (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1591                      od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1592                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1593                                 OD8_UCLK_MAX;
1594                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1595                                 od_table->UclkFmax;
1596                 }
1597         }
1598
1599         if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1600             od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1601             od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1602             od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1603             od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1604                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1605                         OD8_POWER_LIMIT;
1606                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1607                         od_table->OverDrivePct;
1608         }
1609
1610         if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1611                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1612                     od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1613                     od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1614                     (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1615                      od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1616                         od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1617                                 OD8_ACOUSTIC_LIMIT_SCLK;
1618                         od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1619                                 od_table->FanMaximumRpm;
1620                 }
1621
1622                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1623                     od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1624                     od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1625                     (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1626                      od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1627                         od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1628                                 OD8_FAN_SPEED_MIN;
1629                         od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1630                                 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1631                 }
1632         }
1633
1634         if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1635                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1636                     od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1637                     od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1638                     (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1639                      od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1640                         od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1641                                 OD8_TEMPERATURE_FAN;
1642                         od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1643                                 od_table->FanTargetTemperature;
1644                 }
1645
1646                 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1647                     od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1648                     od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1649                     (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1650                      od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1651                         od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1652                                 OD8_TEMPERATURE_SYSTEM;
1653                         od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1654                                 od_table->MaxOpTemp;
1655                 }
1656         }
1657
1658         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1659                 if (od8_settings->od8_settings_array[i].feature_id) {
1660                         od8_settings->od8_settings_array[i].min_value =
1661                                 od8_settings->od_settings_min[i];
1662                         od8_settings->od8_settings_array[i].max_value =
1663                                 od8_settings->od_settings_max[i];
1664                         od8_settings->od8_settings_array[i].current_value =
1665                                 od8_settings->od8_settings_array[i].default_value;
1666                 } else {
1667                         od8_settings->od8_settings_array[i].min_value = 0;
1668                         od8_settings->od8_settings_array[i].max_value = 0;
1669                         od8_settings->od8_settings_array[i].current_value = 0;
1670                 }
1671         }
1672
1673         return 0;
1674 }
1675
1676 static int vega20_get_metrics_table(struct smu_context *smu,
1677                                     SmuMetrics_t *metrics_table)
1678 {
1679         struct smu_table_context *smu_table= &smu->smu_table;
1680         int ret = 0;
1681
1682         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1683                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
1684                                 (void *)smu_table->metrics_table, false);
1685                 if (ret) {
1686                         pr_info("Failed to export SMU metrics table!\n");
1687                         return ret;
1688                 }
1689                 smu_table->metrics_time = jiffies;
1690         }
1691
1692         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1693
1694         return ret;
1695 }
1696
1697 static int vega20_set_default_od_settings(struct smu_context *smu,
1698                                           bool initialize)
1699 {
1700         struct smu_table_context *table_context = &smu->smu_table;
1701         int ret;
1702
1703         if (initialize) {
1704                 if (table_context->overdrive_table)
1705                         return -EINVAL;
1706
1707                 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1708
1709                 if (!table_context->overdrive_table)
1710                         return -ENOMEM;
1711
1712                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1713                                        table_context->overdrive_table, false);
1714                 if (ret) {
1715                         pr_err("Failed to export over drive table!\n");
1716                         return ret;
1717                 }
1718
1719                 ret = vega20_set_default_od8_setttings(smu);
1720                 if (ret)
1721                         return ret;
1722         }
1723
1724         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
1725                                table_context->overdrive_table, true);
1726         if (ret) {
1727                 pr_err("Failed to import over drive table!\n");
1728                 return ret;
1729         }
1730
1731         return 0;
1732 }
1733
1734 static int vega20_get_od_percentage(struct smu_context *smu,
1735                                     enum smu_clk_type clk_type)
1736 {
1737         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1738         struct vega20_dpm_table *dpm_table = NULL;
1739         struct vega20_dpm_table *golden_table = NULL;
1740         struct vega20_single_dpm_table *single_dpm_table;
1741         struct vega20_single_dpm_table *golden_dpm_table;
1742         int value, golden_value;
1743
1744         dpm_table = smu_dpm->dpm_context;
1745         golden_table = smu_dpm->golden_dpm_context;
1746
1747         switch (clk_type) {
1748         case SMU_OD_SCLK:
1749                 single_dpm_table = &(dpm_table->gfx_table);
1750                 golden_dpm_table = &(golden_table->gfx_table);
1751                 break;
1752         case SMU_OD_MCLK:
1753                 single_dpm_table = &(dpm_table->mem_table);
1754                 golden_dpm_table = &(golden_table->mem_table);
1755                 break;
1756         default:
1757                 return -EINVAL;
1758                 break;
1759         }
1760
1761         value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1762         golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1763
1764         value -= golden_value;
1765         value = DIV_ROUND_UP(value * 100, golden_value);
1766
1767         return value;
1768 }
1769
1770 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1771 {
1772         DpmActivityMonitorCoeffInt_t activity_monitor;
1773         uint32_t i, size = 0;
1774         uint16_t workload_type = 0;
1775         static const char *profile_name[] = {
1776                                         "BOOTUP_DEFAULT",
1777                                         "3D_FULL_SCREEN",
1778                                         "POWER_SAVING",
1779                                         "VIDEO",
1780                                         "VR",
1781                                         "COMPUTE",
1782                                         "CUSTOM"};
1783         static const char *title[] = {
1784                         "PROFILE_INDEX(NAME)",
1785                         "CLOCK_TYPE(NAME)",
1786                         "FPS",
1787                         "UseRlcBusy",
1788                         "MinActiveFreqType",
1789                         "MinActiveFreq",
1790                         "BoosterFreqType",
1791                         "BoosterFreq",
1792                         "PD_Data_limit_c",
1793                         "PD_Data_error_coeff",
1794                         "PD_Data_error_rate_coeff"};
1795         int result = 0;
1796
1797         if (!smu->pm_enabled || !buf)
1798                 return -EINVAL;
1799
1800         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1801                         title[0], title[1], title[2], title[3], title[4], title[5],
1802                         title[6], title[7], title[8], title[9], title[10]);
1803
1804         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1805                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1806                 workload_type = smu_workload_get_type(smu, i);
1807                 result = smu_update_table(smu,
1808                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
1809                                           (void *)(&activity_monitor), false);
1810                 if (result) {
1811                         pr_err("[%s] Failed to get activity monitor!", __func__);
1812                         return result;
1813                 }
1814
1815                 size += sprintf(buf + size, "%2d %14s%s:\n",
1816                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1817
1818                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1819                         " ",
1820                         0,
1821                         "GFXCLK",
1822                         activity_monitor.Gfx_FPS,
1823                         activity_monitor.Gfx_UseRlcBusy,
1824                         activity_monitor.Gfx_MinActiveFreqType,
1825                         activity_monitor.Gfx_MinActiveFreq,
1826                         activity_monitor.Gfx_BoosterFreqType,
1827                         activity_monitor.Gfx_BoosterFreq,
1828                         activity_monitor.Gfx_PD_Data_limit_c,
1829                         activity_monitor.Gfx_PD_Data_error_coeff,
1830                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1831
1832                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1833                         " ",
1834                         1,
1835                         "SOCCLK",
1836                         activity_monitor.Soc_FPS,
1837                         activity_monitor.Soc_UseRlcBusy,
1838                         activity_monitor.Soc_MinActiveFreqType,
1839                         activity_monitor.Soc_MinActiveFreq,
1840                         activity_monitor.Soc_BoosterFreqType,
1841                         activity_monitor.Soc_BoosterFreq,
1842                         activity_monitor.Soc_PD_Data_limit_c,
1843                         activity_monitor.Soc_PD_Data_error_coeff,
1844                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1845
1846                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1847                         " ",
1848                         2,
1849                         "UCLK",
1850                         activity_monitor.Mem_FPS,
1851                         activity_monitor.Mem_UseRlcBusy,
1852                         activity_monitor.Mem_MinActiveFreqType,
1853                         activity_monitor.Mem_MinActiveFreq,
1854                         activity_monitor.Mem_BoosterFreqType,
1855                         activity_monitor.Mem_BoosterFreq,
1856                         activity_monitor.Mem_PD_Data_limit_c,
1857                         activity_monitor.Mem_PD_Data_error_coeff,
1858                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1859
1860                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1861                         " ",
1862                         3,
1863                         "FCLK",
1864                         activity_monitor.Fclk_FPS,
1865                         activity_monitor.Fclk_UseRlcBusy,
1866                         activity_monitor.Fclk_MinActiveFreqType,
1867                         activity_monitor.Fclk_MinActiveFreq,
1868                         activity_monitor.Fclk_BoosterFreqType,
1869                         activity_monitor.Fclk_BoosterFreq,
1870                         activity_monitor.Fclk_PD_Data_limit_c,
1871                         activity_monitor.Fclk_PD_Data_error_coeff,
1872                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1873         }
1874
1875         return size;
1876 }
1877
1878 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1879 {
1880         DpmActivityMonitorCoeffInt_t activity_monitor;
1881         int workload_type = 0, ret = 0;
1882
1883         smu->power_profile_mode = input[size];
1884
1885         if (!smu->pm_enabled)
1886                 return ret;
1887         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1888                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1889                 return -EINVAL;
1890         }
1891
1892         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1893                 ret = smu_update_table(smu,
1894                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
1895                                        (void *)(&activity_monitor), false);
1896                 if (ret) {
1897                         pr_err("[%s] Failed to get activity monitor!", __func__);
1898                         return ret;
1899                 }
1900
1901                 switch (input[0]) {
1902                 case 0: /* Gfxclk */
1903                         activity_monitor.Gfx_FPS = input[1];
1904                         activity_monitor.Gfx_UseRlcBusy = input[2];
1905                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1906                         activity_monitor.Gfx_MinActiveFreq = input[4];
1907                         activity_monitor.Gfx_BoosterFreqType = input[5];
1908                         activity_monitor.Gfx_BoosterFreq = input[6];
1909                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1910                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1911                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1912                         break;
1913                 case 1: /* Socclk */
1914                         activity_monitor.Soc_FPS = input[1];
1915                         activity_monitor.Soc_UseRlcBusy = input[2];
1916                         activity_monitor.Soc_MinActiveFreqType = input[3];
1917                         activity_monitor.Soc_MinActiveFreq = input[4];
1918                         activity_monitor.Soc_BoosterFreqType = input[5];
1919                         activity_monitor.Soc_BoosterFreq = input[6];
1920                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1921                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1922                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1923                         break;
1924                 case 2: /* Uclk */
1925                         activity_monitor.Mem_FPS = input[1];
1926                         activity_monitor.Mem_UseRlcBusy = input[2];
1927                         activity_monitor.Mem_MinActiveFreqType = input[3];
1928                         activity_monitor.Mem_MinActiveFreq = input[4];
1929                         activity_monitor.Mem_BoosterFreqType = input[5];
1930                         activity_monitor.Mem_BoosterFreq = input[6];
1931                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1932                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1933                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1934                         break;
1935                 case 3: /* Fclk */
1936                         activity_monitor.Fclk_FPS = input[1];
1937                         activity_monitor.Fclk_UseRlcBusy = input[2];
1938                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1939                         activity_monitor.Fclk_MinActiveFreq = input[4];
1940                         activity_monitor.Fclk_BoosterFreqType = input[5];
1941                         activity_monitor.Fclk_BoosterFreq = input[6];
1942                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1943                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1944                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1945                         break;
1946                 }
1947
1948                 ret = smu_update_table(smu,
1949                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
1950                                        (void *)(&activity_monitor), true);
1951                 if (ret) {
1952                         pr_err("[%s] Failed to set activity monitor!", __func__);
1953                         return ret;
1954                 }
1955         }
1956
1957         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1958         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1959         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1960                                     1 << workload_type);
1961
1962         return ret;
1963 }
1964
1965 static int
1966 vega20_get_profiling_clk_mask(struct smu_context *smu,
1967                               enum amd_dpm_forced_level level,
1968                               uint32_t *sclk_mask,
1969                               uint32_t *mclk_mask,
1970                               uint32_t *soc_mask)
1971 {
1972         struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1973         struct vega20_single_dpm_table *gfx_dpm_table;
1974         struct vega20_single_dpm_table *mem_dpm_table;
1975         struct vega20_single_dpm_table *soc_dpm_table;
1976
1977         if (!smu->smu_dpm.dpm_context)
1978                 return -EINVAL;
1979
1980         gfx_dpm_table = &dpm_table->gfx_table;
1981         mem_dpm_table = &dpm_table->mem_table;
1982         soc_dpm_table = &dpm_table->soc_table;
1983
1984         *sclk_mask = 0;
1985         *mclk_mask = 0;
1986         *soc_mask  = 0;
1987
1988         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1989             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
1990             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
1991                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
1992                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
1993                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
1994         }
1995
1996         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1997                 *sclk_mask = 0;
1998         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1999                 *mclk_mask = 0;
2000         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2001                 *sclk_mask = gfx_dpm_table->count - 1;
2002                 *mclk_mask = mem_dpm_table->count - 1;
2003                 *soc_mask  = soc_dpm_table->count - 1;
2004         }
2005
2006         return 0;
2007 }
2008
2009 static int
2010 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2011                                      struct vega20_single_dpm_table *dpm_table)
2012 {
2013         int ret = 0;
2014         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2015         if (!smu_dpm_ctx->dpm_context)
2016                 return -EINVAL;
2017
2018         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2019                 if (dpm_table->count <= 0) {
2020                         pr_err("[%s] Dpm table has no entry!", __func__);
2021                                 return -EINVAL;
2022                 }
2023
2024                 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2025                         pr_err("[%s] Dpm table has too many entries!", __func__);
2026                                 return -EINVAL;
2027                 }
2028
2029                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2030                 ret = smu_send_smc_msg_with_param(smu,
2031                                 SMU_MSG_SetHardMinByFreq,
2032                                 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2033                 if (ret) {
2034                         pr_err("[%s] Set hard min uclk failed!", __func__);
2035                                 return ret;
2036                 }
2037         }
2038
2039         return ret;
2040 }
2041
2042 static int vega20_pre_display_config_changed(struct smu_context *smu)
2043 {
2044         int ret = 0;
2045         struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2046
2047         if (!smu->smu_dpm.dpm_context)
2048                 return -EINVAL;
2049
2050         smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2051         ret = vega20_set_uclk_to_highest_dpm_level(smu,
2052                                                    &dpm_table->mem_table);
2053         if (ret)
2054                 pr_err("Failed to set uclk to highest dpm level");
2055         return ret;
2056 }
2057
2058 static int vega20_display_config_changed(struct smu_context *smu)
2059 {
2060         int ret = 0;
2061
2062         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2063             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2064                 ret = smu_write_watermarks_table(smu);
2065                 if (ret) {
2066                         pr_err("Failed to update WMTABLE!");
2067                         return ret;
2068                 }
2069                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2070         }
2071
2072         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2073             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2074             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2075                 smu_send_smc_msg_with_param(smu,
2076                                             SMU_MSG_NumOfDisplays,
2077                                             smu->display_config->num_display);
2078         }
2079
2080         return ret;
2081 }
2082
2083 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2084 {
2085         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2086         struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2087         struct vega20_single_dpm_table *dpm_table;
2088         bool vblank_too_short = false;
2089         bool disable_mclk_switching;
2090         uint32_t i, latency;
2091
2092         disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2093                                   !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2094         latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2095
2096         /* gfxclk */
2097         dpm_table = &(dpm_ctx->gfx_table);
2098         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2099         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2100         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2101         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2102
2103                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2104                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2105                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2106                 }
2107
2108                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2109                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2110                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2111                 }
2112
2113                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2114                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2115                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2116                 }
2117
2118         /* memclk */
2119         dpm_table = &(dpm_ctx->mem_table);
2120         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2121         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2122         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2123         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2124
2125                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2126                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2127                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2128                 }
2129
2130                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2131                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2132                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2133                 }
2134
2135                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2136                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2137                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2138                 }
2139
2140         /* honour DAL's UCLK Hardmin */
2141         if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2142                 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2143
2144         /* Hardmin is dependent on displayconfig */
2145         if (disable_mclk_switching) {
2146                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2147                 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2148                         if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2149                                 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2150                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2151                                         break;
2152                                 }
2153                         }
2154                 }
2155         }
2156
2157         if (smu->display_config->nb_pstate_switch_disable)
2158                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2159
2160         /* vclk */
2161         dpm_table = &(dpm_ctx->vclk_table);
2162         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2163         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2164         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2165         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2166
2167                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2168                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2169                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2170                 }
2171
2172                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2173                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2174                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2175                 }
2176
2177         /* dclk */
2178         dpm_table = &(dpm_ctx->dclk_table);
2179         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2180         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2181         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2182         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2183
2184                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2185                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2186                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2187                 }
2188
2189                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2190                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2191                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2192                 }
2193
2194         /* socclk */
2195         dpm_table = &(dpm_ctx->soc_table);
2196         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2197         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2198         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2199         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2200
2201                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2202                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2203                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2204                 }
2205
2206                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2207                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2208                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2209                 }
2210
2211         /* eclk */
2212         dpm_table = &(dpm_ctx->eclk_table);
2213         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2214         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2215         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2216         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2217
2218                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2219                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2220                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2221                 }
2222
2223                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2224                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2225                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2226                 }
2227         return 0;
2228 }
2229
2230 static int
2231 vega20_notify_smc_dispaly_config(struct smu_context *smu)
2232 {
2233         struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2234         struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2235         struct smu_clocks min_clocks = {0};
2236         struct pp_display_clock_request clock_req;
2237         int ret = 0;
2238
2239         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2240         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2241         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2242
2243         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2244                 clock_req.clock_type = amd_pp_dcef_clock;
2245                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2246                 if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
2247                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2248                                 ret = smu_send_smc_msg_with_param(smu,
2249                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
2250                                                                   min_clocks.dcef_clock_in_sr/100);
2251                                 if (ret) {
2252                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
2253                                         return ret;
2254                                 }
2255                         }
2256                 } else {
2257                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2258                 }
2259         }
2260
2261         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2262                 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2263                 ret = smu_send_smc_msg_with_param(smu,
2264                                                   SMU_MSG_SetHardMinByFreq,
2265                                                   (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2266                 if (ret) {
2267                         pr_err("[%s] Set hard min uclk failed!", __func__);
2268                         return ret;
2269                 }
2270         }
2271
2272         return 0;
2273 }
2274
2275 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2276 {
2277         uint32_t i;
2278
2279         for (i = 0; i < table->count; i++) {
2280                 if (table->dpm_levels[i].enabled)
2281                         break;
2282         }
2283         if (i >= table->count) {
2284                 i = 0;
2285                 table->dpm_levels[i].enabled = true;
2286         }
2287
2288         return i;
2289 }
2290
2291 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2292 {
2293         int i = 0;
2294
2295         if (!table) {
2296                 pr_err("[%s] DPM Table does not exist!", __func__);
2297                 return 0;
2298         }
2299         if (table->count <= 0) {
2300                 pr_err("[%s] DPM Table has no entry!", __func__);
2301                 return 0;
2302         }
2303         if (table->count > MAX_REGULAR_DPM_NUMBER) {
2304                 pr_err("[%s] DPM Table has too many entries!", __func__);
2305                 return MAX_REGULAR_DPM_NUMBER - 1;
2306         }
2307
2308         for (i = table->count - 1; i >= 0; i--) {
2309                 if (table->dpm_levels[i].enabled)
2310                         break;
2311         }
2312         if (i < 0) {
2313                 i = 0;
2314                 table->dpm_levels[i].enabled = true;
2315         }
2316
2317         return i;
2318 }
2319
2320 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2321 {
2322         uint32_t soft_level;
2323         int ret = 0;
2324         struct vega20_dpm_table *dpm_table =
2325                 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2326
2327         if (highest)
2328                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2329         else
2330                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2331
2332         dpm_table->gfx_table.dpm_state.soft_min_level =
2333                 dpm_table->gfx_table.dpm_state.soft_max_level =
2334                 dpm_table->gfx_table.dpm_levels[soft_level].value;
2335
2336         if (highest)
2337                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2338         else
2339                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2340
2341         dpm_table->mem_table.dpm_state.soft_min_level =
2342                 dpm_table->mem_table.dpm_state.soft_max_level =
2343                 dpm_table->mem_table.dpm_levels[soft_level].value;
2344
2345         if (highest)
2346                 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2347         else
2348                 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2349
2350         dpm_table->soc_table.dpm_state.soft_min_level =
2351                 dpm_table->soc_table.dpm_state.soft_max_level =
2352                 dpm_table->soc_table.dpm_levels[soft_level].value;
2353
2354         ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2355         if (ret) {
2356                 pr_err("Failed to upload boot level to %s!\n",
2357                                 highest ? "highest" : "lowest");
2358                 return ret;
2359         }
2360
2361         ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2362         if (ret) {
2363                 pr_err("Failed to upload dpm max level to %s!\n!",
2364                                 highest ? "highest" : "lowest");
2365                 return ret;
2366         }
2367
2368         return ret;
2369 }
2370
2371 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2372 {
2373         uint32_t soft_min_level, soft_max_level;
2374         int ret = 0;
2375         struct vega20_dpm_table *dpm_table =
2376                 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2377
2378         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2379         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2380         dpm_table->gfx_table.dpm_state.soft_min_level =
2381                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2382         dpm_table->gfx_table.dpm_state.soft_max_level =
2383                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2384
2385         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2386         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2387         dpm_table->mem_table.dpm_state.soft_min_level =
2388                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2389         dpm_table->mem_table.dpm_state.soft_max_level =
2390                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2391
2392         soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2393         soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2394         dpm_table->soc_table.dpm_state.soft_min_level =
2395                 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2396         dpm_table->soc_table.dpm_state.soft_max_level =
2397                 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2398
2399         ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2400         if (ret) {
2401                 pr_err("Failed to upload DPM Bootup Levels!");
2402                 return ret;
2403         }
2404
2405         ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2406         if (ret) {
2407                 pr_err("Failed to upload DPM Max Levels!");
2408                 return ret;
2409         }
2410
2411         return ret;
2412 }
2413
2414 static int vega20_update_specified_od8_value(struct smu_context *smu,
2415                                              uint32_t index,
2416                                              uint32_t value)
2417 {
2418         struct smu_table_context *table_context = &smu->smu_table;
2419         OverDriveTable_t *od_table =
2420                 (OverDriveTable_t *)(table_context->overdrive_table);
2421         struct vega20_od8_settings *od8_settings =
2422                 (struct vega20_od8_settings *)smu->od_settings;
2423
2424         switch (index) {
2425         case OD8_SETTING_GFXCLK_FMIN:
2426                 od_table->GfxclkFmin = (uint16_t)value;
2427                 break;
2428
2429         case OD8_SETTING_GFXCLK_FMAX:
2430                 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2431                     value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2432                         return -EINVAL;
2433                 od_table->GfxclkFmax = (uint16_t)value;
2434                 break;
2435
2436         case OD8_SETTING_GFXCLK_FREQ1:
2437                 od_table->GfxclkFreq1 = (uint16_t)value;
2438                 break;
2439
2440         case OD8_SETTING_GFXCLK_VOLTAGE1:
2441                 od_table->GfxclkVolt1 = (uint16_t)value;
2442                 break;
2443
2444         case OD8_SETTING_GFXCLK_FREQ2:
2445                 od_table->GfxclkFreq2 = (uint16_t)value;
2446                 break;
2447
2448         case OD8_SETTING_GFXCLK_VOLTAGE2:
2449                 od_table->GfxclkVolt2 = (uint16_t)value;
2450                 break;
2451
2452         case OD8_SETTING_GFXCLK_FREQ3:
2453                 od_table->GfxclkFreq3 = (uint16_t)value;
2454                 break;
2455
2456         case OD8_SETTING_GFXCLK_VOLTAGE3:
2457                 od_table->GfxclkVolt3 = (uint16_t)value;
2458                 break;
2459
2460         case OD8_SETTING_UCLK_FMAX:
2461                 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2462                     value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2463                         return -EINVAL;
2464                 od_table->UclkFmax = (uint16_t)value;
2465                 break;
2466
2467         case OD8_SETTING_POWER_PERCENTAGE:
2468                 od_table->OverDrivePct = (int16_t)value;
2469                 break;
2470
2471         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2472                 od_table->FanMaximumRpm = (uint16_t)value;
2473                 break;
2474
2475         case OD8_SETTING_FAN_MIN_SPEED:
2476                 od_table->FanMinimumPwm = (uint16_t)value;
2477                 break;
2478
2479         case OD8_SETTING_FAN_TARGET_TEMP:
2480                 od_table->FanTargetTemperature = (uint16_t)value;
2481                 break;
2482
2483         case OD8_SETTING_OPERATING_TEMP_MAX:
2484                 od_table->MaxOpTemp = (uint16_t)value;
2485                 break;
2486         }
2487
2488         return 0;
2489 }
2490
2491 static int vega20_update_od8_settings(struct smu_context *smu,
2492                                       uint32_t index,
2493                                       uint32_t value)
2494 {
2495         struct smu_table_context *table_context = &smu->smu_table;
2496         int ret;
2497
2498         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
2499                                table_context->overdrive_table, false);
2500         if (ret) {
2501                 pr_err("Failed to export over drive table!\n");
2502                 return ret;
2503         }
2504
2505         ret = vega20_update_specified_od8_value(smu, index, value);
2506         if (ret)
2507                 return ret;
2508
2509         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
2510                                table_context->overdrive_table, true);
2511         if (ret) {
2512                 pr_err("Failed to import over drive table!\n");
2513                 return ret;
2514         }
2515
2516         return 0;
2517 }
2518
2519 static int vega20_set_od_percentage(struct smu_context *smu,
2520                                     enum smu_clk_type clk_type,
2521                                     uint32_t value)
2522 {
2523         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2524         struct vega20_dpm_table *dpm_table = NULL;
2525         struct vega20_dpm_table *golden_table = NULL;
2526         struct vega20_single_dpm_table *single_dpm_table;
2527         struct vega20_single_dpm_table *golden_dpm_table;
2528         uint32_t od_clk, index;
2529         int ret = 0;
2530         int feature_enabled;
2531         PPCLK_e clk_id;
2532
2533         mutex_lock(&(smu->mutex));
2534
2535         dpm_table = smu_dpm->dpm_context;
2536         golden_table = smu_dpm->golden_dpm_context;
2537
2538         switch (clk_type) {
2539         case SMU_OD_SCLK:
2540                 single_dpm_table = &(dpm_table->gfx_table);
2541                 golden_dpm_table = &(golden_table->gfx_table);
2542                 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2543                 clk_id = PPCLK_GFXCLK;
2544                 index = OD8_SETTING_GFXCLK_FMAX;
2545                 break;
2546         case SMU_OD_MCLK:
2547                 single_dpm_table = &(dpm_table->mem_table);
2548                 golden_dpm_table = &(golden_table->mem_table);
2549                 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2550                 clk_id = PPCLK_UCLK;
2551                 index = OD8_SETTING_UCLK_FMAX;
2552                 break;
2553         default:
2554                 ret = -EINVAL;
2555                 break;
2556         }
2557
2558         if (ret)
2559                 goto set_od_failed;
2560
2561         od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2562         od_clk /= 100;
2563         od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2564
2565         ret = vega20_update_od8_settings(smu, index, od_clk);
2566         if (ret) {
2567                 pr_err("[Setoverdrive] failed to set od clk!\n");
2568                 goto set_od_failed;
2569         }
2570
2571         if (feature_enabled) {
2572                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2573                                                   clk_id);
2574                 if (ret) {
2575                         pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2576                         goto set_od_failed;
2577                 }
2578         } else {
2579                 single_dpm_table->count = 1;
2580                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2581         }
2582
2583         ret = smu_handle_task(smu, smu_dpm->dpm_level,
2584                               AMD_PP_TASK_READJUST_POWER_STATE);
2585
2586 set_od_failed:
2587         mutex_unlock(&(smu->mutex));
2588
2589         return ret;
2590 }
2591
2592 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2593                                      enum PP_OD_DPM_TABLE_COMMAND type,
2594                                      long *input, uint32_t size)
2595 {
2596         struct smu_table_context *table_context = &smu->smu_table;
2597         OverDriveTable_t *od_table =
2598                 (OverDriveTable_t *)(table_context->overdrive_table);
2599         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2600         struct vega20_dpm_table *dpm_table = NULL;
2601         struct vega20_single_dpm_table *single_dpm_table;
2602         struct vega20_od8_settings *od8_settings =
2603                 (struct vega20_od8_settings *)smu->od_settings;
2604         struct pp_clock_levels_with_latency clocks;
2605         int32_t input_index, input_clk, input_vol, i;
2606         int od8_id;
2607         int ret = 0;
2608
2609         dpm_table = smu_dpm->dpm_context;
2610
2611         if (!input) {
2612                 pr_warn("NULL user input for clock and voltage\n");
2613                 return -EINVAL;
2614         }
2615
2616         switch (type) {
2617         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2618                 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2619                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2620                         pr_info("Sclk min/max frequency overdrive not supported\n");
2621                         return -EOPNOTSUPP;
2622                 }
2623
2624                 for (i = 0; i < size; i += 2) {
2625                         if (i + 2 > size) {
2626                                 pr_info("invalid number of input parameters %d\n", size);
2627                                 return -EINVAL;
2628                         }
2629
2630                         input_index = input[i];
2631                         input_clk = input[i + 1];
2632
2633                         if (input_index != 0 && input_index != 1) {
2634                                 pr_info("Invalid index %d\n", input_index);
2635                                 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2636                                 return -EINVAL;
2637                         }
2638
2639                         if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2640                             input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2641                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2642                                         input_clk,
2643                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2644                                         od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2645                                 return -EINVAL;
2646                         }
2647
2648                         if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2649                                 od_table->GfxclkFmin = input_clk;
2650                                 od8_settings->od_gfxclk_update = true;
2651                         } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2652                                 od_table->GfxclkFmax = input_clk;
2653                                 od8_settings->od_gfxclk_update = true;
2654                         }
2655                 }
2656
2657                 break;
2658
2659         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2660                 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2661                         pr_info("Mclk max frequency overdrive not supported\n");
2662                         return -EOPNOTSUPP;
2663                 }
2664
2665                 single_dpm_table = &(dpm_table->mem_table);
2666                 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2667                 if (ret) {
2668                         pr_err("Attempt to get memory clk levels Failed!");
2669                         return ret;
2670                 }
2671
2672                 for (i = 0; i < size; i += 2) {
2673                         if (i + 2 > size) {
2674                                 pr_info("invalid number of input parameters %d\n",
2675                                          size);
2676                                 return -EINVAL;
2677                         }
2678
2679                         input_index = input[i];
2680                         input_clk = input[i + 1];
2681
2682                         if (input_index != 1) {
2683                                 pr_info("Invalid index %d\n", input_index);
2684                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2685                                 return -EINVAL;
2686                         }
2687
2688                         if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2689                             input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2690                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2691                                         input_clk,
2692                                         clocks.data[0].clocks_in_khz / 1000,
2693                                         od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2694                                 return -EINVAL;
2695                         }
2696
2697                         if (input_index == 1 && od_table->UclkFmax != input_clk) {
2698                                 od8_settings->od_gfxclk_update = true;
2699                                 od_table->UclkFmax = input_clk;
2700                         }
2701                 }
2702
2703                 break;
2704
2705         case PP_OD_EDIT_VDDC_CURVE:
2706                 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2707                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2708                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2709                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2710                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2711                       od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2712                         pr_info("Voltage curve calibrate not supported\n");
2713                         return -EOPNOTSUPP;
2714                 }
2715
2716                 for (i = 0; i < size; i += 3) {
2717                         if (i + 3 > size) {
2718                                 pr_info("invalid number of input parameters %d\n",
2719                                         size);
2720                                 return -EINVAL;
2721                         }
2722
2723                         input_index = input[i];
2724                         input_clk = input[i + 1];
2725                         input_vol = input[i + 2];
2726
2727                         if (input_index > 2) {
2728                                 pr_info("Setting for point %d is not supported\n",
2729                                         input_index + 1);
2730                                 pr_info("Three supported points index by 0, 1, 2\n");
2731                                 return -EINVAL;
2732                         }
2733
2734                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2735                         if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2736                             input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2737                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2738                                         input_clk,
2739                                         od8_settings->od8_settings_array[od8_id].min_value,
2740                                         od8_settings->od8_settings_array[od8_id].max_value);
2741                                 return -EINVAL;
2742                         }
2743
2744                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2745                         if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2746                             input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2747                                 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2748                                         input_vol,
2749                                         od8_settings->od8_settings_array[od8_id].min_value,
2750                                         od8_settings->od8_settings_array[od8_id].max_value);
2751                                 return -EINVAL;
2752                         }
2753
2754                         switch (input_index) {
2755                         case 0:
2756                                 od_table->GfxclkFreq1 = input_clk;
2757                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2758                                 break;
2759                         case 1:
2760                                 od_table->GfxclkFreq2 = input_clk;
2761                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2762                                 break;
2763                         case 2:
2764                                 od_table->GfxclkFreq3 = input_clk;
2765                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2766                                 break;
2767                         }
2768                 }
2769
2770                 break;
2771
2772         case PP_OD_RESTORE_DEFAULT_TABLE:
2773                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, false);
2774                 if (ret) {
2775                         pr_err("Failed to export over drive table!\n");
2776                         return ret;
2777                 }
2778
2779                 break;
2780
2781         case PP_OD_COMMIT_DPM_TABLE:
2782                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, true);
2783                 if (ret) {
2784                         pr_err("Failed to import over drive table!\n");
2785                         return ret;
2786                 }
2787
2788                 /* retrieve updated gfxclk table */
2789                 if (od8_settings->od_gfxclk_update) {
2790                         od8_settings->od_gfxclk_update = false;
2791                         single_dpm_table = &(dpm_table->gfx_table);
2792
2793                         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2794                                 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2795                                                                   PPCLK_GFXCLK);
2796                                 if (ret) {
2797                                         pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2798                                         return ret;
2799                                 }
2800                         } else {
2801                                 single_dpm_table->count = 1;
2802                                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2803                         }
2804                 }
2805
2806                 break;
2807
2808         default:
2809                 return -EINVAL;
2810         }
2811
2812         if (type == PP_OD_COMMIT_DPM_TABLE) {
2813                 mutex_lock(&(smu->mutex));
2814                 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2815                                       AMD_PP_TASK_READJUST_POWER_STATE);
2816                 mutex_unlock(&(smu->mutex));
2817         }
2818
2819         return ret;
2820 }
2821
2822 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2823 {
2824         if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2825                 return 0;
2826
2827         if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2828                 return 0;
2829
2830         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2831 }
2832
2833 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2834 {
2835         if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2836                 return 0;
2837
2838         if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2839                 return 0;
2840
2841         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2842 }
2843
2844 static int vega20_get_enabled_smc_features(struct smu_context *smu,
2845                 uint64_t *features_enabled)
2846 {
2847         uint32_t feature_mask[2] = {0, 0};
2848         int ret = 0;
2849
2850         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2851         if (ret)
2852                 return ret;
2853
2854         *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
2855                         (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
2856
2857         return ret;
2858 }
2859
2860 static int vega20_enable_smc_features(struct smu_context *smu,
2861                 bool enable, uint64_t feature_mask)
2862 {
2863         uint32_t smu_features_low, smu_features_high;
2864         int ret = 0;
2865
2866         smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
2867         smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
2868
2869         if (enable) {
2870                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
2871                                                   smu_features_low);
2872                 if (ret)
2873                         return ret;
2874                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
2875                                                   smu_features_high);
2876                 if (ret)
2877                         return ret;
2878         } else {
2879                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
2880                                                   smu_features_low);
2881                 if (ret)
2882                         return ret;
2883                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
2884                                                   smu_features_high);
2885                 if (ret)
2886                         return ret;
2887         }
2888
2889         return 0;
2890
2891 }
2892
2893 static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
2894 {
2895         static const char *ppfeature_name[] = {
2896                                 "DPM_PREFETCHER",
2897                                 "GFXCLK_DPM",
2898                                 "UCLK_DPM",
2899                                 "SOCCLK_DPM",
2900                                 "UVD_DPM",
2901                                 "VCE_DPM",
2902                                 "ULV",
2903                                 "MP0CLK_DPM",
2904                                 "LINK_DPM",
2905                                 "DCEFCLK_DPM",
2906                                 "GFXCLK_DS",
2907                                 "SOCCLK_DS",
2908                                 "LCLK_DS",
2909                                 "PPT",
2910                                 "TDC",
2911                                 "THERMAL",
2912                                 "GFX_PER_CU_CG",
2913                                 "RM",
2914                                 "DCEFCLK_DS",
2915                                 "ACDC",
2916                                 "VR0HOT",
2917                                 "VR1HOT",
2918                                 "FW_CTF",
2919                                 "LED_DISPLAY",
2920                                 "FAN_CONTROL",
2921                                 "GFX_EDC",
2922                                 "GFXOFF",
2923                                 "CG",
2924                                 "FCLK_DPM",
2925                                 "FCLK_DS",
2926                                 "MP1CLK_DS",
2927                                 "MP0CLK_DS",
2928                                 "XGMI",
2929                                 "ECC"};
2930         static const char *output_title[] = {
2931                                 "FEATURES",
2932                                 "BITMASK",
2933                                 "ENABLEMENT"};
2934         uint64_t features_enabled;
2935         int i;
2936         int ret = 0;
2937         int size = 0;
2938
2939         ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2940         if (ret)
2941                 return ret;
2942
2943         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2944         size += sprintf(buf + size, "%-19s %-22s %s\n",
2945                                 output_title[0],
2946                                 output_title[1],
2947                                 output_title[2]);
2948         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2949                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
2950                                         ppfeature_name[i],
2951                                         1ULL << i,
2952                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
2953         }
2954
2955         return size;
2956 }
2957
2958 static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
2959 {
2960         uint64_t features_enabled;
2961         uint64_t features_to_enable;
2962         uint64_t features_to_disable;
2963         int ret = 0;
2964
2965         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2966                 return -EINVAL;
2967
2968         ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2969         if (ret)
2970                 return ret;
2971
2972         features_to_disable =
2973                 features_enabled & ~new_ppfeature_masks;
2974         features_to_enable =
2975                 ~features_enabled & new_ppfeature_masks;
2976
2977         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2978         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2979
2980         if (features_to_disable) {
2981                 ret = vega20_enable_smc_features(smu, false, features_to_disable);
2982                 if (ret)
2983                         return ret;
2984         }
2985
2986         if (features_to_enable) {
2987                 ret = vega20_enable_smc_features(smu, true, features_to_enable);
2988                 if (ret)
2989                         return ret;
2990         }
2991
2992         return 0;
2993 }
2994
2995 static bool vega20_is_dpm_running(struct smu_context *smu)
2996 {
2997         int ret = 0;
2998         uint32_t feature_mask[2];
2999         unsigned long feature_enabled;
3000         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
3001         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
3002                            ((uint64_t)feature_mask[1] << 32));
3003         return !!(feature_enabled & SMC_DPM_FEATURE);
3004 }
3005
3006 static int vega20_set_thermal_fan_table(struct smu_context *smu)
3007 {
3008         int ret;
3009         struct smu_table_context *table_context = &smu->smu_table;
3010         PPTable_t *pptable = table_context->driver_pptable;
3011
3012         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
3013                         (uint32_t)pptable->FanTargetTemperature);
3014
3015         return ret;
3016 }
3017
3018 static int vega20_get_fan_speed_percent(struct smu_context *smu,
3019                                         uint32_t *speed)
3020 {
3021         int ret = 0;
3022         uint32_t current_rpm = 0, percent = 0;
3023         PPTable_t *pptable = smu->smu_table.driver_pptable;
3024
3025         ret = smu_get_current_rpm(smu, &current_rpm);
3026         if (ret)
3027                 return ret;
3028
3029         percent = current_rpm * 100 / pptable->FanMaximumRpm;
3030         *speed = percent > 100 ? 100 : percent;
3031
3032         return 0;
3033 }
3034
3035 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
3036 {
3037         int ret = 0;
3038         SmuMetrics_t metrics;
3039
3040         if (!value)
3041                 return -EINVAL;
3042
3043         ret = vega20_get_metrics_table(smu, &metrics);
3044         if (ret)
3045                 return ret;
3046
3047         *value = metrics.CurrSocketPower << 8;
3048
3049         return 0;
3050 }
3051
3052 static int vega20_get_current_activity_percent(struct smu_context *smu,
3053                                                enum amd_pp_sensors sensor,
3054                                                uint32_t *value)
3055 {
3056         int ret = 0;
3057         SmuMetrics_t metrics;
3058
3059         if (!value)
3060                 return -EINVAL;
3061
3062         ret = vega20_get_metrics_table(smu, &metrics);
3063         if (ret)
3064                 return ret;
3065
3066         switch (sensor) {
3067         case AMDGPU_PP_SENSOR_GPU_LOAD:
3068                 *value = metrics.AverageGfxActivity;
3069                 break;
3070         case AMDGPU_PP_SENSOR_MEM_LOAD:
3071                 *value = metrics.AverageUclkActivity;
3072                 break;
3073         default:
3074                 pr_err("Invalid sensor for retrieving clock activity\n");
3075                 return -EINVAL;
3076         }
3077
3078         return 0;
3079 }
3080
3081 static int vega20_thermal_get_temperature(struct smu_context *smu,
3082                                              enum amd_pp_sensors sensor,
3083                                              uint32_t *value)
3084 {
3085         struct amdgpu_device *adev = smu->adev;
3086         SmuMetrics_t metrics;
3087         uint32_t temp = 0;
3088         int ret = 0;
3089
3090         if (!value)
3091                 return -EINVAL;
3092
3093         ret = vega20_get_metrics_table(smu, &metrics);
3094         if (ret)
3095                 return ret;
3096
3097         switch (sensor) {
3098         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3099                 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
3100                 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
3101                                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
3102
3103                 temp = temp & 0x1ff;
3104                 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3105
3106                 *value = temp;
3107                 break;
3108         case AMDGPU_PP_SENSOR_EDGE_TEMP:
3109                 *value = metrics.TemperatureEdge *
3110                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3111                 break;
3112         case AMDGPU_PP_SENSOR_MEM_TEMP:
3113                 *value = metrics.TemperatureHBM *
3114                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3115                 break;
3116         default:
3117                 pr_err("Invalid sensor for retrieving temp\n");
3118                 return -EINVAL;
3119         }
3120
3121         return 0;
3122 }
3123 static int vega20_read_sensor(struct smu_context *smu,
3124                                  enum amd_pp_sensors sensor,
3125                                  void *data, uint32_t *size)
3126 {
3127         int ret = 0;
3128         struct smu_table_context *table_context = &smu->smu_table;
3129         PPTable_t *pptable = table_context->driver_pptable;
3130
3131         switch (sensor) {
3132         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3133                 *(uint32_t *)data = pptable->FanMaximumRpm;
3134                 *size = 4;
3135                 break;
3136         case AMDGPU_PP_SENSOR_MEM_LOAD:
3137         case AMDGPU_PP_SENSOR_GPU_LOAD:
3138                 ret = vega20_get_current_activity_percent(smu,
3139                                                 sensor,
3140                                                 (uint32_t *)data);
3141                 *size = 4;
3142                 break;
3143         case AMDGPU_PP_SENSOR_GPU_POWER:
3144                 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3145                 *size = 4;
3146                 break;
3147         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3148         case AMDGPU_PP_SENSOR_EDGE_TEMP:
3149         case AMDGPU_PP_SENSOR_MEM_TEMP:
3150                 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3151                 *size = 4;
3152                 break;
3153         default:
3154                 return -EINVAL;
3155         }
3156
3157         return ret;
3158 }
3159
3160 static int vega20_set_watermarks_table(struct smu_context *smu,
3161                                        void *watermarks, struct
3162                                        dm_pp_wm_sets_with_clock_ranges_soc15
3163                                        *clock_ranges)
3164 {
3165         int i;
3166         Watermarks_t *table = watermarks;
3167
3168         if (!table || !clock_ranges)
3169                 return -EINVAL;
3170
3171         if (clock_ranges->num_wm_dmif_sets > 4 ||
3172             clock_ranges->num_wm_mcif_sets > 4)
3173                 return -EINVAL;
3174
3175         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3176                 table->WatermarkRow[1][i].MinClock =
3177                         cpu_to_le16((uint16_t)
3178                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3179                         1000));
3180                 table->WatermarkRow[1][i].MaxClock =
3181                         cpu_to_le16((uint16_t)
3182                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3183                         1000));
3184                 table->WatermarkRow[1][i].MinUclk =
3185                         cpu_to_le16((uint16_t)
3186                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3187                         1000));
3188                 table->WatermarkRow[1][i].MaxUclk =
3189                         cpu_to_le16((uint16_t)
3190                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3191                         1000));
3192                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3193                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3194         }
3195
3196         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3197                 table->WatermarkRow[0][i].MinClock =
3198                         cpu_to_le16((uint16_t)
3199                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3200                         1000));
3201                 table->WatermarkRow[0][i].MaxClock =
3202                         cpu_to_le16((uint16_t)
3203                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3204                         1000));
3205                 table->WatermarkRow[0][i].MinUclk =
3206                         cpu_to_le16((uint16_t)
3207                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3208                         1000));
3209                 table->WatermarkRow[0][i].MaxUclk =
3210                         cpu_to_le16((uint16_t)
3211                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3212                         1000));
3213                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3214                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3215         }
3216
3217         return 0;
3218 }
3219
3220 static const struct smu_temperature_range vega20_thermal_policy[] =
3221 {
3222         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
3223         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
3224 };
3225
3226 static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3227                                                 struct smu_temperature_range *range)
3228 {
3229
3230         PPTable_t *pptable = smu->smu_table.driver_pptable;
3231
3232         if (!range)
3233                 return -EINVAL;
3234
3235         memcpy(range, &vega20_thermal_policy[0], sizeof(struct smu_temperature_range));
3236
3237         range->max = pptable->TedgeLimit *
3238                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3239         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
3240                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3241         range->hotspot_crit_max = pptable->ThotspotLimit *
3242                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3243         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
3244                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3245         range->mem_crit_max = pptable->ThbmLimit *
3246                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3247         range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
3248                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3249
3250
3251         return 0;
3252 }
3253
3254 static const struct pptable_funcs vega20_ppt_funcs = {
3255         .tables_init = vega20_tables_init,
3256         .alloc_dpm_context = vega20_allocate_dpm_context,
3257         .store_powerplay_table = vega20_store_powerplay_table,
3258         .check_powerplay_table = vega20_check_powerplay_table,
3259         .append_powerplay_table = vega20_append_powerplay_table,
3260         .get_smu_msg_index = vega20_get_smu_msg_index,
3261         .get_smu_clk_index = vega20_get_smu_clk_index,
3262         .get_smu_feature_index = vega20_get_smu_feature_index,
3263         .get_smu_table_index = vega20_get_smu_table_index,
3264         .get_smu_power_index = vega20_get_pwr_src_index,
3265         .get_workload_type = vega20_get_workload_type,
3266         .run_afll_btc = vega20_run_btc_afll,
3267         .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3268         .get_current_power_state = vega20_get_current_power_state,
3269         .set_default_dpm_table = vega20_set_default_dpm_table,
3270         .set_power_state = NULL,
3271         .populate_umd_state_clk = vega20_populate_umd_state_clk,
3272         .print_clk_levels = vega20_print_clk_levels,
3273         .force_clk_levels = vega20_force_clk_levels,
3274         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3275         .get_od_percentage = vega20_get_od_percentage,
3276         .get_power_profile_mode = vega20_get_power_profile_mode,
3277         .set_power_profile_mode = vega20_set_power_profile_mode,
3278         .set_od_percentage = vega20_set_od_percentage,
3279         .set_default_od_settings = vega20_set_default_od_settings,
3280         .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3281         .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3282         .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3283         .read_sensor = vega20_read_sensor,
3284         .pre_display_config_changed = vega20_pre_display_config_changed,
3285         .display_config_changed = vega20_display_config_changed,
3286         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3287         .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
3288         .force_dpm_limit_value = vega20_force_dpm_limit_value,
3289         .unforce_dpm_levels = vega20_unforce_dpm_levels,
3290         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3291         .set_ppfeature_status = vega20_set_ppfeature_status,
3292         .get_ppfeature_status = vega20_get_ppfeature_status,
3293         .is_dpm_running = vega20_is_dpm_running,
3294         .set_thermal_fan_table = vega20_set_thermal_fan_table,
3295         .get_fan_speed_percent = vega20_get_fan_speed_percent,
3296         .set_watermarks_table = vega20_set_watermarks_table,
3297         .get_thermal_temperature_range = vega20_get_thermal_temperature_range
3298 };
3299
3300 void vega20_set_ppt_funcs(struct smu_context *smu)
3301 {
3302         struct smu_table_context *smu_table = &smu->smu_table;
3303
3304         smu->ppt_funcs = &vega20_ppt_funcs;
3305         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
3306         smu_table->table_count = TABLE_COUNT;
3307 }