2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "atomfirmware.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "smu_v11_0.h"
31 #include "smu11_driver_if.h"
32 #include "soc15_common.h"
34 #include "power_state.h"
35 #include "vega20_ppt.h"
36 #include "vega20_pptable.h"
37 #include "vega20_ppsmc.h"
38 #include "nbio/nbio_7_4_sh_mask.h"
39 #include "asic_reg/thm/thm_11_0_2_offset.h"
40 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
42 #define smnPCIE_LC_SPEED_CNTL 0x11140290
43 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
45 #define CTF_OFFSET_EDGE 5
46 #define CTF_OFFSET_HOTSPOT 5
47 #define CTF_OFFSET_HBM 5
49 #define MSG_MAP(msg) \
50 [SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
52 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
53 FEATURE_DPM_GFXCLK_MASK | \
54 FEATURE_DPM_UCLK_MASK | \
55 FEATURE_DPM_SOCCLK_MASK | \
56 FEATURE_DPM_UVD_MASK | \
57 FEATURE_DPM_VCE_MASK | \
58 FEATURE_DPM_MP0CLK_MASK | \
59 FEATURE_DPM_LINK_MASK | \
60 FEATURE_DPM_DCEFCLK_MASK)
62 static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
64 MSG_MAP(GetSmuVersion),
65 MSG_MAP(GetDriverIfVersion),
66 MSG_MAP(SetAllowedFeaturesMaskLow),
67 MSG_MAP(SetAllowedFeaturesMaskHigh),
68 MSG_MAP(EnableAllSmuFeatures),
69 MSG_MAP(DisableAllSmuFeatures),
70 MSG_MAP(EnableSmuFeaturesLow),
71 MSG_MAP(EnableSmuFeaturesHigh),
72 MSG_MAP(DisableSmuFeaturesLow),
73 MSG_MAP(DisableSmuFeaturesHigh),
74 MSG_MAP(GetEnabledSmuFeaturesLow),
75 MSG_MAP(GetEnabledSmuFeaturesHigh),
76 MSG_MAP(SetWorkloadMask),
78 MSG_MAP(SetDriverDramAddrHigh),
79 MSG_MAP(SetDriverDramAddrLow),
80 MSG_MAP(SetToolsDramAddrHigh),
81 MSG_MAP(SetToolsDramAddrLow),
82 MSG_MAP(TransferTableSmu2Dram),
83 MSG_MAP(TransferTableDram2Smu),
84 MSG_MAP(UseDefaultPPTable),
85 MSG_MAP(UseBackupPPTable),
87 MSG_MAP(RequestI2CBus),
88 MSG_MAP(ReleaseI2CBus),
89 MSG_MAP(SetFloorSocVoltage),
91 MSG_MAP(StartBacoMonitor),
92 MSG_MAP(CancelBacoMonitor),
94 MSG_MAP(SetSoftMinByFreq),
95 MSG_MAP(SetSoftMaxByFreq),
96 MSG_MAP(SetHardMinByFreq),
97 MSG_MAP(SetHardMaxByFreq),
98 MSG_MAP(GetMinDpmFreq),
99 MSG_MAP(GetMaxDpmFreq),
100 MSG_MAP(GetDpmFreqByIndex),
101 MSG_MAP(GetDpmClockFreq),
102 MSG_MAP(GetSsVoltageByDpm),
103 MSG_MAP(SetMemoryChannelConfig),
104 MSG_MAP(SetGeminiMode),
105 MSG_MAP(SetGeminiApertureHigh),
106 MSG_MAP(SetGeminiApertureLow),
107 MSG_MAP(SetMinLinkDpmByIndex),
108 MSG_MAP(OverridePcieParameters),
109 MSG_MAP(OverDriveSetPercentage),
110 MSG_MAP(SetMinDeepSleepDcefclk),
111 MSG_MAP(ReenableAcDcInterrupt),
112 MSG_MAP(NotifyPowerSource),
113 MSG_MAP(SetUclkFastSwitch),
114 MSG_MAP(SetUclkDownHyst),
115 MSG_MAP(GetCurrentRpm),
116 MSG_MAP(SetVideoFps),
118 MSG_MAP(SetFanTemperatureTarget),
119 MSG_MAP(PrepareMp1ForUnload),
120 MSG_MAP(DramLogSetDramAddrHigh),
121 MSG_MAP(DramLogSetDramAddrLow),
122 MSG_MAP(DramLogSetDramSize),
123 MSG_MAP(SetFanMaxRpm),
124 MSG_MAP(SetFanMinPwm),
125 MSG_MAP(ConfigureGfxDidt),
126 MSG_MAP(NumOfDisplays),
127 MSG_MAP(RemoveMargins),
128 MSG_MAP(ReadSerialNumTop32),
129 MSG_MAP(ReadSerialNumBottom32),
130 MSG_MAP(SetSystemVirtualDramAddrHigh),
131 MSG_MAP(SetSystemVirtualDramAddrLow),
133 MSG_MAP(SetFclkGfxClkRatio),
134 MSG_MAP(AllowGfxOff),
135 MSG_MAP(DisallowGfxOff),
136 MSG_MAP(GetPptLimit),
137 MSG_MAP(GetDcModeMaxDpmFreq),
138 MSG_MAP(GetDebugData),
139 MSG_MAP(SetXgmiMode),
142 MSG_MAP(PrepareMp1ForReset),
143 MSG_MAP(PrepareMp1ForShutdown),
144 MSG_MAP(SetMGpuFanBoostLimitRpm),
145 MSG_MAP(GetAVFSVoltageByDpm),
148 static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
149 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
150 CLK_MAP(VCLK, PPCLK_VCLK),
151 CLK_MAP(DCLK, PPCLK_DCLK),
152 CLK_MAP(ECLK, PPCLK_ECLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(UCLK, PPCLK_UCLK),
155 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
156 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
157 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
158 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
159 CLK_MAP(FCLK, PPCLK_FCLK),
162 static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
163 FEA_MAP(DPM_PREFETCHER),
172 FEA_MAP(DPM_DCEFCLK),
179 FEA_MAP(GFX_PER_CU_CG),
186 FEA_MAP(LED_DISPLAY),
187 FEA_MAP(FAN_CONTROL),
198 static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
202 TAB_MAP(AVFS_PSM_DEBUG),
203 TAB_MAP(AVFS_FUSE_OVERRIDE),
204 TAB_MAP(PMSTATUSLOG),
205 TAB_MAP(SMU_METRICS),
206 TAB_MAP(DRIVER_SMU_CONFIG),
207 TAB_MAP(ACTIVITY_MONITOR_COEFF),
211 static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
216 static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
226 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
228 struct smu_11_0_cmn2aisc_mapping mapping;
230 if (index >= SMU_TABLE_COUNT)
233 mapping = vega20_table_map[index];
234 if (!(mapping.valid_mapping)) {
238 return mapping.map_to;
241 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
243 struct smu_11_0_cmn2aisc_mapping mapping;
245 if (index >= SMU_POWER_SOURCE_COUNT)
248 mapping = vega20_pwr_src_map[index];
249 if (!(mapping.valid_mapping)) {
253 return mapping.map_to;
256 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
258 struct smu_11_0_cmn2aisc_mapping mapping;
260 if (index >= SMU_FEATURE_COUNT)
263 mapping = vega20_feature_mask_map[index];
264 if (!(mapping.valid_mapping)) {
268 return mapping.map_to;
271 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
273 struct smu_11_0_cmn2aisc_mapping mapping;
275 if (index >= SMU_CLK_COUNT)
278 mapping = vega20_clk_map[index];
279 if (!(mapping.valid_mapping)) {
283 return mapping.map_to;
286 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
288 struct smu_11_0_cmn2aisc_mapping mapping;
290 if (index >= SMU_MSG_MAX_COUNT)
293 mapping = vega20_message_map[index];
294 if (!(mapping.valid_mapping)) {
298 return mapping.map_to;
301 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
303 struct smu_11_0_cmn2aisc_mapping mapping;
305 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
308 mapping = vega20_workload_map[profile];
309 if (!(mapping.valid_mapping)) {
313 return mapping.map_to;
316 static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
318 struct smu_table_context *smu_table = &smu->smu_table;
320 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
321 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
322 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
323 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
324 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
325 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
326 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
327 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
328 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
329 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
330 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
331 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
332 AMDGPU_GEM_DOMAIN_VRAM);
334 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
335 if (!smu_table->metrics_table)
337 smu_table->metrics_time = 0;
342 static int vega20_allocate_dpm_context(struct smu_context *smu)
344 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
346 if (smu_dpm->dpm_context)
349 smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
351 if (!smu_dpm->dpm_context)
354 if (smu_dpm->golden_dpm_context)
357 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
359 if (!smu_dpm->golden_dpm_context)
362 smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
364 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
366 if (!smu_dpm->dpm_current_power_state)
369 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
371 if (!smu_dpm->dpm_request_power_state)
377 static int vega20_setup_od8_information(struct smu_context *smu)
379 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
380 struct smu_table_context *table_context = &smu->smu_table;
381 struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
383 uint32_t od_feature_count, od_feature_array_size,
384 od_setting_count, od_setting_array_size;
386 if (!table_context->power_play_table)
389 powerplay_table = table_context->power_play_table;
391 if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
392 /* Setup correct ODFeatureCount, and store ODFeatureArray from
393 * powerplay table to od_feature_capabilities */
395 (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
396 ATOM_VEGA20_ODFEATURE_COUNT) ?
397 ATOM_VEGA20_ODFEATURE_COUNT :
398 le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
400 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
402 if (od8_settings->od_feature_capabilities)
405 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
406 od_feature_array_size,
408 if (!od8_settings->od_feature_capabilities)
411 /* Setup correct ODSettingCount, and store ODSettingArray from
412 * powerplay table to od_settings_max and od_setting_min */
414 (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
415 ATOM_VEGA20_ODSETTING_COUNT) ?
416 ATOM_VEGA20_ODSETTING_COUNT :
417 le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
419 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
421 if (od8_settings->od_settings_max)
424 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
425 od_setting_array_size,
428 if (!od8_settings->od_settings_max) {
429 kfree(od8_settings->od_feature_capabilities);
430 od8_settings->od_feature_capabilities = NULL;
434 if (od8_settings->od_settings_min)
437 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
438 od_setting_array_size,
441 if (!od8_settings->od_settings_min) {
442 kfree(od8_settings->od_feature_capabilities);
443 od8_settings->od_feature_capabilities = NULL;
444 kfree(od8_settings->od_settings_max);
445 od8_settings->od_settings_max = NULL;
453 static int vega20_store_powerplay_table(struct smu_context *smu)
455 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
456 struct smu_table_context *table_context = &smu->smu_table;
458 if (!table_context->power_play_table)
461 powerplay_table = table_context->power_play_table;
463 memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
466 table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp;
467 table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
468 table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
473 static int vega20_append_powerplay_table(struct smu_context *smu)
475 struct smu_table_context *table_context = &smu->smu_table;
476 PPTable_t *smc_pptable = table_context->driver_pptable;
477 struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
480 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
483 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
484 (uint8_t **)&smc_dpm_table);
488 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
489 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
491 smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
492 smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
493 smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
494 smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
496 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
497 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
498 smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
500 smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
501 smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
502 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
504 smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
505 smc_pptable->SocOffset = smc_dpm_table->socoffset;
506 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
508 smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
509 smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
510 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
512 smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
513 smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
514 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
516 smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
517 smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
518 smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
519 smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
521 smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
522 smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
523 smc_pptable->Padding1 = smc_dpm_table->padding1;
524 smc_pptable->Padding2 = smc_dpm_table->padding2;
526 smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
527 smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
528 smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
530 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
531 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
532 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
534 smc_pptable->UclkSpreadEnabled = 0;
535 smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
536 smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
538 smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
539 smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
540 smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
542 smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
543 smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
544 smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
546 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
547 smc_pptable->I2cControllers[i].Enabled =
548 smc_dpm_table->i2ccontrollers[i].enabled;
549 smc_pptable->I2cControllers[i].SlaveAddress =
550 smc_dpm_table->i2ccontrollers[i].slaveaddress;
551 smc_pptable->I2cControllers[i].ControllerPort =
552 smc_dpm_table->i2ccontrollers[i].controllerport;
553 smc_pptable->I2cControllers[i].ThermalThrottler =
554 smc_dpm_table->i2ccontrollers[i].thermalthrottler;
555 smc_pptable->I2cControllers[i].I2cProtocol =
556 smc_dpm_table->i2ccontrollers[i].i2cprotocol;
557 smc_pptable->I2cControllers[i].I2cSpeed =
558 smc_dpm_table->i2ccontrollers[i].i2cspeed;
564 static int vega20_check_powerplay_table(struct smu_context *smu)
566 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
567 struct smu_table_context *table_context = &smu->smu_table;
569 powerplay_table = table_context->power_play_table;
571 if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
572 pr_err("Unsupported PPTable format!");
576 if (!powerplay_table->sHeader.structuresize) {
577 pr_err("Invalid PowerPlay Table!");
584 static int vega20_run_btc_afll(struct smu_context *smu)
586 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
589 #define FEATURE_MASK(feature) (1ULL << feature)
591 vega20_get_allowed_feature_mask(struct smu_context *smu,
592 uint32_t *feature_mask, uint32_t num)
597 memset(feature_mask, 0, sizeof(uint32_t) * num);
599 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
600 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
601 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
602 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
603 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
604 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
605 | FEATURE_MASK(FEATURE_ULV_BIT)
606 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
607 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
608 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
609 | FEATURE_MASK(FEATURE_PPT_BIT)
610 | FEATURE_MASK(FEATURE_TDC_BIT)
611 | FEATURE_MASK(FEATURE_THERMAL_BIT)
612 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
613 | FEATURE_MASK(FEATURE_RM_BIT)
614 | FEATURE_MASK(FEATURE_ACDC_BIT)
615 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
616 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
617 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
618 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
619 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
620 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
621 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
622 | FEATURE_MASK(FEATURE_CG_BIT)
623 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
624 | FEATURE_MASK(FEATURE_XGMI_BIT);
629 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
631 enum amd_pm_state_type pm_type;
632 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
634 if (!smu_dpm_ctx->dpm_context ||
635 !smu_dpm_ctx->dpm_current_power_state)
638 mutex_lock(&(smu->mutex));
639 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
640 case SMU_STATE_UI_LABEL_BATTERY:
641 pm_type = POWER_STATE_TYPE_BATTERY;
643 case SMU_STATE_UI_LABEL_BALLANCED:
644 pm_type = POWER_STATE_TYPE_BALANCED;
646 case SMU_STATE_UI_LABEL_PERFORMANCE:
647 pm_type = POWER_STATE_TYPE_PERFORMANCE;
650 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
651 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
653 pm_type = POWER_STATE_TYPE_DEFAULT;
656 mutex_unlock(&(smu->mutex));
662 vega20_set_single_dpm_table(struct smu_context *smu,
663 struct vega20_single_dpm_table *single_dpm_table,
667 uint32_t i, num_of_levels = 0, clk;
669 ret = smu_send_smc_msg_with_param(smu,
670 SMU_MSG_GetDpmFreqByIndex,
671 (clk_id << 16 | 0xFF));
673 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
677 smu_read_smc_arg(smu, &num_of_levels);
678 if (!num_of_levels) {
679 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
683 single_dpm_table->count = num_of_levels;
685 for (i = 0; i < num_of_levels; i++) {
686 ret = smu_send_smc_msg_with_param(smu,
687 SMU_MSG_GetDpmFreqByIndex,
690 pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
693 smu_read_smc_arg(smu, &clk);
695 pr_err("[GetDpmFreqByIndex] clk value is invalid!");
698 single_dpm_table->dpm_levels[i].value = clk;
699 single_dpm_table->dpm_levels[i].enabled = true;
704 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
706 dpm_state->soft_min_level = 0x0;
707 dpm_state->soft_max_level = 0xffff;
708 dpm_state->hard_min_level = 0x0;
709 dpm_state->hard_max_level = 0xffff;
712 static int vega20_set_default_dpm_table(struct smu_context *smu)
716 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
717 struct vega20_dpm_table *dpm_table = NULL;
718 struct vega20_single_dpm_table *single_dpm_table;
720 dpm_table = smu_dpm->dpm_context;
723 single_dpm_table = &(dpm_table->soc_table);
725 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
726 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
729 pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
733 single_dpm_table->count = 1;
734 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
736 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
739 single_dpm_table = &(dpm_table->gfx_table);
741 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
742 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
745 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
749 single_dpm_table->count = 1;
750 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
752 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
755 single_dpm_table = &(dpm_table->mem_table);
757 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
758 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
761 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
765 single_dpm_table->count = 1;
766 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
768 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
771 single_dpm_table = &(dpm_table->eclk_table);
773 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
774 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
776 pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
780 single_dpm_table->count = 1;
781 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
783 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
786 single_dpm_table = &(dpm_table->vclk_table);
788 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
789 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
791 pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
795 single_dpm_table->count = 1;
796 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
798 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
801 single_dpm_table = &(dpm_table->dclk_table);
803 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
804 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
806 pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
810 single_dpm_table->count = 1;
811 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
813 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
816 single_dpm_table = &(dpm_table->dcef_table);
818 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
819 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
822 pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
826 single_dpm_table->count = 1;
827 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
829 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
832 single_dpm_table = &(dpm_table->pixel_table);
834 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
835 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
838 pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
842 single_dpm_table->count = 0;
844 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
847 single_dpm_table = &(dpm_table->display_table);
849 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
850 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
853 pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
857 single_dpm_table->count = 0;
859 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
862 single_dpm_table = &(dpm_table->phy_table);
864 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
865 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
868 pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
872 single_dpm_table->count = 0;
874 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
877 single_dpm_table = &(dpm_table->fclk_table);
879 if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
880 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
883 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
887 single_dpm_table->count = 0;
889 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
891 memcpy(smu_dpm->golden_dpm_context, dpm_table,
892 sizeof(struct vega20_dpm_table));
897 static int vega20_populate_umd_state_clk(struct smu_context *smu)
899 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
900 struct vega20_dpm_table *dpm_table = NULL;
901 struct vega20_single_dpm_table *gfx_table = NULL;
902 struct vega20_single_dpm_table *mem_table = NULL;
904 dpm_table = smu_dpm->dpm_context;
905 gfx_table = &(dpm_table->gfx_table);
906 mem_table = &(dpm_table->mem_table);
908 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
909 smu->pstate_mclk = mem_table->dpm_levels[0].value;
911 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
912 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
913 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
914 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
917 smu->pstate_sclk = smu->pstate_sclk * 100;
918 smu->pstate_mclk = smu->pstate_mclk * 100;
923 static int vega20_get_clk_table(struct smu_context *smu,
924 struct pp_clock_levels_with_latency *clocks,
925 struct vega20_single_dpm_table *dpm_table)
929 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
930 clocks->num_levels = count;
932 for (i = 0; i < count; i++) {
933 clocks->data[i].clocks_in_khz =
934 dpm_table->dpm_levels[i].value * 1000;
935 clocks->data[i].latency_in_us = 0;
941 static int vega20_print_clk_levels(struct smu_context *smu,
942 enum smu_clk_type type, char *buf)
944 int i, now, size = 0;
946 uint32_t gen_speed, lane_width;
947 struct amdgpu_device *adev = smu->adev;
948 struct pp_clock_levels_with_latency clocks;
949 struct vega20_single_dpm_table *single_dpm_table;
950 struct smu_table_context *table_context = &smu->smu_table;
951 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
952 struct vega20_dpm_table *dpm_table = NULL;
953 struct vega20_od8_settings *od8_settings =
954 (struct vega20_od8_settings *)smu->od_settings;
955 OverDriveTable_t *od_table =
956 (OverDriveTable_t *)(table_context->overdrive_table);
957 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
959 dpm_table = smu_dpm->dpm_context;
963 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
965 pr_err("Attempt to get current gfx clk Failed!");
969 single_dpm_table = &(dpm_table->gfx_table);
970 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
972 pr_err("Attempt to get gfx clk levels Failed!");
976 for (i = 0; i < clocks.num_levels; i++)
977 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
978 clocks.data[i].clocks_in_khz / 1000,
979 (clocks.data[i].clocks_in_khz == now * 10)
984 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
986 pr_err("Attempt to get current mclk Failed!");
990 single_dpm_table = &(dpm_table->mem_table);
991 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
993 pr_err("Attempt to get memory clk levels Failed!");
997 for (i = 0; i < clocks.num_levels; i++)
998 size += sprintf(buf + size, "%d: %uMhz %s\n",
999 i, clocks.data[i].clocks_in_khz / 1000,
1000 (clocks.data[i].clocks_in_khz == now * 10)
1005 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
1007 pr_err("Attempt to get current socclk Failed!");
1011 single_dpm_table = &(dpm_table->soc_table);
1012 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1014 pr_err("Attempt to get socclk levels Failed!");
1018 for (i = 0; i < clocks.num_levels; i++)
1019 size += sprintf(buf + size, "%d: %uMhz %s\n",
1020 i, clocks.data[i].clocks_in_khz / 1000,
1021 (clocks.data[i].clocks_in_khz == now * 10)
1026 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1028 pr_err("Attempt to get current fclk Failed!");
1032 single_dpm_table = &(dpm_table->fclk_table);
1033 for (i = 0; i < single_dpm_table->count; i++)
1034 size += sprintf(buf + size, "%d: %uMhz %s\n",
1035 i, single_dpm_table->dpm_levels[i].value,
1036 (single_dpm_table->dpm_levels[i].value == now / 100)
1041 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1043 pr_err("Attempt to get current dcefclk Failed!");
1047 single_dpm_table = &(dpm_table->dcef_table);
1048 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1050 pr_err("Attempt to get dcefclk levels Failed!");
1054 for (i = 0; i < clocks.num_levels; i++)
1055 size += sprintf(buf + size, "%d: %uMhz %s\n",
1056 i, clocks.data[i].clocks_in_khz / 1000,
1057 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1061 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1062 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1063 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1064 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1065 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1066 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1067 for (i = 0; i < NUM_LINK_LEVELS; i++)
1068 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1069 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1070 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1071 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1072 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1073 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1074 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1075 (pptable->PcieLaneCount[i] == 3) ? "x4" :
1076 (pptable->PcieLaneCount[i] == 4) ? "x8" :
1077 (pptable->PcieLaneCount[i] == 5) ? "x12" :
1078 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1079 pptable->LclkFreq[i],
1080 (gen_speed == pptable->PcieGenSpeed[i]) &&
1081 (lane_width == pptable->PcieLaneCount[i]) ?
1086 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1087 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1088 size = sprintf(buf, "%s:\n", "OD_SCLK");
1089 size += sprintf(buf + size, "0: %10uMhz\n",
1090 od_table->GfxclkFmin);
1091 size += sprintf(buf + size, "1: %10uMhz\n",
1092 od_table->GfxclkFmax);
1098 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1099 size = sprintf(buf, "%s:\n", "OD_MCLK");
1100 size += sprintf(buf + size, "1: %10uMhz\n",
1101 od_table->UclkFmax);
1106 case SMU_OD_VDDC_CURVE:
1107 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1108 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1109 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1110 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1111 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1112 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1113 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1114 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1115 od_table->GfxclkFreq1,
1116 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1117 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1118 od_table->GfxclkFreq2,
1119 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1120 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1121 od_table->GfxclkFreq3,
1122 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1128 size = sprintf(buf, "%s:\n", "OD_RANGE");
1130 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1131 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1132 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1133 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1134 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1137 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1138 single_dpm_table = &(dpm_table->mem_table);
1139 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1141 pr_err("Attempt to get memory clk levels Failed!");
1145 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1146 clocks.data[0].clocks_in_khz / 1000,
1147 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1150 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1151 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1152 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1153 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1154 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1155 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1156 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1157 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1158 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1159 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1160 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1161 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1162 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1163 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1164 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1165 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1166 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1167 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1168 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1169 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1170 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1171 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1172 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1173 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1184 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1185 uint32_t feature_mask)
1187 struct vega20_dpm_table *dpm_table;
1188 struct vega20_single_dpm_table *single_dpm_table;
1192 dpm_table = smu->smu_dpm.dpm_context;
1194 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1195 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1196 single_dpm_table = &(dpm_table->gfx_table);
1197 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1198 single_dpm_table->dpm_state.soft_min_level;
1199 ret = smu_send_smc_msg_with_param(smu,
1200 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1201 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1203 pr_err("Failed to set soft %s gfxclk !\n",
1204 max ? "max" : "min");
1209 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1210 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1211 single_dpm_table = &(dpm_table->mem_table);
1212 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1213 single_dpm_table->dpm_state.soft_min_level;
1214 ret = smu_send_smc_msg_with_param(smu,
1215 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1216 (PPCLK_UCLK << 16) | (freq & 0xffff));
1218 pr_err("Failed to set soft %s memclk !\n",
1219 max ? "max" : "min");
1224 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1225 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1226 single_dpm_table = &(dpm_table->soc_table);
1227 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1228 single_dpm_table->dpm_state.soft_min_level;
1229 ret = smu_send_smc_msg_with_param(smu,
1230 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1231 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1233 pr_err("Failed to set soft %s socclk !\n",
1234 max ? "max" : "min");
1239 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1240 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1241 single_dpm_table = &(dpm_table->fclk_table);
1242 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1243 single_dpm_table->dpm_state.soft_min_level;
1244 ret = smu_send_smc_msg_with_param(smu,
1245 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1246 (PPCLK_FCLK << 16) | (freq & 0xffff));
1248 pr_err("Failed to set soft %s fclk !\n",
1249 max ? "max" : "min");
1254 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1255 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1256 single_dpm_table = &(dpm_table->dcef_table);
1257 freq = single_dpm_table->dpm_state.hard_min_level;
1259 ret = smu_send_smc_msg_with_param(smu,
1260 SMU_MSG_SetHardMinByFreq,
1261 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1263 pr_err("Failed to set hard min dcefclk !\n");
1272 static int vega20_force_clk_levels(struct smu_context *smu,
1273 enum smu_clk_type clk_type, uint32_t mask)
1275 struct vega20_dpm_table *dpm_table;
1276 struct vega20_single_dpm_table *single_dpm_table;
1277 uint32_t soft_min_level, soft_max_level, hard_min_level;
1278 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1281 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1282 pr_info("force clock level is for dpm manual mode only.\n");
1286 mutex_lock(&(smu->mutex));
1288 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1289 soft_max_level = mask ? (fls(mask) - 1) : 0;
1291 dpm_table = smu->smu_dpm.dpm_context;
1295 single_dpm_table = &(dpm_table->gfx_table);
1297 if (soft_max_level >= single_dpm_table->count) {
1298 pr_err("Clock level specified %d is over max allowed %d\n",
1299 soft_max_level, single_dpm_table->count - 1);
1304 single_dpm_table->dpm_state.soft_min_level =
1305 single_dpm_table->dpm_levels[soft_min_level].value;
1306 single_dpm_table->dpm_state.soft_max_level =
1307 single_dpm_table->dpm_levels[soft_max_level].value;
1309 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1311 pr_err("Failed to upload boot level to lowest!\n");
1315 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1317 pr_err("Failed to upload dpm max level to highest!\n");
1322 single_dpm_table = &(dpm_table->mem_table);
1324 if (soft_max_level >= single_dpm_table->count) {
1325 pr_err("Clock level specified %d is over max allowed %d\n",
1326 soft_max_level, single_dpm_table->count - 1);
1331 single_dpm_table->dpm_state.soft_min_level =
1332 single_dpm_table->dpm_levels[soft_min_level].value;
1333 single_dpm_table->dpm_state.soft_max_level =
1334 single_dpm_table->dpm_levels[soft_max_level].value;
1336 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1338 pr_err("Failed to upload boot level to lowest!\n");
1342 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1344 pr_err("Failed to upload dpm max level to highest!\n");
1349 single_dpm_table = &(dpm_table->soc_table);
1351 if (soft_max_level >= single_dpm_table->count) {
1352 pr_err("Clock level specified %d is over max allowed %d\n",
1353 soft_max_level, single_dpm_table->count - 1);
1358 single_dpm_table->dpm_state.soft_min_level =
1359 single_dpm_table->dpm_levels[soft_min_level].value;
1360 single_dpm_table->dpm_state.soft_max_level =
1361 single_dpm_table->dpm_levels[soft_max_level].value;
1363 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1365 pr_err("Failed to upload boot level to lowest!\n");
1369 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1371 pr_err("Failed to upload dpm max level to highest!\n");
1376 single_dpm_table = &(dpm_table->fclk_table);
1378 if (soft_max_level >= single_dpm_table->count) {
1379 pr_err("Clock level specified %d is over max allowed %d\n",
1380 soft_max_level, single_dpm_table->count - 1);
1385 single_dpm_table->dpm_state.soft_min_level =
1386 single_dpm_table->dpm_levels[soft_min_level].value;
1387 single_dpm_table->dpm_state.soft_max_level =
1388 single_dpm_table->dpm_levels[soft_max_level].value;
1390 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1392 pr_err("Failed to upload boot level to lowest!\n");
1396 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1398 pr_err("Failed to upload dpm max level to highest!\n");
1403 hard_min_level = soft_min_level;
1404 single_dpm_table = &(dpm_table->dcef_table);
1406 if (hard_min_level >= single_dpm_table->count) {
1407 pr_err("Clock level specified %d is over max allowed %d\n",
1408 hard_min_level, single_dpm_table->count - 1);
1413 single_dpm_table->dpm_state.hard_min_level =
1414 single_dpm_table->dpm_levels[hard_min_level].value;
1416 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1418 pr_err("Failed to upload boot level to lowest!\n");
1423 if (soft_min_level >= NUM_LINK_LEVELS ||
1424 soft_max_level >= NUM_LINK_LEVELS) {
1429 ret = smu_send_smc_msg_with_param(smu,
1430 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1432 pr_err("Failed to set min link dpm level!\n");
1440 mutex_unlock(&(smu->mutex));
1444 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1445 enum smu_clk_type clk_type,
1446 struct pp_clock_levels_with_latency *clocks)
1449 struct vega20_single_dpm_table *single_dpm_table;
1450 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1451 struct vega20_dpm_table *dpm_table = NULL;
1453 dpm_table = smu_dpm->dpm_context;
1455 mutex_lock(&smu->mutex);
1459 single_dpm_table = &(dpm_table->gfx_table);
1460 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1463 single_dpm_table = &(dpm_table->mem_table);
1464 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1467 single_dpm_table = &(dpm_table->dcef_table);
1468 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1471 single_dpm_table = &(dpm_table->soc_table);
1472 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1478 mutex_unlock(&smu->mutex);
1482 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1488 ret = smu_send_smc_msg_with_param(smu,
1489 SMU_MSG_GetAVFSVoltageByDpm,
1490 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1492 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1496 smu_read_smc_arg(smu, voltage);
1497 *voltage = *voltage / VOLTAGE_SCALE;
1502 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1504 struct smu_table_context *table_context = &smu->smu_table;
1505 OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1506 struct vega20_od8_settings *od8_settings = NULL;
1507 PPTable_t *smc_pptable = table_context->driver_pptable;
1510 if (smu->od_settings)
1513 od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1518 smu->od_settings = (void *)od8_settings;
1520 ret = vega20_setup_od8_information(smu);
1522 pr_err("Retrieve board OD limits failed!\n");
1526 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1527 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1528 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1529 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1530 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1531 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1532 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1534 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1536 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1537 od_table->GfxclkFmin;
1538 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1539 od_table->GfxclkFmax;
1542 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1543 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1544 smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1545 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1546 smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1547 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1548 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1549 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1551 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1553 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1555 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1557 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1559 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1562 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1563 od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1564 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1565 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1566 od_table->GfxclkFreq1;
1567 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1568 od_table->GfxclkFreq2;
1569 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1570 od_table->GfxclkFreq3;
1572 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1573 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1574 od_table->GfxclkFreq1);
1576 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1577 od_table->GfxclkVolt1 =
1578 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1580 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1581 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1582 od_table->GfxclkFreq2);
1584 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1585 od_table->GfxclkVolt2 =
1586 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1588 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1589 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1590 od_table->GfxclkFreq3);
1592 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1593 od_table->GfxclkVolt3 =
1594 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1599 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1600 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1601 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1602 od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1603 (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1604 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1605 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1607 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1612 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1613 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1614 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1615 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1616 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1617 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1619 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1620 od_table->OverDrivePct;
1623 if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1624 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1625 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1626 od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1627 (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1628 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1629 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1630 OD8_ACOUSTIC_LIMIT_SCLK;
1631 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1632 od_table->FanMaximumRpm;
1635 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1636 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1637 od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1638 (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1639 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1640 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1642 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1643 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1647 if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1648 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1649 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1650 od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1651 (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1652 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1653 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1654 OD8_TEMPERATURE_FAN;
1655 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1656 od_table->FanTargetTemperature;
1659 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1660 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1661 od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1662 (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1663 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1664 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1665 OD8_TEMPERATURE_SYSTEM;
1666 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1667 od_table->MaxOpTemp;
1671 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1672 if (od8_settings->od8_settings_array[i].feature_id) {
1673 od8_settings->od8_settings_array[i].min_value =
1674 od8_settings->od_settings_min[i];
1675 od8_settings->od8_settings_array[i].max_value =
1676 od8_settings->od_settings_max[i];
1677 od8_settings->od8_settings_array[i].current_value =
1678 od8_settings->od8_settings_array[i].default_value;
1680 od8_settings->od8_settings_array[i].min_value = 0;
1681 od8_settings->od8_settings_array[i].max_value = 0;
1682 od8_settings->od8_settings_array[i].current_value = 0;
1689 static int vega20_get_metrics_table(struct smu_context *smu,
1690 SmuMetrics_t *metrics_table)
1692 struct smu_table_context *smu_table= &smu->smu_table;
1695 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1696 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1697 (void *)smu_table->metrics_table, false);
1699 pr_info("Failed to export SMU metrics table!\n");
1702 smu_table->metrics_time = jiffies;
1705 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1710 static int vega20_set_default_od_settings(struct smu_context *smu,
1713 struct smu_table_context *table_context = &smu->smu_table;
1717 if (table_context->overdrive_table)
1720 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1722 if (!table_context->overdrive_table)
1725 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1726 table_context->overdrive_table, false);
1728 pr_err("Failed to export over drive table!\n");
1732 ret = vega20_set_default_od8_setttings(smu);
1737 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1738 table_context->overdrive_table, true);
1740 pr_err("Failed to import over drive table!\n");
1747 static int vega20_get_od_percentage(struct smu_context *smu,
1748 enum smu_clk_type clk_type)
1750 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1751 struct vega20_dpm_table *dpm_table = NULL;
1752 struct vega20_dpm_table *golden_table = NULL;
1753 struct vega20_single_dpm_table *single_dpm_table;
1754 struct vega20_single_dpm_table *golden_dpm_table;
1755 int value, golden_value;
1757 dpm_table = smu_dpm->dpm_context;
1758 golden_table = smu_dpm->golden_dpm_context;
1762 single_dpm_table = &(dpm_table->gfx_table);
1763 golden_dpm_table = &(golden_table->gfx_table);
1766 single_dpm_table = &(dpm_table->mem_table);
1767 golden_dpm_table = &(golden_table->mem_table);
1774 value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1775 golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1777 value -= golden_value;
1778 value = DIV_ROUND_UP(value * 100, golden_value);
1783 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1785 DpmActivityMonitorCoeffInt_t activity_monitor;
1786 uint32_t i, size = 0;
1787 int16_t workload_type = 0;
1788 static const char *profile_name[] = {
1796 static const char *title[] = {
1797 "PROFILE_INDEX(NAME)",
1801 "MinActiveFreqType",
1806 "PD_Data_error_coeff",
1807 "PD_Data_error_rate_coeff"};
1810 if (!smu->pm_enabled || !buf)
1813 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1814 title[0], title[1], title[2], title[3], title[4], title[5],
1815 title[6], title[7], title[8], title[9], title[10]);
1817 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1818 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1819 workload_type = smu_workload_get_type(smu, i);
1820 if (workload_type < 0)
1823 result = smu_update_table(smu,
1824 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1825 (void *)(&activity_monitor), false);
1827 pr_err("[%s] Failed to get activity monitor!", __func__);
1831 size += sprintf(buf + size, "%2d %14s%s:\n",
1832 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1834 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1838 activity_monitor.Gfx_FPS,
1839 activity_monitor.Gfx_UseRlcBusy,
1840 activity_monitor.Gfx_MinActiveFreqType,
1841 activity_monitor.Gfx_MinActiveFreq,
1842 activity_monitor.Gfx_BoosterFreqType,
1843 activity_monitor.Gfx_BoosterFreq,
1844 activity_monitor.Gfx_PD_Data_limit_c,
1845 activity_monitor.Gfx_PD_Data_error_coeff,
1846 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1848 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1852 activity_monitor.Soc_FPS,
1853 activity_monitor.Soc_UseRlcBusy,
1854 activity_monitor.Soc_MinActiveFreqType,
1855 activity_monitor.Soc_MinActiveFreq,
1856 activity_monitor.Soc_BoosterFreqType,
1857 activity_monitor.Soc_BoosterFreq,
1858 activity_monitor.Soc_PD_Data_limit_c,
1859 activity_monitor.Soc_PD_Data_error_coeff,
1860 activity_monitor.Soc_PD_Data_error_rate_coeff);
1862 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1866 activity_monitor.Mem_FPS,
1867 activity_monitor.Mem_UseRlcBusy,
1868 activity_monitor.Mem_MinActiveFreqType,
1869 activity_monitor.Mem_MinActiveFreq,
1870 activity_monitor.Mem_BoosterFreqType,
1871 activity_monitor.Mem_BoosterFreq,
1872 activity_monitor.Mem_PD_Data_limit_c,
1873 activity_monitor.Mem_PD_Data_error_coeff,
1874 activity_monitor.Mem_PD_Data_error_rate_coeff);
1876 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1880 activity_monitor.Fclk_FPS,
1881 activity_monitor.Fclk_UseRlcBusy,
1882 activity_monitor.Fclk_MinActiveFreqType,
1883 activity_monitor.Fclk_MinActiveFreq,
1884 activity_monitor.Fclk_BoosterFreqType,
1885 activity_monitor.Fclk_BoosterFreq,
1886 activity_monitor.Fclk_PD_Data_limit_c,
1887 activity_monitor.Fclk_PD_Data_error_coeff,
1888 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1894 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1896 DpmActivityMonitorCoeffInt_t activity_monitor;
1897 int workload_type = 0, ret = 0;
1899 smu->power_profile_mode = input[size];
1901 if (!smu->pm_enabled)
1903 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1904 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1908 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1909 ret = smu_update_table(smu,
1910 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1911 (void *)(&activity_monitor), false);
1913 pr_err("[%s] Failed to get activity monitor!", __func__);
1918 case 0: /* Gfxclk */
1919 activity_monitor.Gfx_FPS = input[1];
1920 activity_monitor.Gfx_UseRlcBusy = input[2];
1921 activity_monitor.Gfx_MinActiveFreqType = input[3];
1922 activity_monitor.Gfx_MinActiveFreq = input[4];
1923 activity_monitor.Gfx_BoosterFreqType = input[5];
1924 activity_monitor.Gfx_BoosterFreq = input[6];
1925 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1926 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1927 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1929 case 1: /* Socclk */
1930 activity_monitor.Soc_FPS = input[1];
1931 activity_monitor.Soc_UseRlcBusy = input[2];
1932 activity_monitor.Soc_MinActiveFreqType = input[3];
1933 activity_monitor.Soc_MinActiveFreq = input[4];
1934 activity_monitor.Soc_BoosterFreqType = input[5];
1935 activity_monitor.Soc_BoosterFreq = input[6];
1936 activity_monitor.Soc_PD_Data_limit_c = input[7];
1937 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1938 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1941 activity_monitor.Mem_FPS = input[1];
1942 activity_monitor.Mem_UseRlcBusy = input[2];
1943 activity_monitor.Mem_MinActiveFreqType = input[3];
1944 activity_monitor.Mem_MinActiveFreq = input[4];
1945 activity_monitor.Mem_BoosterFreqType = input[5];
1946 activity_monitor.Mem_BoosterFreq = input[6];
1947 activity_monitor.Mem_PD_Data_limit_c = input[7];
1948 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1949 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1952 activity_monitor.Fclk_FPS = input[1];
1953 activity_monitor.Fclk_UseRlcBusy = input[2];
1954 activity_monitor.Fclk_MinActiveFreqType = input[3];
1955 activity_monitor.Fclk_MinActiveFreq = input[4];
1956 activity_monitor.Fclk_BoosterFreqType = input[5];
1957 activity_monitor.Fclk_BoosterFreq = input[6];
1958 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1959 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1960 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1964 ret = smu_update_table(smu,
1965 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1966 (void *)(&activity_monitor), true);
1968 pr_err("[%s] Failed to set activity monitor!", __func__);
1973 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1974 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1975 if (workload_type < 0)
1977 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1978 1 << workload_type);
1984 vega20_get_profiling_clk_mask(struct smu_context *smu,
1985 enum amd_dpm_forced_level level,
1986 uint32_t *sclk_mask,
1987 uint32_t *mclk_mask,
1990 struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1991 struct vega20_single_dpm_table *gfx_dpm_table;
1992 struct vega20_single_dpm_table *mem_dpm_table;
1993 struct vega20_single_dpm_table *soc_dpm_table;
1995 if (!smu->smu_dpm.dpm_context)
1998 gfx_dpm_table = &dpm_table->gfx_table;
1999 mem_dpm_table = &dpm_table->mem_table;
2000 soc_dpm_table = &dpm_table->soc_table;
2006 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2007 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2008 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2009 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2010 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2011 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2014 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2016 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2018 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2019 *sclk_mask = gfx_dpm_table->count - 1;
2020 *mclk_mask = mem_dpm_table->count - 1;
2021 *soc_mask = soc_dpm_table->count - 1;
2028 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2029 struct vega20_single_dpm_table *dpm_table)
2032 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2033 if (!smu_dpm_ctx->dpm_context)
2036 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2037 if (dpm_table->count <= 0) {
2038 pr_err("[%s] Dpm table has no entry!", __func__);
2042 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2043 pr_err("[%s] Dpm table has too many entries!", __func__);
2047 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2048 ret = smu_send_smc_msg_with_param(smu,
2049 SMU_MSG_SetHardMinByFreq,
2050 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2052 pr_err("[%s] Set hard min uclk failed!", __func__);
2060 static int vega20_pre_display_config_changed(struct smu_context *smu)
2063 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2065 if (!smu->smu_dpm.dpm_context)
2068 smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2069 ret = vega20_set_uclk_to_highest_dpm_level(smu,
2070 &dpm_table->mem_table);
2072 pr_err("Failed to set uclk to highest dpm level");
2076 static int vega20_display_config_changed(struct smu_context *smu)
2080 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2081 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2082 ret = smu_write_watermarks_table(smu);
2084 pr_err("Failed to update WMTABLE!");
2087 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2090 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2091 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2092 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2093 smu_send_smc_msg_with_param(smu,
2094 SMU_MSG_NumOfDisplays,
2095 smu->display_config->num_display);
2101 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2103 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2104 struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2105 struct vega20_single_dpm_table *dpm_table;
2106 bool vblank_too_short = false;
2107 bool disable_mclk_switching;
2108 uint32_t i, latency;
2110 disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2111 !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2112 latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2115 dpm_table = &(dpm_ctx->gfx_table);
2116 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2117 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2118 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2119 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2121 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2122 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2123 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2126 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2127 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2128 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2131 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2132 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2133 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2137 dpm_table = &(dpm_ctx->mem_table);
2138 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2139 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2140 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2141 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2143 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2144 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2145 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2148 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2149 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2150 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2153 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2154 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2155 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2158 /* honour DAL's UCLK Hardmin */
2159 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2160 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2162 /* Hardmin is dependent on displayconfig */
2163 if (disable_mclk_switching) {
2164 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2165 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2166 if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2167 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2168 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2175 if (smu->display_config->nb_pstate_switch_disable)
2176 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2179 dpm_table = &(dpm_ctx->vclk_table);
2180 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2181 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2182 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2183 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2185 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2186 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2187 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2190 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2191 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2192 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2196 dpm_table = &(dpm_ctx->dclk_table);
2197 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2198 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2199 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2200 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2202 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2203 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2204 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2207 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2208 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2209 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2213 dpm_table = &(dpm_ctx->soc_table);
2214 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2215 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2216 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2217 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2219 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2220 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2221 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2224 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2225 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2226 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2230 dpm_table = &(dpm_ctx->eclk_table);
2231 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2232 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2233 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2234 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2236 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2237 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2238 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2241 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2242 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2243 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2249 vega20_notify_smc_dispaly_config(struct smu_context *smu)
2251 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2252 struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2253 struct smu_clocks min_clocks = {0};
2254 struct pp_display_clock_request clock_req;
2257 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2258 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2259 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2261 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2262 clock_req.clock_type = amd_pp_dcef_clock;
2263 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2264 if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
2265 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2266 ret = smu_send_smc_msg_with_param(smu,
2267 SMU_MSG_SetMinDeepSleepDcefclk,
2268 min_clocks.dcef_clock_in_sr/100);
2270 pr_err("Attempt to set divider for DCEFCLK Failed!");
2275 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2279 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2280 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2281 ret = smu_send_smc_msg_with_param(smu,
2282 SMU_MSG_SetHardMinByFreq,
2283 (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2285 pr_err("[%s] Set hard min uclk failed!", __func__);
2293 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2297 for (i = 0; i < table->count; i++) {
2298 if (table->dpm_levels[i].enabled)
2301 if (i >= table->count) {
2303 table->dpm_levels[i].enabled = true;
2309 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2314 pr_err("[%s] DPM Table does not exist!", __func__);
2317 if (table->count <= 0) {
2318 pr_err("[%s] DPM Table has no entry!", __func__);
2321 if (table->count > MAX_REGULAR_DPM_NUMBER) {
2322 pr_err("[%s] DPM Table has too many entries!", __func__);
2323 return MAX_REGULAR_DPM_NUMBER - 1;
2326 for (i = table->count - 1; i >= 0; i--) {
2327 if (table->dpm_levels[i].enabled)
2332 table->dpm_levels[i].enabled = true;
2338 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2340 uint32_t soft_level;
2342 struct vega20_dpm_table *dpm_table =
2343 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2346 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2348 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2350 dpm_table->gfx_table.dpm_state.soft_min_level =
2351 dpm_table->gfx_table.dpm_state.soft_max_level =
2352 dpm_table->gfx_table.dpm_levels[soft_level].value;
2355 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2357 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2359 dpm_table->mem_table.dpm_state.soft_min_level =
2360 dpm_table->mem_table.dpm_state.soft_max_level =
2361 dpm_table->mem_table.dpm_levels[soft_level].value;
2364 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2366 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2368 dpm_table->soc_table.dpm_state.soft_min_level =
2369 dpm_table->soc_table.dpm_state.soft_max_level =
2370 dpm_table->soc_table.dpm_levels[soft_level].value;
2372 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2374 pr_err("Failed to upload boot level to %s!\n",
2375 highest ? "highest" : "lowest");
2379 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2381 pr_err("Failed to upload dpm max level to %s!\n!",
2382 highest ? "highest" : "lowest");
2389 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2391 uint32_t soft_min_level, soft_max_level;
2393 struct vega20_dpm_table *dpm_table =
2394 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2396 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2397 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2398 dpm_table->gfx_table.dpm_state.soft_min_level =
2399 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2400 dpm_table->gfx_table.dpm_state.soft_max_level =
2401 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2403 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2404 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2405 dpm_table->mem_table.dpm_state.soft_min_level =
2406 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2407 dpm_table->mem_table.dpm_state.soft_max_level =
2408 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2410 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2411 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2412 dpm_table->soc_table.dpm_state.soft_min_level =
2413 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2414 dpm_table->soc_table.dpm_state.soft_max_level =
2415 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2417 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2419 pr_err("Failed to upload DPM Bootup Levels!");
2423 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2425 pr_err("Failed to upload DPM Max Levels!");
2432 static int vega20_update_specified_od8_value(struct smu_context *smu,
2436 struct smu_table_context *table_context = &smu->smu_table;
2437 OverDriveTable_t *od_table =
2438 (OverDriveTable_t *)(table_context->overdrive_table);
2439 struct vega20_od8_settings *od8_settings =
2440 (struct vega20_od8_settings *)smu->od_settings;
2443 case OD8_SETTING_GFXCLK_FMIN:
2444 od_table->GfxclkFmin = (uint16_t)value;
2447 case OD8_SETTING_GFXCLK_FMAX:
2448 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2449 value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2451 od_table->GfxclkFmax = (uint16_t)value;
2454 case OD8_SETTING_GFXCLK_FREQ1:
2455 od_table->GfxclkFreq1 = (uint16_t)value;
2458 case OD8_SETTING_GFXCLK_VOLTAGE1:
2459 od_table->GfxclkVolt1 = (uint16_t)value;
2462 case OD8_SETTING_GFXCLK_FREQ2:
2463 od_table->GfxclkFreq2 = (uint16_t)value;
2466 case OD8_SETTING_GFXCLK_VOLTAGE2:
2467 od_table->GfxclkVolt2 = (uint16_t)value;
2470 case OD8_SETTING_GFXCLK_FREQ3:
2471 od_table->GfxclkFreq3 = (uint16_t)value;
2474 case OD8_SETTING_GFXCLK_VOLTAGE3:
2475 od_table->GfxclkVolt3 = (uint16_t)value;
2478 case OD8_SETTING_UCLK_FMAX:
2479 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2480 value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2482 od_table->UclkFmax = (uint16_t)value;
2485 case OD8_SETTING_POWER_PERCENTAGE:
2486 od_table->OverDrivePct = (int16_t)value;
2489 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2490 od_table->FanMaximumRpm = (uint16_t)value;
2493 case OD8_SETTING_FAN_MIN_SPEED:
2494 od_table->FanMinimumPwm = (uint16_t)value;
2497 case OD8_SETTING_FAN_TARGET_TEMP:
2498 od_table->FanTargetTemperature = (uint16_t)value;
2501 case OD8_SETTING_OPERATING_TEMP_MAX:
2502 od_table->MaxOpTemp = (uint16_t)value;
2509 static int vega20_update_od8_settings(struct smu_context *smu,
2513 struct smu_table_context *table_context = &smu->smu_table;
2516 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2517 table_context->overdrive_table, false);
2519 pr_err("Failed to export over drive table!\n");
2523 ret = vega20_update_specified_od8_value(smu, index, value);
2527 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2528 table_context->overdrive_table, true);
2530 pr_err("Failed to import over drive table!\n");
2537 static int vega20_set_od_percentage(struct smu_context *smu,
2538 enum smu_clk_type clk_type,
2541 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2542 struct vega20_dpm_table *dpm_table = NULL;
2543 struct vega20_dpm_table *golden_table = NULL;
2544 struct vega20_single_dpm_table *single_dpm_table;
2545 struct vega20_single_dpm_table *golden_dpm_table;
2546 uint32_t od_clk, index;
2548 int feature_enabled;
2551 mutex_lock(&(smu->mutex));
2553 dpm_table = smu_dpm->dpm_context;
2554 golden_table = smu_dpm->golden_dpm_context;
2558 single_dpm_table = &(dpm_table->gfx_table);
2559 golden_dpm_table = &(golden_table->gfx_table);
2560 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2561 clk_id = PPCLK_GFXCLK;
2562 index = OD8_SETTING_GFXCLK_FMAX;
2565 single_dpm_table = &(dpm_table->mem_table);
2566 golden_dpm_table = &(golden_table->mem_table);
2567 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2568 clk_id = PPCLK_UCLK;
2569 index = OD8_SETTING_UCLK_FMAX;
2579 od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2581 od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2583 ret = vega20_update_od8_settings(smu, index, od_clk);
2585 pr_err("[Setoverdrive] failed to set od clk!\n");
2589 if (feature_enabled) {
2590 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2593 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2597 single_dpm_table->count = 1;
2598 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2601 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2602 AMD_PP_TASK_READJUST_POWER_STATE);
2605 mutex_unlock(&(smu->mutex));
2610 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2611 enum PP_OD_DPM_TABLE_COMMAND type,
2612 long *input, uint32_t size)
2614 struct smu_table_context *table_context = &smu->smu_table;
2615 OverDriveTable_t *od_table =
2616 (OverDriveTable_t *)(table_context->overdrive_table);
2617 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2618 struct vega20_dpm_table *dpm_table = NULL;
2619 struct vega20_single_dpm_table *single_dpm_table;
2620 struct vega20_od8_settings *od8_settings =
2621 (struct vega20_od8_settings *)smu->od_settings;
2622 struct pp_clock_levels_with_latency clocks;
2623 int32_t input_index, input_clk, input_vol, i;
2627 dpm_table = smu_dpm->dpm_context;
2630 pr_warn("NULL user input for clock and voltage\n");
2635 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2636 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2637 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2638 pr_info("Sclk min/max frequency overdrive not supported\n");
2642 for (i = 0; i < size; i += 2) {
2644 pr_info("invalid number of input parameters %d\n", size);
2648 input_index = input[i];
2649 input_clk = input[i + 1];
2651 if (input_index != 0 && input_index != 1) {
2652 pr_info("Invalid index %d\n", input_index);
2653 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2657 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2658 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2659 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2661 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2662 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2666 if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2667 od_table->GfxclkFmin = input_clk;
2668 od8_settings->od_gfxclk_update = true;
2669 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2670 od_table->GfxclkFmax = input_clk;
2671 od8_settings->od_gfxclk_update = true;
2677 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2678 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2679 pr_info("Mclk max frequency overdrive not supported\n");
2683 single_dpm_table = &(dpm_table->mem_table);
2684 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2686 pr_err("Attempt to get memory clk levels Failed!");
2690 for (i = 0; i < size; i += 2) {
2692 pr_info("invalid number of input parameters %d\n",
2697 input_index = input[i];
2698 input_clk = input[i + 1];
2700 if (input_index != 1) {
2701 pr_info("Invalid index %d\n", input_index);
2702 pr_info("Support max Mclk frequency setting only which index by 1\n");
2706 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2707 input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2708 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2710 clocks.data[0].clocks_in_khz / 1000,
2711 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2715 if (input_index == 1 && od_table->UclkFmax != input_clk) {
2716 od8_settings->od_gfxclk_update = true;
2717 od_table->UclkFmax = input_clk;
2723 case PP_OD_EDIT_VDDC_CURVE:
2724 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2725 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2726 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2727 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2728 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2729 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2730 pr_info("Voltage curve calibrate not supported\n");
2734 for (i = 0; i < size; i += 3) {
2736 pr_info("invalid number of input parameters %d\n",
2741 input_index = input[i];
2742 input_clk = input[i + 1];
2743 input_vol = input[i + 2];
2745 if (input_index > 2) {
2746 pr_info("Setting for point %d is not supported\n",
2748 pr_info("Three supported points index by 0, 1, 2\n");
2752 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2753 if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2754 input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2755 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2757 od8_settings->od8_settings_array[od8_id].min_value,
2758 od8_settings->od8_settings_array[od8_id].max_value);
2762 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2763 if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2764 input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2765 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2767 od8_settings->od8_settings_array[od8_id].min_value,
2768 od8_settings->od8_settings_array[od8_id].max_value);
2772 switch (input_index) {
2774 od_table->GfxclkFreq1 = input_clk;
2775 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2778 od_table->GfxclkFreq2 = input_clk;
2779 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2782 od_table->GfxclkFreq3 = input_clk;
2783 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2790 case PP_OD_RESTORE_DEFAULT_TABLE:
2791 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
2793 pr_err("Failed to export over drive table!\n");
2799 case PP_OD_COMMIT_DPM_TABLE:
2800 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
2802 pr_err("Failed to import over drive table!\n");
2806 /* retrieve updated gfxclk table */
2807 if (od8_settings->od_gfxclk_update) {
2808 od8_settings->od_gfxclk_update = false;
2809 single_dpm_table = &(dpm_table->gfx_table);
2811 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2812 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2815 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2819 single_dpm_table->count = 1;
2820 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2830 if (type == PP_OD_COMMIT_DPM_TABLE) {
2831 mutex_lock(&(smu->mutex));
2832 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2833 AMD_PP_TASK_READJUST_POWER_STATE);
2834 mutex_unlock(&(smu->mutex));
2840 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2842 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2845 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2848 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2851 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2853 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2856 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2859 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2862 static int vega20_get_enabled_smc_features(struct smu_context *smu,
2863 uint64_t *features_enabled)
2865 uint32_t feature_mask[2] = {0, 0};
2868 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2872 *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
2873 (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
2878 static int vega20_enable_smc_features(struct smu_context *smu,
2879 bool enable, uint64_t feature_mask)
2881 uint32_t smu_features_low, smu_features_high;
2884 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
2885 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
2888 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
2892 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
2897 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
2901 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
2911 static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
2913 static const char *ppfeature_name[] = {
2948 static const char *output_title[] = {
2952 uint64_t features_enabled;
2957 ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2961 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2962 size += sprintf(buf + size, "%-19s %-22s %s\n",
2966 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2967 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
2970 (features_enabled & (1ULL << i)) ? "Y" : "N");
2976 static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
2978 uint64_t features_enabled;
2979 uint64_t features_to_enable;
2980 uint64_t features_to_disable;
2983 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2986 ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2990 features_to_disable =
2991 features_enabled & ~new_ppfeature_masks;
2992 features_to_enable =
2993 ~features_enabled & new_ppfeature_masks;
2995 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2996 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2998 if (features_to_disable) {
2999 ret = vega20_enable_smc_features(smu, false, features_to_disable);
3004 if (features_to_enable) {
3005 ret = vega20_enable_smc_features(smu, true, features_to_enable);
3013 static bool vega20_is_dpm_running(struct smu_context *smu)
3016 uint32_t feature_mask[2];
3017 unsigned long feature_enabled;
3018 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
3019 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
3020 ((uint64_t)feature_mask[1] << 32));
3021 return !!(feature_enabled & SMC_DPM_FEATURE);
3024 static int vega20_set_thermal_fan_table(struct smu_context *smu)
3027 struct smu_table_context *table_context = &smu->smu_table;
3028 PPTable_t *pptable = table_context->driver_pptable;
3030 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
3031 (uint32_t)pptable->FanTargetTemperature);
3036 static int vega20_get_fan_speed_percent(struct smu_context *smu,
3040 uint32_t current_rpm = 0, percent = 0;
3041 PPTable_t *pptable = smu->smu_table.driver_pptable;
3043 ret = smu_get_current_rpm(smu, ¤t_rpm);
3047 percent = current_rpm * 100 / pptable->FanMaximumRpm;
3048 *speed = percent > 100 ? 100 : percent;
3053 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
3056 SmuMetrics_t metrics;
3061 ret = vega20_get_metrics_table(smu, &metrics);
3065 *value = metrics.CurrSocketPower << 8;
3070 static int vega20_get_current_activity_percent(struct smu_context *smu,
3071 enum amd_pp_sensors sensor,
3075 SmuMetrics_t metrics;
3080 ret = vega20_get_metrics_table(smu, &metrics);
3085 case AMDGPU_PP_SENSOR_GPU_LOAD:
3086 *value = metrics.AverageGfxActivity;
3088 case AMDGPU_PP_SENSOR_MEM_LOAD:
3089 *value = metrics.AverageUclkActivity;
3092 pr_err("Invalid sensor for retrieving clock activity\n");
3099 static int vega20_thermal_get_temperature(struct smu_context *smu,
3100 enum amd_pp_sensors sensor,
3103 struct amdgpu_device *adev = smu->adev;
3104 SmuMetrics_t metrics;
3111 ret = vega20_get_metrics_table(smu, &metrics);
3116 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3117 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
3118 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
3119 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
3121 temp = temp & 0x1ff;
3122 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3126 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3127 *value = metrics.TemperatureEdge *
3128 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3130 case AMDGPU_PP_SENSOR_MEM_TEMP:
3131 *value = metrics.TemperatureHBM *
3132 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3135 pr_err("Invalid sensor for retrieving temp\n");
3141 static int vega20_read_sensor(struct smu_context *smu,
3142 enum amd_pp_sensors sensor,
3143 void *data, uint32_t *size)
3146 struct smu_table_context *table_context = &smu->smu_table;
3147 PPTable_t *pptable = table_context->driver_pptable;
3150 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3151 *(uint32_t *)data = pptable->FanMaximumRpm;
3154 case AMDGPU_PP_SENSOR_MEM_LOAD:
3155 case AMDGPU_PP_SENSOR_GPU_LOAD:
3156 ret = vega20_get_current_activity_percent(smu,
3161 case AMDGPU_PP_SENSOR_GPU_POWER:
3162 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3165 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3166 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3167 case AMDGPU_PP_SENSOR_MEM_TEMP:
3168 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3178 static int vega20_set_watermarks_table(struct smu_context *smu,
3179 void *watermarks, struct
3180 dm_pp_wm_sets_with_clock_ranges_soc15
3184 Watermarks_t *table = watermarks;
3186 if (!table || !clock_ranges)
3189 if (clock_ranges->num_wm_dmif_sets > 4 ||
3190 clock_ranges->num_wm_mcif_sets > 4)
3193 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3194 table->WatermarkRow[1][i].MinClock =
3195 cpu_to_le16((uint16_t)
3196 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3198 table->WatermarkRow[1][i].MaxClock =
3199 cpu_to_le16((uint16_t)
3200 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3202 table->WatermarkRow[1][i].MinUclk =
3203 cpu_to_le16((uint16_t)
3204 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3206 table->WatermarkRow[1][i].MaxUclk =
3207 cpu_to_le16((uint16_t)
3208 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3210 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3211 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3214 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3215 table->WatermarkRow[0][i].MinClock =
3216 cpu_to_le16((uint16_t)
3217 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3219 table->WatermarkRow[0][i].MaxClock =
3220 cpu_to_le16((uint16_t)
3221 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3223 table->WatermarkRow[0][i].MinUclk =
3224 cpu_to_le16((uint16_t)
3225 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3227 table->WatermarkRow[0][i].MaxUclk =
3228 cpu_to_le16((uint16_t)
3229 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3231 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3232 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3238 static const struct smu_temperature_range vega20_thermal_policy[] =
3240 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
3241 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
3244 static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3245 struct smu_temperature_range *range)
3248 PPTable_t *pptable = smu->smu_table.driver_pptable;
3253 memcpy(range, &vega20_thermal_policy[0], sizeof(struct smu_temperature_range));
3255 range->max = pptable->TedgeLimit *
3256 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3257 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
3258 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3259 range->hotspot_crit_max = pptable->ThotspotLimit *
3260 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3261 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
3262 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3263 range->mem_crit_max = pptable->ThbmLimit *
3264 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3265 range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
3266 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3272 static const struct pptable_funcs vega20_ppt_funcs = {
3273 .tables_init = vega20_tables_init,
3274 .alloc_dpm_context = vega20_allocate_dpm_context,
3275 .store_powerplay_table = vega20_store_powerplay_table,
3276 .check_powerplay_table = vega20_check_powerplay_table,
3277 .append_powerplay_table = vega20_append_powerplay_table,
3278 .get_smu_msg_index = vega20_get_smu_msg_index,
3279 .get_smu_clk_index = vega20_get_smu_clk_index,
3280 .get_smu_feature_index = vega20_get_smu_feature_index,
3281 .get_smu_table_index = vega20_get_smu_table_index,
3282 .get_smu_power_index = vega20_get_pwr_src_index,
3283 .get_workload_type = vega20_get_workload_type,
3284 .run_afll_btc = vega20_run_btc_afll,
3285 .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3286 .get_current_power_state = vega20_get_current_power_state,
3287 .set_default_dpm_table = vega20_set_default_dpm_table,
3288 .set_power_state = NULL,
3289 .populate_umd_state_clk = vega20_populate_umd_state_clk,
3290 .print_clk_levels = vega20_print_clk_levels,
3291 .force_clk_levels = vega20_force_clk_levels,
3292 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3293 .get_od_percentage = vega20_get_od_percentage,
3294 .get_power_profile_mode = vega20_get_power_profile_mode,
3295 .set_power_profile_mode = vega20_set_power_profile_mode,
3296 .set_od_percentage = vega20_set_od_percentage,
3297 .set_default_od_settings = vega20_set_default_od_settings,
3298 .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3299 .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3300 .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3301 .read_sensor = vega20_read_sensor,
3302 .pre_display_config_changed = vega20_pre_display_config_changed,
3303 .display_config_changed = vega20_display_config_changed,
3304 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3305 .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
3306 .force_dpm_limit_value = vega20_force_dpm_limit_value,
3307 .unforce_dpm_levels = vega20_unforce_dpm_levels,
3308 .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3309 .set_ppfeature_status = vega20_set_ppfeature_status,
3310 .get_ppfeature_status = vega20_get_ppfeature_status,
3311 .is_dpm_running = vega20_is_dpm_running,
3312 .set_thermal_fan_table = vega20_set_thermal_fan_table,
3313 .get_fan_speed_percent = vega20_get_fan_speed_percent,
3314 .set_watermarks_table = vega20_set_watermarks_table,
3315 .get_thermal_temperature_range = vega20_get_thermal_temperature_range
3318 void vega20_set_ppt_funcs(struct smu_context *smu)
3320 struct smu_table_context *smu_table = &smu->smu_table;
3322 smu->ppt_funcs = &vega20_ppt_funcs;
3323 smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
3324 smu_table->table_count = TABLE_COUNT;