2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "atomfirmware.h"
29 #include "amdgpu_atomfirmware.h"
30 #include "smu_v11_0.h"
31 #include "smu11_driver_if.h"
32 #include "soc15_common.h"
34 #include "power_state.h"
35 #include "vega20_ppt.h"
36 #include "vega20_pptable.h"
37 #include "vega20_ppsmc.h"
38 #include "nbio/nbio_7_4_sh_mask.h"
39 #include "asic_reg/thm/thm_11_0_2_offset.h"
40 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
42 #define smnPCIE_LC_SPEED_CNTL 0x11140290
43 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
45 #define CTF_OFFSET_EDGE 5
46 #define CTF_OFFSET_HOTSPOT 5
47 #define CTF_OFFSET_HBM 5
49 #define MSG_MAP(msg) \
50 [SMU_MSG_##msg] = PPSMC_MSG_##msg
52 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
53 FEATURE_DPM_GFXCLK_MASK | \
54 FEATURE_DPM_UCLK_MASK | \
55 FEATURE_DPM_SOCCLK_MASK | \
56 FEATURE_DPM_UVD_MASK | \
57 FEATURE_DPM_VCE_MASK | \
58 FEATURE_DPM_MP0CLK_MASK | \
59 FEATURE_DPM_LINK_MASK | \
60 FEATURE_DPM_DCEFCLK_MASK)
62 static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
64 MSG_MAP(GetSmuVersion),
65 MSG_MAP(GetDriverIfVersion),
66 MSG_MAP(SetAllowedFeaturesMaskLow),
67 MSG_MAP(SetAllowedFeaturesMaskHigh),
68 MSG_MAP(EnableAllSmuFeatures),
69 MSG_MAP(DisableAllSmuFeatures),
70 MSG_MAP(EnableSmuFeaturesLow),
71 MSG_MAP(EnableSmuFeaturesHigh),
72 MSG_MAP(DisableSmuFeaturesLow),
73 MSG_MAP(DisableSmuFeaturesHigh),
74 MSG_MAP(GetEnabledSmuFeaturesLow),
75 MSG_MAP(GetEnabledSmuFeaturesHigh),
76 MSG_MAP(SetWorkloadMask),
78 MSG_MAP(SetDriverDramAddrHigh),
79 MSG_MAP(SetDriverDramAddrLow),
80 MSG_MAP(SetToolsDramAddrHigh),
81 MSG_MAP(SetToolsDramAddrLow),
82 MSG_MAP(TransferTableSmu2Dram),
83 MSG_MAP(TransferTableDram2Smu),
84 MSG_MAP(UseDefaultPPTable),
85 MSG_MAP(UseBackupPPTable),
87 MSG_MAP(RequestI2CBus),
88 MSG_MAP(ReleaseI2CBus),
89 MSG_MAP(SetFloorSocVoltage),
91 MSG_MAP(StartBacoMonitor),
92 MSG_MAP(CancelBacoMonitor),
94 MSG_MAP(SetSoftMinByFreq),
95 MSG_MAP(SetSoftMaxByFreq),
96 MSG_MAP(SetHardMinByFreq),
97 MSG_MAP(SetHardMaxByFreq),
98 MSG_MAP(GetMinDpmFreq),
99 MSG_MAP(GetMaxDpmFreq),
100 MSG_MAP(GetDpmFreqByIndex),
101 MSG_MAP(GetDpmClockFreq),
102 MSG_MAP(GetSsVoltageByDpm),
103 MSG_MAP(SetMemoryChannelConfig),
104 MSG_MAP(SetGeminiMode),
105 MSG_MAP(SetGeminiApertureHigh),
106 MSG_MAP(SetGeminiApertureLow),
107 MSG_MAP(SetMinLinkDpmByIndex),
108 MSG_MAP(OverridePcieParameters),
109 MSG_MAP(OverDriveSetPercentage),
110 MSG_MAP(SetMinDeepSleepDcefclk),
111 MSG_MAP(ReenableAcDcInterrupt),
112 MSG_MAP(NotifyPowerSource),
113 MSG_MAP(SetUclkFastSwitch),
114 MSG_MAP(SetUclkDownHyst),
115 MSG_MAP(GetCurrentRpm),
116 MSG_MAP(SetVideoFps),
118 MSG_MAP(SetFanTemperatureTarget),
119 MSG_MAP(PrepareMp1ForUnload),
120 MSG_MAP(DramLogSetDramAddrHigh),
121 MSG_MAP(DramLogSetDramAddrLow),
122 MSG_MAP(DramLogSetDramSize),
123 MSG_MAP(SetFanMaxRpm),
124 MSG_MAP(SetFanMinPwm),
125 MSG_MAP(ConfigureGfxDidt),
126 MSG_MAP(NumOfDisplays),
127 MSG_MAP(RemoveMargins),
128 MSG_MAP(ReadSerialNumTop32),
129 MSG_MAP(ReadSerialNumBottom32),
130 MSG_MAP(SetSystemVirtualDramAddrHigh),
131 MSG_MAP(SetSystemVirtualDramAddrLow),
133 MSG_MAP(SetFclkGfxClkRatio),
134 MSG_MAP(AllowGfxOff),
135 MSG_MAP(DisallowGfxOff),
136 MSG_MAP(GetPptLimit),
137 MSG_MAP(GetDcModeMaxDpmFreq),
138 MSG_MAP(GetDebugData),
139 MSG_MAP(SetXgmiMode),
142 MSG_MAP(PrepareMp1ForReset),
143 MSG_MAP(PrepareMp1ForShutdown),
144 MSG_MAP(SetMGpuFanBoostLimitRpm),
145 MSG_MAP(GetAVFSVoltageByDpm),
148 static int vega20_clk_map[SMU_CLK_COUNT] = {
149 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
150 CLK_MAP(VCLK, PPCLK_VCLK),
151 CLK_MAP(DCLK, PPCLK_DCLK),
152 CLK_MAP(ECLK, PPCLK_ECLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(UCLK, PPCLK_UCLK),
155 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
156 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
157 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
158 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
159 CLK_MAP(FCLK, PPCLK_FCLK),
162 static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
163 FEA_MAP(DPM_PREFETCHER),
172 FEA_MAP(DPM_DCEFCLK),
179 FEA_MAP(GFX_PER_CU_CG),
186 FEA_MAP(LED_DISPLAY),
187 FEA_MAP(FAN_CONTROL),
198 static int vega20_table_map[SMU_TABLE_COUNT] = {
202 TAB_MAP(AVFS_PSM_DEBUG),
203 TAB_MAP(AVFS_FUSE_OVERRIDE),
204 TAB_MAP(PMSTATUSLOG),
205 TAB_MAP(SMU_METRICS),
206 TAB_MAP(DRIVER_SMU_CONFIG),
207 TAB_MAP(ACTIVITY_MONITOR_COEFF),
211 static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
216 static int vega20_workload_map[] = {
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
226 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
229 if (index >= SMU_TABLE_COUNT)
232 val = vega20_table_map[index];
233 if (val >= TABLE_COUNT)
239 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
242 if (index >= SMU_POWER_SOURCE_COUNT)
245 val = vega20_pwr_src_map[index];
246 if (val >= POWER_SOURCE_COUNT)
252 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
255 if (index >= SMU_FEATURE_COUNT)
258 val = vega20_feature_mask_map[index];
265 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
268 if (index >= SMU_CLK_COUNT)
271 val = vega20_clk_map[index];
272 if (val >= PPCLK_COUNT)
278 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
282 if (index >= SMU_MSG_MAX_COUNT)
285 val = vega20_message_map[index];
286 if (val > PPSMC_Message_Count)
292 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
295 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
298 val = vega20_workload_map[profile];
303 static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
305 struct smu_table_context *smu_table = &smu->smu_table;
307 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
308 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
309 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
310 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
311 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
312 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
313 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
314 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
315 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
316 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
317 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
318 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
319 AMDGPU_GEM_DOMAIN_VRAM);
321 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
322 if (!smu_table->metrics_table)
324 smu_table->metrics_time = 0;
329 static int vega20_allocate_dpm_context(struct smu_context *smu)
331 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
333 if (smu_dpm->dpm_context)
336 smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
338 if (!smu_dpm->dpm_context)
341 if (smu_dpm->golden_dpm_context)
344 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
346 if (!smu_dpm->golden_dpm_context)
349 smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
351 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
353 if (!smu_dpm->dpm_current_power_state)
356 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
358 if (!smu_dpm->dpm_request_power_state)
364 static int vega20_setup_od8_information(struct smu_context *smu)
366 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
367 struct smu_table_context *table_context = &smu->smu_table;
368 struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
370 uint32_t od_feature_count, od_feature_array_size,
371 od_setting_count, od_setting_array_size;
373 if (!table_context->power_play_table)
376 powerplay_table = table_context->power_play_table;
378 if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
379 /* Setup correct ODFeatureCount, and store ODFeatureArray from
380 * powerplay table to od_feature_capabilities */
382 (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
383 ATOM_VEGA20_ODFEATURE_COUNT) ?
384 ATOM_VEGA20_ODFEATURE_COUNT :
385 le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
387 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
389 if (od8_settings->od_feature_capabilities)
392 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
393 od_feature_array_size,
395 if (!od8_settings->od_feature_capabilities)
398 /* Setup correct ODSettingCount, and store ODSettingArray from
399 * powerplay table to od_settings_max and od_setting_min */
401 (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
402 ATOM_VEGA20_ODSETTING_COUNT) ?
403 ATOM_VEGA20_ODSETTING_COUNT :
404 le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
406 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
408 if (od8_settings->od_settings_max)
411 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
412 od_setting_array_size,
415 if (!od8_settings->od_settings_max) {
416 kfree(od8_settings->od_feature_capabilities);
417 od8_settings->od_feature_capabilities = NULL;
421 if (od8_settings->od_settings_min)
424 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
425 od_setting_array_size,
428 if (!od8_settings->od_settings_min) {
429 kfree(od8_settings->od_feature_capabilities);
430 od8_settings->od_feature_capabilities = NULL;
431 kfree(od8_settings->od_settings_max);
432 od8_settings->od_settings_max = NULL;
440 static int vega20_store_powerplay_table(struct smu_context *smu)
442 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
443 struct smu_table_context *table_context = &smu->smu_table;
445 if (!table_context->power_play_table)
448 powerplay_table = table_context->power_play_table;
450 memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
453 table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
454 table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
459 static int vega20_append_powerplay_table(struct smu_context *smu)
461 struct smu_table_context *table_context = &smu->smu_table;
462 PPTable_t *smc_pptable = table_context->driver_pptable;
463 struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
466 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
469 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
470 (uint8_t **)&smc_dpm_table);
474 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
475 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
477 smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
478 smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
479 smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
480 smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
482 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
483 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
484 smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
486 smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
487 smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
488 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
490 smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
491 smc_pptable->SocOffset = smc_dpm_table->socoffset;
492 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
494 smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
495 smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
496 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
498 smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
499 smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
500 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
502 smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
503 smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
504 smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
505 smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
507 smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
508 smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
509 smc_pptable->Padding1 = smc_dpm_table->padding1;
510 smc_pptable->Padding2 = smc_dpm_table->padding2;
512 smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
513 smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
514 smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
516 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
517 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
518 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
520 smc_pptable->UclkSpreadEnabled = 0;
521 smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
522 smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
524 smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
525 smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
526 smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
528 smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
529 smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
530 smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
532 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
533 smc_pptable->I2cControllers[i].Enabled =
534 smc_dpm_table->i2ccontrollers[i].enabled;
535 smc_pptable->I2cControllers[i].SlaveAddress =
536 smc_dpm_table->i2ccontrollers[i].slaveaddress;
537 smc_pptable->I2cControllers[i].ControllerPort =
538 smc_dpm_table->i2ccontrollers[i].controllerport;
539 smc_pptable->I2cControllers[i].ThermalThrottler =
540 smc_dpm_table->i2ccontrollers[i].thermalthrottler;
541 smc_pptable->I2cControllers[i].I2cProtocol =
542 smc_dpm_table->i2ccontrollers[i].i2cprotocol;
543 smc_pptable->I2cControllers[i].I2cSpeed =
544 smc_dpm_table->i2ccontrollers[i].i2cspeed;
550 static int vega20_check_powerplay_table(struct smu_context *smu)
552 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
553 struct smu_table_context *table_context = &smu->smu_table;
555 powerplay_table = table_context->power_play_table;
557 if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
558 pr_err("Unsupported PPTable format!");
562 if (!powerplay_table->sHeader.structuresize) {
563 pr_err("Invalid PowerPlay Table!");
570 static int vega20_run_btc_afll(struct smu_context *smu)
572 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
575 #define FEATURE_MASK(feature) (1ULL << feature)
577 vega20_get_allowed_feature_mask(struct smu_context *smu,
578 uint32_t *feature_mask, uint32_t num)
583 memset(feature_mask, 0, sizeof(uint32_t) * num);
585 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
586 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
587 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
588 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
589 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
590 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
591 | FEATURE_MASK(FEATURE_ULV_BIT)
592 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
593 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
594 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
595 | FEATURE_MASK(FEATURE_PPT_BIT)
596 | FEATURE_MASK(FEATURE_TDC_BIT)
597 | FEATURE_MASK(FEATURE_THERMAL_BIT)
598 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
599 | FEATURE_MASK(FEATURE_RM_BIT)
600 | FEATURE_MASK(FEATURE_ACDC_BIT)
601 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
602 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
603 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
604 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
605 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
606 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
607 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
608 | FEATURE_MASK(FEATURE_CG_BIT)
609 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
610 | FEATURE_MASK(FEATURE_XGMI_BIT);
615 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
617 enum amd_pm_state_type pm_type;
618 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
620 if (!smu_dpm_ctx->dpm_context ||
621 !smu_dpm_ctx->dpm_current_power_state)
624 mutex_lock(&(smu->mutex));
625 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
626 case SMU_STATE_UI_LABEL_BATTERY:
627 pm_type = POWER_STATE_TYPE_BATTERY;
629 case SMU_STATE_UI_LABEL_BALLANCED:
630 pm_type = POWER_STATE_TYPE_BALANCED;
632 case SMU_STATE_UI_LABEL_PERFORMANCE:
633 pm_type = POWER_STATE_TYPE_PERFORMANCE;
636 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
637 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
639 pm_type = POWER_STATE_TYPE_DEFAULT;
642 mutex_unlock(&(smu->mutex));
648 vega20_set_single_dpm_table(struct smu_context *smu,
649 struct vega20_single_dpm_table *single_dpm_table,
653 uint32_t i, num_of_levels = 0, clk;
655 ret = smu_send_smc_msg_with_param(smu,
656 SMU_MSG_GetDpmFreqByIndex,
657 (clk_id << 16 | 0xFF));
659 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
663 smu_read_smc_arg(smu, &num_of_levels);
664 if (!num_of_levels) {
665 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
669 single_dpm_table->count = num_of_levels;
671 for (i = 0; i < num_of_levels; i++) {
672 ret = smu_send_smc_msg_with_param(smu,
673 SMU_MSG_GetDpmFreqByIndex,
676 pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
679 smu_read_smc_arg(smu, &clk);
681 pr_err("[GetDpmFreqByIndex] clk value is invalid!");
684 single_dpm_table->dpm_levels[i].value = clk;
685 single_dpm_table->dpm_levels[i].enabled = true;
690 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
692 dpm_state->soft_min_level = 0x0;
693 dpm_state->soft_max_level = 0xffff;
694 dpm_state->hard_min_level = 0x0;
695 dpm_state->hard_max_level = 0xffff;
698 static int vega20_set_default_dpm_table(struct smu_context *smu)
702 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
703 struct vega20_dpm_table *dpm_table = NULL;
704 struct vega20_single_dpm_table *single_dpm_table;
706 dpm_table = smu_dpm->dpm_context;
709 single_dpm_table = &(dpm_table->soc_table);
711 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
712 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
715 pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
719 single_dpm_table->count = 1;
720 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
722 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
725 single_dpm_table = &(dpm_table->gfx_table);
727 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
728 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
731 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
735 single_dpm_table->count = 1;
736 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
738 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
741 single_dpm_table = &(dpm_table->mem_table);
743 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
744 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
747 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
751 single_dpm_table->count = 1;
752 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
754 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
757 single_dpm_table = &(dpm_table->eclk_table);
759 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
760 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
762 pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
766 single_dpm_table->count = 1;
767 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
769 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
772 single_dpm_table = &(dpm_table->vclk_table);
774 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
775 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
777 pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
781 single_dpm_table->count = 1;
782 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
784 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
787 single_dpm_table = &(dpm_table->dclk_table);
789 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
790 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
792 pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
796 single_dpm_table->count = 1;
797 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
799 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
802 single_dpm_table = &(dpm_table->dcef_table);
804 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
805 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
808 pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
812 single_dpm_table->count = 1;
813 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
815 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
818 single_dpm_table = &(dpm_table->pixel_table);
820 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
821 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
824 pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
828 single_dpm_table->count = 0;
830 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
833 single_dpm_table = &(dpm_table->display_table);
835 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
836 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
839 pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
843 single_dpm_table->count = 0;
845 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
848 single_dpm_table = &(dpm_table->phy_table);
850 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
851 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
854 pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
858 single_dpm_table->count = 0;
860 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
863 single_dpm_table = &(dpm_table->fclk_table);
865 if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
866 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
869 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
873 single_dpm_table->count = 0;
875 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
877 memcpy(smu_dpm->golden_dpm_context, dpm_table,
878 sizeof(struct vega20_dpm_table));
883 static int vega20_populate_umd_state_clk(struct smu_context *smu)
885 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
886 struct vega20_dpm_table *dpm_table = NULL;
887 struct vega20_single_dpm_table *gfx_table = NULL;
888 struct vega20_single_dpm_table *mem_table = NULL;
890 dpm_table = smu_dpm->dpm_context;
891 gfx_table = &(dpm_table->gfx_table);
892 mem_table = &(dpm_table->mem_table);
894 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
895 smu->pstate_mclk = mem_table->dpm_levels[0].value;
897 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
898 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
899 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
900 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
903 smu->pstate_sclk = smu->pstate_sclk * 100;
904 smu->pstate_mclk = smu->pstate_mclk * 100;
909 static int vega20_get_clk_table(struct smu_context *smu,
910 struct pp_clock_levels_with_latency *clocks,
911 struct vega20_single_dpm_table *dpm_table)
915 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
916 clocks->num_levels = count;
918 for (i = 0; i < count; i++) {
919 clocks->data[i].clocks_in_khz =
920 dpm_table->dpm_levels[i].value * 1000;
921 clocks->data[i].latency_in_us = 0;
927 static int vega20_print_clk_levels(struct smu_context *smu,
928 enum smu_clk_type type, char *buf)
930 int i, now, size = 0;
932 uint32_t gen_speed, lane_width;
933 struct amdgpu_device *adev = smu->adev;
934 struct pp_clock_levels_with_latency clocks;
935 struct vega20_single_dpm_table *single_dpm_table;
936 struct smu_table_context *table_context = &smu->smu_table;
937 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
938 struct vega20_dpm_table *dpm_table = NULL;
939 struct vega20_od8_settings *od8_settings =
940 (struct vega20_od8_settings *)smu->od_settings;
941 OverDriveTable_t *od_table =
942 (OverDriveTable_t *)(table_context->overdrive_table);
943 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
945 dpm_table = smu_dpm->dpm_context;
949 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
951 pr_err("Attempt to get current gfx clk Failed!");
955 single_dpm_table = &(dpm_table->gfx_table);
956 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
958 pr_err("Attempt to get gfx clk levels Failed!");
962 for (i = 0; i < clocks.num_levels; i++)
963 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
964 clocks.data[i].clocks_in_khz / 1000,
965 (clocks.data[i].clocks_in_khz == now * 10)
970 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
972 pr_err("Attempt to get current mclk Failed!");
976 single_dpm_table = &(dpm_table->mem_table);
977 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
979 pr_err("Attempt to get memory clk levels Failed!");
983 for (i = 0; i < clocks.num_levels; i++)
984 size += sprintf(buf + size, "%d: %uMhz %s\n",
985 i, clocks.data[i].clocks_in_khz / 1000,
986 (clocks.data[i].clocks_in_khz == now * 10)
991 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
993 pr_err("Attempt to get current socclk Failed!");
997 single_dpm_table = &(dpm_table->soc_table);
998 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1000 pr_err("Attempt to get socclk levels Failed!");
1004 for (i = 0; i < clocks.num_levels; i++)
1005 size += sprintf(buf + size, "%d: %uMhz %s\n",
1006 i, clocks.data[i].clocks_in_khz / 1000,
1007 (clocks.data[i].clocks_in_khz == now * 10)
1012 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1014 pr_err("Attempt to get current fclk Failed!");
1018 single_dpm_table = &(dpm_table->fclk_table);
1019 for (i = 0; i < single_dpm_table->count; i++)
1020 size += sprintf(buf + size, "%d: %uMhz %s\n",
1021 i, single_dpm_table->dpm_levels[i].value,
1022 (single_dpm_table->dpm_levels[i].value == now / 100)
1027 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1029 pr_err("Attempt to get current dcefclk Failed!");
1033 single_dpm_table = &(dpm_table->dcef_table);
1034 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1036 pr_err("Attempt to get dcefclk levels Failed!");
1040 for (i = 0; i < clocks.num_levels; i++)
1041 size += sprintf(buf + size, "%d: %uMhz %s\n",
1042 i, clocks.data[i].clocks_in_khz / 1000,
1043 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1047 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1048 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1049 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1050 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1051 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1052 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1053 for (i = 0; i < NUM_LINK_LEVELS; i++)
1054 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1055 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1056 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1057 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1058 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1059 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1060 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1061 (pptable->PcieLaneCount[i] == 3) ? "x4" :
1062 (pptable->PcieLaneCount[i] == 4) ? "x8" :
1063 (pptable->PcieLaneCount[i] == 5) ? "x12" :
1064 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1065 pptable->LclkFreq[i],
1066 (gen_speed == pptable->PcieGenSpeed[i]) &&
1067 (lane_width == pptable->PcieLaneCount[i]) ?
1072 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1073 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1074 size = sprintf(buf, "%s:\n", "OD_SCLK");
1075 size += sprintf(buf + size, "0: %10uMhz\n",
1076 od_table->GfxclkFmin);
1077 size += sprintf(buf + size, "1: %10uMhz\n",
1078 od_table->GfxclkFmax);
1084 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1085 size = sprintf(buf, "%s:\n", "OD_MCLK");
1086 size += sprintf(buf + size, "1: %10uMhz\n",
1087 od_table->UclkFmax);
1092 case SMU_OD_VDDC_CURVE:
1093 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1094 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1095 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1096 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1097 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1098 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1099 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1100 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1101 od_table->GfxclkFreq1,
1102 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1103 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1104 od_table->GfxclkFreq2,
1105 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1106 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1107 od_table->GfxclkFreq3,
1108 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1114 size = sprintf(buf, "%s:\n", "OD_RANGE");
1116 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1117 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1118 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1119 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1120 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1123 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1124 single_dpm_table = &(dpm_table->mem_table);
1125 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1127 pr_err("Attempt to get memory clk levels Failed!");
1131 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1132 clocks.data[0].clocks_in_khz / 1000,
1133 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1136 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1137 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1138 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1139 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1140 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1141 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1142 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1143 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1144 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1145 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1146 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1147 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1148 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1149 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1150 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1151 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1152 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1153 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1154 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1155 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1156 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1157 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1158 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1159 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1170 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1171 uint32_t feature_mask)
1173 struct vega20_dpm_table *dpm_table;
1174 struct vega20_single_dpm_table *single_dpm_table;
1178 dpm_table = smu->smu_dpm.dpm_context;
1180 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1181 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1182 single_dpm_table = &(dpm_table->gfx_table);
1183 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1184 single_dpm_table->dpm_state.soft_min_level;
1185 ret = smu_send_smc_msg_with_param(smu,
1186 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1187 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1189 pr_err("Failed to set soft %s gfxclk !\n",
1190 max ? "max" : "min");
1195 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1196 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1197 single_dpm_table = &(dpm_table->mem_table);
1198 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1199 single_dpm_table->dpm_state.soft_min_level;
1200 ret = smu_send_smc_msg_with_param(smu,
1201 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1202 (PPCLK_UCLK << 16) | (freq & 0xffff));
1204 pr_err("Failed to set soft %s memclk !\n",
1205 max ? "max" : "min");
1210 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1211 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1212 single_dpm_table = &(dpm_table->soc_table);
1213 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1214 single_dpm_table->dpm_state.soft_min_level;
1215 ret = smu_send_smc_msg_with_param(smu,
1216 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1217 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1219 pr_err("Failed to set soft %s socclk !\n",
1220 max ? "max" : "min");
1225 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1226 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1227 single_dpm_table = &(dpm_table->fclk_table);
1228 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1229 single_dpm_table->dpm_state.soft_min_level;
1230 ret = smu_send_smc_msg_with_param(smu,
1231 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1232 (PPCLK_FCLK << 16) | (freq & 0xffff));
1234 pr_err("Failed to set soft %s fclk !\n",
1235 max ? "max" : "min");
1240 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1241 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1242 single_dpm_table = &(dpm_table->dcef_table);
1243 freq = single_dpm_table->dpm_state.hard_min_level;
1245 ret = smu_send_smc_msg_with_param(smu,
1246 SMU_MSG_SetHardMinByFreq,
1247 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1249 pr_err("Failed to set hard min dcefclk !\n");
1258 static int vega20_force_clk_levels(struct smu_context *smu,
1259 enum smu_clk_type clk_type, uint32_t mask)
1261 struct vega20_dpm_table *dpm_table;
1262 struct vega20_single_dpm_table *single_dpm_table;
1263 uint32_t soft_min_level, soft_max_level, hard_min_level;
1264 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1267 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1268 pr_info("force clock level is for dpm manual mode only.\n");
1272 mutex_lock(&(smu->mutex));
1274 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1275 soft_max_level = mask ? (fls(mask) - 1) : 0;
1277 dpm_table = smu->smu_dpm.dpm_context;
1281 single_dpm_table = &(dpm_table->gfx_table);
1283 if (soft_max_level >= single_dpm_table->count) {
1284 pr_err("Clock level specified %d is over max allowed %d\n",
1285 soft_max_level, single_dpm_table->count - 1);
1290 single_dpm_table->dpm_state.soft_min_level =
1291 single_dpm_table->dpm_levels[soft_min_level].value;
1292 single_dpm_table->dpm_state.soft_max_level =
1293 single_dpm_table->dpm_levels[soft_max_level].value;
1295 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1297 pr_err("Failed to upload boot level to lowest!\n");
1301 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1303 pr_err("Failed to upload dpm max level to highest!\n");
1308 single_dpm_table = &(dpm_table->mem_table);
1310 if (soft_max_level >= single_dpm_table->count) {
1311 pr_err("Clock level specified %d is over max allowed %d\n",
1312 soft_max_level, single_dpm_table->count - 1);
1317 single_dpm_table->dpm_state.soft_min_level =
1318 single_dpm_table->dpm_levels[soft_min_level].value;
1319 single_dpm_table->dpm_state.soft_max_level =
1320 single_dpm_table->dpm_levels[soft_max_level].value;
1322 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1324 pr_err("Failed to upload boot level to lowest!\n");
1328 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1330 pr_err("Failed to upload dpm max level to highest!\n");
1335 single_dpm_table = &(dpm_table->soc_table);
1337 if (soft_max_level >= single_dpm_table->count) {
1338 pr_err("Clock level specified %d is over max allowed %d\n",
1339 soft_max_level, single_dpm_table->count - 1);
1344 single_dpm_table->dpm_state.soft_min_level =
1345 single_dpm_table->dpm_levels[soft_min_level].value;
1346 single_dpm_table->dpm_state.soft_max_level =
1347 single_dpm_table->dpm_levels[soft_max_level].value;
1349 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1351 pr_err("Failed to upload boot level to lowest!\n");
1355 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1357 pr_err("Failed to upload dpm max level to highest!\n");
1362 single_dpm_table = &(dpm_table->fclk_table);
1364 if (soft_max_level >= single_dpm_table->count) {
1365 pr_err("Clock level specified %d is over max allowed %d\n",
1366 soft_max_level, single_dpm_table->count - 1);
1371 single_dpm_table->dpm_state.soft_min_level =
1372 single_dpm_table->dpm_levels[soft_min_level].value;
1373 single_dpm_table->dpm_state.soft_max_level =
1374 single_dpm_table->dpm_levels[soft_max_level].value;
1376 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1378 pr_err("Failed to upload boot level to lowest!\n");
1382 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1384 pr_err("Failed to upload dpm max level to highest!\n");
1389 hard_min_level = soft_min_level;
1390 single_dpm_table = &(dpm_table->dcef_table);
1392 if (hard_min_level >= single_dpm_table->count) {
1393 pr_err("Clock level specified %d is over max allowed %d\n",
1394 hard_min_level, single_dpm_table->count - 1);
1399 single_dpm_table->dpm_state.hard_min_level =
1400 single_dpm_table->dpm_levels[hard_min_level].value;
1402 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1404 pr_err("Failed to upload boot level to lowest!\n");
1409 if (soft_min_level >= NUM_LINK_LEVELS ||
1410 soft_max_level >= NUM_LINK_LEVELS) {
1415 ret = smu_send_smc_msg_with_param(smu,
1416 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1418 pr_err("Failed to set min link dpm level!\n");
1426 mutex_unlock(&(smu->mutex));
1430 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1431 enum smu_clk_type clk_type,
1432 struct pp_clock_levels_with_latency *clocks)
1435 struct vega20_single_dpm_table *single_dpm_table;
1436 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1437 struct vega20_dpm_table *dpm_table = NULL;
1439 dpm_table = smu_dpm->dpm_context;
1441 mutex_lock(&smu->mutex);
1445 single_dpm_table = &(dpm_table->gfx_table);
1446 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1449 single_dpm_table = &(dpm_table->mem_table);
1450 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1453 single_dpm_table = &(dpm_table->dcef_table);
1454 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1457 single_dpm_table = &(dpm_table->soc_table);
1458 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1464 mutex_unlock(&smu->mutex);
1468 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1474 ret = smu_send_smc_msg_with_param(smu,
1475 SMU_MSG_GetAVFSVoltageByDpm,
1476 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1478 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1482 smu_read_smc_arg(smu, voltage);
1483 *voltage = *voltage / VOLTAGE_SCALE;
1488 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1490 struct smu_table_context *table_context = &smu->smu_table;
1491 OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1492 struct vega20_od8_settings *od8_settings = NULL;
1493 PPTable_t *smc_pptable = table_context->driver_pptable;
1496 if (smu->od_settings)
1499 od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1504 smu->od_settings = (void *)od8_settings;
1506 ret = vega20_setup_od8_information(smu);
1508 pr_err("Retrieve board OD limits failed!\n");
1512 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1513 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1514 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1515 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1516 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1517 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1518 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1520 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1522 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1523 od_table->GfxclkFmin;
1524 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1525 od_table->GfxclkFmax;
1528 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1529 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1530 smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1531 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1532 smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1533 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1534 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1535 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1537 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1539 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1541 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1543 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1545 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1548 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1549 od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1550 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1551 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1552 od_table->GfxclkFreq1;
1553 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1554 od_table->GfxclkFreq2;
1555 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1556 od_table->GfxclkFreq3;
1558 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1559 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1560 od_table->GfxclkFreq1);
1562 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1563 od_table->GfxclkVolt1 =
1564 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1566 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1567 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1568 od_table->GfxclkFreq2);
1570 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1571 od_table->GfxclkVolt2 =
1572 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1574 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1575 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1576 od_table->GfxclkFreq3);
1578 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1579 od_table->GfxclkVolt3 =
1580 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1585 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1586 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1587 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1588 od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1589 (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1590 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1591 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1593 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1598 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1599 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1600 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1601 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1602 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1603 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1605 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1606 od_table->OverDrivePct;
1609 if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1610 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1611 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1612 od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1613 (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1614 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1615 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1616 OD8_ACOUSTIC_LIMIT_SCLK;
1617 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1618 od_table->FanMaximumRpm;
1621 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1622 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1623 od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1624 (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1625 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1626 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1628 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1629 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1633 if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1634 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1635 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1636 od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1637 (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1638 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1639 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1640 OD8_TEMPERATURE_FAN;
1641 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1642 od_table->FanTargetTemperature;
1645 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1646 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1647 od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1648 (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1649 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1650 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1651 OD8_TEMPERATURE_SYSTEM;
1652 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1653 od_table->MaxOpTemp;
1657 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1658 if (od8_settings->od8_settings_array[i].feature_id) {
1659 od8_settings->od8_settings_array[i].min_value =
1660 od8_settings->od_settings_min[i];
1661 od8_settings->od8_settings_array[i].max_value =
1662 od8_settings->od_settings_max[i];
1663 od8_settings->od8_settings_array[i].current_value =
1664 od8_settings->od8_settings_array[i].default_value;
1666 od8_settings->od8_settings_array[i].min_value = 0;
1667 od8_settings->od8_settings_array[i].max_value = 0;
1668 od8_settings->od8_settings_array[i].current_value = 0;
1675 static int vega20_get_metrics_table(struct smu_context *smu,
1676 SmuMetrics_t *metrics_table)
1678 struct smu_table_context *smu_table= &smu->smu_table;
1681 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1682 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1683 (void *)smu_table->metrics_table, false);
1685 pr_info("Failed to export SMU metrics table!\n");
1688 smu_table->metrics_time = jiffies;
1691 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1696 static int vega20_set_default_od_settings(struct smu_context *smu,
1699 struct smu_table_context *table_context = &smu->smu_table;
1703 if (table_context->overdrive_table)
1706 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1708 if (!table_context->overdrive_table)
1711 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1712 table_context->overdrive_table, false);
1714 pr_err("Failed to export over drive table!\n");
1718 ret = vega20_set_default_od8_setttings(smu);
1723 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1724 table_context->overdrive_table, true);
1726 pr_err("Failed to import over drive table!\n");
1733 static int vega20_get_od_percentage(struct smu_context *smu,
1734 enum smu_clk_type clk_type)
1736 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1737 struct vega20_dpm_table *dpm_table = NULL;
1738 struct vega20_dpm_table *golden_table = NULL;
1739 struct vega20_single_dpm_table *single_dpm_table;
1740 struct vega20_single_dpm_table *golden_dpm_table;
1741 int value, golden_value;
1743 dpm_table = smu_dpm->dpm_context;
1744 golden_table = smu_dpm->golden_dpm_context;
1748 single_dpm_table = &(dpm_table->gfx_table);
1749 golden_dpm_table = &(golden_table->gfx_table);
1752 single_dpm_table = &(dpm_table->mem_table);
1753 golden_dpm_table = &(golden_table->mem_table);
1760 value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1761 golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1763 value -= golden_value;
1764 value = DIV_ROUND_UP(value * 100, golden_value);
1769 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1771 DpmActivityMonitorCoeffInt_t activity_monitor;
1772 uint32_t i, size = 0;
1773 uint16_t workload_type = 0;
1774 static const char *profile_name[] = {
1782 static const char *title[] = {
1783 "PROFILE_INDEX(NAME)",
1787 "MinActiveFreqType",
1792 "PD_Data_error_coeff",
1793 "PD_Data_error_rate_coeff"};
1796 if (!smu->pm_enabled || !buf)
1799 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1800 title[0], title[1], title[2], title[3], title[4], title[5],
1801 title[6], title[7], title[8], title[9], title[10]);
1803 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1804 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1805 workload_type = smu_workload_get_type(smu, i);
1806 result = smu_update_table(smu,
1807 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1808 (void *)(&activity_monitor), false);
1810 pr_err("[%s] Failed to get activity monitor!", __func__);
1814 size += sprintf(buf + size, "%2d %14s%s:\n",
1815 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1817 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1821 activity_monitor.Gfx_FPS,
1822 activity_monitor.Gfx_UseRlcBusy,
1823 activity_monitor.Gfx_MinActiveFreqType,
1824 activity_monitor.Gfx_MinActiveFreq,
1825 activity_monitor.Gfx_BoosterFreqType,
1826 activity_monitor.Gfx_BoosterFreq,
1827 activity_monitor.Gfx_PD_Data_limit_c,
1828 activity_monitor.Gfx_PD_Data_error_coeff,
1829 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1831 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1835 activity_monitor.Soc_FPS,
1836 activity_monitor.Soc_UseRlcBusy,
1837 activity_monitor.Soc_MinActiveFreqType,
1838 activity_monitor.Soc_MinActiveFreq,
1839 activity_monitor.Soc_BoosterFreqType,
1840 activity_monitor.Soc_BoosterFreq,
1841 activity_monitor.Soc_PD_Data_limit_c,
1842 activity_monitor.Soc_PD_Data_error_coeff,
1843 activity_monitor.Soc_PD_Data_error_rate_coeff);
1845 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1849 activity_monitor.Mem_FPS,
1850 activity_monitor.Mem_UseRlcBusy,
1851 activity_monitor.Mem_MinActiveFreqType,
1852 activity_monitor.Mem_MinActiveFreq,
1853 activity_monitor.Mem_BoosterFreqType,
1854 activity_monitor.Mem_BoosterFreq,
1855 activity_monitor.Mem_PD_Data_limit_c,
1856 activity_monitor.Mem_PD_Data_error_coeff,
1857 activity_monitor.Mem_PD_Data_error_rate_coeff);
1859 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1863 activity_monitor.Fclk_FPS,
1864 activity_monitor.Fclk_UseRlcBusy,
1865 activity_monitor.Fclk_MinActiveFreqType,
1866 activity_monitor.Fclk_MinActiveFreq,
1867 activity_monitor.Fclk_BoosterFreqType,
1868 activity_monitor.Fclk_BoosterFreq,
1869 activity_monitor.Fclk_PD_Data_limit_c,
1870 activity_monitor.Fclk_PD_Data_error_coeff,
1871 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1877 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1879 DpmActivityMonitorCoeffInt_t activity_monitor;
1880 int workload_type = 0, ret = 0;
1882 smu->power_profile_mode = input[size];
1884 if (!smu->pm_enabled)
1886 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1887 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1891 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1892 ret = smu_update_table(smu,
1893 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1894 (void *)(&activity_monitor), false);
1896 pr_err("[%s] Failed to get activity monitor!", __func__);
1901 case 0: /* Gfxclk */
1902 activity_monitor.Gfx_FPS = input[1];
1903 activity_monitor.Gfx_UseRlcBusy = input[2];
1904 activity_monitor.Gfx_MinActiveFreqType = input[3];
1905 activity_monitor.Gfx_MinActiveFreq = input[4];
1906 activity_monitor.Gfx_BoosterFreqType = input[5];
1907 activity_monitor.Gfx_BoosterFreq = input[6];
1908 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1909 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1910 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1912 case 1: /* Socclk */
1913 activity_monitor.Soc_FPS = input[1];
1914 activity_monitor.Soc_UseRlcBusy = input[2];
1915 activity_monitor.Soc_MinActiveFreqType = input[3];
1916 activity_monitor.Soc_MinActiveFreq = input[4];
1917 activity_monitor.Soc_BoosterFreqType = input[5];
1918 activity_monitor.Soc_BoosterFreq = input[6];
1919 activity_monitor.Soc_PD_Data_limit_c = input[7];
1920 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1921 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1924 activity_monitor.Mem_FPS = input[1];
1925 activity_monitor.Mem_UseRlcBusy = input[2];
1926 activity_monitor.Mem_MinActiveFreqType = input[3];
1927 activity_monitor.Mem_MinActiveFreq = input[4];
1928 activity_monitor.Mem_BoosterFreqType = input[5];
1929 activity_monitor.Mem_BoosterFreq = input[6];
1930 activity_monitor.Mem_PD_Data_limit_c = input[7];
1931 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1932 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1935 activity_monitor.Fclk_FPS = input[1];
1936 activity_monitor.Fclk_UseRlcBusy = input[2];
1937 activity_monitor.Fclk_MinActiveFreqType = input[3];
1938 activity_monitor.Fclk_MinActiveFreq = input[4];
1939 activity_monitor.Fclk_BoosterFreqType = input[5];
1940 activity_monitor.Fclk_BoosterFreq = input[6];
1941 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1942 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1943 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1947 ret = smu_update_table(smu,
1948 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1949 (void *)(&activity_monitor), true);
1951 pr_err("[%s] Failed to set activity monitor!", __func__);
1956 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1957 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1958 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1959 1 << workload_type);
1965 vega20_get_profiling_clk_mask(struct smu_context *smu,
1966 enum amd_dpm_forced_level level,
1967 uint32_t *sclk_mask,
1968 uint32_t *mclk_mask,
1971 struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1972 struct vega20_single_dpm_table *gfx_dpm_table;
1973 struct vega20_single_dpm_table *mem_dpm_table;
1974 struct vega20_single_dpm_table *soc_dpm_table;
1976 if (!smu->smu_dpm.dpm_context)
1979 gfx_dpm_table = &dpm_table->gfx_table;
1980 mem_dpm_table = &dpm_table->mem_table;
1981 soc_dpm_table = &dpm_table->soc_table;
1987 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1988 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
1989 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
1990 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
1991 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
1992 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
1995 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1997 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1999 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2000 *sclk_mask = gfx_dpm_table->count - 1;
2001 *mclk_mask = mem_dpm_table->count - 1;
2002 *soc_mask = soc_dpm_table->count - 1;
2009 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2010 struct vega20_single_dpm_table *dpm_table)
2013 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2014 if (!smu_dpm_ctx->dpm_context)
2017 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2018 if (dpm_table->count <= 0) {
2019 pr_err("[%s] Dpm table has no entry!", __func__);
2023 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2024 pr_err("[%s] Dpm table has too many entries!", __func__);
2028 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2029 ret = smu_send_smc_msg_with_param(smu,
2030 SMU_MSG_SetHardMinByFreq,
2031 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2033 pr_err("[%s] Set hard min uclk failed!", __func__);
2041 static int vega20_pre_display_config_changed(struct smu_context *smu)
2044 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2046 if (!smu->smu_dpm.dpm_context)
2049 smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2050 ret = vega20_set_uclk_to_highest_dpm_level(smu,
2051 &dpm_table->mem_table);
2053 pr_err("Failed to set uclk to highest dpm level");
2057 static int vega20_display_config_changed(struct smu_context *smu)
2061 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2062 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2063 ret = smu_write_watermarks_table(smu);
2065 pr_err("Failed to update WMTABLE!");
2068 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2071 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2072 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2073 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2074 smu_send_smc_msg_with_param(smu,
2075 SMU_MSG_NumOfDisplays,
2076 smu->display_config->num_display);
2082 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2084 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2085 struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2086 struct vega20_single_dpm_table *dpm_table;
2087 bool vblank_too_short = false;
2088 bool disable_mclk_switching;
2089 uint32_t i, latency;
2091 disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2092 !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2093 latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2096 dpm_table = &(dpm_ctx->gfx_table);
2097 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2098 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2099 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2100 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2102 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2103 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2104 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2107 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2108 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2109 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2112 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2113 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2114 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2118 dpm_table = &(dpm_ctx->mem_table);
2119 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2120 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2121 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2122 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2124 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2125 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2126 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2129 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2130 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2131 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2134 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2135 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2136 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2139 /* honour DAL's UCLK Hardmin */
2140 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2141 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2143 /* Hardmin is dependent on displayconfig */
2144 if (disable_mclk_switching) {
2145 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2146 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2147 if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2148 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2149 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2156 if (smu->display_config->nb_pstate_switch_disable)
2157 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2160 dpm_table = &(dpm_ctx->vclk_table);
2161 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2162 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2163 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2164 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2166 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2167 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2168 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2171 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2172 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2173 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2177 dpm_table = &(dpm_ctx->dclk_table);
2178 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2179 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2180 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2181 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2183 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2184 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2185 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2188 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2189 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2190 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2194 dpm_table = &(dpm_ctx->soc_table);
2195 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2196 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2197 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2198 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2200 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2201 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2202 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2205 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2206 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2207 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2211 dpm_table = &(dpm_ctx->eclk_table);
2212 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2213 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2214 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2215 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2217 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2218 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2219 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2222 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2223 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2224 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2230 vega20_notify_smc_dispaly_config(struct smu_context *smu)
2232 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2233 struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2234 struct smu_clocks min_clocks = {0};
2235 struct pp_display_clock_request clock_req;
2238 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2239 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2240 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2242 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2243 clock_req.clock_type = amd_pp_dcef_clock;
2244 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2245 if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
2246 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2247 ret = smu_send_smc_msg_with_param(smu,
2248 SMU_MSG_SetMinDeepSleepDcefclk,
2249 min_clocks.dcef_clock_in_sr/100);
2251 pr_err("Attempt to set divider for DCEFCLK Failed!");
2256 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2260 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2261 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2262 ret = smu_send_smc_msg_with_param(smu,
2263 SMU_MSG_SetHardMinByFreq,
2264 (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2266 pr_err("[%s] Set hard min uclk failed!", __func__);
2274 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2278 for (i = 0; i < table->count; i++) {
2279 if (table->dpm_levels[i].enabled)
2282 if (i >= table->count) {
2284 table->dpm_levels[i].enabled = true;
2290 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2295 pr_err("[%s] DPM Table does not exist!", __func__);
2298 if (table->count <= 0) {
2299 pr_err("[%s] DPM Table has no entry!", __func__);
2302 if (table->count > MAX_REGULAR_DPM_NUMBER) {
2303 pr_err("[%s] DPM Table has too many entries!", __func__);
2304 return MAX_REGULAR_DPM_NUMBER - 1;
2307 for (i = table->count - 1; i >= 0; i--) {
2308 if (table->dpm_levels[i].enabled)
2313 table->dpm_levels[i].enabled = true;
2319 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2321 uint32_t soft_level;
2323 struct vega20_dpm_table *dpm_table =
2324 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2327 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2329 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2331 dpm_table->gfx_table.dpm_state.soft_min_level =
2332 dpm_table->gfx_table.dpm_state.soft_max_level =
2333 dpm_table->gfx_table.dpm_levels[soft_level].value;
2336 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2338 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2340 dpm_table->mem_table.dpm_state.soft_min_level =
2341 dpm_table->mem_table.dpm_state.soft_max_level =
2342 dpm_table->mem_table.dpm_levels[soft_level].value;
2345 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2347 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2349 dpm_table->soc_table.dpm_state.soft_min_level =
2350 dpm_table->soc_table.dpm_state.soft_max_level =
2351 dpm_table->soc_table.dpm_levels[soft_level].value;
2353 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2355 pr_err("Failed to upload boot level to %s!\n",
2356 highest ? "highest" : "lowest");
2360 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2362 pr_err("Failed to upload dpm max level to %s!\n!",
2363 highest ? "highest" : "lowest");
2370 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2372 uint32_t soft_min_level, soft_max_level;
2374 struct vega20_dpm_table *dpm_table =
2375 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2377 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2378 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2379 dpm_table->gfx_table.dpm_state.soft_min_level =
2380 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2381 dpm_table->gfx_table.dpm_state.soft_max_level =
2382 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2384 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2385 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2386 dpm_table->mem_table.dpm_state.soft_min_level =
2387 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2388 dpm_table->mem_table.dpm_state.soft_max_level =
2389 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2391 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2392 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2393 dpm_table->soc_table.dpm_state.soft_min_level =
2394 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2395 dpm_table->soc_table.dpm_state.soft_max_level =
2396 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2398 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2400 pr_err("Failed to upload DPM Bootup Levels!");
2404 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2406 pr_err("Failed to upload DPM Max Levels!");
2413 static int vega20_update_specified_od8_value(struct smu_context *smu,
2417 struct smu_table_context *table_context = &smu->smu_table;
2418 OverDriveTable_t *od_table =
2419 (OverDriveTable_t *)(table_context->overdrive_table);
2420 struct vega20_od8_settings *od8_settings =
2421 (struct vega20_od8_settings *)smu->od_settings;
2424 case OD8_SETTING_GFXCLK_FMIN:
2425 od_table->GfxclkFmin = (uint16_t)value;
2428 case OD8_SETTING_GFXCLK_FMAX:
2429 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2430 value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2432 od_table->GfxclkFmax = (uint16_t)value;
2435 case OD8_SETTING_GFXCLK_FREQ1:
2436 od_table->GfxclkFreq1 = (uint16_t)value;
2439 case OD8_SETTING_GFXCLK_VOLTAGE1:
2440 od_table->GfxclkVolt1 = (uint16_t)value;
2443 case OD8_SETTING_GFXCLK_FREQ2:
2444 od_table->GfxclkFreq2 = (uint16_t)value;
2447 case OD8_SETTING_GFXCLK_VOLTAGE2:
2448 od_table->GfxclkVolt2 = (uint16_t)value;
2451 case OD8_SETTING_GFXCLK_FREQ3:
2452 od_table->GfxclkFreq3 = (uint16_t)value;
2455 case OD8_SETTING_GFXCLK_VOLTAGE3:
2456 od_table->GfxclkVolt3 = (uint16_t)value;
2459 case OD8_SETTING_UCLK_FMAX:
2460 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2461 value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2463 od_table->UclkFmax = (uint16_t)value;
2466 case OD8_SETTING_POWER_PERCENTAGE:
2467 od_table->OverDrivePct = (int16_t)value;
2470 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2471 od_table->FanMaximumRpm = (uint16_t)value;
2474 case OD8_SETTING_FAN_MIN_SPEED:
2475 od_table->FanMinimumPwm = (uint16_t)value;
2478 case OD8_SETTING_FAN_TARGET_TEMP:
2479 od_table->FanTargetTemperature = (uint16_t)value;
2482 case OD8_SETTING_OPERATING_TEMP_MAX:
2483 od_table->MaxOpTemp = (uint16_t)value;
2490 static int vega20_update_od8_settings(struct smu_context *smu,
2494 struct smu_table_context *table_context = &smu->smu_table;
2497 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2498 table_context->overdrive_table, false);
2500 pr_err("Failed to export over drive table!\n");
2504 ret = vega20_update_specified_od8_value(smu, index, value);
2508 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2509 table_context->overdrive_table, true);
2511 pr_err("Failed to import over drive table!\n");
2518 static int vega20_set_od_percentage(struct smu_context *smu,
2519 enum smu_clk_type clk_type,
2522 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2523 struct vega20_dpm_table *dpm_table = NULL;
2524 struct vega20_dpm_table *golden_table = NULL;
2525 struct vega20_single_dpm_table *single_dpm_table;
2526 struct vega20_single_dpm_table *golden_dpm_table;
2527 uint32_t od_clk, index;
2529 int feature_enabled;
2532 mutex_lock(&(smu->mutex));
2534 dpm_table = smu_dpm->dpm_context;
2535 golden_table = smu_dpm->golden_dpm_context;
2539 single_dpm_table = &(dpm_table->gfx_table);
2540 golden_dpm_table = &(golden_table->gfx_table);
2541 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2542 clk_id = PPCLK_GFXCLK;
2543 index = OD8_SETTING_GFXCLK_FMAX;
2546 single_dpm_table = &(dpm_table->mem_table);
2547 golden_dpm_table = &(golden_table->mem_table);
2548 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2549 clk_id = PPCLK_UCLK;
2550 index = OD8_SETTING_UCLK_FMAX;
2560 od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2562 od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2564 ret = vega20_update_od8_settings(smu, index, od_clk);
2566 pr_err("[Setoverdrive] failed to set od clk!\n");
2570 if (feature_enabled) {
2571 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2574 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2578 single_dpm_table->count = 1;
2579 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2582 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2583 AMD_PP_TASK_READJUST_POWER_STATE);
2586 mutex_unlock(&(smu->mutex));
2591 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2592 enum PP_OD_DPM_TABLE_COMMAND type,
2593 long *input, uint32_t size)
2595 struct smu_table_context *table_context = &smu->smu_table;
2596 OverDriveTable_t *od_table =
2597 (OverDriveTable_t *)(table_context->overdrive_table);
2598 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2599 struct vega20_dpm_table *dpm_table = NULL;
2600 struct vega20_single_dpm_table *single_dpm_table;
2601 struct vega20_od8_settings *od8_settings =
2602 (struct vega20_od8_settings *)smu->od_settings;
2603 struct pp_clock_levels_with_latency clocks;
2604 int32_t input_index, input_clk, input_vol, i;
2608 dpm_table = smu_dpm->dpm_context;
2611 pr_warn("NULL user input for clock and voltage\n");
2616 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2617 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2618 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2619 pr_info("Sclk min/max frequency overdrive not supported\n");
2623 for (i = 0; i < size; i += 2) {
2625 pr_info("invalid number of input parameters %d\n", size);
2629 input_index = input[i];
2630 input_clk = input[i + 1];
2632 if (input_index != 0 && input_index != 1) {
2633 pr_info("Invalid index %d\n", input_index);
2634 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2638 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2639 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2640 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2642 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2643 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2647 if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2648 od_table->GfxclkFmin = input_clk;
2649 od8_settings->od_gfxclk_update = true;
2650 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2651 od_table->GfxclkFmax = input_clk;
2652 od8_settings->od_gfxclk_update = true;
2658 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2659 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2660 pr_info("Mclk max frequency overdrive not supported\n");
2664 single_dpm_table = &(dpm_table->mem_table);
2665 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2667 pr_err("Attempt to get memory clk levels Failed!");
2671 for (i = 0; i < size; i += 2) {
2673 pr_info("invalid number of input parameters %d\n",
2678 input_index = input[i];
2679 input_clk = input[i + 1];
2681 if (input_index != 1) {
2682 pr_info("Invalid index %d\n", input_index);
2683 pr_info("Support max Mclk frequency setting only which index by 1\n");
2687 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2688 input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2689 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2691 clocks.data[0].clocks_in_khz / 1000,
2692 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2696 if (input_index == 1 && od_table->UclkFmax != input_clk) {
2697 od8_settings->od_gfxclk_update = true;
2698 od_table->UclkFmax = input_clk;
2704 case PP_OD_EDIT_VDDC_CURVE:
2705 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2706 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2707 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2708 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2709 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2710 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2711 pr_info("Voltage curve calibrate not supported\n");
2715 for (i = 0; i < size; i += 3) {
2717 pr_info("invalid number of input parameters %d\n",
2722 input_index = input[i];
2723 input_clk = input[i + 1];
2724 input_vol = input[i + 2];
2726 if (input_index > 2) {
2727 pr_info("Setting for point %d is not supported\n",
2729 pr_info("Three supported points index by 0, 1, 2\n");
2733 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2734 if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2735 input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2736 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2738 od8_settings->od8_settings_array[od8_id].min_value,
2739 od8_settings->od8_settings_array[od8_id].max_value);
2743 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2744 if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2745 input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2746 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2748 od8_settings->od8_settings_array[od8_id].min_value,
2749 od8_settings->od8_settings_array[od8_id].max_value);
2753 switch (input_index) {
2755 od_table->GfxclkFreq1 = input_clk;
2756 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2759 od_table->GfxclkFreq2 = input_clk;
2760 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2763 od_table->GfxclkFreq3 = input_clk;
2764 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2771 case PP_OD_RESTORE_DEFAULT_TABLE:
2772 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
2774 pr_err("Failed to export over drive table!\n");
2780 case PP_OD_COMMIT_DPM_TABLE:
2781 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
2783 pr_err("Failed to import over drive table!\n");
2787 /* retrieve updated gfxclk table */
2788 if (od8_settings->od_gfxclk_update) {
2789 od8_settings->od_gfxclk_update = false;
2790 single_dpm_table = &(dpm_table->gfx_table);
2792 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2793 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2796 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2800 single_dpm_table->count = 1;
2801 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2811 if (type == PP_OD_COMMIT_DPM_TABLE) {
2812 mutex_lock(&(smu->mutex));
2813 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2814 AMD_PP_TASK_READJUST_POWER_STATE);
2815 mutex_unlock(&(smu->mutex));
2821 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2823 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2826 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2829 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2832 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2834 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2837 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2840 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2843 static int vega20_get_enabled_smc_features(struct smu_context *smu,
2844 uint64_t *features_enabled)
2846 uint32_t feature_mask[2] = {0, 0};
2849 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2853 *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
2854 (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
2859 static int vega20_enable_smc_features(struct smu_context *smu,
2860 bool enable, uint64_t feature_mask)
2862 uint32_t smu_features_low, smu_features_high;
2865 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
2866 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
2869 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
2873 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
2878 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
2882 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
2892 static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
2894 static const char *ppfeature_name[] = {
2929 static const char *output_title[] = {
2933 uint64_t features_enabled;
2938 ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2942 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2943 size += sprintf(buf + size, "%-19s %-22s %s\n",
2947 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2948 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
2951 (features_enabled & (1ULL << i)) ? "Y" : "N");
2957 static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
2959 uint64_t features_enabled;
2960 uint64_t features_to_enable;
2961 uint64_t features_to_disable;
2964 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2967 ret = vega20_get_enabled_smc_features(smu, &features_enabled);
2971 features_to_disable =
2972 features_enabled & ~new_ppfeature_masks;
2973 features_to_enable =
2974 ~features_enabled & new_ppfeature_masks;
2976 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2977 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2979 if (features_to_disable) {
2980 ret = vega20_enable_smc_features(smu, false, features_to_disable);
2985 if (features_to_enable) {
2986 ret = vega20_enable_smc_features(smu, true, features_to_enable);
2994 static bool vega20_is_dpm_running(struct smu_context *smu)
2997 uint32_t feature_mask[2];
2998 unsigned long feature_enabled;
2999 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
3000 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
3001 ((uint64_t)feature_mask[1] << 32));
3002 return !!(feature_enabled & SMC_DPM_FEATURE);
3005 static int vega20_set_thermal_fan_table(struct smu_context *smu)
3008 struct smu_table_context *table_context = &smu->smu_table;
3009 PPTable_t *pptable = table_context->driver_pptable;
3011 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
3012 (uint32_t)pptable->FanTargetTemperature);
3017 static int vega20_get_fan_speed_rpm(struct smu_context *smu,
3022 ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
3025 pr_err("Attempt to get current RPM from SMC Failed!\n");
3029 smu_read_smc_arg(smu, speed);
3034 static int vega20_get_fan_speed_percent(struct smu_context *smu,
3038 uint32_t current_rpm = 0, percent = 0;
3039 PPTable_t *pptable = smu->smu_table.driver_pptable;
3041 ret = vega20_get_fan_speed_rpm(smu, ¤t_rpm);
3045 percent = current_rpm * 100 / pptable->FanMaximumRpm;
3046 *speed = percent > 100 ? 100 : percent;
3051 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
3054 SmuMetrics_t metrics;
3059 ret = vega20_get_metrics_table(smu, &metrics);
3063 *value = metrics.CurrSocketPower << 8;
3068 static int vega20_get_current_activity_percent(struct smu_context *smu,
3069 enum amd_pp_sensors sensor,
3073 SmuMetrics_t metrics;
3078 ret = vega20_get_metrics_table(smu, &metrics);
3083 case AMDGPU_PP_SENSOR_GPU_LOAD:
3084 *value = metrics.AverageGfxActivity;
3086 case AMDGPU_PP_SENSOR_MEM_LOAD:
3087 *value = metrics.AverageUclkActivity;
3090 pr_err("Invalid sensor for retrieving clock activity\n");
3097 static int vega20_thermal_get_temperature(struct smu_context *smu,
3098 enum amd_pp_sensors sensor,
3101 struct amdgpu_device *adev = smu->adev;
3102 SmuMetrics_t metrics;
3109 ret = vega20_get_metrics_table(smu, &metrics);
3114 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3115 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
3116 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
3117 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
3119 temp = temp & 0x1ff;
3120 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3124 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3125 *value = metrics.TemperatureEdge *
3126 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3128 case AMDGPU_PP_SENSOR_MEM_TEMP:
3129 *value = metrics.TemperatureHBM *
3130 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3133 pr_err("Invalid sensor for retrieving temp\n");
3139 static int vega20_read_sensor(struct smu_context *smu,
3140 enum amd_pp_sensors sensor,
3141 void *data, uint32_t *size)
3144 struct smu_table_context *table_context = &smu->smu_table;
3145 PPTable_t *pptable = table_context->driver_pptable;
3148 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3149 *(uint32_t *)data = pptable->FanMaximumRpm;
3152 case AMDGPU_PP_SENSOR_MEM_LOAD:
3153 case AMDGPU_PP_SENSOR_GPU_LOAD:
3154 ret = vega20_get_current_activity_percent(smu,
3159 case AMDGPU_PP_SENSOR_GPU_POWER:
3160 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3163 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3164 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3165 case AMDGPU_PP_SENSOR_MEM_TEMP:
3166 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3176 static int vega20_set_watermarks_table(struct smu_context *smu,
3177 void *watermarks, struct
3178 dm_pp_wm_sets_with_clock_ranges_soc15
3182 Watermarks_t *table = watermarks;
3184 if (!table || !clock_ranges)
3187 if (clock_ranges->num_wm_dmif_sets > 4 ||
3188 clock_ranges->num_wm_mcif_sets > 4)
3191 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3192 table->WatermarkRow[1][i].MinClock =
3193 cpu_to_le16((uint16_t)
3194 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3196 table->WatermarkRow[1][i].MaxClock =
3197 cpu_to_le16((uint16_t)
3198 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3200 table->WatermarkRow[1][i].MinUclk =
3201 cpu_to_le16((uint16_t)
3202 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3204 table->WatermarkRow[1][i].MaxUclk =
3205 cpu_to_le16((uint16_t)
3206 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3208 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3209 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3212 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3213 table->WatermarkRow[0][i].MinClock =
3214 cpu_to_le16((uint16_t)
3215 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3217 table->WatermarkRow[0][i].MaxClock =
3218 cpu_to_le16((uint16_t)
3219 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3221 table->WatermarkRow[0][i].MinUclk =
3222 cpu_to_le16((uint16_t)
3223 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3225 table->WatermarkRow[0][i].MaxUclk =
3226 cpu_to_le16((uint16_t)
3227 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3229 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3230 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3236 static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3237 struct smu_temperature_range *range)
3239 struct smu_table_context *table_context = &smu->smu_table;
3240 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = table_context->power_play_table;
3241 PPTable_t *pptable = smu->smu_table.driver_pptable;
3243 if (!range || !powerplay_table)
3246 /* The unit is temperature */
3248 range->max = powerplay_table->usSoftwareShutdownTemp;
3249 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE);
3250 range->hotspot_crit_max = pptable->ThotspotLimit;
3251 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT);
3252 range->mem_crit_max = pptable->ThbmLimit;
3253 range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM);
3259 static const struct pptable_funcs vega20_ppt_funcs = {
3260 .tables_init = vega20_tables_init,
3261 .alloc_dpm_context = vega20_allocate_dpm_context,
3262 .store_powerplay_table = vega20_store_powerplay_table,
3263 .check_powerplay_table = vega20_check_powerplay_table,
3264 .append_powerplay_table = vega20_append_powerplay_table,
3265 .get_smu_msg_index = vega20_get_smu_msg_index,
3266 .get_smu_clk_index = vega20_get_smu_clk_index,
3267 .get_smu_feature_index = vega20_get_smu_feature_index,
3268 .get_smu_table_index = vega20_get_smu_table_index,
3269 .get_smu_power_index = vega20_get_pwr_src_index,
3270 .get_workload_type = vega20_get_workload_type,
3271 .run_afll_btc = vega20_run_btc_afll,
3272 .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3273 .get_current_power_state = vega20_get_current_power_state,
3274 .set_default_dpm_table = vega20_set_default_dpm_table,
3275 .set_power_state = NULL,
3276 .populate_umd_state_clk = vega20_populate_umd_state_clk,
3277 .print_clk_levels = vega20_print_clk_levels,
3278 .force_clk_levels = vega20_force_clk_levels,
3279 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3280 .get_od_percentage = vega20_get_od_percentage,
3281 .get_power_profile_mode = vega20_get_power_profile_mode,
3282 .set_power_profile_mode = vega20_set_power_profile_mode,
3283 .set_od_percentage = vega20_set_od_percentage,
3284 .set_default_od_settings = vega20_set_default_od_settings,
3285 .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3286 .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3287 .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3288 .read_sensor = vega20_read_sensor,
3289 .pre_display_config_changed = vega20_pre_display_config_changed,
3290 .display_config_changed = vega20_display_config_changed,
3291 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3292 .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
3293 .force_dpm_limit_value = vega20_force_dpm_limit_value,
3294 .unforce_dpm_levels = vega20_unforce_dpm_levels,
3295 .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3296 .set_ppfeature_status = vega20_set_ppfeature_status,
3297 .get_ppfeature_status = vega20_get_ppfeature_status,
3298 .is_dpm_running = vega20_is_dpm_running,
3299 .set_thermal_fan_table = vega20_set_thermal_fan_table,
3300 .get_fan_speed_percent = vega20_get_fan_speed_percent,
3301 .get_fan_speed_rpm = vega20_get_fan_speed_rpm,
3302 .set_watermarks_table = vega20_set_watermarks_table,
3303 .get_thermal_temperature_range = vega20_get_thermal_temperature_range
3306 void vega20_set_ppt_funcs(struct smu_context *smu)
3308 struct smu_table_context *smu_table = &smu->smu_table;
3310 smu->ppt_funcs = &vega20_ppt_funcs;
3311 smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
3312 smu_table->table_count = TABLE_COUNT;