2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "smu_internal.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "smu_v11_0.h"
32 #include "smu11_driver_if.h"
33 #include "soc15_common.h"
35 #include "power_state.h"
36 #include "vega20_ppt.h"
37 #include "vega20_pptable.h"
38 #include "vega20_ppsmc.h"
39 #include "nbio/nbio_7_4_sh_mask.h"
40 #include "asic_reg/thm/thm_11_0_2_offset.h"
41 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
43 #define smnPCIE_LC_SPEED_CNTL 0x11140290
44 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
46 #define CTF_OFFSET_EDGE 5
47 #define CTF_OFFSET_HOTSPOT 5
48 #define CTF_OFFSET_HBM 5
50 #define MSG_MAP(msg) \
51 [SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
53 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
54 FEATURE_DPM_GFXCLK_MASK | \
55 FEATURE_DPM_UCLK_MASK | \
56 FEATURE_DPM_SOCCLK_MASK | \
57 FEATURE_DPM_UVD_MASK | \
58 FEATURE_DPM_VCE_MASK | \
59 FEATURE_DPM_MP0CLK_MASK | \
60 FEATURE_DPM_LINK_MASK | \
61 FEATURE_DPM_DCEFCLK_MASK)
63 static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
65 MSG_MAP(GetSmuVersion),
66 MSG_MAP(GetDriverIfVersion),
67 MSG_MAP(SetAllowedFeaturesMaskLow),
68 MSG_MAP(SetAllowedFeaturesMaskHigh),
69 MSG_MAP(EnableAllSmuFeatures),
70 MSG_MAP(DisableAllSmuFeatures),
71 MSG_MAP(EnableSmuFeaturesLow),
72 MSG_MAP(EnableSmuFeaturesHigh),
73 MSG_MAP(DisableSmuFeaturesLow),
74 MSG_MAP(DisableSmuFeaturesHigh),
75 MSG_MAP(GetEnabledSmuFeaturesLow),
76 MSG_MAP(GetEnabledSmuFeaturesHigh),
77 MSG_MAP(SetWorkloadMask),
79 MSG_MAP(SetDriverDramAddrHigh),
80 MSG_MAP(SetDriverDramAddrLow),
81 MSG_MAP(SetToolsDramAddrHigh),
82 MSG_MAP(SetToolsDramAddrLow),
83 MSG_MAP(TransferTableSmu2Dram),
84 MSG_MAP(TransferTableDram2Smu),
85 MSG_MAP(UseDefaultPPTable),
86 MSG_MAP(UseBackupPPTable),
88 MSG_MAP(RequestI2CBus),
89 MSG_MAP(ReleaseI2CBus),
90 MSG_MAP(SetFloorSocVoltage),
92 MSG_MAP(StartBacoMonitor),
93 MSG_MAP(CancelBacoMonitor),
95 MSG_MAP(SetSoftMinByFreq),
96 MSG_MAP(SetSoftMaxByFreq),
97 MSG_MAP(SetHardMinByFreq),
98 MSG_MAP(SetHardMaxByFreq),
99 MSG_MAP(GetMinDpmFreq),
100 MSG_MAP(GetMaxDpmFreq),
101 MSG_MAP(GetDpmFreqByIndex),
102 MSG_MAP(GetDpmClockFreq),
103 MSG_MAP(GetSsVoltageByDpm),
104 MSG_MAP(SetMemoryChannelConfig),
105 MSG_MAP(SetGeminiMode),
106 MSG_MAP(SetGeminiApertureHigh),
107 MSG_MAP(SetGeminiApertureLow),
108 MSG_MAP(SetMinLinkDpmByIndex),
109 MSG_MAP(OverridePcieParameters),
110 MSG_MAP(OverDriveSetPercentage),
111 MSG_MAP(SetMinDeepSleepDcefclk),
112 MSG_MAP(ReenableAcDcInterrupt),
113 MSG_MAP(NotifyPowerSource),
114 MSG_MAP(SetUclkFastSwitch),
115 MSG_MAP(SetUclkDownHyst),
116 MSG_MAP(GetCurrentRpm),
117 MSG_MAP(SetVideoFps),
119 MSG_MAP(SetFanTemperatureTarget),
120 MSG_MAP(PrepareMp1ForUnload),
121 MSG_MAP(DramLogSetDramAddrHigh),
122 MSG_MAP(DramLogSetDramAddrLow),
123 MSG_MAP(DramLogSetDramSize),
124 MSG_MAP(SetFanMaxRpm),
125 MSG_MAP(SetFanMinPwm),
126 MSG_MAP(ConfigureGfxDidt),
127 MSG_MAP(NumOfDisplays),
128 MSG_MAP(RemoveMargins),
129 MSG_MAP(ReadSerialNumTop32),
130 MSG_MAP(ReadSerialNumBottom32),
131 MSG_MAP(SetSystemVirtualDramAddrHigh),
132 MSG_MAP(SetSystemVirtualDramAddrLow),
134 MSG_MAP(SetFclkGfxClkRatio),
135 MSG_MAP(AllowGfxOff),
136 MSG_MAP(DisallowGfxOff),
137 MSG_MAP(GetPptLimit),
138 MSG_MAP(GetDcModeMaxDpmFreq),
139 MSG_MAP(GetDebugData),
140 MSG_MAP(SetXgmiMode),
143 MSG_MAP(PrepareMp1ForReset),
144 MSG_MAP(PrepareMp1ForShutdown),
145 MSG_MAP(SetMGpuFanBoostLimitRpm),
146 MSG_MAP(GetAVFSVoltageByDpm),
147 MSG_MAP(DFCstateControl),
150 static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(VCLK, PPCLK_VCLK),
153 CLK_MAP(DCLK, PPCLK_DCLK),
154 CLK_MAP(ECLK, PPCLK_ECLK),
155 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
156 CLK_MAP(UCLK, PPCLK_UCLK),
157 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
158 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
159 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
160 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
161 CLK_MAP(FCLK, PPCLK_FCLK),
164 static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
165 FEA_MAP(DPM_PREFETCHER),
174 FEA_MAP(DPM_DCEFCLK),
181 FEA_MAP(GFX_PER_CU_CG),
188 FEA_MAP(LED_DISPLAY),
189 FEA_MAP(FAN_CONTROL),
200 static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
204 TAB_MAP(AVFS_PSM_DEBUG),
205 TAB_MAP(AVFS_FUSE_OVERRIDE),
206 TAB_MAP(PMSTATUSLOG),
207 TAB_MAP(SMU_METRICS),
208 TAB_MAP(DRIVER_SMU_CONFIG),
209 TAB_MAP(ACTIVITY_MONITOR_COEFF),
213 static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
218 static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
224 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
228 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
230 struct smu_11_0_cmn2aisc_mapping mapping;
232 if (index >= SMU_TABLE_COUNT)
235 mapping = vega20_table_map[index];
236 if (!(mapping.valid_mapping)) {
240 return mapping.map_to;
243 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
245 struct smu_11_0_cmn2aisc_mapping mapping;
247 if (index >= SMU_POWER_SOURCE_COUNT)
250 mapping = vega20_pwr_src_map[index];
251 if (!(mapping.valid_mapping)) {
255 return mapping.map_to;
258 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
260 struct smu_11_0_cmn2aisc_mapping mapping;
262 if (index >= SMU_FEATURE_COUNT)
265 mapping = vega20_feature_mask_map[index];
266 if (!(mapping.valid_mapping)) {
270 return mapping.map_to;
273 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
275 struct smu_11_0_cmn2aisc_mapping mapping;
277 if (index >= SMU_CLK_COUNT)
280 mapping = vega20_clk_map[index];
281 if (!(mapping.valid_mapping)) {
285 return mapping.map_to;
288 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
290 struct smu_11_0_cmn2aisc_mapping mapping;
292 if (index >= SMU_MSG_MAX_COUNT)
295 mapping = vega20_message_map[index];
296 if (!(mapping.valid_mapping)) {
300 return mapping.map_to;
303 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
305 struct smu_11_0_cmn2aisc_mapping mapping;
307 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
310 mapping = vega20_workload_map[profile];
311 if (!(mapping.valid_mapping)) {
315 return mapping.map_to;
318 static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
320 struct smu_table_context *smu_table = &smu->smu_table;
322 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
323 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
324 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
325 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
326 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
327 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
328 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
329 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
330 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
331 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
332 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
333 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
334 AMDGPU_GEM_DOMAIN_VRAM);
336 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
337 if (!smu_table->metrics_table)
339 smu_table->metrics_time = 0;
344 static int vega20_allocate_dpm_context(struct smu_context *smu)
346 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
348 if (smu_dpm->dpm_context)
351 smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
353 if (!smu_dpm->dpm_context)
356 if (smu_dpm->golden_dpm_context)
359 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
361 if (!smu_dpm->golden_dpm_context)
364 smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
366 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
368 if (!smu_dpm->dpm_current_power_state)
371 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
373 if (!smu_dpm->dpm_request_power_state)
379 static int vega20_setup_od8_information(struct smu_context *smu)
381 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
382 struct smu_table_context *table_context = &smu->smu_table;
383 struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
385 uint32_t od_feature_count, od_feature_array_size,
386 od_setting_count, od_setting_array_size;
388 if (!table_context->power_play_table)
391 powerplay_table = table_context->power_play_table;
393 if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
394 /* Setup correct ODFeatureCount, and store ODFeatureArray from
395 * powerplay table to od_feature_capabilities */
397 (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
398 ATOM_VEGA20_ODFEATURE_COUNT) ?
399 ATOM_VEGA20_ODFEATURE_COUNT :
400 le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
402 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
404 if (od8_settings->od_feature_capabilities)
407 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
408 od_feature_array_size,
410 if (!od8_settings->od_feature_capabilities)
413 /* Setup correct ODSettingCount, and store ODSettingArray from
414 * powerplay table to od_settings_max and od_setting_min */
416 (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
417 ATOM_VEGA20_ODSETTING_COUNT) ?
418 ATOM_VEGA20_ODSETTING_COUNT :
419 le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
421 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
423 if (od8_settings->od_settings_max)
426 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
427 od_setting_array_size,
430 if (!od8_settings->od_settings_max) {
431 kfree(od8_settings->od_feature_capabilities);
432 od8_settings->od_feature_capabilities = NULL;
436 if (od8_settings->od_settings_min)
439 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
440 od_setting_array_size,
443 if (!od8_settings->od_settings_min) {
444 kfree(od8_settings->od_feature_capabilities);
445 od8_settings->od_feature_capabilities = NULL;
446 kfree(od8_settings->od_settings_max);
447 od8_settings->od_settings_max = NULL;
455 static int vega20_store_powerplay_table(struct smu_context *smu)
457 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
458 struct smu_table_context *table_context = &smu->smu_table;
460 if (!table_context->power_play_table)
463 powerplay_table = table_context->power_play_table;
465 memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
468 table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
469 table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
474 static int vega20_append_powerplay_table(struct smu_context *smu)
476 struct smu_table_context *table_context = &smu->smu_table;
477 PPTable_t *smc_pptable = table_context->driver_pptable;
478 struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
481 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
484 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
485 (uint8_t **)&smc_dpm_table);
489 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
490 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
492 smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
493 smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
494 smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
495 smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
497 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
498 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
499 smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
501 smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
502 smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
503 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
505 smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
506 smc_pptable->SocOffset = smc_dpm_table->socoffset;
507 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
509 smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
510 smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
511 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
513 smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
514 smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
515 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
517 smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
518 smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
519 smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
520 smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
522 smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
523 smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
524 smc_pptable->Padding1 = smc_dpm_table->padding1;
525 smc_pptable->Padding2 = smc_dpm_table->padding2;
527 smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
528 smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
529 smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
531 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
532 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
533 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
535 smc_pptable->UclkSpreadEnabled = 0;
536 smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
537 smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
539 smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
540 smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
541 smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
543 smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
544 smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
545 smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
547 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
548 smc_pptable->I2cControllers[i].Enabled =
549 smc_dpm_table->i2ccontrollers[i].enabled;
550 smc_pptable->I2cControllers[i].SlaveAddress =
551 smc_dpm_table->i2ccontrollers[i].slaveaddress;
552 smc_pptable->I2cControllers[i].ControllerPort =
553 smc_dpm_table->i2ccontrollers[i].controllerport;
554 smc_pptable->I2cControllers[i].ThermalThrottler =
555 smc_dpm_table->i2ccontrollers[i].thermalthrottler;
556 smc_pptable->I2cControllers[i].I2cProtocol =
557 smc_dpm_table->i2ccontrollers[i].i2cprotocol;
558 smc_pptable->I2cControllers[i].I2cSpeed =
559 smc_dpm_table->i2ccontrollers[i].i2cspeed;
565 static int vega20_check_powerplay_table(struct smu_context *smu)
567 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
568 struct smu_table_context *table_context = &smu->smu_table;
570 powerplay_table = table_context->power_play_table;
572 if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
573 pr_err("Unsupported PPTable format!");
577 if (!powerplay_table->sHeader.structuresize) {
578 pr_err("Invalid PowerPlay Table!");
585 static int vega20_run_btc_afll(struct smu_context *smu)
587 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
590 #define FEATURE_MASK(feature) (1ULL << feature)
592 vega20_get_allowed_feature_mask(struct smu_context *smu,
593 uint32_t *feature_mask, uint32_t num)
598 memset(feature_mask, 0, sizeof(uint32_t) * num);
600 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
601 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
602 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
603 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
604 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
605 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
606 | FEATURE_MASK(FEATURE_ULV_BIT)
607 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
608 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
609 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
610 | FEATURE_MASK(FEATURE_PPT_BIT)
611 | FEATURE_MASK(FEATURE_TDC_BIT)
612 | FEATURE_MASK(FEATURE_THERMAL_BIT)
613 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
614 | FEATURE_MASK(FEATURE_RM_BIT)
615 | FEATURE_MASK(FEATURE_ACDC_BIT)
616 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
617 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
618 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
619 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
620 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
621 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
622 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
623 | FEATURE_MASK(FEATURE_CG_BIT)
624 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
625 | FEATURE_MASK(FEATURE_XGMI_BIT);
630 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
632 enum amd_pm_state_type pm_type;
633 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
635 if (!smu_dpm_ctx->dpm_context ||
636 !smu_dpm_ctx->dpm_current_power_state)
639 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
640 case SMU_STATE_UI_LABEL_BATTERY:
641 pm_type = POWER_STATE_TYPE_BATTERY;
643 case SMU_STATE_UI_LABEL_BALLANCED:
644 pm_type = POWER_STATE_TYPE_BALANCED;
646 case SMU_STATE_UI_LABEL_PERFORMANCE:
647 pm_type = POWER_STATE_TYPE_PERFORMANCE;
650 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
651 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
653 pm_type = POWER_STATE_TYPE_DEFAULT;
661 vega20_set_single_dpm_table(struct smu_context *smu,
662 struct vega20_single_dpm_table *single_dpm_table,
666 uint32_t i, num_of_levels = 0, clk;
668 ret = smu_send_smc_msg_with_param(smu,
669 SMU_MSG_GetDpmFreqByIndex,
670 (clk_id << 16 | 0xFF));
672 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
676 smu_read_smc_arg(smu, &num_of_levels);
677 if (!num_of_levels) {
678 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
682 single_dpm_table->count = num_of_levels;
684 for (i = 0; i < num_of_levels; i++) {
685 ret = smu_send_smc_msg_with_param(smu,
686 SMU_MSG_GetDpmFreqByIndex,
689 pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
692 smu_read_smc_arg(smu, &clk);
694 pr_err("[GetDpmFreqByIndex] clk value is invalid!");
697 single_dpm_table->dpm_levels[i].value = clk;
698 single_dpm_table->dpm_levels[i].enabled = true;
703 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
705 dpm_state->soft_min_level = 0x0;
706 dpm_state->soft_max_level = 0xffff;
707 dpm_state->hard_min_level = 0x0;
708 dpm_state->hard_max_level = 0xffff;
711 static int vega20_set_default_dpm_table(struct smu_context *smu)
715 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
716 struct vega20_dpm_table *dpm_table = NULL;
717 struct vega20_single_dpm_table *single_dpm_table;
719 dpm_table = smu_dpm->dpm_context;
722 single_dpm_table = &(dpm_table->soc_table);
724 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
725 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
728 pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
732 single_dpm_table->count = 1;
733 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
735 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
738 single_dpm_table = &(dpm_table->gfx_table);
740 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
741 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
744 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
748 single_dpm_table->count = 1;
749 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
751 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
754 single_dpm_table = &(dpm_table->mem_table);
756 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
757 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
760 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
764 single_dpm_table->count = 1;
765 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
767 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
770 single_dpm_table = &(dpm_table->eclk_table);
772 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
773 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
775 pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
779 single_dpm_table->count = 1;
780 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
782 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
785 single_dpm_table = &(dpm_table->vclk_table);
787 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
788 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
790 pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
794 single_dpm_table->count = 1;
795 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
797 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
800 single_dpm_table = &(dpm_table->dclk_table);
802 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
803 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
805 pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
809 single_dpm_table->count = 1;
810 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
812 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
815 single_dpm_table = &(dpm_table->dcef_table);
817 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
818 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
821 pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
825 single_dpm_table->count = 1;
826 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
828 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
831 single_dpm_table = &(dpm_table->pixel_table);
833 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
834 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
837 pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
841 single_dpm_table->count = 0;
843 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
846 single_dpm_table = &(dpm_table->display_table);
848 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
849 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
852 pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
856 single_dpm_table->count = 0;
858 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
861 single_dpm_table = &(dpm_table->phy_table);
863 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
864 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
867 pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
871 single_dpm_table->count = 0;
873 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
876 single_dpm_table = &(dpm_table->fclk_table);
878 if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
879 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
882 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
886 single_dpm_table->count = 0;
888 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
890 memcpy(smu_dpm->golden_dpm_context, dpm_table,
891 sizeof(struct vega20_dpm_table));
896 static int vega20_populate_umd_state_clk(struct smu_context *smu)
898 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
899 struct vega20_dpm_table *dpm_table = NULL;
900 struct vega20_single_dpm_table *gfx_table = NULL;
901 struct vega20_single_dpm_table *mem_table = NULL;
903 dpm_table = smu_dpm->dpm_context;
904 gfx_table = &(dpm_table->gfx_table);
905 mem_table = &(dpm_table->mem_table);
907 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
908 smu->pstate_mclk = mem_table->dpm_levels[0].value;
910 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
911 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
912 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
913 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
916 smu->pstate_sclk = smu->pstate_sclk * 100;
917 smu->pstate_mclk = smu->pstate_mclk * 100;
922 static int vega20_get_clk_table(struct smu_context *smu,
923 struct pp_clock_levels_with_latency *clocks,
924 struct vega20_single_dpm_table *dpm_table)
928 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
929 clocks->num_levels = count;
931 for (i = 0; i < count; i++) {
932 clocks->data[i].clocks_in_khz =
933 dpm_table->dpm_levels[i].value * 1000;
934 clocks->data[i].latency_in_us = 0;
940 static int vega20_print_clk_levels(struct smu_context *smu,
941 enum smu_clk_type type, char *buf)
943 int i, now, size = 0;
945 uint32_t gen_speed, lane_width;
946 struct amdgpu_device *adev = smu->adev;
947 struct pp_clock_levels_with_latency clocks;
948 struct vega20_single_dpm_table *single_dpm_table;
949 struct smu_table_context *table_context = &smu->smu_table;
950 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
951 struct vega20_dpm_table *dpm_table = NULL;
952 struct vega20_od8_settings *od8_settings =
953 (struct vega20_od8_settings *)smu->od_settings;
954 OverDriveTable_t *od_table =
955 (OverDriveTable_t *)(table_context->overdrive_table);
956 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
958 dpm_table = smu_dpm->dpm_context;
962 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
964 pr_err("Attempt to get current gfx clk Failed!");
968 single_dpm_table = &(dpm_table->gfx_table);
969 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
971 pr_err("Attempt to get gfx clk levels Failed!");
975 for (i = 0; i < clocks.num_levels; i++)
976 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
977 clocks.data[i].clocks_in_khz / 1000,
978 (clocks.data[i].clocks_in_khz == now * 10)
983 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
985 pr_err("Attempt to get current mclk Failed!");
989 single_dpm_table = &(dpm_table->mem_table);
990 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
992 pr_err("Attempt to get memory clk levels Failed!");
996 for (i = 0; i < clocks.num_levels; i++)
997 size += sprintf(buf + size, "%d: %uMhz %s\n",
998 i, clocks.data[i].clocks_in_khz / 1000,
999 (clocks.data[i].clocks_in_khz == now * 10)
1004 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
1006 pr_err("Attempt to get current socclk Failed!");
1010 single_dpm_table = &(dpm_table->soc_table);
1011 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1013 pr_err("Attempt to get socclk levels Failed!");
1017 for (i = 0; i < clocks.num_levels; i++)
1018 size += sprintf(buf + size, "%d: %uMhz %s\n",
1019 i, clocks.data[i].clocks_in_khz / 1000,
1020 (clocks.data[i].clocks_in_khz == now * 10)
1025 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1027 pr_err("Attempt to get current fclk Failed!");
1031 single_dpm_table = &(dpm_table->fclk_table);
1032 for (i = 0; i < single_dpm_table->count; i++)
1033 size += sprintf(buf + size, "%d: %uMhz %s\n",
1034 i, single_dpm_table->dpm_levels[i].value,
1035 (single_dpm_table->dpm_levels[i].value == now / 100)
1040 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1042 pr_err("Attempt to get current dcefclk Failed!");
1046 single_dpm_table = &(dpm_table->dcef_table);
1047 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1049 pr_err("Attempt to get dcefclk levels Failed!");
1053 for (i = 0; i < clocks.num_levels; i++)
1054 size += sprintf(buf + size, "%d: %uMhz %s\n",
1055 i, clocks.data[i].clocks_in_khz / 1000,
1056 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1060 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1061 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1062 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1063 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1064 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1065 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1066 for (i = 0; i < NUM_LINK_LEVELS; i++)
1067 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1068 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1069 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1070 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1071 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1072 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1073 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1074 (pptable->PcieLaneCount[i] == 3) ? "x4" :
1075 (pptable->PcieLaneCount[i] == 4) ? "x8" :
1076 (pptable->PcieLaneCount[i] == 5) ? "x12" :
1077 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1078 pptable->LclkFreq[i],
1079 (gen_speed == pptable->PcieGenSpeed[i]) &&
1080 (lane_width == pptable->PcieLaneCount[i]) ?
1085 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1086 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1087 size = sprintf(buf, "%s:\n", "OD_SCLK");
1088 size += sprintf(buf + size, "0: %10uMhz\n",
1089 od_table->GfxclkFmin);
1090 size += sprintf(buf + size, "1: %10uMhz\n",
1091 od_table->GfxclkFmax);
1097 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1098 size = sprintf(buf, "%s:\n", "OD_MCLK");
1099 size += sprintf(buf + size, "1: %10uMhz\n",
1100 od_table->UclkFmax);
1105 case SMU_OD_VDDC_CURVE:
1106 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1107 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1108 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1109 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1110 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1111 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1112 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1113 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1114 od_table->GfxclkFreq1,
1115 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1116 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1117 od_table->GfxclkFreq2,
1118 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1119 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1120 od_table->GfxclkFreq3,
1121 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1127 size = sprintf(buf, "%s:\n", "OD_RANGE");
1129 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1130 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1131 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1132 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1133 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1136 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1137 single_dpm_table = &(dpm_table->mem_table);
1138 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1140 pr_err("Attempt to get memory clk levels Failed!");
1144 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1145 clocks.data[0].clocks_in_khz / 1000,
1146 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1149 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1150 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1151 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1152 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1153 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1154 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1155 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1156 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1157 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1158 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1159 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1160 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1161 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1162 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1163 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1164 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1165 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1166 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1167 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1168 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1169 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1170 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1171 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1172 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1183 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1184 uint32_t feature_mask)
1186 struct vega20_dpm_table *dpm_table;
1187 struct vega20_single_dpm_table *single_dpm_table;
1191 dpm_table = smu->smu_dpm.dpm_context;
1193 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1194 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1195 single_dpm_table = &(dpm_table->gfx_table);
1196 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1197 single_dpm_table->dpm_state.soft_min_level;
1198 ret = smu_send_smc_msg_with_param(smu,
1199 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1200 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1202 pr_err("Failed to set soft %s gfxclk !\n",
1203 max ? "max" : "min");
1208 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1209 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1210 single_dpm_table = &(dpm_table->mem_table);
1211 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1212 single_dpm_table->dpm_state.soft_min_level;
1213 ret = smu_send_smc_msg_with_param(smu,
1214 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1215 (PPCLK_UCLK << 16) | (freq & 0xffff));
1217 pr_err("Failed to set soft %s memclk !\n",
1218 max ? "max" : "min");
1223 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1224 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1225 single_dpm_table = &(dpm_table->soc_table);
1226 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1227 single_dpm_table->dpm_state.soft_min_level;
1228 ret = smu_send_smc_msg_with_param(smu,
1229 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1230 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1232 pr_err("Failed to set soft %s socclk !\n",
1233 max ? "max" : "min");
1238 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1239 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1240 single_dpm_table = &(dpm_table->fclk_table);
1241 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1242 single_dpm_table->dpm_state.soft_min_level;
1243 ret = smu_send_smc_msg_with_param(smu,
1244 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1245 (PPCLK_FCLK << 16) | (freq & 0xffff));
1247 pr_err("Failed to set soft %s fclk !\n",
1248 max ? "max" : "min");
1253 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1254 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1255 single_dpm_table = &(dpm_table->dcef_table);
1256 freq = single_dpm_table->dpm_state.hard_min_level;
1258 ret = smu_send_smc_msg_with_param(smu,
1259 SMU_MSG_SetHardMinByFreq,
1260 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1262 pr_err("Failed to set hard min dcefclk !\n");
1271 static int vega20_force_clk_levels(struct smu_context *smu,
1272 enum smu_clk_type clk_type, uint32_t mask)
1274 struct vega20_dpm_table *dpm_table;
1275 struct vega20_single_dpm_table *single_dpm_table;
1276 uint32_t soft_min_level, soft_max_level, hard_min_level;
1279 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1280 soft_max_level = mask ? (fls(mask) - 1) : 0;
1282 dpm_table = smu->smu_dpm.dpm_context;
1286 single_dpm_table = &(dpm_table->gfx_table);
1288 if (soft_max_level >= single_dpm_table->count) {
1289 pr_err("Clock level specified %d is over max allowed %d\n",
1290 soft_max_level, single_dpm_table->count - 1);
1295 single_dpm_table->dpm_state.soft_min_level =
1296 single_dpm_table->dpm_levels[soft_min_level].value;
1297 single_dpm_table->dpm_state.soft_max_level =
1298 single_dpm_table->dpm_levels[soft_max_level].value;
1300 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1302 pr_err("Failed to upload boot level to lowest!\n");
1306 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1308 pr_err("Failed to upload dpm max level to highest!\n");
1313 single_dpm_table = &(dpm_table->mem_table);
1315 if (soft_max_level >= single_dpm_table->count) {
1316 pr_err("Clock level specified %d is over max allowed %d\n",
1317 soft_max_level, single_dpm_table->count - 1);
1322 single_dpm_table->dpm_state.soft_min_level =
1323 single_dpm_table->dpm_levels[soft_min_level].value;
1324 single_dpm_table->dpm_state.soft_max_level =
1325 single_dpm_table->dpm_levels[soft_max_level].value;
1327 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1329 pr_err("Failed to upload boot level to lowest!\n");
1333 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1335 pr_err("Failed to upload dpm max level to highest!\n");
1340 single_dpm_table = &(dpm_table->soc_table);
1342 if (soft_max_level >= single_dpm_table->count) {
1343 pr_err("Clock level specified %d is over max allowed %d\n",
1344 soft_max_level, single_dpm_table->count - 1);
1349 single_dpm_table->dpm_state.soft_min_level =
1350 single_dpm_table->dpm_levels[soft_min_level].value;
1351 single_dpm_table->dpm_state.soft_max_level =
1352 single_dpm_table->dpm_levels[soft_max_level].value;
1354 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1356 pr_err("Failed to upload boot level to lowest!\n");
1360 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1362 pr_err("Failed to upload dpm max level to highest!\n");
1367 single_dpm_table = &(dpm_table->fclk_table);
1369 if (soft_max_level >= single_dpm_table->count) {
1370 pr_err("Clock level specified %d is over max allowed %d\n",
1371 soft_max_level, single_dpm_table->count - 1);
1376 single_dpm_table->dpm_state.soft_min_level =
1377 single_dpm_table->dpm_levels[soft_min_level].value;
1378 single_dpm_table->dpm_state.soft_max_level =
1379 single_dpm_table->dpm_levels[soft_max_level].value;
1381 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1383 pr_err("Failed to upload boot level to lowest!\n");
1387 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1389 pr_err("Failed to upload dpm max level to highest!\n");
1394 hard_min_level = soft_min_level;
1395 single_dpm_table = &(dpm_table->dcef_table);
1397 if (hard_min_level >= single_dpm_table->count) {
1398 pr_err("Clock level specified %d is over max allowed %d\n",
1399 hard_min_level, single_dpm_table->count - 1);
1404 single_dpm_table->dpm_state.hard_min_level =
1405 single_dpm_table->dpm_levels[hard_min_level].value;
1407 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1409 pr_err("Failed to upload boot level to lowest!\n");
1414 if (soft_min_level >= NUM_LINK_LEVELS ||
1415 soft_max_level >= NUM_LINK_LEVELS) {
1420 ret = smu_send_smc_msg_with_param(smu,
1421 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1423 pr_err("Failed to set min link dpm level!\n");
1434 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1435 enum smu_clk_type clk_type,
1436 struct pp_clock_levels_with_latency *clocks)
1439 struct vega20_single_dpm_table *single_dpm_table;
1440 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1441 struct vega20_dpm_table *dpm_table = NULL;
1443 dpm_table = smu_dpm->dpm_context;
1447 single_dpm_table = &(dpm_table->gfx_table);
1448 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1451 single_dpm_table = &(dpm_table->mem_table);
1452 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1455 single_dpm_table = &(dpm_table->dcef_table);
1456 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1459 single_dpm_table = &(dpm_table->soc_table);
1460 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1469 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1475 ret = smu_send_smc_msg_with_param(smu,
1476 SMU_MSG_GetAVFSVoltageByDpm,
1477 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1479 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1483 smu_read_smc_arg(smu, voltage);
1484 *voltage = *voltage / VOLTAGE_SCALE;
1489 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1491 struct smu_table_context *table_context = &smu->smu_table;
1492 OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1493 struct vega20_od8_settings *od8_settings = NULL;
1494 PPTable_t *smc_pptable = table_context->driver_pptable;
1497 if (smu->od_settings)
1500 od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1505 smu->od_settings = (void *)od8_settings;
1507 ret = vega20_setup_od8_information(smu);
1509 pr_err("Retrieve board OD limits failed!\n");
1513 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1514 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1515 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1516 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1517 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1518 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1519 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1521 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1523 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1524 od_table->GfxclkFmin;
1525 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1526 od_table->GfxclkFmax;
1529 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1530 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1531 smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1532 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1533 smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1534 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1535 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1536 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1538 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1540 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1542 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1544 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1546 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1549 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1550 od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1551 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1552 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1553 od_table->GfxclkFreq1;
1554 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1555 od_table->GfxclkFreq2;
1556 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1557 od_table->GfxclkFreq3;
1559 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1560 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1561 od_table->GfxclkFreq1);
1563 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1564 od_table->GfxclkVolt1 =
1565 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1567 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1568 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1569 od_table->GfxclkFreq2);
1571 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1572 od_table->GfxclkVolt2 =
1573 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1575 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1576 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1577 od_table->GfxclkFreq3);
1579 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1580 od_table->GfxclkVolt3 =
1581 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1586 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1587 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1588 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1589 od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1590 (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1591 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1592 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1594 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1599 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1600 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1601 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1602 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1603 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1604 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1606 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1607 od_table->OverDrivePct;
1610 if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1611 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1612 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1613 od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1614 (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1615 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1616 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1617 OD8_ACOUSTIC_LIMIT_SCLK;
1618 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1619 od_table->FanMaximumRpm;
1622 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1623 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1624 od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1625 (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1626 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1627 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1629 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1630 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1634 if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1635 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1636 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1637 od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1638 (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1639 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1640 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1641 OD8_TEMPERATURE_FAN;
1642 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1643 od_table->FanTargetTemperature;
1646 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1647 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1648 od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1649 (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1650 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1651 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1652 OD8_TEMPERATURE_SYSTEM;
1653 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1654 od_table->MaxOpTemp;
1658 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1659 if (od8_settings->od8_settings_array[i].feature_id) {
1660 od8_settings->od8_settings_array[i].min_value =
1661 od8_settings->od_settings_min[i];
1662 od8_settings->od8_settings_array[i].max_value =
1663 od8_settings->od_settings_max[i];
1664 od8_settings->od8_settings_array[i].current_value =
1665 od8_settings->od8_settings_array[i].default_value;
1667 od8_settings->od8_settings_array[i].min_value = 0;
1668 od8_settings->od8_settings_array[i].max_value = 0;
1669 od8_settings->od8_settings_array[i].current_value = 0;
1676 static int vega20_get_metrics_table(struct smu_context *smu,
1677 SmuMetrics_t *metrics_table)
1679 struct smu_table_context *smu_table= &smu->smu_table;
1682 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1683 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1684 (void *)smu_table->metrics_table, false);
1686 pr_info("Failed to export SMU metrics table!\n");
1689 smu_table->metrics_time = jiffies;
1692 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1697 static int vega20_set_default_od_settings(struct smu_context *smu,
1700 struct smu_table_context *table_context = &smu->smu_table;
1704 if (table_context->overdrive_table)
1707 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1709 if (!table_context->overdrive_table)
1712 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1713 table_context->overdrive_table, false);
1715 pr_err("Failed to export over drive table!\n");
1719 ret = vega20_set_default_od8_setttings(smu);
1724 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1725 table_context->overdrive_table, true);
1727 pr_err("Failed to import over drive table!\n");
1734 static int vega20_get_od_percentage(struct smu_context *smu,
1735 enum smu_clk_type clk_type)
1737 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1738 struct vega20_dpm_table *dpm_table = NULL;
1739 struct vega20_dpm_table *golden_table = NULL;
1740 struct vega20_single_dpm_table *single_dpm_table;
1741 struct vega20_single_dpm_table *golden_dpm_table;
1742 int value, golden_value;
1744 dpm_table = smu_dpm->dpm_context;
1745 golden_table = smu_dpm->golden_dpm_context;
1749 single_dpm_table = &(dpm_table->gfx_table);
1750 golden_dpm_table = &(golden_table->gfx_table);
1753 single_dpm_table = &(dpm_table->mem_table);
1754 golden_dpm_table = &(golden_table->mem_table);
1761 value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1762 golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1764 value -= golden_value;
1765 value = DIV_ROUND_UP(value * 100, golden_value);
1770 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1772 DpmActivityMonitorCoeffInt_t activity_monitor;
1773 uint32_t i, size = 0;
1774 int16_t workload_type = 0;
1775 static const char *profile_name[] = {
1783 static const char *title[] = {
1784 "PROFILE_INDEX(NAME)",
1788 "MinActiveFreqType",
1793 "PD_Data_error_coeff",
1794 "PD_Data_error_rate_coeff"};
1797 if (!smu->pm_enabled || !buf)
1800 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1801 title[0], title[1], title[2], title[3], title[4], title[5],
1802 title[6], title[7], title[8], title[9], title[10]);
1804 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1805 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1806 workload_type = smu_workload_get_type(smu, i);
1807 if (workload_type < 0)
1810 result = smu_update_table(smu,
1811 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1812 (void *)(&activity_monitor), false);
1814 pr_err("[%s] Failed to get activity monitor!", __func__);
1818 size += sprintf(buf + size, "%2d %14s%s:\n",
1819 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1821 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1825 activity_monitor.Gfx_FPS,
1826 activity_monitor.Gfx_UseRlcBusy,
1827 activity_monitor.Gfx_MinActiveFreqType,
1828 activity_monitor.Gfx_MinActiveFreq,
1829 activity_monitor.Gfx_BoosterFreqType,
1830 activity_monitor.Gfx_BoosterFreq,
1831 activity_monitor.Gfx_PD_Data_limit_c,
1832 activity_monitor.Gfx_PD_Data_error_coeff,
1833 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1835 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1839 activity_monitor.Soc_FPS,
1840 activity_monitor.Soc_UseRlcBusy,
1841 activity_monitor.Soc_MinActiveFreqType,
1842 activity_monitor.Soc_MinActiveFreq,
1843 activity_monitor.Soc_BoosterFreqType,
1844 activity_monitor.Soc_BoosterFreq,
1845 activity_monitor.Soc_PD_Data_limit_c,
1846 activity_monitor.Soc_PD_Data_error_coeff,
1847 activity_monitor.Soc_PD_Data_error_rate_coeff);
1849 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1853 activity_monitor.Mem_FPS,
1854 activity_monitor.Mem_UseRlcBusy,
1855 activity_monitor.Mem_MinActiveFreqType,
1856 activity_monitor.Mem_MinActiveFreq,
1857 activity_monitor.Mem_BoosterFreqType,
1858 activity_monitor.Mem_BoosterFreq,
1859 activity_monitor.Mem_PD_Data_limit_c,
1860 activity_monitor.Mem_PD_Data_error_coeff,
1861 activity_monitor.Mem_PD_Data_error_rate_coeff);
1863 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1867 activity_monitor.Fclk_FPS,
1868 activity_monitor.Fclk_UseRlcBusy,
1869 activity_monitor.Fclk_MinActiveFreqType,
1870 activity_monitor.Fclk_MinActiveFreq,
1871 activity_monitor.Fclk_BoosterFreqType,
1872 activity_monitor.Fclk_BoosterFreq,
1873 activity_monitor.Fclk_PD_Data_limit_c,
1874 activity_monitor.Fclk_PD_Data_error_coeff,
1875 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1881 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1883 DpmActivityMonitorCoeffInt_t activity_monitor;
1884 int workload_type = 0, ret = 0;
1886 smu->power_profile_mode = input[size];
1888 if (!smu->pm_enabled)
1890 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1891 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1895 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1896 ret = smu_update_table(smu,
1897 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1898 (void *)(&activity_monitor), false);
1900 pr_err("[%s] Failed to get activity monitor!", __func__);
1905 case 0: /* Gfxclk */
1906 activity_monitor.Gfx_FPS = input[1];
1907 activity_monitor.Gfx_UseRlcBusy = input[2];
1908 activity_monitor.Gfx_MinActiveFreqType = input[3];
1909 activity_monitor.Gfx_MinActiveFreq = input[4];
1910 activity_monitor.Gfx_BoosterFreqType = input[5];
1911 activity_monitor.Gfx_BoosterFreq = input[6];
1912 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1913 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1914 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1916 case 1: /* Socclk */
1917 activity_monitor.Soc_FPS = input[1];
1918 activity_monitor.Soc_UseRlcBusy = input[2];
1919 activity_monitor.Soc_MinActiveFreqType = input[3];
1920 activity_monitor.Soc_MinActiveFreq = input[4];
1921 activity_monitor.Soc_BoosterFreqType = input[5];
1922 activity_monitor.Soc_BoosterFreq = input[6];
1923 activity_monitor.Soc_PD_Data_limit_c = input[7];
1924 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1925 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1928 activity_monitor.Mem_FPS = input[1];
1929 activity_monitor.Mem_UseRlcBusy = input[2];
1930 activity_monitor.Mem_MinActiveFreqType = input[3];
1931 activity_monitor.Mem_MinActiveFreq = input[4];
1932 activity_monitor.Mem_BoosterFreqType = input[5];
1933 activity_monitor.Mem_BoosterFreq = input[6];
1934 activity_monitor.Mem_PD_Data_limit_c = input[7];
1935 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1936 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1939 activity_monitor.Fclk_FPS = input[1];
1940 activity_monitor.Fclk_UseRlcBusy = input[2];
1941 activity_monitor.Fclk_MinActiveFreqType = input[3];
1942 activity_monitor.Fclk_MinActiveFreq = input[4];
1943 activity_monitor.Fclk_BoosterFreqType = input[5];
1944 activity_monitor.Fclk_BoosterFreq = input[6];
1945 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1946 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1947 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1951 ret = smu_update_table(smu,
1952 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1953 (void *)(&activity_monitor), true);
1955 pr_err("[%s] Failed to set activity monitor!", __func__);
1960 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1961 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1962 if (workload_type < 0)
1964 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1965 1 << workload_type);
1971 vega20_get_profiling_clk_mask(struct smu_context *smu,
1972 enum amd_dpm_forced_level level,
1973 uint32_t *sclk_mask,
1974 uint32_t *mclk_mask,
1977 struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1978 struct vega20_single_dpm_table *gfx_dpm_table;
1979 struct vega20_single_dpm_table *mem_dpm_table;
1980 struct vega20_single_dpm_table *soc_dpm_table;
1982 if (!smu->smu_dpm.dpm_context)
1985 gfx_dpm_table = &dpm_table->gfx_table;
1986 mem_dpm_table = &dpm_table->mem_table;
1987 soc_dpm_table = &dpm_table->soc_table;
1993 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1994 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
1995 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
1996 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
1997 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
1998 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2001 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2003 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2005 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2006 *sclk_mask = gfx_dpm_table->count - 1;
2007 *mclk_mask = mem_dpm_table->count - 1;
2008 *soc_mask = soc_dpm_table->count - 1;
2015 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2016 struct vega20_single_dpm_table *dpm_table)
2019 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2020 if (!smu_dpm_ctx->dpm_context)
2023 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2024 if (dpm_table->count <= 0) {
2025 pr_err("[%s] Dpm table has no entry!", __func__);
2029 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2030 pr_err("[%s] Dpm table has too many entries!", __func__);
2034 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2035 ret = smu_send_smc_msg_with_param(smu,
2036 SMU_MSG_SetHardMinByFreq,
2037 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2039 pr_err("[%s] Set hard min uclk failed!", __func__);
2047 static int vega20_pre_display_config_changed(struct smu_context *smu)
2050 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2052 if (!smu->smu_dpm.dpm_context)
2055 smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2056 ret = vega20_set_uclk_to_highest_dpm_level(smu,
2057 &dpm_table->mem_table);
2059 pr_err("Failed to set uclk to highest dpm level");
2063 static int vega20_display_config_changed(struct smu_context *smu)
2067 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2068 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2069 ret = smu_write_watermarks_table(smu);
2071 pr_err("Failed to update WMTABLE!");
2074 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2077 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2078 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2079 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2080 smu_send_smc_msg_with_param(smu,
2081 SMU_MSG_NumOfDisplays,
2082 smu->display_config->num_display);
2088 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2090 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2091 struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2092 struct vega20_single_dpm_table *dpm_table;
2093 bool vblank_too_short = false;
2094 bool disable_mclk_switching;
2095 uint32_t i, latency;
2097 disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2098 !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2099 latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2102 dpm_table = &(dpm_ctx->gfx_table);
2103 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2104 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2105 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2106 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2108 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2109 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2110 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2113 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2114 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2115 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2118 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2119 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2120 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2124 dpm_table = &(dpm_ctx->mem_table);
2125 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2126 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2127 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2128 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2130 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2131 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2132 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2135 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2136 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2137 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2140 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2141 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2142 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2145 /* honour DAL's UCLK Hardmin */
2146 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2147 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2149 /* Hardmin is dependent on displayconfig */
2150 if (disable_mclk_switching) {
2151 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2152 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2153 if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2154 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2155 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2162 if (smu->display_config->nb_pstate_switch_disable)
2163 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2166 dpm_table = &(dpm_ctx->vclk_table);
2167 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2168 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2169 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2170 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2172 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2173 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2174 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2177 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2178 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2179 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2183 dpm_table = &(dpm_ctx->dclk_table);
2184 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2185 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2186 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2187 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2189 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2190 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2191 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2194 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2195 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2196 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2200 dpm_table = &(dpm_ctx->soc_table);
2201 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2202 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2203 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2204 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2206 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2207 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2208 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2211 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2212 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2213 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2217 dpm_table = &(dpm_ctx->eclk_table);
2218 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2219 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2220 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2221 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2223 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2224 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2225 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2228 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2229 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2230 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2236 vega20_notify_smc_dispaly_config(struct smu_context *smu)
2238 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2239 struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2240 struct smu_clocks min_clocks = {0};
2241 struct pp_display_clock_request clock_req;
2244 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2245 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2246 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2248 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2249 clock_req.clock_type = amd_pp_dcef_clock;
2250 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2251 if (!smu->funcs->display_clock_voltage_request(smu, &clock_req)) {
2252 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2253 ret = smu_send_smc_msg_with_param(smu,
2254 SMU_MSG_SetMinDeepSleepDcefclk,
2255 min_clocks.dcef_clock_in_sr/100);
2257 pr_err("Attempt to set divider for DCEFCLK Failed!");
2262 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2266 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2267 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2268 ret = smu_send_smc_msg_with_param(smu,
2269 SMU_MSG_SetHardMinByFreq,
2270 (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2272 pr_err("[%s] Set hard min uclk failed!", __func__);
2280 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2284 for (i = 0; i < table->count; i++) {
2285 if (table->dpm_levels[i].enabled)
2288 if (i >= table->count) {
2290 table->dpm_levels[i].enabled = true;
2296 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2301 pr_err("[%s] DPM Table does not exist!", __func__);
2304 if (table->count <= 0) {
2305 pr_err("[%s] DPM Table has no entry!", __func__);
2308 if (table->count > MAX_REGULAR_DPM_NUMBER) {
2309 pr_err("[%s] DPM Table has too many entries!", __func__);
2310 return MAX_REGULAR_DPM_NUMBER - 1;
2313 for (i = table->count - 1; i >= 0; i--) {
2314 if (table->dpm_levels[i].enabled)
2319 table->dpm_levels[i].enabled = true;
2325 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2327 uint32_t soft_level;
2329 struct vega20_dpm_table *dpm_table =
2330 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2333 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2335 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2337 dpm_table->gfx_table.dpm_state.soft_min_level =
2338 dpm_table->gfx_table.dpm_state.soft_max_level =
2339 dpm_table->gfx_table.dpm_levels[soft_level].value;
2342 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2344 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2346 dpm_table->mem_table.dpm_state.soft_min_level =
2347 dpm_table->mem_table.dpm_state.soft_max_level =
2348 dpm_table->mem_table.dpm_levels[soft_level].value;
2351 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2353 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2355 dpm_table->soc_table.dpm_state.soft_min_level =
2356 dpm_table->soc_table.dpm_state.soft_max_level =
2357 dpm_table->soc_table.dpm_levels[soft_level].value;
2359 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2361 pr_err("Failed to upload boot level to %s!\n",
2362 highest ? "highest" : "lowest");
2366 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2368 pr_err("Failed to upload dpm max level to %s!\n!",
2369 highest ? "highest" : "lowest");
2376 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2378 uint32_t soft_min_level, soft_max_level;
2380 struct vega20_dpm_table *dpm_table =
2381 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2383 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2384 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2385 dpm_table->gfx_table.dpm_state.soft_min_level =
2386 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2387 dpm_table->gfx_table.dpm_state.soft_max_level =
2388 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2390 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2391 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2392 dpm_table->mem_table.dpm_state.soft_min_level =
2393 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2394 dpm_table->mem_table.dpm_state.soft_max_level =
2395 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2397 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2398 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2399 dpm_table->soc_table.dpm_state.soft_min_level =
2400 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2401 dpm_table->soc_table.dpm_state.soft_max_level =
2402 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2404 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2406 pr_err("Failed to upload DPM Bootup Levels!");
2410 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2412 pr_err("Failed to upload DPM Max Levels!");
2419 static int vega20_update_specified_od8_value(struct smu_context *smu,
2423 struct smu_table_context *table_context = &smu->smu_table;
2424 OverDriveTable_t *od_table =
2425 (OverDriveTable_t *)(table_context->overdrive_table);
2426 struct vega20_od8_settings *od8_settings =
2427 (struct vega20_od8_settings *)smu->od_settings;
2430 case OD8_SETTING_GFXCLK_FMIN:
2431 od_table->GfxclkFmin = (uint16_t)value;
2434 case OD8_SETTING_GFXCLK_FMAX:
2435 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2436 value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2438 od_table->GfxclkFmax = (uint16_t)value;
2441 case OD8_SETTING_GFXCLK_FREQ1:
2442 od_table->GfxclkFreq1 = (uint16_t)value;
2445 case OD8_SETTING_GFXCLK_VOLTAGE1:
2446 od_table->GfxclkVolt1 = (uint16_t)value;
2449 case OD8_SETTING_GFXCLK_FREQ2:
2450 od_table->GfxclkFreq2 = (uint16_t)value;
2453 case OD8_SETTING_GFXCLK_VOLTAGE2:
2454 od_table->GfxclkVolt2 = (uint16_t)value;
2457 case OD8_SETTING_GFXCLK_FREQ3:
2458 od_table->GfxclkFreq3 = (uint16_t)value;
2461 case OD8_SETTING_GFXCLK_VOLTAGE3:
2462 od_table->GfxclkVolt3 = (uint16_t)value;
2465 case OD8_SETTING_UCLK_FMAX:
2466 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2467 value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2469 od_table->UclkFmax = (uint16_t)value;
2472 case OD8_SETTING_POWER_PERCENTAGE:
2473 od_table->OverDrivePct = (int16_t)value;
2476 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2477 od_table->FanMaximumRpm = (uint16_t)value;
2480 case OD8_SETTING_FAN_MIN_SPEED:
2481 od_table->FanMinimumPwm = (uint16_t)value;
2484 case OD8_SETTING_FAN_TARGET_TEMP:
2485 od_table->FanTargetTemperature = (uint16_t)value;
2488 case OD8_SETTING_OPERATING_TEMP_MAX:
2489 od_table->MaxOpTemp = (uint16_t)value;
2496 static int vega20_update_od8_settings(struct smu_context *smu,
2500 struct smu_table_context *table_context = &smu->smu_table;
2503 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2504 table_context->overdrive_table, false);
2506 pr_err("Failed to export over drive table!\n");
2510 ret = vega20_update_specified_od8_value(smu, index, value);
2514 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2515 table_context->overdrive_table, true);
2517 pr_err("Failed to import over drive table!\n");
2524 static int vega20_set_od_percentage(struct smu_context *smu,
2525 enum smu_clk_type clk_type,
2528 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2529 struct vega20_dpm_table *dpm_table = NULL;
2530 struct vega20_dpm_table *golden_table = NULL;
2531 struct vega20_single_dpm_table *single_dpm_table;
2532 struct vega20_single_dpm_table *golden_dpm_table;
2533 uint32_t od_clk, index;
2535 int feature_enabled;
2538 dpm_table = smu_dpm->dpm_context;
2539 golden_table = smu_dpm->golden_dpm_context;
2543 single_dpm_table = &(dpm_table->gfx_table);
2544 golden_dpm_table = &(golden_table->gfx_table);
2545 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2546 clk_id = PPCLK_GFXCLK;
2547 index = OD8_SETTING_GFXCLK_FMAX;
2550 single_dpm_table = &(dpm_table->mem_table);
2551 golden_dpm_table = &(golden_table->mem_table);
2552 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2553 clk_id = PPCLK_UCLK;
2554 index = OD8_SETTING_UCLK_FMAX;
2564 od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2566 od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2568 ret = vega20_update_od8_settings(smu, index, od_clk);
2570 pr_err("[Setoverdrive] failed to set od clk!\n");
2574 if (feature_enabled) {
2575 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2578 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2582 single_dpm_table->count = 1;
2583 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2586 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2587 AMD_PP_TASK_READJUST_POWER_STATE,
2594 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2595 enum PP_OD_DPM_TABLE_COMMAND type,
2596 long *input, uint32_t size)
2598 struct smu_table_context *table_context = &smu->smu_table;
2599 OverDriveTable_t *od_table =
2600 (OverDriveTable_t *)(table_context->overdrive_table);
2601 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2602 struct vega20_dpm_table *dpm_table = NULL;
2603 struct vega20_single_dpm_table *single_dpm_table;
2604 struct vega20_od8_settings *od8_settings =
2605 (struct vega20_od8_settings *)smu->od_settings;
2606 struct pp_clock_levels_with_latency clocks;
2607 int32_t input_index, input_clk, input_vol, i;
2611 dpm_table = smu_dpm->dpm_context;
2614 pr_warn("NULL user input for clock and voltage\n");
2619 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2620 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2621 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2622 pr_info("Sclk min/max frequency overdrive not supported\n");
2626 for (i = 0; i < size; i += 2) {
2628 pr_info("invalid number of input parameters %d\n", size);
2632 input_index = input[i];
2633 input_clk = input[i + 1];
2635 if (input_index != 0 && input_index != 1) {
2636 pr_info("Invalid index %d\n", input_index);
2637 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2641 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2642 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2643 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2645 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2646 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2650 if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2651 od_table->GfxclkFmin = input_clk;
2652 od8_settings->od_gfxclk_update = true;
2653 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2654 od_table->GfxclkFmax = input_clk;
2655 od8_settings->od_gfxclk_update = true;
2661 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2662 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2663 pr_info("Mclk max frequency overdrive not supported\n");
2667 single_dpm_table = &(dpm_table->mem_table);
2668 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2670 pr_err("Attempt to get memory clk levels Failed!");
2674 for (i = 0; i < size; i += 2) {
2676 pr_info("invalid number of input parameters %d\n",
2681 input_index = input[i];
2682 input_clk = input[i + 1];
2684 if (input_index != 1) {
2685 pr_info("Invalid index %d\n", input_index);
2686 pr_info("Support max Mclk frequency setting only which index by 1\n");
2690 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2691 input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2692 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2694 clocks.data[0].clocks_in_khz / 1000,
2695 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2699 if (input_index == 1 && od_table->UclkFmax != input_clk) {
2700 od8_settings->od_gfxclk_update = true;
2701 od_table->UclkFmax = input_clk;
2707 case PP_OD_EDIT_VDDC_CURVE:
2708 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2709 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2710 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2711 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2712 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2713 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2714 pr_info("Voltage curve calibrate not supported\n");
2718 for (i = 0; i < size; i += 3) {
2720 pr_info("invalid number of input parameters %d\n",
2725 input_index = input[i];
2726 input_clk = input[i + 1];
2727 input_vol = input[i + 2];
2729 if (input_index > 2) {
2730 pr_info("Setting for point %d is not supported\n",
2732 pr_info("Three supported points index by 0, 1, 2\n");
2736 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2737 if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2738 input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2739 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2741 od8_settings->od8_settings_array[od8_id].min_value,
2742 od8_settings->od8_settings_array[od8_id].max_value);
2746 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2747 if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2748 input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2749 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2751 od8_settings->od8_settings_array[od8_id].min_value,
2752 od8_settings->od8_settings_array[od8_id].max_value);
2756 switch (input_index) {
2758 od_table->GfxclkFreq1 = input_clk;
2759 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2762 od_table->GfxclkFreq2 = input_clk;
2763 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2766 od_table->GfxclkFreq3 = input_clk;
2767 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2774 case PP_OD_RESTORE_DEFAULT_TABLE:
2775 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
2777 pr_err("Failed to export over drive table!\n");
2783 case PP_OD_COMMIT_DPM_TABLE:
2784 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
2786 pr_err("Failed to import over drive table!\n");
2790 /* retrieve updated gfxclk table */
2791 if (od8_settings->od_gfxclk_update) {
2792 od8_settings->od_gfxclk_update = false;
2793 single_dpm_table = &(dpm_table->gfx_table);
2795 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2796 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2799 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2803 single_dpm_table->count = 1;
2804 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2814 if (type == PP_OD_COMMIT_DPM_TABLE) {
2815 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2816 AMD_PP_TASK_READJUST_POWER_STATE,
2823 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2825 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2828 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2831 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2834 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2836 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2839 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2842 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2845 static bool vega20_is_dpm_running(struct smu_context *smu)
2848 uint32_t feature_mask[2];
2849 unsigned long feature_enabled;
2850 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2851 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
2852 ((uint64_t)feature_mask[1] << 32));
2853 return !!(feature_enabled & SMC_DPM_FEATURE);
2856 static int vega20_set_thermal_fan_table(struct smu_context *smu)
2859 struct smu_table_context *table_context = &smu->smu_table;
2860 PPTable_t *pptable = table_context->driver_pptable;
2862 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
2863 (uint32_t)pptable->FanTargetTemperature);
2868 static int vega20_get_fan_speed_rpm(struct smu_context *smu,
2873 ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
2876 pr_err("Attempt to get current RPM from SMC Failed!\n");
2880 smu_read_smc_arg(smu, speed);
2885 static int vega20_get_fan_speed_percent(struct smu_context *smu,
2889 uint32_t current_rpm = 0, percent = 0;
2890 PPTable_t *pptable = smu->smu_table.driver_pptable;
2892 ret = vega20_get_fan_speed_rpm(smu, ¤t_rpm);
2896 percent = current_rpm * 100 / pptable->FanMaximumRpm;
2897 *speed = percent > 100 ? 100 : percent;
2902 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
2904 uint32_t smu_version;
2906 SmuMetrics_t metrics;
2911 ret = vega20_get_metrics_table(smu, &metrics);
2915 ret = smu_get_smc_version(smu, NULL, &smu_version);
2919 /* For the 40.46 release, they changed the value name */
2920 if (smu_version == 0x282e00)
2921 *value = metrics.AverageSocketPower << 8;
2923 *value = metrics.CurrSocketPower << 8;
2928 static int vega20_get_current_activity_percent(struct smu_context *smu,
2929 enum amd_pp_sensors sensor,
2933 SmuMetrics_t metrics;
2938 ret = vega20_get_metrics_table(smu, &metrics);
2943 case AMDGPU_PP_SENSOR_GPU_LOAD:
2944 *value = metrics.AverageGfxActivity;
2946 case AMDGPU_PP_SENSOR_MEM_LOAD:
2947 *value = metrics.AverageUclkActivity;
2950 pr_err("Invalid sensor for retrieving clock activity\n");
2957 static int vega20_thermal_get_temperature(struct smu_context *smu,
2958 enum amd_pp_sensors sensor,
2961 struct amdgpu_device *adev = smu->adev;
2962 SmuMetrics_t metrics;
2969 ret = vega20_get_metrics_table(smu, &metrics);
2974 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2975 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
2976 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
2977 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
2979 temp = temp & 0x1ff;
2980 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2984 case AMDGPU_PP_SENSOR_EDGE_TEMP:
2985 *value = metrics.TemperatureEdge *
2986 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2988 case AMDGPU_PP_SENSOR_MEM_TEMP:
2989 *value = metrics.TemperatureHBM *
2990 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2993 pr_err("Invalid sensor for retrieving temp\n");
2999 static int vega20_read_sensor(struct smu_context *smu,
3000 enum amd_pp_sensors sensor,
3001 void *data, uint32_t *size)
3004 struct smu_table_context *table_context = &smu->smu_table;
3005 PPTable_t *pptable = table_context->driver_pptable;
3010 mutex_lock(&smu->sensor_lock);
3012 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3013 *(uint32_t *)data = pptable->FanMaximumRpm;
3016 case AMDGPU_PP_SENSOR_MEM_LOAD:
3017 case AMDGPU_PP_SENSOR_GPU_LOAD:
3018 ret = vega20_get_current_activity_percent(smu,
3023 case AMDGPU_PP_SENSOR_GPU_POWER:
3024 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3027 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3028 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3029 case AMDGPU_PP_SENSOR_MEM_TEMP:
3030 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3034 ret = smu_smc_read_sensor(smu, sensor, data, size);
3036 mutex_unlock(&smu->sensor_lock);
3041 static int vega20_set_watermarks_table(struct smu_context *smu,
3042 void *watermarks, struct
3043 dm_pp_wm_sets_with_clock_ranges_soc15
3047 Watermarks_t *table = watermarks;
3049 if (!table || !clock_ranges)
3052 if (clock_ranges->num_wm_dmif_sets > 4 ||
3053 clock_ranges->num_wm_mcif_sets > 4)
3056 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3057 table->WatermarkRow[1][i].MinClock =
3058 cpu_to_le16((uint16_t)
3059 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3061 table->WatermarkRow[1][i].MaxClock =
3062 cpu_to_le16((uint16_t)
3063 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3065 table->WatermarkRow[1][i].MinUclk =
3066 cpu_to_le16((uint16_t)
3067 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3069 table->WatermarkRow[1][i].MaxUclk =
3070 cpu_to_le16((uint16_t)
3071 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3073 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3074 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3077 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3078 table->WatermarkRow[0][i].MinClock =
3079 cpu_to_le16((uint16_t)
3080 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3082 table->WatermarkRow[0][i].MaxClock =
3083 cpu_to_le16((uint16_t)
3084 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3086 table->WatermarkRow[0][i].MinUclk =
3087 cpu_to_le16((uint16_t)
3088 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3090 table->WatermarkRow[0][i].MaxUclk =
3091 cpu_to_le16((uint16_t)
3092 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3094 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3095 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3101 static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3102 struct smu_temperature_range *range)
3104 struct smu_table_context *table_context = &smu->smu_table;
3105 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = table_context->power_play_table;
3106 PPTable_t *pptable = smu->smu_table.driver_pptable;
3108 if (!range || !powerplay_table)
3111 range->max = powerplay_table->usSoftwareShutdownTemp *
3112 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3113 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
3114 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3115 range->hotspot_crit_max = pptable->ThotspotLimit *
3116 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3117 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
3118 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3119 range->mem_crit_max = pptable->ThbmLimit *
3120 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3121 range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM) *
3122 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3128 static int vega20_set_df_cstate(struct smu_context *smu,
3129 enum pp_df_cstate state)
3131 uint32_t smu_version;
3134 ret = smu_get_smc_version(smu, NULL, &smu_version);
3136 pr_err("Failed to get smu version!\n");
3140 /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
3141 if (smu_version < 0x283200) {
3142 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
3146 return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
3149 static int vega20_update_pcie_parameters(struct smu_context *smu,
3150 uint32_t pcie_gen_cap,
3151 uint32_t pcie_width_cap)
3153 PPTable_t *pptable = smu->smu_table.driver_pptable;
3155 uint32_t smu_pcie_arg;
3157 for (i = 0; i < NUM_LINK_LEVELS; i++) {
3158 smu_pcie_arg = (i << 16) |
3159 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
3160 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
3161 pptable->PcieLaneCount[i] : pcie_width_cap);
3162 ret = smu_send_smc_msg_with_param(smu,
3163 SMU_MSG_OverridePcieParameters,
3171 static const struct pptable_funcs vega20_ppt_funcs = {
3172 .tables_init = vega20_tables_init,
3173 .alloc_dpm_context = vega20_allocate_dpm_context,
3174 .store_powerplay_table = vega20_store_powerplay_table,
3175 .check_powerplay_table = vega20_check_powerplay_table,
3176 .append_powerplay_table = vega20_append_powerplay_table,
3177 .get_smu_msg_index = vega20_get_smu_msg_index,
3178 .get_smu_clk_index = vega20_get_smu_clk_index,
3179 .get_smu_feature_index = vega20_get_smu_feature_index,
3180 .get_smu_table_index = vega20_get_smu_table_index,
3181 .get_smu_power_index = vega20_get_pwr_src_index,
3182 .get_workload_type = vega20_get_workload_type,
3183 .run_btc = vega20_run_btc_afll,
3184 .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3185 .get_current_power_state = vega20_get_current_power_state,
3186 .set_default_dpm_table = vega20_set_default_dpm_table,
3187 .set_power_state = NULL,
3188 .populate_umd_state_clk = vega20_populate_umd_state_clk,
3189 .print_clk_levels = vega20_print_clk_levels,
3190 .force_clk_levels = vega20_force_clk_levels,
3191 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3192 .get_od_percentage = vega20_get_od_percentage,
3193 .get_power_profile_mode = vega20_get_power_profile_mode,
3194 .set_power_profile_mode = vega20_set_power_profile_mode,
3195 .set_od_percentage = vega20_set_od_percentage,
3196 .set_default_od_settings = vega20_set_default_od_settings,
3197 .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3198 .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3199 .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3200 .read_sensor = vega20_read_sensor,
3201 .pre_display_config_changed = vega20_pre_display_config_changed,
3202 .display_config_changed = vega20_display_config_changed,
3203 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3204 .notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
3205 .force_dpm_limit_value = vega20_force_dpm_limit_value,
3206 .unforce_dpm_levels = vega20_unforce_dpm_levels,
3207 .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3208 .is_dpm_running = vega20_is_dpm_running,
3209 .set_thermal_fan_table = vega20_set_thermal_fan_table,
3210 .get_fan_speed_percent = vega20_get_fan_speed_percent,
3211 .get_fan_speed_rpm = vega20_get_fan_speed_rpm,
3212 .set_watermarks_table = vega20_set_watermarks_table,
3213 .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3214 .set_df_cstate = vega20_set_df_cstate,
3215 .update_pcie_parameters = vega20_update_pcie_parameters
3218 void vega20_set_ppt_funcs(struct smu_context *smu)
3220 smu->ppt_funcs = &vega20_ppt_funcs;