2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
27 #include "amdgpu_smu.h"
28 #include "smu_internal.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "smu_v11_0.h"
32 #include "smu11_driver_if.h"
33 #include "soc15_common.h"
35 #include "power_state.h"
36 #include "vega20_ppt.h"
37 #include "vega20_pptable.h"
38 #include "vega20_ppsmc.h"
39 #include "nbio/nbio_7_4_sh_mask.h"
40 #include "asic_reg/thm/thm_11_0_2_offset.h"
41 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
43 #define smnPCIE_LC_SPEED_CNTL 0x11140290
44 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
46 #define CTF_OFFSET_EDGE 5
47 #define CTF_OFFSET_HOTSPOT 5
48 #define CTF_OFFSET_HBM 5
50 #define MSG_MAP(msg) \
51 [SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
53 #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
54 FEATURE_DPM_GFXCLK_MASK | \
55 FEATURE_DPM_UCLK_MASK | \
56 FEATURE_DPM_SOCCLK_MASK | \
57 FEATURE_DPM_UVD_MASK | \
58 FEATURE_DPM_VCE_MASK | \
59 FEATURE_DPM_MP0CLK_MASK | \
60 FEATURE_DPM_LINK_MASK | \
61 FEATURE_DPM_DCEFCLK_MASK)
63 static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
65 MSG_MAP(GetSmuVersion),
66 MSG_MAP(GetDriverIfVersion),
67 MSG_MAP(SetAllowedFeaturesMaskLow),
68 MSG_MAP(SetAllowedFeaturesMaskHigh),
69 MSG_MAP(EnableAllSmuFeatures),
70 MSG_MAP(DisableAllSmuFeatures),
71 MSG_MAP(EnableSmuFeaturesLow),
72 MSG_MAP(EnableSmuFeaturesHigh),
73 MSG_MAP(DisableSmuFeaturesLow),
74 MSG_MAP(DisableSmuFeaturesHigh),
75 MSG_MAP(GetEnabledSmuFeaturesLow),
76 MSG_MAP(GetEnabledSmuFeaturesHigh),
77 MSG_MAP(SetWorkloadMask),
79 MSG_MAP(SetDriverDramAddrHigh),
80 MSG_MAP(SetDriverDramAddrLow),
81 MSG_MAP(SetToolsDramAddrHigh),
82 MSG_MAP(SetToolsDramAddrLow),
83 MSG_MAP(TransferTableSmu2Dram),
84 MSG_MAP(TransferTableDram2Smu),
85 MSG_MAP(UseDefaultPPTable),
86 MSG_MAP(UseBackupPPTable),
88 MSG_MAP(RequestI2CBus),
89 MSG_MAP(ReleaseI2CBus),
90 MSG_MAP(SetFloorSocVoltage),
92 MSG_MAP(StartBacoMonitor),
93 MSG_MAP(CancelBacoMonitor),
95 MSG_MAP(SetSoftMinByFreq),
96 MSG_MAP(SetSoftMaxByFreq),
97 MSG_MAP(SetHardMinByFreq),
98 MSG_MAP(SetHardMaxByFreq),
99 MSG_MAP(GetMinDpmFreq),
100 MSG_MAP(GetMaxDpmFreq),
101 MSG_MAP(GetDpmFreqByIndex),
102 MSG_MAP(GetDpmClockFreq),
103 MSG_MAP(GetSsVoltageByDpm),
104 MSG_MAP(SetMemoryChannelConfig),
105 MSG_MAP(SetGeminiMode),
106 MSG_MAP(SetGeminiApertureHigh),
107 MSG_MAP(SetGeminiApertureLow),
108 MSG_MAP(SetMinLinkDpmByIndex),
109 MSG_MAP(OverridePcieParameters),
110 MSG_MAP(OverDriveSetPercentage),
111 MSG_MAP(SetMinDeepSleepDcefclk),
112 MSG_MAP(ReenableAcDcInterrupt),
113 MSG_MAP(NotifyPowerSource),
114 MSG_MAP(SetUclkFastSwitch),
115 MSG_MAP(SetUclkDownHyst),
116 MSG_MAP(GetCurrentRpm),
117 MSG_MAP(SetVideoFps),
119 MSG_MAP(SetFanTemperatureTarget),
120 MSG_MAP(PrepareMp1ForUnload),
121 MSG_MAP(DramLogSetDramAddrHigh),
122 MSG_MAP(DramLogSetDramAddrLow),
123 MSG_MAP(DramLogSetDramSize),
124 MSG_MAP(SetFanMaxRpm),
125 MSG_MAP(SetFanMinPwm),
126 MSG_MAP(ConfigureGfxDidt),
127 MSG_MAP(NumOfDisplays),
128 MSG_MAP(RemoveMargins),
129 MSG_MAP(ReadSerialNumTop32),
130 MSG_MAP(ReadSerialNumBottom32),
131 MSG_MAP(SetSystemVirtualDramAddrHigh),
132 MSG_MAP(SetSystemVirtualDramAddrLow),
134 MSG_MAP(SetFclkGfxClkRatio),
135 MSG_MAP(AllowGfxOff),
136 MSG_MAP(DisallowGfxOff),
137 MSG_MAP(GetPptLimit),
138 MSG_MAP(GetDcModeMaxDpmFreq),
139 MSG_MAP(GetDebugData),
140 MSG_MAP(SetXgmiMode),
143 MSG_MAP(PrepareMp1ForReset),
144 MSG_MAP(PrepareMp1ForShutdown),
145 MSG_MAP(SetMGpuFanBoostLimitRpm),
146 MSG_MAP(GetAVFSVoltageByDpm),
147 MSG_MAP(DFCstateControl),
150 static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(VCLK, PPCLK_VCLK),
153 CLK_MAP(DCLK, PPCLK_DCLK),
154 CLK_MAP(ECLK, PPCLK_ECLK),
155 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
156 CLK_MAP(UCLK, PPCLK_UCLK),
157 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
158 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
159 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
160 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
161 CLK_MAP(FCLK, PPCLK_FCLK),
164 static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
165 FEA_MAP(DPM_PREFETCHER),
174 FEA_MAP(DPM_DCEFCLK),
181 FEA_MAP(GFX_PER_CU_CG),
188 FEA_MAP(LED_DISPLAY),
189 FEA_MAP(FAN_CONTROL),
200 static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
204 TAB_MAP(AVFS_PSM_DEBUG),
205 TAB_MAP(AVFS_FUSE_OVERRIDE),
206 TAB_MAP(PMSTATUSLOG),
207 TAB_MAP(SMU_METRICS),
208 TAB_MAP(DRIVER_SMU_CONFIG),
209 TAB_MAP(ACTIVITY_MONITOR_COEFF),
213 static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
218 static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
222 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
224 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
228 static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
230 struct smu_11_0_cmn2aisc_mapping mapping;
232 if (index >= SMU_TABLE_COUNT)
235 mapping = vega20_table_map[index];
236 if (!(mapping.valid_mapping)) {
240 return mapping.map_to;
243 static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
245 struct smu_11_0_cmn2aisc_mapping mapping;
247 if (index >= SMU_POWER_SOURCE_COUNT)
250 mapping = vega20_pwr_src_map[index];
251 if (!(mapping.valid_mapping)) {
255 return mapping.map_to;
258 static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
260 struct smu_11_0_cmn2aisc_mapping mapping;
262 if (index >= SMU_FEATURE_COUNT)
265 mapping = vega20_feature_mask_map[index];
266 if (!(mapping.valid_mapping)) {
270 return mapping.map_to;
273 static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
275 struct smu_11_0_cmn2aisc_mapping mapping;
277 if (index >= SMU_CLK_COUNT)
280 mapping = vega20_clk_map[index];
281 if (!(mapping.valid_mapping)) {
285 return mapping.map_to;
288 static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
290 struct smu_11_0_cmn2aisc_mapping mapping;
292 if (index >= SMU_MSG_MAX_COUNT)
295 mapping = vega20_message_map[index];
296 if (!(mapping.valid_mapping)) {
300 return mapping.map_to;
303 static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
305 struct smu_11_0_cmn2aisc_mapping mapping;
307 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
310 mapping = vega20_workload_map[profile];
311 if (!(mapping.valid_mapping)) {
315 return mapping.map_to;
318 static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
320 struct smu_table_context *smu_table = &smu->smu_table;
322 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
323 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
324 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
325 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
326 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
327 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
328 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
329 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
330 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
331 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
332 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
333 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
334 AMDGPU_GEM_DOMAIN_VRAM);
336 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
337 if (!smu_table->metrics_table)
339 smu_table->metrics_time = 0;
344 static int vega20_allocate_dpm_context(struct smu_context *smu)
346 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
348 if (smu_dpm->dpm_context)
351 smu_dpm->dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
353 if (!smu_dpm->dpm_context)
356 if (smu_dpm->golden_dpm_context)
359 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct vega20_dpm_table),
361 if (!smu_dpm->golden_dpm_context)
364 smu_dpm->dpm_context_size = sizeof(struct vega20_dpm_table);
366 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
368 if (!smu_dpm->dpm_current_power_state)
371 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
373 if (!smu_dpm->dpm_request_power_state)
379 static int vega20_setup_od8_information(struct smu_context *smu)
381 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
382 struct smu_table_context *table_context = &smu->smu_table;
383 struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings *)smu->od_settings;
385 uint32_t od_feature_count, od_feature_array_size,
386 od_setting_count, od_setting_array_size;
388 if (!table_context->power_play_table)
391 powerplay_table = table_context->power_play_table;
393 if (powerplay_table->OverDrive8Table.ucODTableRevision == 1) {
394 /* Setup correct ODFeatureCount, and store ODFeatureArray from
395 * powerplay table to od_feature_capabilities */
397 (le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount) >
398 ATOM_VEGA20_ODFEATURE_COUNT) ?
399 ATOM_VEGA20_ODFEATURE_COUNT :
400 le32_to_cpu(powerplay_table->OverDrive8Table.ODFeatureCount);
402 od_feature_array_size = sizeof(uint8_t) * od_feature_count;
404 if (od8_settings->od_feature_capabilities)
407 od8_settings->od_feature_capabilities = kmemdup(&powerplay_table->OverDrive8Table.ODFeatureCapabilities,
408 od_feature_array_size,
410 if (!od8_settings->od_feature_capabilities)
413 /* Setup correct ODSettingCount, and store ODSettingArray from
414 * powerplay table to od_settings_max and od_setting_min */
416 (le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount) >
417 ATOM_VEGA20_ODSETTING_COUNT) ?
418 ATOM_VEGA20_ODSETTING_COUNT :
419 le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingCount);
421 od_setting_array_size = sizeof(uint32_t) * od_setting_count;
423 if (od8_settings->od_settings_max)
426 od8_settings->od_settings_max = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMax,
427 od_setting_array_size,
430 if (!od8_settings->od_settings_max) {
431 kfree(od8_settings->od_feature_capabilities);
432 od8_settings->od_feature_capabilities = NULL;
436 if (od8_settings->od_settings_min)
439 od8_settings->od_settings_min = kmemdup(&powerplay_table->OverDrive8Table.ODSettingsMin,
440 od_setting_array_size,
443 if (!od8_settings->od_settings_min) {
444 kfree(od8_settings->od_feature_capabilities);
445 od8_settings->od_feature_capabilities = NULL;
446 kfree(od8_settings->od_settings_max);
447 od8_settings->od_settings_max = NULL;
455 static int vega20_store_powerplay_table(struct smu_context *smu)
457 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
458 struct smu_table_context *table_context = &smu->smu_table;
460 if (!table_context->power_play_table)
463 powerplay_table = table_context->power_play_table;
465 memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable,
468 table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
473 static int vega20_append_powerplay_table(struct smu_context *smu)
475 struct smu_table_context *table_context = &smu->smu_table;
476 PPTable_t *smc_pptable = table_context->driver_pptable;
477 struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
480 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
483 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
484 (uint8_t **)&smc_dpm_table);
488 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
489 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
491 smc_pptable->VddGfxVrMapping = smc_dpm_table->vddgfxvrmapping;
492 smc_pptable->VddSocVrMapping = smc_dpm_table->vddsocvrmapping;
493 smc_pptable->VddMem0VrMapping = smc_dpm_table->vddmem0vrmapping;
494 smc_pptable->VddMem1VrMapping = smc_dpm_table->vddmem1vrmapping;
496 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->gfxulvphasesheddingmask;
497 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->soculvphasesheddingmask;
498 smc_pptable->ExternalSensorPresent = smc_dpm_table->externalsensorpresent;
500 smc_pptable->GfxMaxCurrent = smc_dpm_table->gfxmaxcurrent;
501 smc_pptable->GfxOffset = smc_dpm_table->gfxoffset;
502 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->padding_telemetrygfx;
504 smc_pptable->SocMaxCurrent = smc_dpm_table->socmaxcurrent;
505 smc_pptable->SocOffset = smc_dpm_table->socoffset;
506 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->padding_telemetrysoc;
508 smc_pptable->Mem0MaxCurrent = smc_dpm_table->mem0maxcurrent;
509 smc_pptable->Mem0Offset = smc_dpm_table->mem0offset;
510 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->padding_telemetrymem0;
512 smc_pptable->Mem1MaxCurrent = smc_dpm_table->mem1maxcurrent;
513 smc_pptable->Mem1Offset = smc_dpm_table->mem1offset;
514 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->padding_telemetrymem1;
516 smc_pptable->AcDcGpio = smc_dpm_table->acdcgpio;
517 smc_pptable->AcDcPolarity = smc_dpm_table->acdcpolarity;
518 smc_pptable->VR0HotGpio = smc_dpm_table->vr0hotgpio;
519 smc_pptable->VR0HotPolarity = smc_dpm_table->vr0hotpolarity;
521 smc_pptable->VR1HotGpio = smc_dpm_table->vr1hotgpio;
522 smc_pptable->VR1HotPolarity = smc_dpm_table->vr1hotpolarity;
523 smc_pptable->Padding1 = smc_dpm_table->padding1;
524 smc_pptable->Padding2 = smc_dpm_table->padding2;
526 smc_pptable->LedPin0 = smc_dpm_table->ledpin0;
527 smc_pptable->LedPin1 = smc_dpm_table->ledpin1;
528 smc_pptable->LedPin2 = smc_dpm_table->ledpin2;
530 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->pllgfxclkspreadenabled;
531 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->pllgfxclkspreadpercent;
532 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->pllgfxclkspreadfreq;
534 smc_pptable->UclkSpreadEnabled = 0;
535 smc_pptable->UclkSpreadPercent = smc_dpm_table->uclkspreadpercent;
536 smc_pptable->UclkSpreadFreq = smc_dpm_table->uclkspreadfreq;
538 smc_pptable->FclkSpreadEnabled = smc_dpm_table->fclkspreadenabled;
539 smc_pptable->FclkSpreadPercent = smc_dpm_table->fclkspreadpercent;
540 smc_pptable->FclkSpreadFreq = smc_dpm_table->fclkspreadfreq;
542 smc_pptable->FllGfxclkSpreadEnabled = smc_dpm_table->fllgfxclkspreadenabled;
543 smc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
544 smc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
546 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
547 smc_pptable->I2cControllers[i].Enabled =
548 smc_dpm_table->i2ccontrollers[i].enabled;
549 smc_pptable->I2cControllers[i].SlaveAddress =
550 smc_dpm_table->i2ccontrollers[i].slaveaddress;
551 smc_pptable->I2cControllers[i].ControllerPort =
552 smc_dpm_table->i2ccontrollers[i].controllerport;
553 smc_pptable->I2cControllers[i].ThermalThrottler =
554 smc_dpm_table->i2ccontrollers[i].thermalthrottler;
555 smc_pptable->I2cControllers[i].I2cProtocol =
556 smc_dpm_table->i2ccontrollers[i].i2cprotocol;
557 smc_pptable->I2cControllers[i].I2cSpeed =
558 smc_dpm_table->i2ccontrollers[i].i2cspeed;
564 static int vega20_check_powerplay_table(struct smu_context *smu)
566 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
567 struct smu_table_context *table_context = &smu->smu_table;
569 powerplay_table = table_context->power_play_table;
571 if (powerplay_table->sHeader.format_revision < ATOM_VEGA20_TABLE_REVISION_VEGA20) {
572 pr_err("Unsupported PPTable format!");
576 if (!powerplay_table->sHeader.structuresize) {
577 pr_err("Invalid PowerPlay Table!");
584 static int vega20_run_btc_afll(struct smu_context *smu)
586 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
589 #define FEATURE_MASK(feature) (1ULL << feature)
591 vega20_get_allowed_feature_mask(struct smu_context *smu,
592 uint32_t *feature_mask, uint32_t num)
597 memset(feature_mask, 0, sizeof(uint32_t) * num);
599 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
600 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
601 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
602 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
603 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
604 | FEATURE_MASK(FEATURE_DPM_VCE_BIT)
605 | FEATURE_MASK(FEATURE_ULV_BIT)
606 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
607 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
608 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
609 | FEATURE_MASK(FEATURE_PPT_BIT)
610 | FEATURE_MASK(FEATURE_TDC_BIT)
611 | FEATURE_MASK(FEATURE_THERMAL_BIT)
612 | FEATURE_MASK(FEATURE_GFX_PER_CU_CG_BIT)
613 | FEATURE_MASK(FEATURE_RM_BIT)
614 | FEATURE_MASK(FEATURE_ACDC_BIT)
615 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
616 | FEATURE_MASK(FEATURE_VR1HOT_BIT)
617 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
618 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
619 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
620 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
621 | FEATURE_MASK(FEATURE_GFXOFF_BIT)
622 | FEATURE_MASK(FEATURE_CG_BIT)
623 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
624 | FEATURE_MASK(FEATURE_XGMI_BIT);
629 amd_pm_state_type vega20_get_current_power_state(struct smu_context *smu)
631 enum amd_pm_state_type pm_type;
632 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
634 if (!smu_dpm_ctx->dpm_context ||
635 !smu_dpm_ctx->dpm_current_power_state)
638 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
639 case SMU_STATE_UI_LABEL_BATTERY:
640 pm_type = POWER_STATE_TYPE_BATTERY;
642 case SMU_STATE_UI_LABEL_BALLANCED:
643 pm_type = POWER_STATE_TYPE_BALANCED;
645 case SMU_STATE_UI_LABEL_PERFORMANCE:
646 pm_type = POWER_STATE_TYPE_PERFORMANCE;
649 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
650 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
652 pm_type = POWER_STATE_TYPE_DEFAULT;
660 vega20_set_single_dpm_table(struct smu_context *smu,
661 struct vega20_single_dpm_table *single_dpm_table,
665 uint32_t i, num_of_levels = 0, clk;
667 ret = smu_send_smc_msg_with_param(smu,
668 SMU_MSG_GetDpmFreqByIndex,
669 (clk_id << 16 | 0xFF));
671 pr_err("[GetNumOfDpmLevel] failed to get dpm levels!");
675 smu_read_smc_arg(smu, &num_of_levels);
676 if (!num_of_levels) {
677 pr_err("[GetNumOfDpmLevel] number of clk levels is invalid!");
681 single_dpm_table->count = num_of_levels;
683 for (i = 0; i < num_of_levels; i++) {
684 ret = smu_send_smc_msg_with_param(smu,
685 SMU_MSG_GetDpmFreqByIndex,
688 pr_err("[GetDpmFreqByIndex] failed to get dpm freq by index!");
691 smu_read_smc_arg(smu, &clk);
693 pr_err("[GetDpmFreqByIndex] clk value is invalid!");
696 single_dpm_table->dpm_levels[i].value = clk;
697 single_dpm_table->dpm_levels[i].enabled = true;
702 static void vega20_init_single_dpm_state(struct vega20_dpm_state *dpm_state)
704 dpm_state->soft_min_level = 0x0;
705 dpm_state->soft_max_level = 0xffff;
706 dpm_state->hard_min_level = 0x0;
707 dpm_state->hard_max_level = 0xffff;
710 static int vega20_set_default_dpm_table(struct smu_context *smu)
714 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
715 struct vega20_dpm_table *dpm_table = NULL;
716 struct vega20_single_dpm_table *single_dpm_table;
718 dpm_table = smu_dpm->dpm_context;
721 single_dpm_table = &(dpm_table->soc_table);
723 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
724 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
727 pr_err("[SetupDefaultDpmTable] failed to get socclk dpm levels!");
731 single_dpm_table->count = 1;
732 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
734 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
737 single_dpm_table = &(dpm_table->gfx_table);
739 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
740 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
743 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
747 single_dpm_table->count = 1;
748 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
750 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
753 single_dpm_table = &(dpm_table->mem_table);
755 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
756 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
759 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
763 single_dpm_table->count = 1;
764 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
766 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
769 single_dpm_table = &(dpm_table->eclk_table);
771 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)) {
772 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_ECLK);
774 pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
778 single_dpm_table->count = 1;
779 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
781 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
784 single_dpm_table = &(dpm_table->vclk_table);
786 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
787 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_VCLK);
789 pr_err("[SetupDefaultDpmTable] failed to get vclk dpm levels!");
793 single_dpm_table->count = 1;
794 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
796 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
799 single_dpm_table = &(dpm_table->dclk_table);
801 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
802 ret = vega20_set_single_dpm_table(smu, single_dpm_table, PPCLK_DCLK);
804 pr_err("[SetupDefaultDpmTable] failed to get dclk dpm levels!");
808 single_dpm_table->count = 1;
809 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
811 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
814 single_dpm_table = &(dpm_table->dcef_table);
816 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
817 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
820 pr_err("[SetupDefaultDpmTable] failed to get dcefclk dpm levels!");
824 single_dpm_table->count = 1;
825 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
827 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
830 single_dpm_table = &(dpm_table->pixel_table);
832 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
833 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
836 pr_err("[SetupDefaultDpmTable] failed to get pixclk dpm levels!");
840 single_dpm_table->count = 0;
842 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
845 single_dpm_table = &(dpm_table->display_table);
847 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
848 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
851 pr_err("[SetupDefaultDpmTable] failed to get dispclk dpm levels!");
855 single_dpm_table->count = 0;
857 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
860 single_dpm_table = &(dpm_table->phy_table);
862 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
863 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
866 pr_err("[SetupDefaultDpmTable] failed to get phyclk dpm levels!");
870 single_dpm_table->count = 0;
872 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
875 single_dpm_table = &(dpm_table->fclk_table);
877 if (smu_feature_is_enabled(smu,FEATURE_DPM_FCLK_BIT)) {
878 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
881 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
885 single_dpm_table->count = 0;
887 vega20_init_single_dpm_state(&(single_dpm_table->dpm_state));
889 memcpy(smu_dpm->golden_dpm_context, dpm_table,
890 sizeof(struct vega20_dpm_table));
895 static int vega20_populate_umd_state_clk(struct smu_context *smu)
897 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
898 struct vega20_dpm_table *dpm_table = NULL;
899 struct vega20_single_dpm_table *gfx_table = NULL;
900 struct vega20_single_dpm_table *mem_table = NULL;
902 dpm_table = smu_dpm->dpm_context;
903 gfx_table = &(dpm_table->gfx_table);
904 mem_table = &(dpm_table->mem_table);
906 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
907 smu->pstate_mclk = mem_table->dpm_levels[0].value;
909 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
910 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
911 smu->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
912 smu->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
915 smu->pstate_sclk = smu->pstate_sclk * 100;
916 smu->pstate_mclk = smu->pstate_mclk * 100;
921 static int vega20_get_clk_table(struct smu_context *smu,
922 struct pp_clock_levels_with_latency *clocks,
923 struct vega20_single_dpm_table *dpm_table)
927 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
928 clocks->num_levels = count;
930 for (i = 0; i < count; i++) {
931 clocks->data[i].clocks_in_khz =
932 dpm_table->dpm_levels[i].value * 1000;
933 clocks->data[i].latency_in_us = 0;
939 static int vega20_print_clk_levels(struct smu_context *smu,
940 enum smu_clk_type type, char *buf)
942 int i, now, size = 0;
944 uint32_t gen_speed, lane_width;
945 struct amdgpu_device *adev = smu->adev;
946 struct pp_clock_levels_with_latency clocks;
947 struct vega20_single_dpm_table *single_dpm_table;
948 struct smu_table_context *table_context = &smu->smu_table;
949 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
950 struct vega20_dpm_table *dpm_table = NULL;
951 struct vega20_od8_settings *od8_settings =
952 (struct vega20_od8_settings *)smu->od_settings;
953 OverDriveTable_t *od_table =
954 (OverDriveTable_t *)(table_context->overdrive_table);
955 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
957 dpm_table = smu_dpm->dpm_context;
961 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
963 pr_err("Attempt to get current gfx clk Failed!");
967 single_dpm_table = &(dpm_table->gfx_table);
968 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
970 pr_err("Attempt to get gfx clk levels Failed!");
974 for (i = 0; i < clocks.num_levels; i++)
975 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
976 clocks.data[i].clocks_in_khz / 1000,
977 (clocks.data[i].clocks_in_khz == now * 10)
982 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
984 pr_err("Attempt to get current mclk Failed!");
988 single_dpm_table = &(dpm_table->mem_table);
989 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
991 pr_err("Attempt to get memory clk levels Failed!");
995 for (i = 0; i < clocks.num_levels; i++)
996 size += sprintf(buf + size, "%d: %uMhz %s\n",
997 i, clocks.data[i].clocks_in_khz / 1000,
998 (clocks.data[i].clocks_in_khz == now * 10)
1003 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
1005 pr_err("Attempt to get current socclk Failed!");
1009 single_dpm_table = &(dpm_table->soc_table);
1010 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1012 pr_err("Attempt to get socclk levels Failed!");
1016 for (i = 0; i < clocks.num_levels; i++)
1017 size += sprintf(buf + size, "%d: %uMhz %s\n",
1018 i, clocks.data[i].clocks_in_khz / 1000,
1019 (clocks.data[i].clocks_in_khz == now * 10)
1024 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
1026 pr_err("Attempt to get current fclk Failed!");
1030 single_dpm_table = &(dpm_table->fclk_table);
1031 for (i = 0; i < single_dpm_table->count; i++)
1032 size += sprintf(buf + size, "%d: %uMhz %s\n",
1033 i, single_dpm_table->dpm_levels[i].value,
1034 (single_dpm_table->dpm_levels[i].value == now / 100)
1039 ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
1041 pr_err("Attempt to get current dcefclk Failed!");
1045 single_dpm_table = &(dpm_table->dcef_table);
1046 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1048 pr_err("Attempt to get dcefclk levels Failed!");
1052 for (i = 0; i < clocks.num_levels; i++)
1053 size += sprintf(buf + size, "%d: %uMhz %s\n",
1054 i, clocks.data[i].clocks_in_khz / 1000,
1055 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
1059 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1060 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1061 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1062 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1063 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1064 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1065 for (i = 0; i < NUM_LINK_LEVELS; i++)
1066 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1067 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
1068 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
1069 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
1070 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
1071 (pptable->PcieLaneCount[i] == 1) ? "x1" :
1072 (pptable->PcieLaneCount[i] == 2) ? "x2" :
1073 (pptable->PcieLaneCount[i] == 3) ? "x4" :
1074 (pptable->PcieLaneCount[i] == 4) ? "x8" :
1075 (pptable->PcieLaneCount[i] == 5) ? "x12" :
1076 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
1077 pptable->LclkFreq[i],
1078 (gen_speed == pptable->PcieGenSpeed[i]) &&
1079 (lane_width == pptable->PcieLaneCount[i]) ?
1084 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1085 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1086 size = sprintf(buf, "%s:\n", "OD_SCLK");
1087 size += sprintf(buf + size, "0: %10uMhz\n",
1088 od_table->GfxclkFmin);
1089 size += sprintf(buf + size, "1: %10uMhz\n",
1090 od_table->GfxclkFmax);
1096 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1097 size = sprintf(buf, "%s:\n", "OD_MCLK");
1098 size += sprintf(buf + size, "1: %10uMhz\n",
1099 od_table->UclkFmax);
1104 case SMU_OD_VDDC_CURVE:
1105 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1106 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1107 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1108 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1109 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1110 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1111 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
1112 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
1113 od_table->GfxclkFreq1,
1114 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
1115 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
1116 od_table->GfxclkFreq2,
1117 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
1118 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
1119 od_table->GfxclkFreq3,
1120 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
1126 size = sprintf(buf, "%s:\n", "OD_RANGE");
1128 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
1129 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id) {
1130 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1131 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
1132 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
1135 if (od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
1136 single_dpm_table = &(dpm_table->mem_table);
1137 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
1139 pr_err("Attempt to get memory clk levels Failed!");
1143 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1144 clocks.data[0].clocks_in_khz / 1000,
1145 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
1148 if (od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
1149 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
1150 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
1151 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
1152 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
1153 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
1154 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1155 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].min_value,
1156 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].max_value);
1157 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1158 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
1159 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
1160 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1161 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].min_value,
1162 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].max_value);
1163 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1164 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
1165 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
1166 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1167 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].min_value,
1168 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].max_value);
1169 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1170 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
1171 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
1182 static int vega20_upload_dpm_level(struct smu_context *smu, bool max,
1183 uint32_t feature_mask)
1185 struct vega20_dpm_table *dpm_table;
1186 struct vega20_single_dpm_table *single_dpm_table;
1190 dpm_table = smu->smu_dpm.dpm_context;
1192 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1193 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1194 single_dpm_table = &(dpm_table->gfx_table);
1195 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1196 single_dpm_table->dpm_state.soft_min_level;
1197 ret = smu_send_smc_msg_with_param(smu,
1198 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1199 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
1201 pr_err("Failed to set soft %s gfxclk !\n",
1202 max ? "max" : "min");
1207 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1208 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1209 single_dpm_table = &(dpm_table->mem_table);
1210 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1211 single_dpm_table->dpm_state.soft_min_level;
1212 ret = smu_send_smc_msg_with_param(smu,
1213 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1214 (PPCLK_UCLK << 16) | (freq & 0xffff));
1216 pr_err("Failed to set soft %s memclk !\n",
1217 max ? "max" : "min");
1222 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1223 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1224 single_dpm_table = &(dpm_table->soc_table);
1225 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1226 single_dpm_table->dpm_state.soft_min_level;
1227 ret = smu_send_smc_msg_with_param(smu,
1228 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1229 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
1231 pr_err("Failed to set soft %s socclk !\n",
1232 max ? "max" : "min");
1237 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT) &&
1238 (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1239 single_dpm_table = &(dpm_table->fclk_table);
1240 freq = max ? single_dpm_table->dpm_state.soft_max_level :
1241 single_dpm_table->dpm_state.soft_min_level;
1242 ret = smu_send_smc_msg_with_param(smu,
1243 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
1244 (PPCLK_FCLK << 16) | (freq & 0xffff));
1246 pr_err("Failed to set soft %s fclk !\n",
1247 max ? "max" : "min");
1252 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1253 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1254 single_dpm_table = &(dpm_table->dcef_table);
1255 freq = single_dpm_table->dpm_state.hard_min_level;
1257 ret = smu_send_smc_msg_with_param(smu,
1258 SMU_MSG_SetHardMinByFreq,
1259 (PPCLK_DCEFCLK << 16) | (freq & 0xffff));
1261 pr_err("Failed to set hard min dcefclk !\n");
1270 static int vega20_force_clk_levels(struct smu_context *smu,
1271 enum smu_clk_type clk_type, uint32_t mask)
1273 struct vega20_dpm_table *dpm_table;
1274 struct vega20_single_dpm_table *single_dpm_table;
1275 uint32_t soft_min_level, soft_max_level, hard_min_level;
1278 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1279 soft_max_level = mask ? (fls(mask) - 1) : 0;
1281 dpm_table = smu->smu_dpm.dpm_context;
1285 single_dpm_table = &(dpm_table->gfx_table);
1287 if (soft_max_level >= single_dpm_table->count) {
1288 pr_err("Clock level specified %d is over max allowed %d\n",
1289 soft_max_level, single_dpm_table->count - 1);
1294 single_dpm_table->dpm_state.soft_min_level =
1295 single_dpm_table->dpm_levels[soft_min_level].value;
1296 single_dpm_table->dpm_state.soft_max_level =
1297 single_dpm_table->dpm_levels[soft_max_level].value;
1299 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1301 pr_err("Failed to upload boot level to lowest!\n");
1305 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1307 pr_err("Failed to upload dpm max level to highest!\n");
1312 single_dpm_table = &(dpm_table->mem_table);
1314 if (soft_max_level >= single_dpm_table->count) {
1315 pr_err("Clock level specified %d is over max allowed %d\n",
1316 soft_max_level, single_dpm_table->count - 1);
1321 single_dpm_table->dpm_state.soft_min_level =
1322 single_dpm_table->dpm_levels[soft_min_level].value;
1323 single_dpm_table->dpm_state.soft_max_level =
1324 single_dpm_table->dpm_levels[soft_max_level].value;
1326 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
1328 pr_err("Failed to upload boot level to lowest!\n");
1332 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
1334 pr_err("Failed to upload dpm max level to highest!\n");
1339 single_dpm_table = &(dpm_table->soc_table);
1341 if (soft_max_level >= single_dpm_table->count) {
1342 pr_err("Clock level specified %d is over max allowed %d\n",
1343 soft_max_level, single_dpm_table->count - 1);
1348 single_dpm_table->dpm_state.soft_min_level =
1349 single_dpm_table->dpm_levels[soft_min_level].value;
1350 single_dpm_table->dpm_state.soft_max_level =
1351 single_dpm_table->dpm_levels[soft_max_level].value;
1353 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
1355 pr_err("Failed to upload boot level to lowest!\n");
1359 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
1361 pr_err("Failed to upload dpm max level to highest!\n");
1366 single_dpm_table = &(dpm_table->fclk_table);
1368 if (soft_max_level >= single_dpm_table->count) {
1369 pr_err("Clock level specified %d is over max allowed %d\n",
1370 soft_max_level, single_dpm_table->count - 1);
1375 single_dpm_table->dpm_state.soft_min_level =
1376 single_dpm_table->dpm_levels[soft_min_level].value;
1377 single_dpm_table->dpm_state.soft_max_level =
1378 single_dpm_table->dpm_levels[soft_max_level].value;
1380 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
1382 pr_err("Failed to upload boot level to lowest!\n");
1386 ret = vega20_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
1388 pr_err("Failed to upload dpm max level to highest!\n");
1393 hard_min_level = soft_min_level;
1394 single_dpm_table = &(dpm_table->dcef_table);
1396 if (hard_min_level >= single_dpm_table->count) {
1397 pr_err("Clock level specified %d is over max allowed %d\n",
1398 hard_min_level, single_dpm_table->count - 1);
1403 single_dpm_table->dpm_state.hard_min_level =
1404 single_dpm_table->dpm_levels[hard_min_level].value;
1406 ret = vega20_upload_dpm_level(smu, false, FEATURE_DPM_DCEFCLK_MASK);
1408 pr_err("Failed to upload boot level to lowest!\n");
1413 if (soft_min_level >= NUM_LINK_LEVELS ||
1414 soft_max_level >= NUM_LINK_LEVELS) {
1419 ret = smu_send_smc_msg_with_param(smu,
1420 SMU_MSG_SetMinLinkDpmByIndex, soft_min_level);
1422 pr_err("Failed to set min link dpm level!\n");
1433 static int vega20_get_clock_by_type_with_latency(struct smu_context *smu,
1434 enum smu_clk_type clk_type,
1435 struct pp_clock_levels_with_latency *clocks)
1438 struct vega20_single_dpm_table *single_dpm_table;
1439 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1440 struct vega20_dpm_table *dpm_table = NULL;
1442 dpm_table = smu_dpm->dpm_context;
1446 single_dpm_table = &(dpm_table->gfx_table);
1447 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1450 single_dpm_table = &(dpm_table->mem_table);
1451 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1454 single_dpm_table = &(dpm_table->dcef_table);
1455 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1458 single_dpm_table = &(dpm_table->soc_table);
1459 ret = vega20_get_clk_table(smu, clocks, single_dpm_table);
1468 static int vega20_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1474 ret = smu_send_smc_msg_with_param(smu,
1475 SMU_MSG_GetAVFSVoltageByDpm,
1476 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1478 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1482 smu_read_smc_arg(smu, voltage);
1483 *voltage = *voltage / VOLTAGE_SCALE;
1488 static int vega20_set_default_od8_setttings(struct smu_context *smu)
1490 struct smu_table_context *table_context = &smu->smu_table;
1491 OverDriveTable_t *od_table = (OverDriveTable_t *)(table_context->overdrive_table);
1492 struct vega20_od8_settings *od8_settings = NULL;
1493 PPTable_t *smc_pptable = table_context->driver_pptable;
1496 if (smu->od_settings)
1499 od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
1504 smu->od_settings = (void *)od8_settings;
1506 ret = vega20_setup_od8_information(smu);
1508 pr_err("Retrieve board OD limits failed!\n");
1512 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1513 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1514 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1515 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1516 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1517 od8_settings->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) {
1518 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1520 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1522 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1523 od_table->GfxclkFmin;
1524 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1525 od_table->GfxclkFmax;
1528 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1529 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1530 smc_pptable->MinVoltageGfx / VOLTAGE_SCALE) &&
1531 (od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1532 smc_pptable->MaxVoltageGfx / VOLTAGE_SCALE) &&
1533 (od8_settings->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] <=
1534 od8_settings->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3])) {
1535 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1537 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1539 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1541 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1543 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1545 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1548 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1549 od_table->GfxclkFreq2 = (od_table->GfxclkFmin + od_table->GfxclkFmax) / 2;
1550 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1551 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1552 od_table->GfxclkFreq1;
1553 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1554 od_table->GfxclkFreq2;
1555 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1556 od_table->GfxclkFreq3;
1558 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1559 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value,
1560 od_table->GfxclkFreq1);
1562 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0;
1563 od_table->GfxclkVolt1 =
1564 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1566 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1567 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value,
1568 od_table->GfxclkFreq2);
1570 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0;
1571 od_table->GfxclkVolt2 =
1572 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1574 ret = vega20_overdrive_get_gfx_clk_base_voltage(smu,
1575 &od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value,
1576 od_table->GfxclkFreq3);
1578 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0;
1579 od_table->GfxclkVolt3 =
1580 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1585 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1586 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1587 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1588 od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1589 (od8_settings->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1590 od8_settings->od_settings_min[OD8_SETTING_UCLK_FMAX])) {
1591 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id =
1593 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1598 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1599 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1600 od8_settings->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1601 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1602 od8_settings->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100) {
1603 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id =
1605 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1606 od_table->OverDrivePct;
1609 if (smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) {
1610 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1611 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1612 od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1613 (od8_settings->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1614 od8_settings->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) {
1615 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1616 OD8_ACOUSTIC_LIMIT_SCLK;
1617 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1618 od_table->FanMaximumRpm;
1621 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1622 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1623 od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1624 (od8_settings->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1625 od8_settings->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) {
1626 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1628 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1629 od_table->FanMinimumPwm * smc_pptable->FanMaximumRpm / 100;
1633 if (smu_feature_is_enabled(smu, SMU_FEATURE_THERMAL_BIT)) {
1634 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1635 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1636 od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1637 (od8_settings->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1638 od8_settings->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) {
1639 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1640 OD8_TEMPERATURE_FAN;
1641 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1642 od_table->FanTargetTemperature;
1645 if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1646 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1647 od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1648 (od8_settings->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1649 od8_settings->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) {
1650 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1651 OD8_TEMPERATURE_SYSTEM;
1652 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1653 od_table->MaxOpTemp;
1657 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1658 if (od8_settings->od8_settings_array[i].feature_id) {
1659 od8_settings->od8_settings_array[i].min_value =
1660 od8_settings->od_settings_min[i];
1661 od8_settings->od8_settings_array[i].max_value =
1662 od8_settings->od_settings_max[i];
1663 od8_settings->od8_settings_array[i].current_value =
1664 od8_settings->od8_settings_array[i].default_value;
1666 od8_settings->od8_settings_array[i].min_value = 0;
1667 od8_settings->od8_settings_array[i].max_value = 0;
1668 od8_settings->od8_settings_array[i].current_value = 0;
1675 static int vega20_get_metrics_table(struct smu_context *smu,
1676 SmuMetrics_t *metrics_table)
1678 struct smu_table_context *smu_table= &smu->smu_table;
1681 mutex_lock(&smu->metrics_lock);
1682 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
1683 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
1684 (void *)smu_table->metrics_table, false);
1686 pr_info("Failed to export SMU metrics table!\n");
1687 mutex_unlock(&smu->metrics_lock);
1690 smu_table->metrics_time = jiffies;
1693 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
1694 mutex_unlock(&smu->metrics_lock);
1699 static int vega20_set_default_od_settings(struct smu_context *smu,
1702 struct smu_table_context *table_context = &smu->smu_table;
1706 if (table_context->overdrive_table)
1709 table_context->overdrive_table = kzalloc(sizeof(OverDriveTable_t), GFP_KERNEL);
1711 if (!table_context->overdrive_table)
1714 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1715 table_context->overdrive_table, false);
1717 pr_err("Failed to export over drive table!\n");
1721 ret = vega20_set_default_od8_setttings(smu);
1726 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
1727 table_context->overdrive_table, true);
1729 pr_err("Failed to import over drive table!\n");
1736 static int vega20_get_od_percentage(struct smu_context *smu,
1737 enum smu_clk_type clk_type)
1739 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1740 struct vega20_dpm_table *dpm_table = NULL;
1741 struct vega20_dpm_table *golden_table = NULL;
1742 struct vega20_single_dpm_table *single_dpm_table;
1743 struct vega20_single_dpm_table *golden_dpm_table;
1744 int value, golden_value;
1746 dpm_table = smu_dpm->dpm_context;
1747 golden_table = smu_dpm->golden_dpm_context;
1751 single_dpm_table = &(dpm_table->gfx_table);
1752 golden_dpm_table = &(golden_table->gfx_table);
1755 single_dpm_table = &(dpm_table->mem_table);
1756 golden_dpm_table = &(golden_table->mem_table);
1763 value = single_dpm_table->dpm_levels[single_dpm_table->count - 1].value;
1764 golden_value = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
1766 value -= golden_value;
1767 value = DIV_ROUND_UP(value * 100, golden_value);
1772 static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
1774 DpmActivityMonitorCoeffInt_t activity_monitor;
1775 uint32_t i, size = 0;
1776 int16_t workload_type = 0;
1777 static const char *profile_name[] = {
1785 static const char *title[] = {
1786 "PROFILE_INDEX(NAME)",
1790 "MinActiveFreqType",
1795 "PD_Data_error_coeff",
1796 "PD_Data_error_rate_coeff"};
1799 if (!smu->pm_enabled || !buf)
1802 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1803 title[0], title[1], title[2], title[3], title[4], title[5],
1804 title[6], title[7], title[8], title[9], title[10]);
1806 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1807 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1808 workload_type = smu_workload_get_type(smu, i);
1809 if (workload_type < 0)
1812 result = smu_update_table(smu,
1813 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1814 (void *)(&activity_monitor), false);
1816 pr_err("[%s] Failed to get activity monitor!", __func__);
1820 size += sprintf(buf + size, "%2d %14s%s:\n",
1821 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1823 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1827 activity_monitor.Gfx_FPS,
1828 activity_monitor.Gfx_UseRlcBusy,
1829 activity_monitor.Gfx_MinActiveFreqType,
1830 activity_monitor.Gfx_MinActiveFreq,
1831 activity_monitor.Gfx_BoosterFreqType,
1832 activity_monitor.Gfx_BoosterFreq,
1833 activity_monitor.Gfx_PD_Data_limit_c,
1834 activity_monitor.Gfx_PD_Data_error_coeff,
1835 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1837 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1841 activity_monitor.Soc_FPS,
1842 activity_monitor.Soc_UseRlcBusy,
1843 activity_monitor.Soc_MinActiveFreqType,
1844 activity_monitor.Soc_MinActiveFreq,
1845 activity_monitor.Soc_BoosterFreqType,
1846 activity_monitor.Soc_BoosterFreq,
1847 activity_monitor.Soc_PD_Data_limit_c,
1848 activity_monitor.Soc_PD_Data_error_coeff,
1849 activity_monitor.Soc_PD_Data_error_rate_coeff);
1851 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1855 activity_monitor.Mem_FPS,
1856 activity_monitor.Mem_UseRlcBusy,
1857 activity_monitor.Mem_MinActiveFreqType,
1858 activity_monitor.Mem_MinActiveFreq,
1859 activity_monitor.Mem_BoosterFreqType,
1860 activity_monitor.Mem_BoosterFreq,
1861 activity_monitor.Mem_PD_Data_limit_c,
1862 activity_monitor.Mem_PD_Data_error_coeff,
1863 activity_monitor.Mem_PD_Data_error_rate_coeff);
1865 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1869 activity_monitor.Fclk_FPS,
1870 activity_monitor.Fclk_UseRlcBusy,
1871 activity_monitor.Fclk_MinActiveFreqType,
1872 activity_monitor.Fclk_MinActiveFreq,
1873 activity_monitor.Fclk_BoosterFreqType,
1874 activity_monitor.Fclk_BoosterFreq,
1875 activity_monitor.Fclk_PD_Data_limit_c,
1876 activity_monitor.Fclk_PD_Data_error_coeff,
1877 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1883 static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1885 DpmActivityMonitorCoeffInt_t activity_monitor;
1886 int workload_type = 0, ret = 0;
1888 smu->power_profile_mode = input[size];
1890 if (!smu->pm_enabled)
1892 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1893 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1897 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1898 ret = smu_update_table(smu,
1899 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1900 (void *)(&activity_monitor), false);
1902 pr_err("[%s] Failed to get activity monitor!", __func__);
1907 case 0: /* Gfxclk */
1908 activity_monitor.Gfx_FPS = input[1];
1909 activity_monitor.Gfx_UseRlcBusy = input[2];
1910 activity_monitor.Gfx_MinActiveFreqType = input[3];
1911 activity_monitor.Gfx_MinActiveFreq = input[4];
1912 activity_monitor.Gfx_BoosterFreqType = input[5];
1913 activity_monitor.Gfx_BoosterFreq = input[6];
1914 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1915 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1916 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1918 case 1: /* Socclk */
1919 activity_monitor.Soc_FPS = input[1];
1920 activity_monitor.Soc_UseRlcBusy = input[2];
1921 activity_monitor.Soc_MinActiveFreqType = input[3];
1922 activity_monitor.Soc_MinActiveFreq = input[4];
1923 activity_monitor.Soc_BoosterFreqType = input[5];
1924 activity_monitor.Soc_BoosterFreq = input[6];
1925 activity_monitor.Soc_PD_Data_limit_c = input[7];
1926 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1927 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1930 activity_monitor.Mem_FPS = input[1];
1931 activity_monitor.Mem_UseRlcBusy = input[2];
1932 activity_monitor.Mem_MinActiveFreqType = input[3];
1933 activity_monitor.Mem_MinActiveFreq = input[4];
1934 activity_monitor.Mem_BoosterFreqType = input[5];
1935 activity_monitor.Mem_BoosterFreq = input[6];
1936 activity_monitor.Mem_PD_Data_limit_c = input[7];
1937 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1938 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1941 activity_monitor.Fclk_FPS = input[1];
1942 activity_monitor.Fclk_UseRlcBusy = input[2];
1943 activity_monitor.Fclk_MinActiveFreqType = input[3];
1944 activity_monitor.Fclk_MinActiveFreq = input[4];
1945 activity_monitor.Fclk_BoosterFreqType = input[5];
1946 activity_monitor.Fclk_BoosterFreq = input[6];
1947 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1948 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1949 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1953 ret = smu_update_table(smu,
1954 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1955 (void *)(&activity_monitor), true);
1957 pr_err("[%s] Failed to set activity monitor!", __func__);
1962 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1963 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1964 if (workload_type < 0)
1966 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1967 1 << workload_type);
1973 vega20_get_profiling_clk_mask(struct smu_context *smu,
1974 enum amd_dpm_forced_level level,
1975 uint32_t *sclk_mask,
1976 uint32_t *mclk_mask,
1979 struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
1980 struct vega20_single_dpm_table *gfx_dpm_table;
1981 struct vega20_single_dpm_table *mem_dpm_table;
1982 struct vega20_single_dpm_table *soc_dpm_table;
1984 if (!smu->smu_dpm.dpm_context)
1987 gfx_dpm_table = &dpm_table->gfx_table;
1988 mem_dpm_table = &dpm_table->mem_table;
1989 soc_dpm_table = &dpm_table->soc_table;
1995 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1996 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
1997 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
1998 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
1999 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2000 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2003 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2005 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2007 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2008 *sclk_mask = gfx_dpm_table->count - 1;
2009 *mclk_mask = mem_dpm_table->count - 1;
2010 *soc_mask = soc_dpm_table->count - 1;
2017 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu,
2018 struct vega20_single_dpm_table *dpm_table)
2021 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2022 if (!smu_dpm_ctx->dpm_context)
2025 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2026 if (dpm_table->count <= 0) {
2027 pr_err("[%s] Dpm table has no entry!", __func__);
2031 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) {
2032 pr_err("[%s] Dpm table has too many entries!", __func__);
2036 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2037 ret = smu_send_smc_msg_with_param(smu,
2038 SMU_MSG_SetHardMinByFreq,
2039 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level);
2041 pr_err("[%s] Set hard min uclk failed!", __func__);
2049 static int vega20_pre_display_config_changed(struct smu_context *smu)
2052 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2054 if (!smu->smu_dpm.dpm_context)
2057 smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
2058 ret = vega20_set_uclk_to_highest_dpm_level(smu,
2059 &dpm_table->mem_table);
2061 pr_err("Failed to set uclk to highest dpm level");
2065 static int vega20_display_config_changed(struct smu_context *smu)
2069 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2070 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2071 ret = smu_write_watermarks_table(smu);
2073 pr_err("Failed to update WMTABLE!");
2076 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2079 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2080 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
2081 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
2082 smu_send_smc_msg_with_param(smu,
2083 SMU_MSG_NumOfDisplays,
2084 smu->display_config->num_display);
2090 static int vega20_apply_clocks_adjust_rules(struct smu_context *smu)
2092 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2093 struct vega20_dpm_table *dpm_ctx = (struct vega20_dpm_table *)(smu_dpm_ctx->dpm_context);
2094 struct vega20_single_dpm_table *dpm_table;
2095 bool vblank_too_short = false;
2096 bool disable_mclk_switching;
2097 uint32_t i, latency;
2099 disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2100 !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2101 latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2104 dpm_table = &(dpm_ctx->gfx_table);
2105 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2106 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2107 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2108 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2110 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2111 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2112 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
2115 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2116 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2117 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2120 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2121 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2122 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2126 dpm_table = &(dpm_ctx->mem_table);
2127 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2128 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2129 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2130 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2132 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2133 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2134 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
2137 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2138 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2139 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2142 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2143 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2144 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2147 /* honour DAL's UCLK Hardmin */
2148 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2149 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2151 /* Hardmin is dependent on displayconfig */
2152 if (disable_mclk_switching) {
2153 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2154 for (i = 0; i < smu_dpm_ctx->mclk_latency_table->count - 1; i++) {
2155 if (smu_dpm_ctx->mclk_latency_table->entries[i].latency <= latency) {
2156 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2157 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2164 if (smu->display_config->nb_pstate_switch_disable)
2165 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2168 dpm_table = &(dpm_ctx->vclk_table);
2169 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2170 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2171 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2172 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2174 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2175 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2176 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2179 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2180 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2181 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2185 dpm_table = &(dpm_ctx->dclk_table);
2186 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2187 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2188 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2189 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2191 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2192 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2193 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
2196 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2197 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2198 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2202 dpm_table = &(dpm_ctx->soc_table);
2203 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2204 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2205 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2206 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2208 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2209 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2210 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
2213 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2214 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2215 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2219 dpm_table = &(dpm_ctx->eclk_table);
2220 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2221 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2222 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2223 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2225 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2226 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2227 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
2230 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2231 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2232 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2238 vega20_notify_smc_display_config(struct smu_context *smu)
2240 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context;
2241 struct vega20_single_dpm_table *memtable = &dpm_table->mem_table;
2242 struct smu_clocks min_clocks = {0};
2243 struct pp_display_clock_request clock_req;
2246 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2247 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2248 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2250 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2251 clock_req.clock_type = amd_pp_dcef_clock;
2252 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2253 if (!smu_v11_0_display_clock_voltage_request(smu, &clock_req)) {
2254 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2255 ret = smu_send_smc_msg_with_param(smu,
2256 SMU_MSG_SetMinDeepSleepDcefclk,
2257 min_clocks.dcef_clock_in_sr/100);
2259 pr_err("Attempt to set divider for DCEFCLK Failed!");
2264 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2268 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2269 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100;
2270 ret = smu_send_smc_msg_with_param(smu,
2271 SMU_MSG_SetHardMinByFreq,
2272 (PPCLK_UCLK << 16) | memtable->dpm_state.hard_min_level);
2274 pr_err("[%s] Set hard min uclk failed!", __func__);
2282 static uint32_t vega20_find_lowest_dpm_level(struct vega20_single_dpm_table *table)
2286 for (i = 0; i < table->count; i++) {
2287 if (table->dpm_levels[i].enabled)
2290 if (i >= table->count) {
2292 table->dpm_levels[i].enabled = true;
2298 static uint32_t vega20_find_highest_dpm_level(struct vega20_single_dpm_table *table)
2303 pr_err("[%s] DPM Table does not exist!", __func__);
2306 if (table->count <= 0) {
2307 pr_err("[%s] DPM Table has no entry!", __func__);
2310 if (table->count > MAX_REGULAR_DPM_NUMBER) {
2311 pr_err("[%s] DPM Table has too many entries!", __func__);
2312 return MAX_REGULAR_DPM_NUMBER - 1;
2315 for (i = table->count - 1; i >= 0; i--) {
2316 if (table->dpm_levels[i].enabled)
2321 table->dpm_levels[i].enabled = true;
2327 static int vega20_force_dpm_limit_value(struct smu_context *smu, bool highest)
2329 uint32_t soft_level;
2331 struct vega20_dpm_table *dpm_table =
2332 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2335 soft_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2337 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2339 dpm_table->gfx_table.dpm_state.soft_min_level =
2340 dpm_table->gfx_table.dpm_state.soft_max_level =
2341 dpm_table->gfx_table.dpm_levels[soft_level].value;
2344 soft_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2346 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2348 dpm_table->mem_table.dpm_state.soft_min_level =
2349 dpm_table->mem_table.dpm_state.soft_max_level =
2350 dpm_table->mem_table.dpm_levels[soft_level].value;
2353 soft_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2355 soft_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2357 dpm_table->soc_table.dpm_state.soft_min_level =
2358 dpm_table->soc_table.dpm_state.soft_max_level =
2359 dpm_table->soc_table.dpm_levels[soft_level].value;
2361 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2363 pr_err("Failed to upload boot level to %s!\n",
2364 highest ? "highest" : "lowest");
2368 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2370 pr_err("Failed to upload dpm max level to %s!\n!",
2371 highest ? "highest" : "lowest");
2378 static int vega20_unforce_dpm_levels(struct smu_context *smu)
2380 uint32_t soft_min_level, soft_max_level;
2382 struct vega20_dpm_table *dpm_table =
2383 (struct vega20_dpm_table *)smu->smu_dpm.dpm_context;
2385 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->gfx_table));
2386 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->gfx_table));
2387 dpm_table->gfx_table.dpm_state.soft_min_level =
2388 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2389 dpm_table->gfx_table.dpm_state.soft_max_level =
2390 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2392 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->mem_table));
2393 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->mem_table));
2394 dpm_table->mem_table.dpm_state.soft_min_level =
2395 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
2396 dpm_table->mem_table.dpm_state.soft_max_level =
2397 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
2399 soft_min_level = vega20_find_lowest_dpm_level(&(dpm_table->soc_table));
2400 soft_max_level = vega20_find_highest_dpm_level(&(dpm_table->soc_table));
2401 dpm_table->soc_table.dpm_state.soft_min_level =
2402 dpm_table->soc_table.dpm_levels[soft_min_level].value;
2403 dpm_table->soc_table.dpm_state.soft_max_level =
2404 dpm_table->soc_table.dpm_levels[soft_max_level].value;
2406 ret = vega20_upload_dpm_level(smu, false, 0xFFFFFFFF);
2408 pr_err("Failed to upload DPM Bootup Levels!");
2412 ret = vega20_upload_dpm_level(smu, true, 0xFFFFFFFF);
2414 pr_err("Failed to upload DPM Max Levels!");
2421 static int vega20_update_specified_od8_value(struct smu_context *smu,
2425 struct smu_table_context *table_context = &smu->smu_table;
2426 OverDriveTable_t *od_table =
2427 (OverDriveTable_t *)(table_context->overdrive_table);
2428 struct vega20_od8_settings *od8_settings =
2429 (struct vega20_od8_settings *)smu->od_settings;
2432 case OD8_SETTING_GFXCLK_FMIN:
2433 od_table->GfxclkFmin = (uint16_t)value;
2436 case OD8_SETTING_GFXCLK_FMAX:
2437 if (value < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].min_value ||
2438 value > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value)
2440 od_table->GfxclkFmax = (uint16_t)value;
2443 case OD8_SETTING_GFXCLK_FREQ1:
2444 od_table->GfxclkFreq1 = (uint16_t)value;
2447 case OD8_SETTING_GFXCLK_VOLTAGE1:
2448 od_table->GfxclkVolt1 = (uint16_t)value;
2451 case OD8_SETTING_GFXCLK_FREQ2:
2452 od_table->GfxclkFreq2 = (uint16_t)value;
2455 case OD8_SETTING_GFXCLK_VOLTAGE2:
2456 od_table->GfxclkVolt2 = (uint16_t)value;
2459 case OD8_SETTING_GFXCLK_FREQ3:
2460 od_table->GfxclkFreq3 = (uint16_t)value;
2463 case OD8_SETTING_GFXCLK_VOLTAGE3:
2464 od_table->GfxclkVolt3 = (uint16_t)value;
2467 case OD8_SETTING_UCLK_FMAX:
2468 if (value < od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].min_value ||
2469 value > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value)
2471 od_table->UclkFmax = (uint16_t)value;
2474 case OD8_SETTING_POWER_PERCENTAGE:
2475 od_table->OverDrivePct = (int16_t)value;
2478 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
2479 od_table->FanMaximumRpm = (uint16_t)value;
2482 case OD8_SETTING_FAN_MIN_SPEED:
2483 od_table->FanMinimumPwm = (uint16_t)value;
2486 case OD8_SETTING_FAN_TARGET_TEMP:
2487 od_table->FanTargetTemperature = (uint16_t)value;
2490 case OD8_SETTING_OPERATING_TEMP_MAX:
2491 od_table->MaxOpTemp = (uint16_t)value;
2498 static int vega20_update_od8_settings(struct smu_context *smu,
2502 struct smu_table_context *table_context = &smu->smu_table;
2505 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2506 table_context->overdrive_table, false);
2508 pr_err("Failed to export over drive table!\n");
2512 ret = vega20_update_specified_od8_value(smu, index, value);
2516 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
2517 table_context->overdrive_table, true);
2519 pr_err("Failed to import over drive table!\n");
2526 static int vega20_set_od_percentage(struct smu_context *smu,
2527 enum smu_clk_type clk_type,
2530 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2531 struct vega20_dpm_table *dpm_table = NULL;
2532 struct vega20_dpm_table *golden_table = NULL;
2533 struct vega20_single_dpm_table *single_dpm_table;
2534 struct vega20_single_dpm_table *golden_dpm_table;
2535 uint32_t od_clk, index;
2537 int feature_enabled;
2540 dpm_table = smu_dpm->dpm_context;
2541 golden_table = smu_dpm->golden_dpm_context;
2545 single_dpm_table = &(dpm_table->gfx_table);
2546 golden_dpm_table = &(golden_table->gfx_table);
2547 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT);
2548 clk_id = PPCLK_GFXCLK;
2549 index = OD8_SETTING_GFXCLK_FMAX;
2552 single_dpm_table = &(dpm_table->mem_table);
2553 golden_dpm_table = &(golden_table->mem_table);
2554 feature_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT);
2555 clk_id = PPCLK_UCLK;
2556 index = OD8_SETTING_UCLK_FMAX;
2566 od_clk = golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value * value;
2568 od_clk += golden_dpm_table->dpm_levels[golden_dpm_table->count - 1].value;
2570 ret = vega20_update_od8_settings(smu, index, od_clk);
2572 pr_err("[Setoverdrive] failed to set od clk!\n");
2576 if (feature_enabled) {
2577 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2580 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2584 single_dpm_table->count = 1;
2585 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2588 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2589 AMD_PP_TASK_READJUST_POWER_STATE,
2596 static int vega20_odn_edit_dpm_table(struct smu_context *smu,
2597 enum PP_OD_DPM_TABLE_COMMAND type,
2598 long *input, uint32_t size)
2600 struct smu_table_context *table_context = &smu->smu_table;
2601 OverDriveTable_t *od_table =
2602 (OverDriveTable_t *)(table_context->overdrive_table);
2603 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2604 struct vega20_dpm_table *dpm_table = NULL;
2605 struct vega20_single_dpm_table *single_dpm_table;
2606 struct vega20_od8_settings *od8_settings =
2607 (struct vega20_od8_settings *)smu->od_settings;
2608 struct pp_clock_levels_with_latency clocks;
2609 int32_t input_index, input_clk, input_vol, i;
2613 dpm_table = smu_dpm->dpm_context;
2616 pr_warn("NULL user input for clock and voltage\n");
2621 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2622 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2623 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2624 pr_info("Sclk min/max frequency overdrive not supported\n");
2628 for (i = 0; i < size; i += 2) {
2630 pr_info("invalid number of input parameters %d\n", size);
2634 input_index = input[i];
2635 input_clk = input[i + 1];
2637 if (input_index != 0 && input_index != 1) {
2638 pr_info("Invalid index %d\n", input_index);
2639 pr_info("Support min/max sclk frequency settingonly which index by 0/1\n");
2643 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value ||
2644 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) {
2645 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2647 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value,
2648 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value);
2652 if (input_index == 0 && od_table->GfxclkFmin != input_clk) {
2653 od_table->GfxclkFmin = input_clk;
2654 od8_settings->od_gfxclk_update = true;
2655 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) {
2656 od_table->GfxclkFmax = input_clk;
2657 od8_settings->od_gfxclk_update = true;
2663 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2664 if (!od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id) {
2665 pr_info("Mclk max frequency overdrive not supported\n");
2669 single_dpm_table = &(dpm_table->mem_table);
2670 ret = vega20_get_clk_table(smu, &clocks, single_dpm_table);
2672 pr_err("Attempt to get memory clk levels Failed!");
2676 for (i = 0; i < size; i += 2) {
2678 pr_info("invalid number of input parameters %d\n",
2683 input_index = input[i];
2684 input_clk = input[i + 1];
2686 if (input_index != 1) {
2687 pr_info("Invalid index %d\n", input_index);
2688 pr_info("Support max Mclk frequency setting only which index by 1\n");
2692 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2693 input_clk > od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value) {
2694 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2696 clocks.data[0].clocks_in_khz / 1000,
2697 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].max_value);
2701 if (input_index == 1 && od_table->UclkFmax != input_clk) {
2702 od8_settings->od_gfxclk_update = true;
2703 od_table->UclkFmax = input_clk;
2709 case PP_OD_EDIT_VDDC_CURVE:
2710 if (!(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2711 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2712 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2713 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2714 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2715 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2716 pr_info("Voltage curve calibrate not supported\n");
2720 for (i = 0; i < size; i += 3) {
2722 pr_info("invalid number of input parameters %d\n",
2727 input_index = input[i];
2728 input_clk = input[i + 1];
2729 input_vol = input[i + 2];
2731 if (input_index > 2) {
2732 pr_info("Setting for point %d is not supported\n",
2734 pr_info("Three supported points index by 0, 1, 2\n");
2738 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2739 if (input_clk < od8_settings->od8_settings_array[od8_id].min_value ||
2740 input_clk > od8_settings->od8_settings_array[od8_id].max_value) {
2741 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2743 od8_settings->od8_settings_array[od8_id].min_value,
2744 od8_settings->od8_settings_array[od8_id].max_value);
2748 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2749 if (input_vol < od8_settings->od8_settings_array[od8_id].min_value ||
2750 input_vol > od8_settings->od8_settings_array[od8_id].max_value) {
2751 pr_info("clock voltage %d is not within allowed range [%d- %d]\n",
2753 od8_settings->od8_settings_array[od8_id].min_value,
2754 od8_settings->od8_settings_array[od8_id].max_value);
2758 switch (input_index) {
2760 od_table->GfxclkFreq1 = input_clk;
2761 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2764 od_table->GfxclkFreq2 = input_clk;
2765 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2768 od_table->GfxclkFreq3 = input_clk;
2769 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2776 case PP_OD_RESTORE_DEFAULT_TABLE:
2777 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
2779 pr_err("Failed to export over drive table!\n");
2785 case PP_OD_COMMIT_DPM_TABLE:
2786 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
2788 pr_err("Failed to import over drive table!\n");
2792 /* retrieve updated gfxclk table */
2793 if (od8_settings->od_gfxclk_update) {
2794 od8_settings->od_gfxclk_update = false;
2795 single_dpm_table = &(dpm_table->gfx_table);
2797 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
2798 ret = vega20_set_single_dpm_table(smu, single_dpm_table,
2801 pr_err("[Setoverdrive] failed to refresh dpm table!\n");
2805 single_dpm_table->count = 1;
2806 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
2816 if (type == PP_OD_COMMIT_DPM_TABLE) {
2817 ret = smu_handle_task(smu, smu_dpm->dpm_level,
2818 AMD_PP_TASK_READJUST_POWER_STATE,
2825 static int vega20_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2827 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_UVD_BIT))
2830 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT))
2833 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_UVD_BIT, enable);
2836 static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
2838 if (!smu_feature_is_supported(smu, SMU_FEATURE_DPM_VCE_BIT))
2841 if (enable == smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT))
2844 return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
2847 static bool vega20_is_dpm_running(struct smu_context *smu)
2850 uint32_t feature_mask[2];
2851 unsigned long feature_enabled;
2852 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
2853 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
2854 ((uint64_t)feature_mask[1] << 32));
2855 return !!(feature_enabled & SMC_DPM_FEATURE);
2858 static int vega20_set_thermal_fan_table(struct smu_context *smu)
2861 struct smu_table_context *table_context = &smu->smu_table;
2862 PPTable_t *pptable = table_context->driver_pptable;
2864 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
2865 (uint32_t)pptable->FanTargetTemperature);
2870 static int vega20_get_fan_speed_rpm(struct smu_context *smu,
2875 ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);
2878 pr_err("Attempt to get current RPM from SMC Failed!\n");
2882 smu_read_smc_arg(smu, speed);
2887 static int vega20_get_fan_speed_percent(struct smu_context *smu,
2891 uint32_t current_rpm = 0, percent = 0;
2892 PPTable_t *pptable = smu->smu_table.driver_pptable;
2894 ret = vega20_get_fan_speed_rpm(smu, ¤t_rpm);
2898 percent = current_rpm * 100 / pptable->FanMaximumRpm;
2899 *speed = percent > 100 ? 100 : percent;
2904 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
2906 uint32_t smu_version;
2908 SmuMetrics_t metrics;
2913 ret = vega20_get_metrics_table(smu, &metrics);
2917 ret = smu_get_smc_version(smu, NULL, &smu_version);
2921 /* For the 40.46 release, they changed the value name */
2922 if (smu_version == 0x282e00)
2923 *value = metrics.AverageSocketPower << 8;
2925 *value = metrics.CurrSocketPower << 8;
2930 static int vega20_get_current_activity_percent(struct smu_context *smu,
2931 enum amd_pp_sensors sensor,
2935 SmuMetrics_t metrics;
2940 ret = vega20_get_metrics_table(smu, &metrics);
2945 case AMDGPU_PP_SENSOR_GPU_LOAD:
2946 *value = metrics.AverageGfxActivity;
2948 case AMDGPU_PP_SENSOR_MEM_LOAD:
2949 *value = metrics.AverageUclkActivity;
2952 pr_err("Invalid sensor for retrieving clock activity\n");
2959 static int vega20_thermal_get_temperature(struct smu_context *smu,
2960 enum amd_pp_sensors sensor,
2963 struct amdgpu_device *adev = smu->adev;
2964 SmuMetrics_t metrics;
2971 ret = vega20_get_metrics_table(smu, &metrics);
2976 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2977 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
2978 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
2979 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
2981 temp = temp & 0x1ff;
2982 temp *= SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2986 case AMDGPU_PP_SENSOR_EDGE_TEMP:
2987 *value = metrics.TemperatureEdge *
2988 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2990 case AMDGPU_PP_SENSOR_MEM_TEMP:
2991 *value = metrics.TemperatureHBM *
2992 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2995 pr_err("Invalid sensor for retrieving temp\n");
3001 static int vega20_read_sensor(struct smu_context *smu,
3002 enum amd_pp_sensors sensor,
3003 void *data, uint32_t *size)
3006 struct smu_table_context *table_context = &smu->smu_table;
3007 PPTable_t *pptable = table_context->driver_pptable;
3012 mutex_lock(&smu->sensor_lock);
3014 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
3015 *(uint32_t *)data = pptable->FanMaximumRpm;
3018 case AMDGPU_PP_SENSOR_MEM_LOAD:
3019 case AMDGPU_PP_SENSOR_GPU_LOAD:
3020 ret = vega20_get_current_activity_percent(smu,
3025 case AMDGPU_PP_SENSOR_GPU_POWER:
3026 ret = vega20_get_gpu_power(smu, (uint32_t *)data);
3029 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3030 case AMDGPU_PP_SENSOR_EDGE_TEMP:
3031 case AMDGPU_PP_SENSOR_MEM_TEMP:
3032 ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t *)data);
3036 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
3038 mutex_unlock(&smu->sensor_lock);
3043 static int vega20_set_watermarks_table(struct smu_context *smu,
3044 void *watermarks, struct
3045 dm_pp_wm_sets_with_clock_ranges_soc15
3049 Watermarks_t *table = watermarks;
3051 if (!table || !clock_ranges)
3054 if (clock_ranges->num_wm_dmif_sets > 4 ||
3055 clock_ranges->num_wm_mcif_sets > 4)
3058 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
3059 table->WatermarkRow[1][i].MinClock =
3060 cpu_to_le16((uint16_t)
3061 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
3063 table->WatermarkRow[1][i].MaxClock =
3064 cpu_to_le16((uint16_t)
3065 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
3067 table->WatermarkRow[1][i].MinUclk =
3068 cpu_to_le16((uint16_t)
3069 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3071 table->WatermarkRow[1][i].MaxUclk =
3072 cpu_to_le16((uint16_t)
3073 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3075 table->WatermarkRow[1][i].WmSetting = (uint8_t)
3076 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
3079 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
3080 table->WatermarkRow[0][i].MinClock =
3081 cpu_to_le16((uint16_t)
3082 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
3084 table->WatermarkRow[0][i].MaxClock =
3085 cpu_to_le16((uint16_t)
3086 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
3088 table->WatermarkRow[0][i].MinUclk =
3089 cpu_to_le16((uint16_t)
3090 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
3092 table->WatermarkRow[0][i].MaxUclk =
3093 cpu_to_le16((uint16_t)
3094 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
3096 table->WatermarkRow[0][i].WmSetting = (uint8_t)
3097 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
3103 static int vega20_get_thermal_temperature_range(struct smu_context *smu,
3104 struct smu_temperature_range *range)
3106 struct smu_table_context *table_context = &smu->smu_table;
3107 ATOM_Vega20_POWERPLAYTABLE *powerplay_table = table_context->power_play_table;
3108 PPTable_t *pptable = smu->smu_table.driver_pptable;
3110 if (!range || !powerplay_table)
3113 range->max = powerplay_table->usSoftwareShutdownTemp *
3114 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3115 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
3116 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3117 range->hotspot_crit_max = pptable->ThotspotLimit *
3118 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3119 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
3120 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3121 range->mem_crit_max = pptable->ThbmLimit *
3122 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3123 range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM) *
3124 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3130 static int vega20_set_df_cstate(struct smu_context *smu,
3131 enum pp_df_cstate state)
3133 uint32_t smu_version;
3136 ret = smu_get_smc_version(smu, NULL, &smu_version);
3138 pr_err("Failed to get smu version!\n");
3142 /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
3143 if (smu_version < 0x283200) {
3144 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
3148 return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state);
3151 static int vega20_update_pcie_parameters(struct smu_context *smu,
3152 uint32_t pcie_gen_cap,
3153 uint32_t pcie_width_cap)
3155 PPTable_t *pptable = smu->smu_table.driver_pptable;
3157 uint32_t smu_pcie_arg;
3159 for (i = 0; i < NUM_LINK_LEVELS; i++) {
3160 smu_pcie_arg = (i << 16) |
3161 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
3162 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
3163 pptable->PcieLaneCount[i] : pcie_width_cap);
3164 ret = smu_send_smc_msg_with_param(smu,
3165 SMU_MSG_OverridePcieParameters,
3173 static const struct pptable_funcs vega20_ppt_funcs = {
3174 .tables_init = vega20_tables_init,
3175 .alloc_dpm_context = vega20_allocate_dpm_context,
3176 .store_powerplay_table = vega20_store_powerplay_table,
3177 .check_powerplay_table = vega20_check_powerplay_table,
3178 .append_powerplay_table = vega20_append_powerplay_table,
3179 .get_smu_msg_index = vega20_get_smu_msg_index,
3180 .get_smu_clk_index = vega20_get_smu_clk_index,
3181 .get_smu_feature_index = vega20_get_smu_feature_index,
3182 .get_smu_table_index = vega20_get_smu_table_index,
3183 .get_smu_power_index = vega20_get_pwr_src_index,
3184 .get_workload_type = vega20_get_workload_type,
3185 .run_btc = vega20_run_btc_afll,
3186 .get_allowed_feature_mask = vega20_get_allowed_feature_mask,
3187 .get_current_power_state = vega20_get_current_power_state,
3188 .set_default_dpm_table = vega20_set_default_dpm_table,
3189 .set_power_state = NULL,
3190 .populate_umd_state_clk = vega20_populate_umd_state_clk,
3191 .print_clk_levels = vega20_print_clk_levels,
3192 .force_clk_levels = vega20_force_clk_levels,
3193 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3194 .get_od_percentage = vega20_get_od_percentage,
3195 .get_power_profile_mode = vega20_get_power_profile_mode,
3196 .set_power_profile_mode = vega20_set_power_profile_mode,
3197 .set_performance_level = smu_v11_0_set_performance_level,
3198 .set_od_percentage = vega20_set_od_percentage,
3199 .set_default_od_settings = vega20_set_default_od_settings,
3200 .od_edit_dpm_table = vega20_odn_edit_dpm_table,
3201 .dpm_set_uvd_enable = vega20_dpm_set_uvd_enable,
3202 .dpm_set_vce_enable = vega20_dpm_set_vce_enable,
3203 .read_sensor = vega20_read_sensor,
3204 .pre_display_config_changed = vega20_pre_display_config_changed,
3205 .display_config_changed = vega20_display_config_changed,
3206 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3207 .notify_smc_display_config = vega20_notify_smc_display_config,
3208 .force_dpm_limit_value = vega20_force_dpm_limit_value,
3209 .unforce_dpm_levels = vega20_unforce_dpm_levels,
3210 .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
3211 .is_dpm_running = vega20_is_dpm_running,
3212 .set_thermal_fan_table = vega20_set_thermal_fan_table,
3213 .get_fan_speed_percent = vega20_get_fan_speed_percent,
3214 .get_fan_speed_rpm = vega20_get_fan_speed_rpm,
3215 .set_watermarks_table = vega20_set_watermarks_table,
3216 .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3217 .set_df_cstate = vega20_set_df_cstate,
3218 .update_pcie_parameters = vega20_update_pcie_parameters,
3219 .init_microcode = smu_v11_0_init_microcode,
3220 .load_microcode = smu_v11_0_load_microcode,
3221 .init_smc_tables = smu_v11_0_init_smc_tables,
3222 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3223 .init_power = smu_v11_0_init_power,
3224 .fini_power = smu_v11_0_fini_power,
3225 .check_fw_status = smu_v11_0_check_fw_status,
3226 .setup_pptable = smu_v11_0_setup_pptable,
3227 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3228 .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
3229 .check_pptable = smu_v11_0_check_pptable,
3230 .parse_pptable = smu_v11_0_parse_pptable,
3231 .populate_smc_tables = smu_v11_0_populate_smc_pptable,
3232 .check_fw_version = smu_v11_0_check_fw_version,
3233 .write_pptable = smu_v11_0_write_pptable,
3234 .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
3235 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3236 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3237 .system_features_control = smu_v11_0_system_features_control,
3238 .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
3239 .read_smc_arg = smu_v11_0_read_arg,
3240 .init_display_count = smu_v11_0_init_display_count,
3241 .set_allowed_mask = smu_v11_0_set_allowed_mask,
3242 .get_enabled_mask = smu_v11_0_get_enabled_mask,
3243 .notify_display_change = smu_v11_0_notify_display_change,
3244 .set_power_limit = smu_v11_0_set_power_limit,
3245 .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
3246 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3247 .start_thermal_control = smu_v11_0_start_thermal_control,
3248 .stop_thermal_control = smu_v11_0_stop_thermal_control,
3249 .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
3250 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3251 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3252 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3253 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
3254 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3255 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3256 .gfx_off_control = smu_v11_0_gfx_off_control,
3257 .register_irq_handler = smu_v11_0_register_irq_handler,
3258 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3259 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3260 .baco_is_support= smu_v11_0_baco_is_support,
3261 .baco_get_state = smu_v11_0_baco_get_state,
3262 .baco_set_state = smu_v11_0_baco_set_state,
3263 .baco_enter = smu_v11_0_baco_enter,
3264 .baco_exit = smu_v11_0_baco_exit,
3265 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3266 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3267 .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
3270 void vega20_set_ppt_funcs(struct smu_context *smu)
3272 smu->ppt_funcs = &vega20_ppt_funcs;