1 // SPDX-License-Identifier: GPL-2.0
3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
4 * Author: James.Qian.Wang <james.qian.wang@arm.com>
8 #include <linux/of_device.h>
9 #include <linux/of_graph.h>
10 #include <linux/platform_device.h>
11 #include <linux/dma-mapping.h>
12 #ifdef CONFIG_DEBUG_FS
13 #include <linux/debugfs.h>
14 #include <linux/seq_file.h>
17 #include <drm/drm_print.h>
19 #include "komeda_dev.h"
21 static int komeda_register_show(struct seq_file *sf, void *x)
23 struct komeda_dev *mdev = sf->private;
26 if (mdev->funcs->dump_register)
27 mdev->funcs->dump_register(mdev, sf);
29 for (i = 0; i < mdev->n_pipelines; i++)
30 komeda_pipeline_dump_register(mdev->pipelines[i], sf);
35 static int komeda_register_open(struct inode *inode, struct file *filp)
37 return single_open(filp, komeda_register_show, inode->i_private);
40 static const struct file_operations komeda_register_fops = {
42 .open = komeda_register_open,
45 .release = single_release,
48 #ifdef CONFIG_DEBUG_FS
49 static void komeda_debugfs_init(struct komeda_dev *mdev)
51 if (!debugfs_initialized())
54 mdev->debugfs_root = debugfs_create_dir("komeda", NULL);
55 if (IS_ERR_OR_NULL(mdev->debugfs_root))
58 debugfs_create_file("register", 0444, mdev->debugfs_root,
59 mdev, &komeda_register_fops);
64 core_id_show(struct device *dev, struct device_attribute *attr, char *buf)
66 struct komeda_dev *mdev = dev_to_mdev(dev);
68 return snprintf(buf, PAGE_SIZE, "0x%08x\n", mdev->chip.core_id);
70 static DEVICE_ATTR_RO(core_id);
73 config_id_show(struct device *dev, struct device_attribute *attr, char *buf)
75 struct komeda_dev *mdev = dev_to_mdev(dev);
76 struct komeda_pipeline *pipe = mdev->pipelines[0];
77 union komeda_config_id config_id;
80 memset(&config_id, 0, sizeof(config_id));
82 config_id.max_line_sz = pipe->layers[0]->hsize_in.end;
83 config_id.n_pipelines = mdev->n_pipelines;
84 config_id.n_scalers = pipe->n_scalers;
85 config_id.n_layers = pipe->n_layers;
86 config_id.n_richs = 0;
87 for (i = 0; i < pipe->n_layers; i++) {
88 if (pipe->layers[i]->layer_type == KOMEDA_FMT_RICH_LAYER)
91 return snprintf(buf, PAGE_SIZE, "0x%08x\n", config_id.value);
93 static DEVICE_ATTR_RO(config_id);
95 static struct attribute *komeda_sysfs_entries[] = {
96 &dev_attr_core_id.attr,
97 &dev_attr_config_id.attr,
101 static struct attribute_group komeda_sysfs_attr_group = {
102 .attrs = komeda_sysfs_entries,
105 static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node *np)
107 struct komeda_pipeline *pipe;
112 ret = of_property_read_u32(np, "reg", &pipe_id);
113 if (ret != 0 || pipe_id >= mdev->n_pipelines)
116 pipe = mdev->pipelines[pipe_id];
118 clk = of_clk_get_by_name(np, "aclk");
120 DRM_ERROR("get aclk for pipeline %d failed!\n", pipe_id);
125 clk = of_clk_get_by_name(np, "pxclk");
127 DRM_ERROR("get pxclk for pipeline %d failed!\n", pipe_id);
133 pipe->of_output_dev =
134 of_graph_get_remote_node(np, KOMEDA_OF_PORT_OUTPUT, 0);
135 pipe->of_output_port =
136 of_graph_get_port_by_id(np, KOMEDA_OF_PORT_OUTPUT);
143 static int komeda_parse_dt(struct device *dev, struct komeda_dev *mdev)
145 struct platform_device *pdev = to_platform_device(dev);
146 struct device_node *child, *np = dev->of_node;
150 clk = devm_clk_get(dev, "mclk");
155 mdev->irq = platform_get_irq(pdev, 0);
157 DRM_ERROR("could not get IRQ number.\n");
161 for_each_available_child_of_node(np, child) {
162 if (of_node_cmp(child->name, "pipeline") == 0) {
163 ret = komeda_parse_pipe_dt(mdev, child);
165 DRM_ERROR("parse pipeline dt error!\n");
175 struct komeda_dev *komeda_dev_create(struct device *dev)
177 struct platform_device *pdev = to_platform_device(dev);
178 const struct komeda_product_data *product;
179 struct komeda_dev *mdev;
180 struct resource *io_res;
183 product = of_device_get_match_data(dev);
185 return ERR_PTR(-ENODEV);
187 io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
189 DRM_ERROR("No registers defined.\n");
190 return ERR_PTR(-ENODEV);
193 mdev = devm_kzalloc(dev, sizeof(*mdev), GFP_KERNEL);
195 return ERR_PTR(-ENOMEM);
197 mutex_init(&mdev->lock);
200 mdev->reg_base = devm_ioremap_resource(dev, io_res);
201 if (IS_ERR(mdev->reg_base)) {
202 DRM_ERROR("Map register space failed.\n");
203 err = PTR_ERR(mdev->reg_base);
204 mdev->reg_base = NULL;
208 mdev->pclk = devm_clk_get(dev, "pclk");
209 if (IS_ERR(mdev->pclk)) {
210 DRM_ERROR("Get APB clk failed.\n");
211 err = PTR_ERR(mdev->pclk);
216 /* Enable APB clock to access the registers */
217 clk_prepare_enable(mdev->pclk);
219 mdev->funcs = product->identify(mdev->reg_base, &mdev->chip);
220 if (!komeda_product_match(mdev, product->product_id)) {
221 DRM_ERROR("DT configured %x mismatch with real HW %x.\n",
223 MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id));
228 DRM_INFO("Found ARM Mali-D%x version r%dp%d\n",
229 MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id),
230 MALIDP_CORE_ID_MAJOR(mdev->chip.core_id),
231 MALIDP_CORE_ID_MINOR(mdev->chip.core_id));
233 mdev->funcs->init_format_table(mdev);
235 err = mdev->funcs->enum_resources(mdev);
237 DRM_ERROR("enumerate display resource failed.\n");
241 err = komeda_parse_dt(dev, mdev);
243 DRM_ERROR("parse device tree failed.\n");
247 err = komeda_assemble_pipelines(mdev);
249 DRM_ERROR("assemble display pipelines failed.\n");
253 dev->dma_parms = &mdev->dma_parms;
254 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
256 err = sysfs_create_group(&dev->kobj, &komeda_sysfs_attr_group);
258 DRM_ERROR("create sysfs group failed.\n");
262 #ifdef CONFIG_DEBUG_FS
263 komeda_debugfs_init(mdev);
269 komeda_dev_destroy(mdev);
273 void komeda_dev_destroy(struct komeda_dev *mdev)
275 struct device *dev = mdev->dev;
276 const struct komeda_dev_funcs *funcs = mdev->funcs;
279 sysfs_remove_group(&dev->kobj, &komeda_sysfs_attr_group);
281 #ifdef CONFIG_DEBUG_FS
282 debugfs_remove_recursive(mdev->debugfs_root);
285 for (i = 0; i < mdev->n_pipelines; i++) {
286 komeda_pipeline_destroy(mdev, mdev->pipelines[i]);
287 mdev->pipelines[i] = NULL;
290 mdev->n_pipelines = 0;
292 if (funcs && funcs->cleanup)
293 funcs->cleanup(mdev);
295 if (mdev->reg_base) {
296 devm_iounmap(dev, mdev->reg_base);
297 mdev->reg_base = NULL;
301 devm_clk_put(dev, mdev->mclk);
306 clk_disable_unprepare(mdev->pclk);
307 devm_clk_put(dev, mdev->pclk);
311 devm_kfree(dev, mdev);