1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
4 * Author: James.Qian.Wang <james.qian.wang@arm.com>
10 #include <linux/device.h>
11 #include <linux/clk.h>
12 #include "komeda_pipeline.h"
13 #include "malidp_product.h"
14 #include "komeda_format_caps.h"
16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
24 #define KOMEDA_ERR_TETO BIT_ULL(14)
25 #define KOMEDA_ERR_TEMR BIT_ULL(15)
26 #define KOMEDA_ERR_TITR BIT_ULL(16)
27 #define KOMEDA_ERR_CPE BIT_ULL(17)
28 #define KOMEDA_ERR_CFGE BIT_ULL(18)
29 #define KOMEDA_ERR_AXIE BIT_ULL(19)
30 #define KOMEDA_ERR_ACE0 BIT_ULL(20)
31 #define KOMEDA_ERR_ACE1 BIT_ULL(21)
32 #define KOMEDA_ERR_ACE2 BIT_ULL(22)
33 #define KOMEDA_ERR_ACE3 BIT_ULL(23)
34 #define KOMEDA_ERR_DRIFTTO BIT_ULL(24)
35 #define KOMEDA_ERR_FRAMETO BIT_ULL(25)
36 #define KOMEDA_ERR_CSCE BIT_ULL(26)
37 #define KOMEDA_ERR_ZME BIT_ULL(27)
38 #define KOMEDA_ERR_MERR BIT_ULL(28)
39 #define KOMEDA_ERR_TCF BIT_ULL(29)
40 #define KOMEDA_ERR_TTNG BIT_ULL(30)
41 #define KOMEDA_ERR_TTF BIT_ULL(31)
43 #define KOMEDA_ERR_EVENTS \
44 (KOMEDA_EVENT_URUN | KOMEDA_EVENT_IBSY | KOMEDA_EVENT_OVR |\
45 KOMEDA_ERR_TETO | KOMEDA_ERR_TEMR | KOMEDA_ERR_TITR |\
46 KOMEDA_ERR_CPE | KOMEDA_ERR_CFGE | KOMEDA_ERR_AXIE |\
47 KOMEDA_ERR_ACE0 | KOMEDA_ERR_ACE1 | KOMEDA_ERR_ACE2 |\
48 KOMEDA_ERR_ACE3 | KOMEDA_ERR_DRIFTTO | KOMEDA_ERR_FRAMETO |\
49 KOMEDA_ERR_ZME | KOMEDA_ERR_MERR | KOMEDA_ERR_TCF |\
50 KOMEDA_ERR_TTNG | KOMEDA_ERR_TTF)
52 #define KOMEDA_WARN_EVENTS KOMEDA_ERR_CSCE
54 #define KOMEDA_INFO_EVENTS (0 \
55 | KOMEDA_EVENT_VSYNC \
61 /* pipeline DT ports */
63 KOMEDA_OF_PORT_OUTPUT = 0,
64 KOMEDA_OF_PORT_COPROC = 1,
67 struct komeda_chip_info {
76 struct komeda_events {
78 u64 pipes[KOMEDA_MAX_PIPELINES];
82 * struct komeda_dev_funcs
84 * Supplied by chip level and returned by the chip entry function xxx_identify,
86 struct komeda_dev_funcs {
90 * initialize &komeda_dev->format_table, this function should be called
91 * before the &enum_resource
93 void (*init_format_table)(struct komeda_dev *mdev);
97 * for CHIP to report or add pipeline and component resources to CORE
99 int (*enum_resources)(struct komeda_dev *mdev);
100 /** @cleanup: call to chip to cleanup komeda_dev->chip data */
101 void (*cleanup)(struct komeda_dev *mdev);
102 /** @connect_iommu: Optional, connect to external iommu */
103 int (*connect_iommu)(struct komeda_dev *mdev);
104 /** @disconnect_iommu: Optional, disconnect to external iommu */
105 int (*disconnect_iommu)(struct komeda_dev *mdev);
109 * for CORE to get the HW event from the CHIP when interrupt happened.
111 irqreturn_t (*irq_handler)(struct komeda_dev *mdev,
112 struct komeda_events *events);
113 /** @enable_irq: enable irq */
114 int (*enable_irq)(struct komeda_dev *mdev);
115 /** @disable_irq: disable irq */
116 int (*disable_irq)(struct komeda_dev *mdev);
117 /** @on_off_vblank: notify HW to on/off vblank */
118 void (*on_off_vblank)(struct komeda_dev *mdev,
119 int master_pipe, bool on);
121 /** @dump_register: Optional, dump registers to seq_file */
122 void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
126 * Notify HW to switch to a new display operation mode.
128 int (*change_opmode)(struct komeda_dev *mdev, int new_mode);
129 /** @flush: Notify the HW to flush or kickoff the update */
130 void (*flush)(struct komeda_dev *mdev,
131 int master_pipe, u32 active_pipes);
135 * DISPLAY_MODE describes how many display been enabled, and which will be
136 * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
137 * pipeline resources assignment according to this usage hint.
138 * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
139 * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
140 * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
141 * And D71 supports assign two pipelines to one single display on mode
142 * KOMEDA_MODE_DISP0/DISP1
145 KOMEDA_MODE_INACTIVE = 0,
146 KOMEDA_MODE_DISP0 = BIT(0),
147 KOMEDA_MODE_DISP1 = BIT(1),
148 KOMEDA_MODE_DUAL_DISP = KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1,
154 * Pipeline and component are used to describe how to handle the pixel data.
155 * komeda_device is for describing the whole view of the device, and the
156 * control-abilites of device.
159 /** @dev: the base device structure */
161 /** @reg_base: the base address of komeda io space */
162 u32 __iomem *reg_base;
163 /** @dma_parms: the dma parameters of komeda */
164 struct device_dma_parameters dma_parms;
166 /** @chip: the basic chip information */
167 struct komeda_chip_info chip;
168 /** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
169 struct komeda_format_caps_table fmt_tbl;
170 /** @aclk: HW main engine clk */
173 /** @irq: irq number */
176 /** @lock: used to protect dpmode */
178 /** @dpmode: current display mode */
181 /** @n_pipelines: the number of pipe in @pipelines */
183 /** @pipelines: the komeda pipelines */
184 struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
186 /** @funcs: chip funcs to access to HW */
187 const struct komeda_dev_funcs *funcs;
191 * chip data will be added by &komeda_dev_funcs.enum_resources() and
192 * destroyed by &komeda_dev_funcs.cleanup()
196 /** @iommu: iommu domain */
197 struct iommu_domain *iommu;
199 /** @debugfs_root: root directory of komeda debugfs */
200 struct dentry *debugfs_root;
202 * @err_verbosity: bitmask for how much extra info to print on error
204 * See KOMEDA_DEV_* macros for details. Low byte contains the debug
205 * level categories, the high byte contains extra debug options.
208 /* Print a single line per error per frame with error events. */
209 #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0)
210 /* Print a single line per warning per frame with error events. */
211 #define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1)
212 /* Print a single line per info event per frame with error events. */
213 #define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2)
214 /* Dump DRM state on an error or warning event. */
215 #define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8)
216 /* Disable rate limiting of event prints (normally one per commit) */
217 #define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12)
221 komeda_product_match(struct komeda_dev *mdev, u32 target)
223 return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;
226 typedef const struct komeda_dev_funcs *
227 (*komeda_identify_func)(u32 __iomem *reg, struct komeda_chip_info *chip);
229 const struct komeda_dev_funcs *
230 d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip);
232 struct komeda_dev *komeda_dev_create(struct device *dev);
233 void komeda_dev_destroy(struct komeda_dev *mdev);
235 struct komeda_dev *dev_to_mdev(struct device *dev);
237 void komeda_print_events(struct komeda_events *evts, struct drm_device *dev);
239 int komeda_dev_resume(struct komeda_dev *mdev);
240 int komeda_dev_suspend(struct komeda_dev *mdev);
242 #endif /*_KOMEDA_DEV_H_*/