1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
4 * Author: James.Qian.Wang <james.qian.wang@arm.com>
10 #include <linux/device.h>
11 #include <linux/clk.h>
12 #include "komeda_pipeline.h"
13 #include "malidp_product.h"
14 #include "komeda_format_caps.h"
16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
24 #define KOMEDA_ERR_TETO BIT_ULL(14)
25 #define KOMEDA_ERR_TEMR BIT_ULL(15)
26 #define KOMEDA_ERR_TITR BIT_ULL(16)
27 #define KOMEDA_ERR_CPE BIT_ULL(17)
28 #define KOMEDA_ERR_CFGE BIT_ULL(18)
29 #define KOMEDA_ERR_AXIE BIT_ULL(19)
30 #define KOMEDA_ERR_ACE0 BIT_ULL(20)
31 #define KOMEDA_ERR_ACE1 BIT_ULL(21)
32 #define KOMEDA_ERR_ACE2 BIT_ULL(22)
33 #define KOMEDA_ERR_ACE3 BIT_ULL(23)
34 #define KOMEDA_ERR_DRIFTTO BIT_ULL(24)
35 #define KOMEDA_ERR_FRAMETO BIT_ULL(25)
36 #define KOMEDA_ERR_CSCE BIT_ULL(26)
37 #define KOMEDA_ERR_ZME BIT_ULL(27)
38 #define KOMEDA_ERR_MERR BIT_ULL(28)
39 #define KOMEDA_ERR_TCF BIT_ULL(29)
40 #define KOMEDA_ERR_TTNG BIT_ULL(30)
41 #define KOMEDA_ERR_TTF BIT_ULL(31)
43 #define KOMEDA_ERR_EVENTS \
44 (KOMEDA_EVENT_URUN | KOMEDA_EVENT_IBSY | KOMEDA_EVENT_OVR |\
45 KOMEDA_ERR_TETO | KOMEDA_ERR_TEMR | KOMEDA_ERR_TITR |\
46 KOMEDA_ERR_CPE | KOMEDA_ERR_CFGE | KOMEDA_ERR_AXIE |\
47 KOMEDA_ERR_ACE0 | KOMEDA_ERR_ACE1 | KOMEDA_ERR_ACE2 |\
48 KOMEDA_ERR_ACE3 | KOMEDA_ERR_DRIFTTO | KOMEDA_ERR_FRAMETO |\
49 KOMEDA_ERR_ZME | KOMEDA_ERR_MERR | KOMEDA_ERR_TCF |\
50 KOMEDA_ERR_TTNG | KOMEDA_ERR_TTF)
52 #define KOMEDA_WARN_EVENTS KOMEDA_ERR_CSCE
54 /* malidp device id */
59 /* pipeline DT ports */
61 KOMEDA_OF_PORT_OUTPUT = 0,
62 KOMEDA_OF_PORT_COPROC = 1,
65 struct komeda_chip_info {
72 struct komeda_product_data {
74 const struct komeda_dev_funcs *(*identify)(u32 __iomem *reg,
75 struct komeda_chip_info *info);
80 struct komeda_events {
82 u64 pipes[KOMEDA_MAX_PIPELINES];
86 * struct komeda_dev_funcs
88 * Supplied by chip level and returned by the chip entry function xxx_identify,
90 struct komeda_dev_funcs {
94 * initialize &komeda_dev->format_table, this function should be called
95 * before the &enum_resource
97 void (*init_format_table)(struct komeda_dev *mdev);
101 * for CHIP to report or add pipeline and component resources to CORE
103 int (*enum_resources)(struct komeda_dev *mdev);
104 /** @cleanup: call to chip to cleanup komeda_dev->chip data */
105 void (*cleanup)(struct komeda_dev *mdev);
106 /** @connect_iommu: Optional, connect to external iommu */
107 int (*connect_iommu)(struct komeda_dev *mdev);
108 /** @disconnect_iommu: Optional, disconnect to external iommu */
109 int (*disconnect_iommu)(struct komeda_dev *mdev);
113 * for CORE to get the HW event from the CHIP when interrupt happened.
115 irqreturn_t (*irq_handler)(struct komeda_dev *mdev,
116 struct komeda_events *events);
117 /** @enable_irq: enable irq */
118 int (*enable_irq)(struct komeda_dev *mdev);
119 /** @disable_irq: disable irq */
120 int (*disable_irq)(struct komeda_dev *mdev);
121 /** @on_off_vblank: notify HW to on/off vblank */
122 void (*on_off_vblank)(struct komeda_dev *mdev,
123 int master_pipe, bool on);
125 /** @dump_register: Optional, dump registers to seq_file */
126 void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
130 * Notify HW to switch to a new display operation mode.
132 int (*change_opmode)(struct komeda_dev *mdev, int new_mode);
133 /** @flush: Notify the HW to flush or kickoff the update */
134 void (*flush)(struct komeda_dev *mdev,
135 int master_pipe, u32 active_pipes);
139 * DISPLAY_MODE describes how many display been enabled, and which will be
140 * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
141 * pipeline resources assignment according to this usage hint.
142 * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
143 * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
144 * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
145 * And D71 supports assign two pipelines to one single display on mode
146 * KOMEDA_MODE_DISP0/DISP1
149 KOMEDA_MODE_INACTIVE = 0,
150 KOMEDA_MODE_DISP0 = BIT(0),
151 KOMEDA_MODE_DISP1 = BIT(1),
152 KOMEDA_MODE_DUAL_DISP = KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1,
158 * Pipeline and component are used to describe how to handle the pixel data.
159 * komeda_device is for describing the whole view of the device, and the
160 * control-abilites of device.
163 /** @dev: the base device structure */
165 /** @reg_base: the base address of komeda io space */
166 u32 __iomem *reg_base;
167 /** @dma_parms: the dma parameters of komeda */
168 struct device_dma_parameters dma_parms;
170 /** @chip: the basic chip information */
171 struct komeda_chip_info chip;
172 /** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
173 struct komeda_format_caps_table fmt_tbl;
174 /** @aclk: HW main engine clk */
177 /** @irq: irq number */
180 /** @lock: used to protect dpmode */
182 /** @dpmode: current display mode */
185 /** @n_pipelines: the number of pipe in @pipelines */
187 /** @pipelines: the komeda pipelines */
188 struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
190 /** @funcs: chip funcs to access to HW */
191 const struct komeda_dev_funcs *funcs;
195 * chip data will be added by &komeda_dev_funcs.enum_resources() and
196 * destroyed by &komeda_dev_funcs.cleanup()
200 /** @iommu: iommu domain */
201 struct iommu_domain *iommu;
203 /** @debugfs_root: root directory of komeda debugfs */
204 struct dentry *debugfs_root;
206 * @err_verbosity: bitmask for how much extra info to print on error
208 * See KOMEDA_DEV_* macros for details.
211 /* Print a single line per error per frame with error events. */
212 #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0)
216 komeda_product_match(struct komeda_dev *mdev, u32 target)
218 return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;
221 const struct komeda_dev_funcs *
222 d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip);
224 struct komeda_dev *komeda_dev_create(struct device *dev);
225 void komeda_dev_destroy(struct komeda_dev *mdev);
227 struct komeda_dev *dev_to_mdev(struct device *dev);
229 #ifdef CONFIG_DRM_KOMEDA_ERROR_PRINT
230 void komeda_print_events(struct komeda_events *evts, struct drm_device *dev);
232 static inline void komeda_print_events(struct komeda_events *evts,
233 struct drm_device *dev)
237 int komeda_dev_resume(struct komeda_dev *mdev);
238 int komeda_dev_suspend(struct komeda_dev *mdev);
240 #endif /*_KOMEDA_DEV_H_*/