1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2016, Analogix Semiconductor.
5 * Based on anx7808 driver obtained from chromeos with copyright:
6 * Copyright(c) 2013, Google Inc.
8 #ifndef _ANALOGIX_I2C_DPTX_H_
9 #define _ANALOGIX_I2C_DPTX_H_
11 /***************************************************************/
12 /* Register definitions for TX_P0 */
13 /***************************************************************/
15 /* HDCP Status Register */
16 #define SP_TX_HDCP_STATUS_REG 0x00
17 #define SP_AUTH_FAIL BIT(5)
18 #define SP_AUTHEN_PASS BIT(1)
20 /* HDCP Control Register 0 */
21 #define SP_HDCP_CTRL0_REG 0x01
22 #define SP_RX_REPEATER BIT(6)
23 #define SP_RE_AUTH BIT(5)
24 #define SP_SW_AUTH_OK BIT(4)
25 #define SP_HARD_AUTH_EN BIT(3)
26 #define SP_HDCP_ENC_EN BIT(2)
27 #define SP_BKSV_SRM_PASS BIT(1)
28 #define SP_KSVLIST_VLD BIT(0)
29 /* HDCP Function Enabled */
30 #define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3))
32 /* HDCP Receiver BSTATUS Register 0 */
33 #define SP_HDCP_RX_BSTATUS0_REG 0x1b
34 /* HDCP Receiver BSTATUS Register 1 */
35 #define SP_HDCP_RX_BSTATUS1_REG 0x1c
37 /* HDCP Embedded "Blue Screen" Content Registers */
38 #define SP_HDCP_VID0_BLUE_SCREEN_REG 0x2c
39 #define SP_HDCP_VID1_BLUE_SCREEN_REG 0x2d
40 #define SP_HDCP_VID2_BLUE_SCREEN_REG 0x2e
42 /* HDCP Wait R0 Timing Register */
43 #define SP_HDCP_WAIT_R0_TIME_REG 0x40
45 /* HDCP Link Integrity Check Timer Register */
46 #define SP_HDCP_LINK_CHECK_TIMER_REG 0x41
48 /* HDCP Repeater Ready Wait Timer Register */
49 #define SP_HDCP_RPTR_RDY_WAIT_TIME_REG 0x42
51 /* HDCP Auto Timer Register */
52 #define SP_HDCP_AUTO_TIMER_REG 0x51
54 /* HDCP Key Status Register */
55 #define SP_HDCP_KEY_STATUS_REG 0x5e
57 /* HDCP Key Command Register */
58 #define SP_HDCP_KEY_COMMAND_REG 0x5f
59 #define SP_DISABLE_SYNC_HDCP BIT(2)
61 /* OTP Memory Key Protection Registers */
62 #define SP_OTP_KEY_PROTECT1_REG 0x60
63 #define SP_OTP_KEY_PROTECT2_REG 0x61
64 #define SP_OTP_KEY_PROTECT3_REG 0x62
65 #define SP_OTP_PSW1 0xa2
66 #define SP_OTP_PSW2 0x7e
67 #define SP_OTP_PSW3 0xc6
69 /* DP System Control Registers */
70 #define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1)
71 /* Bits for DP System Control Register 2 */
72 #define SP_CHA_STA BIT(2)
73 /* Bits for DP System Control Register 3 */
74 #define SP_HPD_STATUS BIT(6)
75 #define SP_STRM_VALID BIT(2)
76 /* Bits for DP System Control Register 4 */
77 #define SP_ENHANCED_MODE BIT(3)
79 /* DP Video Control Register */
80 #define SP_DP_VIDEO_CTRL_REG 0x84
81 #define SP_COLOR_F_MASK 0x06
82 #define SP_COLOR_F_SHIFT 1
83 #define SP_BPC_MASK 0xe0
84 #define SP_BPC_SHIFT 5
85 # define SP_BPC_6BITS 0x00
86 # define SP_BPC_8BITS 0x01
87 # define SP_BPC_10BITS 0x02
88 # define SP_BPC_12BITS 0x03
90 /* DP Audio Control Register */
91 #define SP_DP_AUDIO_CTRL_REG 0x87
92 #define SP_AUD_EN BIT(0)
94 /* 10us Pulse Generate Timer Registers */
95 #define SP_I2C_GEN_10US_TIMER0_REG 0x88
96 #define SP_I2C_GEN_10US_TIMER1_REG 0x89
98 /* Packet Send Control Register */
99 #define SP_PACKET_SEND_CTRL_REG 0x90
100 #define SP_AUD_IF_UP BIT(7)
101 #define SP_AVI_IF_UD BIT(6)
102 #define SP_MPEG_IF_UD BIT(5)
103 #define SP_SPD_IF_UD BIT(4)
104 #define SP_AUD_IF_EN BIT(3)
105 #define SP_AVI_IF_EN BIT(2)
106 #define SP_MPEG_IF_EN BIT(1)
107 #define SP_SPD_IF_EN BIT(0)
109 /* DP HDCP Control Register */
110 #define SP_DP_HDCP_CTRL_REG 0x92
111 #define SP_AUTO_EN BIT(7)
112 #define SP_AUTO_START BIT(5)
113 #define SP_LINK_POLLING BIT(1)
115 /* DP Main Link Bandwidth Setting Register */
116 #define SP_DP_MAIN_LINK_BW_SET_REG 0xa0
117 #define SP_LINK_BW_SET_MASK 0x1f
118 #define SP_INITIAL_SLIM_M_AUD_SEL BIT(5)
120 /* DP Training Pattern Set Register */
121 #define SP_DP_TRAINING_PATTERN_SET_REG 0xa2
123 /* DP Lane 0 Link Training Control Register */
124 #define SP_DP_LANE0_LT_CTRL_REG 0xa3
125 #define SP_TX_SW_SET_MASK 0x1b
126 #define SP_MAX_PRE_REACH BIT(5)
127 #define SP_MAX_DRIVE_REACH BIT(4)
128 #define SP_PRE_EMP_LEVEL1 BIT(3)
129 #define SP_DRVIE_CURRENT_LEVEL1 BIT(0)
131 /* DP Link Training Control Register */
132 #define SP_DP_LT_CTRL_REG 0xa8
133 #define SP_LT_ERROR_TYPE_MASK 0x70
134 # define SP_LT_NO_ERROR 0x00
135 # define SP_LT_AUX_WRITE_ERROR 0x01
136 # define SP_LT_MAX_DRIVE_REACHED 0x02
137 # define SP_LT_WRONG_LANE_COUNT_SET 0x03
138 # define SP_LT_LOOP_SAME_5_TIME 0x04
139 # define SP_LT_CR_FAIL_IN_EQ 0x05
140 # define SP_LT_EQ_LOOP_5_TIME 0x06
141 #define SP_LT_EN BIT(0)
143 /* DP CEP Training Control Registers */
144 #define SP_DP_CEP_TRAINING_CTRL0_REG 0xa9
145 #define SP_DP_CEP_TRAINING_CTRL1_REG 0xaa
147 /* DP Debug Register 1 */
148 #define SP_DP_DEBUG1_REG 0xb0
149 #define SP_DEBUG_PLL_LOCK BIT(4)
150 #define SP_POLLING_EN BIT(1)
152 /* DP Polling Control Register */
153 #define SP_DP_POLLING_CTRL_REG 0xb4
154 #define SP_AUTO_POLLING_DISABLE BIT(0)
156 /* DP Link Debug Control Register */
157 #define SP_DP_LINK_DEBUG_CTRL_REG 0xb8
158 #define SP_M_VID_DEBUG BIT(5)
159 #define SP_NEW_PRBS7 BIT(4)
160 #define SP_INSERT_ER BIT(1)
161 #define SP_PRBS31_EN BIT(0)
163 /* AUX Misc control Register */
164 #define SP_AUX_MISC_CTRL_REG 0xbf
166 /* DP PLL control Register */
167 #define SP_DP_PLL_CTRL_REG 0xc7
168 #define SP_PLL_RST BIT(6)
170 /* DP Analog Power Down Register */
171 #define SP_DP_ANALOG_POWER_DOWN_REG 0xc8
172 #define SP_CH0_PD BIT(0)
174 /* DP Misc Control Register */
175 #define SP_DP_MISC_CTRL_REG 0xcd
176 #define SP_EQ_TRAINING_LOOP BIT(6)
178 /* DP Extra I2C Device Address Register */
179 #define SP_DP_EXTRA_I2C_DEV_ADDR_REG 0xce
180 #define SP_I2C_STRETCH_DISABLE BIT(7)
182 #define SP_I2C_EXTRA_ADDR 0x50
184 /* DP Downspread Control Register 1 */
185 #define SP_DP_DOWNSPREAD_CTRL1_REG 0xd0
187 /* DP M Value Calculation Control Register */
188 #define SP_DP_M_CALCULATION_CTRL_REG 0xd9
189 #define SP_M_GEN_CLK_SEL BIT(0)
191 /* AUX Channel Access Status Register */
192 #define SP_AUX_CH_STATUS_REG 0xe0
193 #define SP_AUX_STATUS 0x0f
195 /* AUX Channel DEFER Control Register */
196 #define SP_AUX_DEFER_CTRL_REG 0xe2
197 #define SP_DEFER_CTRL_EN BIT(7)
199 /* DP Buffer Data Count Register */
200 #define SP_BUF_DATA_COUNT_REG 0xe4
201 #define SP_BUF_DATA_COUNT_MASK 0x1f
202 #define SP_BUF_CLR BIT(7)
204 /* DP AUX Channel Control Register 1 */
205 #define SP_DP_AUX_CH_CTRL1_REG 0xe5
206 #define SP_AUX_TX_COMM_MASK 0x0f
207 #define SP_AUX_LENGTH_MASK 0xf0
208 #define SP_AUX_LENGTH_SHIFT 4
210 /* DP AUX CH Address Register 0 */
211 #define SP_AUX_ADDR_7_0_REG 0xe6
213 /* DP AUX CH Address Register 1 */
214 #define SP_AUX_ADDR_15_8_REG 0xe7
216 /* DP AUX CH Address Register 2 */
217 #define SP_AUX_ADDR_19_16_REG 0xe8
218 #define SP_AUX_ADDR_19_16_MASK 0x0f
220 /* DP AUX Channel Control Register 2 */
221 #define SP_DP_AUX_CH_CTRL2_REG 0xe9
222 #define SP_AUX_SEL_RXCM BIT(6)
223 #define SP_AUX_CHSEL BIT(3)
224 #define SP_AUX_PN_INV BIT(2)
225 #define SP_ADDR_ONLY BIT(1)
226 #define SP_AUX_EN BIT(0)
228 /* DP Video Stream Control InfoFrame Register */
229 #define SP_DP_3D_VSC_CTRL_REG 0xea
230 #define SP_INFO_FRAME_VSC_EN BIT(0)
232 /* DP Video Stream Data Byte 1 Register */
233 #define SP_DP_VSC_DB1_REG 0xeb
235 /* DP AUX Channel Control Register 3 */
236 #define SP_DP_AUX_CH_CTRL3_REG 0xec
237 #define SP_WAIT_COUNTER_7_0_MASK 0xff
239 /* DP AUX Channel Control Register 4 */
240 #define SP_DP_AUX_CH_CTRL4_REG 0xed
242 /* DP AUX Buffer Data Registers */
243 #define SP_DP_BUF_DATA0_REG 0xf0
245 ssize_t anx_dp_aux_transfer(struct regmap *map_dptx,
246 struct drm_dp_aux_msg *msg);