drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/irq.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/mutex.h>
  21 #include <linux/of_device.h>
  22 #include <linux/regmap.h>
  23 #include <linux/spinlock.h>
  24
  25 #include <drm/drm_of.h>
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_encoder_slave.h>
  30 #include <drm/drm_scdc_helper.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/bridge/dw_hdmi.h>
  33
  34 #include <uapi/linux/media-bus-format.h>
  35 #include <uapi/linux/videodev2.h>
  36
  37 #include "dw-hdmi.h"
  38 #include "dw-hdmi-audio.h"
  39 #include "dw-hdmi-cec.h"
  40
  41 #include <media/cec-notifier.h>
  42
  43 #define DDC_SEGMENT_ADDR        0x30
  44
  45 #define HDMI_EDID_LEN           512
  46
  47 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
  48 #define SCDC_MIN_SOURCE_VERSION 0x1
  49
  50 #define HDMI14_MAX_TMDSCLK      340000000
  51
  52 enum hdmi_datamap {
  53         RGB444_8B = 0x01,
  54         RGB444_10B = 0x03,
  55         RGB444_12B = 0x05,
  56         RGB444_16B = 0x07,
  57         YCbCr444_8B = 0x09,
  58         YCbCr444_10B = 0x0B,
  59         YCbCr444_12B = 0x0D,
  60         YCbCr444_16B = 0x0F,
  61         YCbCr422_8B = 0x16,
  62         YCbCr422_10B = 0x14,
  63         YCbCr422_12B = 0x12,
  64 };
  65
  66 static const u16 csc_coeff_default[3][4] = {
  67         { 0x2000, 0x0000, 0x0000, 0x0000 },
  68         { 0x0000, 0x2000, 0x0000, 0x0000 },
  69         { 0x0000, 0x0000, 0x2000, 0x0000 }
  70 };
  71
  72 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  73         { 0x2000, 0x6926, 0x74fd, 0x010e },
  74         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  75         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  76 };
  77
  78 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  79         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  80         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  81         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  82 };
  83
  84 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  85         { 0x2591, 0x1322, 0x074b, 0x0000 },
  86         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  87         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  88 };
  89
  90 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  91         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  92         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  93         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  94 };
  95
  96 struct hdmi_vmode {
  97         bool mdataenablepolarity;
  98
  99         unsigned int mpixelclock;
 100         unsigned int mpixelrepetitioninput;
 101         unsigned int mpixelrepetitionoutput;
 102         unsigned int mtmdsclock;
 103 };
 104
 105 struct hdmi_data_info {
 106         unsigned int enc_in_bus_format;
 107         unsigned int enc_out_bus_format;
 108         unsigned int enc_in_encoding;
 109         unsigned int enc_out_encoding;
 110         unsigned int pix_repet_factor;
 111         unsigned int hdcp_enable;
 112         struct hdmi_vmode video_mode;
 113 };
 114
 115 struct dw_hdmi_i2c {
 116         struct i2c_adapter      adap;
 117
 118         struct mutex            lock;   /* used to serialize data transfers */
 119         struct completion       cmp;
 120         u8                      stat;
 121
 122         u8                      slave_reg;
 123         bool                    is_regaddr;
 124         bool                    is_segment;
 125 };
 126
 127 struct dw_hdmi_phy_data {
 128         enum dw_hdmi_phy_type type;
 129         const char *name;
 130         unsigned int gen;
 131         bool has_svsret;
 132         int (*configure)(struct dw_hdmi *hdmi,
 133                          const struct dw_hdmi_plat_data *pdata,
 134                          unsigned long mpixelclock);
 135 };
 136
 137 struct dw_hdmi {
 138         struct drm_connector connector;
 139         struct drm_bridge bridge;
 140
 141         unsigned int version;
 142
 143         struct platform_device *audio;
 144         struct platform_device *cec;
 145         struct device *dev;
 146         struct clk *isfr_clk;
 147         struct clk *iahb_clk;
 148         struct clk *cec_clk;
 149         struct dw_hdmi_i2c *i2c;
 150
 151         struct hdmi_data_info hdmi_data;
 152         const struct dw_hdmi_plat_data *plat_data;
 153
 154         int vic;
 155
 156         u8 edid[HDMI_EDID_LEN];
 157
 158         struct {
 159                 const struct dw_hdmi_phy_ops *ops;
 160                 const char *name;
 161                 void *data;
 162                 bool enabled;
 163         } phy;
 164
 165         struct drm_display_mode previous_mode;
 166
 167         struct i2c_adapter *ddc;
 168         void __iomem *regs;
 169         bool sink_is_hdmi;
 170         bool sink_has_audio;
 171
 172         struct mutex mutex;             /* for state below and previous_mode */
 173         enum drm_connector_force force; /* mutex-protected force state */
 174         bool disabled;                  /* DRM has disabled our bridge */
 175         bool bridge_is_on;              /* indicates the bridge is on */
 176         bool rxsense;                   /* rxsense state */
 177         u8 phy_mask;                    /* desired phy int mask settings */
 178         u8 mc_clkdis;                   /* clock disable register */
 179
 180         spinlock_t audio_lock;
 181         struct mutex audio_mutex;
 182         unsigned int sample_rate;
 183         unsigned int audio_cts;
 184         unsigned int audio_n;
 185         bool audio_enable;
 186
 187         unsigned int reg_shift;
 188         struct regmap *regm;
 189         void (*enable_audio)(struct dw_hdmi *hdmi);
 190         void (*disable_audio)(struct dw_hdmi *hdmi);
 191
 192         struct cec_notifier *cec_notifier;
 193 };
 194
 195 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 196         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 197          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 198
 199 #define HDMI_PHY_RX_SENSE \
 200         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 201          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 202
 203 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 204 {
 205         regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
 206 }
 207
 208 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 209 {
 210         unsigned int val = 0;
 211
 212         regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
 213
 214         return val;
 215 }
 216
 217 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 218 {
 219         regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
 220 }
 221
 222 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 223                              u8 shift, u8 mask)
 224 {
 225         hdmi_modb(hdmi, data << shift, mask, reg);
 226 }
 227
 228 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 229 {
 230         /* Software reset */
 231         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 232
 233         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
 234         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
 235
 236         /* Set done, not acknowledged and arbitration interrupt polarities */
 237         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 238         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 239                     HDMI_I2CM_CTLINT);
 240
 241         /* Clear DONE and ERROR interrupts */
 242         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 243                     HDMI_IH_I2CM_STAT0);
 244
 245         /* Mute DONE and ERROR interrupts */
 246         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 247                     HDMI_IH_MUTE_I2CM_STAT0);
 248 }
 249
 250 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 251                             unsigned char *buf, unsigned int length)
 252 {
 253         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 254         int stat;
 255
 256         if (!i2c->is_regaddr) {
 257                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 258                 i2c->slave_reg = 0x00;
 259                 i2c->is_regaddr = true;
 260         }
 261
 262         while (length--) {
 263                 reinit_completion(&i2c->cmp);
 264
 265                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 266                 if (i2c->is_segment)
 267                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 268                                     HDMI_I2CM_OPERATION);
 269                 else
 270                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 271                                     HDMI_I2CM_OPERATION);
 272
 273                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 274                 if (!stat)
 275                         return -EAGAIN;
 276
 277                 /* Check for error condition on the bus */
 278                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 279                         return -EIO;
 280
 281                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 282         }
 283         i2c->is_segment = false;
 284
 285         return 0;
 286 }
 287
 288 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 289                              unsigned char *buf, unsigned int length)
 290 {
 291         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 292         int stat;
 293
 294         if (!i2c->is_regaddr) {
 295                 /* Use the first write byte as register address */
 296                 i2c->slave_reg = buf[0];
 297                 length--;
 298                 buf++;
 299                 i2c->is_regaddr = true;
 300         }
 301
 302         while (length--) {
 303                 reinit_completion(&i2c->cmp);
 304
 305                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 306                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 307                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 308                             HDMI_I2CM_OPERATION);
 309
 310                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 311                 if (!stat)
 312                         return -EAGAIN;
 313
 314                 /* Check for error condition on the bus */
 315                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 316                         return -EIO;
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 323                             struct i2c_msg *msgs, int num)
 324 {
 325         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 326         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 327         u8 addr = msgs[0].addr;
 328         int i, ret = 0;
 329
 330         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 331
 332         for (i = 0; i < num; i++) {
 333                 if (msgs[i].len == 0) {
 334                         dev_dbg(hdmi->dev,
 335                                 "unsupported transfer %d/%d, no data\n",
 336                                 i + 1, num);
 337                         return -EOPNOTSUPP;
 338                 }
 339         }
 340
 341         mutex_lock(&i2c->lock);
 342
 343         /* Unmute DONE and ERROR interrupts */
 344         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 345
 346         /* Set slave device address taken from the first I2C message */
 347         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 348
 349         /* Set slave device register address on transfer */
 350         i2c->is_regaddr = false;
 351
 352         /* Set segment pointer for I2C extended read mode operation */
 353         i2c->is_segment = false;
 354
 355         for (i = 0; i < num; i++) {
 356                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 357                         i + 1, num, msgs[i].len, msgs[i].flags);
 358                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 359                         i2c->is_segment = true;
 360                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 361                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 362                 } else {
 363                         if (msgs[i].flags & I2C_M_RD)
 364                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 365                                                        msgs[i].len);
 366                         else
 367                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 368                                                         msgs[i].len);
 369                 }
 370                 if (ret < 0)
 371                         break;
 372         }
 373
 374         if (!ret)
 375                 ret = num;
 376
 377         /* Mute DONE and ERROR interrupts */
 378         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 379                     HDMI_IH_MUTE_I2CM_STAT0);
 380
 381         mutex_unlock(&i2c->lock);
 382
 383         return ret;
 384 }
 385
 386 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 387 {
 388         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 389 }
 390
 391 static const struct i2c_algorithm dw_hdmi_algorithm = {
 392         .master_xfer    = dw_hdmi_i2c_xfer,
 393         .functionality  = dw_hdmi_i2c_func,
 394 };
 395
 396 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 397 {
 398         struct i2c_adapter *adap;
 399         struct dw_hdmi_i2c *i2c;
 400         int ret;
 401
 402         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 403         if (!i2c)
 404                 return ERR_PTR(-ENOMEM);
 405
 406         mutex_init(&i2c->lock);
 407         init_completion(&i2c->cmp);
 408
 409         adap = &i2c->adap;
 410         adap->class = I2C_CLASS_DDC;
 411         adap->owner = THIS_MODULE;
 412         adap->dev.parent = hdmi->dev;
 413         adap->algo = &dw_hdmi_algorithm;
 414         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 415         i2c_set_adapdata(adap, hdmi);
 416
 417         ret = i2c_add_adapter(adap);
 418         if (ret) {
 419                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 420                 devm_kfree(hdmi->dev, i2c);
 421                 return ERR_PTR(ret);
 422         }
 423
 424         hdmi->i2c = i2c;
 425
 426         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 427
 428         return adap;
 429 }
 430
 431 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 432                            unsigned int n)
 433 {
 434         /* Must be set/cleared first */
 435         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 436
 437         /* nshift factor = 0 */
 438         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 439
 440         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 441                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 442         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 443         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 444
 445         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 446         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 447         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 448 }
 449
 450 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 451 {
 452         unsigned int n = (128 * freq) / 1000;
 453         unsigned int mult = 1;
 454
 455         while (freq > 48000) {
 456                 mult *= 2;
 457                 freq /= 2;
 458         }
 459
 460         switch (freq) {
 461         case 32000:
 462                 if (pixel_clk == 25175000)
 463                         n = 4576;
 464                 else if (pixel_clk == 27027000)
 465                         n = 4096;
 466                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 467                         n = 11648;
 468                 else
 469                         n = 4096;
 470                 n *= mult;
 471                 break;
 472
 473         case 44100:
 474                 if (pixel_clk == 25175000)
 475                         n = 7007;
 476                 else if (pixel_clk == 74176000)
 477                         n = 17836;
 478                 else if (pixel_clk == 148352000)
 479                         n = 8918;
 480                 else
 481                         n = 6272;
 482                 n *= mult;
 483                 break;
 484
 485         case 48000:
 486                 if (pixel_clk == 25175000)
 487                         n = 6864;
 488                 else if (pixel_clk == 27027000)
 489                         n = 6144;
 490                 else if (pixel_clk == 74176000)
 491                         n = 11648;
 492                 else if (pixel_clk == 148352000)
 493                         n = 5824;
 494                 else
 495                         n = 6144;
 496                 n *= mult;
 497                 break;
 498
 499         default:
 500                 break;
 501         }
 502
 503         return n;
 504 }
 505
 506 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 507         unsigned long pixel_clk, unsigned int sample_rate)
 508 {
 509         unsigned long ftdms = pixel_clk;
 510         unsigned int n, cts;
 511         u64 tmp;
 512
 513         n = hdmi_compute_n(sample_rate, pixel_clk);
 514
 515         /*
 516          * Compute the CTS value from the N value.  Note that CTS and N
 517          * can be up to 20 bits in total, so we need 64-bit math.  Also
 518          * note that our TDMS clock is not fully accurate; it is accurate
 519          * to kHz.  This can introduce an unnecessary remainder in the
 520          * calculation below, so we don't try to warn about that.
 521          */
 522         tmp = (u64)ftdms * n;
 523         do_div(tmp, 128 * sample_rate);
 524         cts = tmp;
 525
 526         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 527                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 528                 n, cts);
 529
 530         spin_lock_irq(&hdmi->audio_lock);
 531         hdmi->audio_n = n;
 532         hdmi->audio_cts = cts;
 533         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 534         spin_unlock_irq(&hdmi->audio_lock);
 535 }
 536
 537 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 538 {
 539         mutex_lock(&hdmi->audio_mutex);
 540         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 541         mutex_unlock(&hdmi->audio_mutex);
 542 }
 543
 544 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 545 {
 546         mutex_lock(&hdmi->audio_mutex);
 547         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
 548                                  hdmi->sample_rate);
 549         mutex_unlock(&hdmi->audio_mutex);
 550 }
 551
 552 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 553 {
 554         mutex_lock(&hdmi->audio_mutex);
 555         hdmi->sample_rate = rate;
 556         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
 557                                  hdmi->sample_rate);
 558         mutex_unlock(&hdmi->audio_mutex);
 559 }
 560 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 561
 562 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
 563 {
 564         if (enable)
 565                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 566         else
 567                 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 568         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
 569 }
 570
 571 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
 572 {
 573         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 574 }
 575
 576 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
 577 {
 578         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 579 }
 580
 581 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
 582 {
 583         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 584         hdmi_enable_audio_clk(hdmi, true);
 585 }
 586
 587 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
 588 {
 589         hdmi_enable_audio_clk(hdmi, false);
 590 }
 591
 592 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 593 {
 594         unsigned long flags;
 595
 596         spin_lock_irqsave(&hdmi->audio_lock, flags);
 597         hdmi->audio_enable = true;
 598         if (hdmi->enable_audio)
 599                 hdmi->enable_audio(hdmi);
 600         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 601 }
 602 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 603
 604 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 605 {
 606         unsigned long flags;
 607
 608         spin_lock_irqsave(&hdmi->audio_lock, flags);
 609         hdmi->audio_enable = false;
 610         if (hdmi->disable_audio)
 611                 hdmi->disable_audio(hdmi);
 612         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 613 }
 614 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 615
 616 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
 617 {
 618         switch (bus_format) {
 619         case MEDIA_BUS_FMT_RGB888_1X24:
 620         case MEDIA_BUS_FMT_RGB101010_1X30:
 621         case MEDIA_BUS_FMT_RGB121212_1X36:
 622         case MEDIA_BUS_FMT_RGB161616_1X48:
 623                 return true;
 624
 625         default:
 626                 return false;
 627         }
 628 }
 629
 630 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
 631 {
 632         switch (bus_format) {
 633         case MEDIA_BUS_FMT_YUV8_1X24:
 634         case MEDIA_BUS_FMT_YUV10_1X30:
 635         case MEDIA_BUS_FMT_YUV12_1X36:
 636         case MEDIA_BUS_FMT_YUV16_1X48:
 637                 return true;
 638
 639         default:
 640                 return false;
 641         }
 642 }
 643
 644 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
 645 {
 646         switch (bus_format) {
 647         case MEDIA_BUS_FMT_UYVY8_1X16:
 648         case MEDIA_BUS_FMT_UYVY10_1X20:
 649         case MEDIA_BUS_FMT_UYVY12_1X24:
 650                 return true;
 651
 652         default:
 653                 return false;
 654         }
 655 }
 656
 657 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
 658 {
 659         switch (bus_format) {
 660         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 661         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 662         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 663         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 664                 return true;
 665
 666         default:
 667                 return false;
 668         }
 669 }
 670
 671 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
 672 {
 673         switch (bus_format) {
 674         case MEDIA_BUS_FMT_RGB888_1X24:
 675         case MEDIA_BUS_FMT_YUV8_1X24:
 676         case MEDIA_BUS_FMT_UYVY8_1X16:
 677         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 678                 return 8;
 679
 680         case MEDIA_BUS_FMT_RGB101010_1X30:
 681         case MEDIA_BUS_FMT_YUV10_1X30:
 682         case MEDIA_BUS_FMT_UYVY10_1X20:
 683         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 684                 return 10;
 685
 686         case MEDIA_BUS_FMT_RGB121212_1X36:
 687         case MEDIA_BUS_FMT_YUV12_1X36:
 688         case MEDIA_BUS_FMT_UYVY12_1X24:
 689         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 690                 return 12;
 691
 692         case MEDIA_BUS_FMT_RGB161616_1X48:
 693         case MEDIA_BUS_FMT_YUV16_1X48:
 694         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 695                 return 16;
 696
 697         default:
 698                 return 0;
 699         }
 700 }
 701
 702 /*
 703  * this submodule is responsible for the video data synchronization.
 704  * for example, for RGB 4:4:4 input, the data map is defined as
 705  *                      pin{47~40} <==> R[7:0]
 706  *                      pin{31~24} <==> G[7:0]
 707  *                      pin{15~8}  <==> B[7:0]
 708  */
 709 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 710 {
 711         int color_format = 0;
 712         u8 val;
 713
 714         switch (hdmi->hdmi_data.enc_in_bus_format) {
 715         case MEDIA_BUS_FMT_RGB888_1X24:
 716                 color_format = 0x01;
 717                 break;
 718         case MEDIA_BUS_FMT_RGB101010_1X30:
 719                 color_format = 0x03;
 720                 break;
 721         case MEDIA_BUS_FMT_RGB121212_1X36:
 722                 color_format = 0x05;
 723                 break;
 724         case MEDIA_BUS_FMT_RGB161616_1X48:
 725                 color_format = 0x07;
 726                 break;
 727
 728         case MEDIA_BUS_FMT_YUV8_1X24:
 729         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 730                 color_format = 0x09;
 731                 break;
 732         case MEDIA_BUS_FMT_YUV10_1X30:
 733         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 734                 color_format = 0x0B;
 735                 break;
 736         case MEDIA_BUS_FMT_YUV12_1X36:
 737         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 738                 color_format = 0x0D;
 739                 break;
 740         case MEDIA_BUS_FMT_YUV16_1X48:
 741         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 742                 color_format = 0x0F;
 743                 break;
 744
 745         case MEDIA_BUS_FMT_UYVY8_1X16:
 746                 color_format = 0x16;
 747                 break;
 748         case MEDIA_BUS_FMT_UYVY10_1X20:
 749                 color_format = 0x14;
 750                 break;
 751         case MEDIA_BUS_FMT_UYVY12_1X24:
 752                 color_format = 0x12;
 753                 break;
 754
 755         default:
 756                 return;
 757         }
 758
 759         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 760                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 761                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 762         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 763
 764         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 765         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 766                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 767                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 768         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 769         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 770         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 771         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 772         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 773         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 774         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 775 }
 776
 777 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 778 {
 779         return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
 780 }
 781
 782 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 783 {
 784         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
 785                 return 0;
 786
 787         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
 788             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
 789                 return 1;
 790
 791         return 0;
 792 }
 793
 794 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 795 {
 796         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
 797                 return 0;
 798
 799         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 800             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
 801                 return 1;
 802
 803         return 0;
 804 }
 805
 806 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 807 {
 808         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 809         unsigned i;
 810         u32 csc_scale = 1;
 811
 812         if (is_color_space_conversion(hdmi)) {
 813                 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
 814                         if (hdmi->hdmi_data.enc_out_encoding ==
 815                                                 V4L2_YCBCR_ENC_601)
 816                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 817                         else
 818                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 819                 } else if (hdmi_bus_fmt_is_rgb(
 820                                         hdmi->hdmi_data.enc_in_bus_format)) {
 821                         if (hdmi->hdmi_data.enc_out_encoding ==
 822                                                 V4L2_YCBCR_ENC_601)
 823                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 824                         else
 825                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 826                         csc_scale = 0;
 827                 }
 828         }
 829
 830         /* The CSC registers are sequential, alternating MSB then LSB */
 831         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 832                 u16 coeff_a = (*csc_coeff)[0][i];
 833                 u16 coeff_b = (*csc_coeff)[1][i];
 834                 u16 coeff_c = (*csc_coeff)[2][i];
 835
 836                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 837                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 838                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 839                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 840                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 841                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 842         }
 843
 844         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 845                   HDMI_CSC_SCALE);
 846 }
 847
 848 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 849 {
 850         int color_depth = 0;
 851         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 852         int decimation = 0;
 853
 854         /* YCC422 interpolation to 444 mode */
 855         if (is_color_space_interpolation(hdmi))
 856                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 857         else if (is_color_space_decimation(hdmi))
 858                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 859
 860         switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
 861         case 8:
 862                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 863                 break;
 864         case 10:
 865                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 866                 break;
 867         case 12:
 868                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 869                 break;
 870         case 16:
 871                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 872                 break;
 873
 874         default:
 875                 return;
 876         }
 877
 878         /* Configure the CSC registers */
 879         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 880         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 881                   HDMI_CSC_SCALE);
 882
 883         dw_hdmi_update_csc_coeffs(hdmi);
 884 }
 885
 886 /*
 887  * HDMI video packetizer is used to packetize the data.
 888  * for example, if input is YCC422 mode or repeater is used,
 889  * data should be repacked this module can be bypassed.
 890  */
 891 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 892 {
 893         unsigned int color_depth = 0;
 894         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 895         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 896         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 897         u8 val, vp_conf;
 898
 899         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 900             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
 901             hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
 902                 switch (hdmi_bus_fmt_color_depth(
 903                                         hdmi->hdmi_data.enc_out_bus_format)) {
 904                 case 8:
 905                         color_depth = 4;
 906                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 907                         break;
 908                 case 10:
 909                         color_depth = 5;
 910                         break;
 911                 case 12:
 912                         color_depth = 6;
 913                         break;
 914                 case 16:
 915                         color_depth = 7;
 916                         break;
 917                 default:
 918                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 919                 }
 920         } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
 921                 switch (hdmi_bus_fmt_color_depth(
 922                                         hdmi->hdmi_data.enc_out_bus_format)) {
 923                 case 0:
 924                 case 8:
 925                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 926                         break;
 927                 case 10:
 928                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 929                         break;
 930                 case 12:
 931                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 932                         break;
 933
 934                 default:
 935                         return;
 936                 }
 937                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 938         } else {
 939                 return;
 940         }
 941
 942         /* set the packetizer registers */
 943         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 944                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 945                 ((hdmi_data->pix_repet_factor <<
 946                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 947                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 948         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 949
 950         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 951                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 952
 953         /* Data from pixel repeater block */
 954         if (hdmi_data->pix_repet_factor > 1) {
 955                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 956                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 957         } else { /* data from packetizer block */
 958                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 959                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 960         }
 961
 962         hdmi_modb(hdmi, vp_conf,
 963                   HDMI_VP_CONF_PR_EN_MASK |
 964                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 965
 966         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 967                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 968
 969         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 970
 971         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 972                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 973                           HDMI_VP_CONF_PP_EN_ENABLE |
 974                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 975         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 976                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 977                           HDMI_VP_CONF_PP_EN_DISABLE |
 978                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 979         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 980                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 981                           HDMI_VP_CONF_PP_EN_DISABLE |
 982                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 983         } else {
 984                 return;
 985         }
 986
 987         hdmi_modb(hdmi, vp_conf,
 988                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 989                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 990
 991         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 992                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 993                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 994                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 995
 996         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 997                   HDMI_VP_CONF);
 998 }
 999
1000 /* -----------------------------------------------------------------------------
1001  * Synopsys PHY Handling
1002  */
1003
1004 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1005                                        unsigned char bit)
1006 {
1007         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1008                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1009 }
1010
1011 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1012 {
1013         u32 val;
1014
1015         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1016                 if (msec-- == 0)
1017                         return false;
1018                 udelay(1000);
1019         }
1020         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1021
1022         return true;
1023 }
1024
1025 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1026                            unsigned char addr)
1027 {
1028         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1029         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1030         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1031                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1032         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1033                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1034         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1035                     HDMI_PHY_I2CM_OPERATION_ADDR);
1036         hdmi_phy_wait_i2c_done(hdmi, 1000);
1037 }
1038 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1039
1040 /*
1041  * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1042  * - The Source shall suspend transmission of the TMDS clock and data
1043  * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1044  * from a 0 to a 1 or from a 1 to a 0
1045  * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1046  * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1047  * transmission of TMDS clock and data
1048  *
1049  * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1050  * helper should called right before enabling the TMDS Clock and Data in
1051  * the PHY configuration callback.
1052  */
1053 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1054 {
1055         unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1056
1057         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1058         if (hdmi->connector.display_info.hdmi.scdc.supported) {
1059                 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1060                         drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1061                 else
1062                         drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1063         }
1064 }
1065 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1066
1067 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1068 {
1069         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1070                          HDMI_PHY_CONF0_PDZ_OFFSET,
1071                          HDMI_PHY_CONF0_PDZ_MASK);
1072 }
1073
1074 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1075 {
1076         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1077                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1078                          HDMI_PHY_CONF0_ENTMDS_MASK);
1079 }
1080
1081 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1082 {
1083         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1084                          HDMI_PHY_CONF0_SVSRET_OFFSET,
1085                          HDMI_PHY_CONF0_SVSRET_MASK);
1086 }
1087
1088 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1089 {
1090         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1091                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1092                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1093 }
1094 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1095
1096 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1097 {
1098         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1099                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1100                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1101 }
1102 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1103
1104 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1105 {
1106         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1107                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1108                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1109 }
1110
1111 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1112 {
1113         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1114                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1115                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1116 }
1117
1118 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1119 {
1120         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1121         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1122         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1123 }
1124 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1125
1126 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1127 {
1128         hdmi_phy_test_clear(hdmi, 1);
1129         hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1130         hdmi_phy_test_clear(hdmi, 0);
1131 }
1132 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1133
1134 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1135 {
1136         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1137         unsigned int i;
1138         u16 val;
1139
1140         if (phy->gen == 1) {
1141                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1142                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1143                 return;
1144         }
1145
1146         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1147
1148         /*
1149          * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1150          * to low power mode.
1151          */
1152         for (i = 0; i < 5; ++i) {
1153                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1154                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1155                         break;
1156
1157                 usleep_range(1000, 2000);
1158         }
1159
1160         if (val & HDMI_PHY_TX_PHY_LOCK)
1161                 dev_warn(hdmi->dev, "PHY failed to power down\n");
1162         else
1163                 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1164
1165         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1166 }
1167
1168 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1169 {
1170         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1171         unsigned int i;
1172         u8 val;
1173
1174         if (phy->gen == 1) {
1175                 dw_hdmi_phy_enable_powerdown(hdmi, false);
1176
1177                 /* Toggle TMDS enable. */
1178                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1179                 dw_hdmi_phy_enable_tmds(hdmi, 1);
1180                 return 0;
1181         }
1182
1183         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1184         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1185
1186         /* Wait for PHY PLL lock */
1187         for (i = 0; i < 5; ++i) {
1188                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1189                 if (val)
1190                         break;
1191
1192                 usleep_range(1000, 2000);
1193         }
1194
1195         if (!val) {
1196                 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1197                 return -ETIMEDOUT;
1198         }
1199
1200         dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1201         return 0;
1202 }
1203
1204 /*
1205  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1206  * information the DWC MHL PHY has the same register layout and is thus also
1207  * supported by this function.
1208  */
1209 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1210                 const struct dw_hdmi_plat_data *pdata,
1211                 unsigned long mpixelclock)
1212 {
1213         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1214         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1215         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1216
1217         /* TOFIX Will need 420 specific PHY configuration tables */
1218
1219         /* PLL/MPLL Cfg - always match on final entry */
1220         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1221                 if (mpixelclock <= mpll_config->mpixelclock)
1222                         break;
1223
1224         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1225                 if (mpixelclock <= curr_ctrl->mpixelclock)
1226                         break;
1227
1228         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1229                 if (mpixelclock <= phy_config->mpixelclock)
1230                         break;
1231
1232         if (mpll_config->mpixelclock == ~0UL ||
1233             curr_ctrl->mpixelclock == ~0UL ||
1234             phy_config->mpixelclock == ~0UL)
1235                 return -EINVAL;
1236
1237         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1238                               HDMI_3D_TX_PHY_CPCE_CTRL);
1239         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1240                               HDMI_3D_TX_PHY_GMPCTRL);
1241         dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1242                               HDMI_3D_TX_PHY_CURRCTRL);
1243
1244         dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1245         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1246                               HDMI_3D_TX_PHY_MSM_CTRL);
1247
1248         dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1249         dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1250                               HDMI_3D_TX_PHY_CKSYMTXCTRL);
1251         dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1252                               HDMI_3D_TX_PHY_VLEVCTRL);
1253
1254         /* Override and disable clock termination. */
1255         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1256                               HDMI_3D_TX_PHY_CKCALCTRL);
1257
1258         return 0;
1259 }
1260
1261 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1262 {
1263         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1264         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1265         unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1266         unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1267         int ret;
1268
1269         dw_hdmi_phy_power_off(hdmi);
1270
1271         dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1272
1273         /* Leave low power consumption mode by asserting SVSRET. */
1274         if (phy->has_svsret)
1275                 dw_hdmi_phy_enable_svsret(hdmi, 1);
1276
1277         dw_hdmi_phy_reset(hdmi);
1278
1279         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1280
1281         dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1282
1283         /* Write to the PHY as configured by the platform */
1284         if (pdata->configure_phy)
1285                 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1286         else
1287                 ret = phy->configure(hdmi, pdata, mpixelclock);
1288         if (ret) {
1289                 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1290                         mpixelclock);
1291                 return ret;
1292         }
1293
1294         /* Wait for resuming transmission of TMDS clock and data */
1295         if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1296                 msleep(100);
1297
1298         return dw_hdmi_phy_power_on(hdmi);
1299 }
1300
1301 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1302                             struct drm_display_mode *mode)
1303 {
1304         int i, ret;
1305
1306         /* HDMI Phy spec says to do the phy initialization sequence twice */
1307         for (i = 0; i < 2; i++) {
1308                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1309                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1310
1311                 ret = hdmi_phy_configure(hdmi);
1312                 if (ret)
1313                         return ret;
1314         }
1315
1316         return 0;
1317 }
1318
1319 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1320 {
1321         dw_hdmi_phy_power_off(hdmi);
1322 }
1323
1324 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1325                                                void *data)
1326 {
1327         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1328                 connector_status_connected : connector_status_disconnected;
1329 }
1330 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1331
1332 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1333                             bool force, bool disabled, bool rxsense)
1334 {
1335         u8 old_mask = hdmi->phy_mask;
1336
1337         if (force || disabled || !rxsense)
1338                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1339         else
1340                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1341
1342         if (old_mask != hdmi->phy_mask)
1343                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1344 }
1345 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1346
1347 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1348 {
1349         /*
1350          * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1351          * any pending interrupt.
1352          */
1353         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1354         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1355                     HDMI_IH_PHY_STAT0);
1356
1357         /* Enable cable hot plug irq. */
1358         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1359
1360         /* Clear and unmute interrupts. */
1361         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1362                     HDMI_IH_PHY_STAT0);
1363         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1364                     HDMI_IH_MUTE_PHY_STAT0);
1365 }
1366 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1367
1368 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1369         .init = dw_hdmi_phy_init,
1370         .disable = dw_hdmi_phy_disable,
1371         .read_hpd = dw_hdmi_phy_read_hpd,
1372         .update_hpd = dw_hdmi_phy_update_hpd,
1373         .setup_hpd = dw_hdmi_phy_setup_hpd,
1374 };
1375
1376 /* -----------------------------------------------------------------------------
1377  * HDMI TX Setup
1378  */
1379
1380 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1381 {
1382         u8 de;
1383
1384         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1385                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1386         else
1387                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1388
1389         /* disable rx detect */
1390         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1391                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1392
1393         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1394
1395         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1396                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1397 }
1398
1399 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1400 {
1401         struct hdmi_avi_infoframe frame;
1402         u8 val;
1403
1404         /* Initialise info frame from DRM mode */
1405         drm_hdmi_avi_infoframe_from_display_mode(&frame,
1406                                                  &hdmi->connector, mode);
1407
1408         if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1409                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1410         else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1411                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1412         else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1413                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1414         else
1415                 frame.colorspace = HDMI_COLORSPACE_RGB;
1416
1417         /* Set up colorimetry */
1418         switch (hdmi->hdmi_data.enc_out_encoding) {
1419         case V4L2_YCBCR_ENC_601:
1420                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1421                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1422                 else
1423                         frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1424                 frame.extended_colorimetry =
1425                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1426                 break;
1427         case V4L2_YCBCR_ENC_709:
1428                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1429                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1430                 else
1431                         frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1432                 frame.extended_colorimetry =
1433                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1434                 break;
1435         default: /* Carries no data */
1436                 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1437                 frame.extended_colorimetry =
1438                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1439                 break;
1440         }
1441
1442         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1443
1444         /*
1445          * The Designware IP uses a different byte format from standard
1446          * AVI info frames, though generally the bits are in the correct
1447          * bytes.
1448          */
1449
1450         /*
1451          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1452          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1453          * bit 6 rather than 4.
1454          */
1455         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1456         if (frame.active_aspect & 15)
1457                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1458         if (frame.top_bar || frame.bottom_bar)
1459                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1460         if (frame.left_bar || frame.right_bar)
1461                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1462         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1463
1464         /* AVI data byte 2 differences: none */
1465         val = ((frame.colorimetry & 0x3) << 6) |
1466               ((frame.picture_aspect & 0x3) << 4) |
1467               (frame.active_aspect & 0xf);
1468         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1469
1470         /* AVI data byte 3 differences: none */
1471         val = ((frame.extended_colorimetry & 0x7) << 4) |
1472               ((frame.quantization_range & 0x3) << 2) |
1473               (frame.nups & 0x3);
1474         if (frame.itc)
1475                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1476         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1477
1478         /* AVI data byte 4 differences: none */
1479         val = frame.video_code & 0x7f;
1480         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1481
1482         /* AVI Data Byte 5- set up input and output pixel repetition */
1483         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1484                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1485                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1486                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1487                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1488                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1489         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1490
1491         /*
1492          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1493          * ycc range in bits 2,3 rather than 6,7
1494          */
1495         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1496               (frame.content_type & 0x3);
1497         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1498
1499         /* AVI Data Bytes 6-13 */
1500         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1501         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1502         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1503         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1504         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1505         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1506         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1507         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1508 }
1509
1510 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1511                                                  struct drm_display_mode *mode)
1512 {
1513         struct hdmi_vendor_infoframe frame;
1514         u8 buffer[10];
1515         ssize_t err;
1516
1517         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1518                                                           &hdmi->connector,
1519                                                           mode);
1520         if (err < 0)
1521                 /*
1522                  * Going into that statement does not means vendor infoframe
1523                  * fails. It just informed us that vendor infoframe is not
1524                  * needed for the selected mode. Only 4k or stereoscopic 3D
1525                  * mode requires vendor infoframe. So just simply return.
1526                  */
1527                 return;
1528
1529         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1530         if (err < 0) {
1531                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1532                         err);
1533                 return;
1534         }
1535         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1536                         HDMI_FC_DATAUTO0_VSD_MASK);
1537
1538         /* Set the length of HDMI vendor specific InfoFrame payload */
1539         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1540
1541         /* Set 24bit IEEE Registration Identifier */
1542         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1543         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1544         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1545
1546         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1547         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1548         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1549
1550         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1551                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1552
1553         /* Packet frame interpolation */
1554         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1555
1556         /* Auto packets per frame and line spacing */
1557         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1558
1559         /* Configures the Frame Composer On RDRB mode */
1560         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1561                         HDMI_FC_DATAUTO0_VSD_MASK);
1562 }
1563
1564 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1565                              const struct drm_display_mode *mode)
1566 {
1567         u8 inv_val, bytes;
1568         struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
1569         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1570         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1571         unsigned int vdisplay, hdisplay;
1572
1573         vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000;
1574
1575         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1576
1577         if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1578                 vmode->mtmdsclock /= 2;
1579
1580         /* Set up HDMI_FC_INVIDCONF */
1581         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1582                    vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1583                    hdmi_info->scdc.scrambling.low_rates ?
1584                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1585                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1586
1587         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1588                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1589                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1590
1591         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1592                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1593                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1594
1595         inv_val |= (vmode->mdataenablepolarity ?
1596                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1597                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1598
1599         if (hdmi->vic == 39)
1600                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1601         else
1602                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1603                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1604                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1605
1606         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1607                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1608                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1609
1610         inv_val |= hdmi->sink_is_hdmi ?
1611                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1612                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1613
1614         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1615
1616         hdisplay = mode->hdisplay;
1617         hblank = mode->htotal - mode->hdisplay;
1618         h_de_hs = mode->hsync_start - mode->hdisplay;
1619         hsync_len = mode->hsync_end - mode->hsync_start;
1620
1621         /*
1622          * When we're setting a YCbCr420 mode, we need
1623          * to adjust the horizontal timing to suit.
1624          */
1625         if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1626                 hdisplay /= 2;
1627                 hblank /= 2;
1628                 h_de_hs /= 2;
1629                 hsync_len /= 2;
1630         }
1631
1632         vdisplay = mode->vdisplay;
1633         vblank = mode->vtotal - mode->vdisplay;
1634         v_de_vs = mode->vsync_start - mode->vdisplay;
1635         vsync_len = mode->vsync_end - mode->vsync_start;
1636
1637         /*
1638          * When we're setting an interlaced mode, we need
1639          * to adjust the vertical timing to suit.
1640          */
1641         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1642                 vdisplay /= 2;
1643                 vblank /= 2;
1644                 v_de_vs /= 2;
1645                 vsync_len /= 2;
1646         }
1647
1648         /* Scrambling Control */
1649         if (hdmi_info->scdc.supported) {
1650                 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1651                     hdmi_info->scdc.scrambling.low_rates) {
1652                         /*
1653                          * HDMI2.0 Specifies the following procedure:
1654                          * After the Source Device has determined that
1655                          * SCDC_Present is set (=1), the Source Device should
1656                          * write the accurate Version of the Source Device
1657                          * to the Source Version field in the SCDCS.
1658                          * Source Devices compliant shall set the
1659                          * Source Version = 1.
1660                          */
1661                         drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1662                                        &bytes);
1663                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1664                                 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1665
1666                         /* Enabled Scrambling in the Sink */
1667                         drm_scdc_set_scrambling(&hdmi->i2c->adap, 1);
1668
1669                         /*
1670                          * To activate the scrambler feature, you must ensure
1671                          * that the quasi-static configuration bit
1672                          * fc_invidconf.HDCP_keepout is set at configuration
1673                          * time, before the required mc_swrstzreq.tmdsswrst_req
1674                          * reset request is issued.
1675                          */
1676                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1677                                     HDMI_MC_SWRSTZ);
1678                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1679                 } else {
1680                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1681                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1682                                     HDMI_MC_SWRSTZ);
1683                         drm_scdc_set_scrambling(&hdmi->i2c->adap, 0);
1684                 }
1685         }
1686
1687         /* Set up horizontal active pixel width */
1688         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1689         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1690
1691         /* Set up vertical active lines */
1692         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1693         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1694
1695         /* Set up horizontal blanking pixel region width */
1696         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1697         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1698
1699         /* Set up vertical blanking pixel region width */
1700         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1701
1702         /* Set up HSYNC active edge delay width (in pixel clks) */
1703         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1704         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1705
1706         /* Set up VSYNC active edge delay (in lines) */
1707         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1708
1709         /* Set up HSYNC active pulse width (in pixel clks) */
1710         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1711         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1712
1713         /* Set up VSYNC active edge delay (in lines) */
1714         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1715 }
1716
1717 /* HDMI Initialization Step B.4 */
1718 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1719 {
1720         /* control period minimum duration */
1721         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1722         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1723         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1724
1725         /* Set to fill TMDS data channels */
1726         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1727         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1728         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1729
1730         /* Enable pixel clock and tmds data path */
1731         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1732                            HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1733                            HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1734                            HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1735                            HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1736         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1737         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1738
1739         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1740         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1741
1742         /* Enable csc path */
1743         if (is_color_space_conversion(hdmi)) {
1744                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1745                 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1746         }
1747
1748         /* Enable color space conversion if needed */
1749         if (is_color_space_conversion(hdmi))
1750                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1751                             HDMI_MC_FLOWCTRL);
1752         else
1753                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1754                             HDMI_MC_FLOWCTRL);
1755 }
1756
1757 /* Workaround to clear the overflow condition */
1758 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1759 {
1760         unsigned int count;
1761         unsigned int i;
1762         u8 val;
1763
1764         /*
1765          * Under some circumstances the Frame Composer arithmetic unit can miss
1766          * an FC register write due to being busy processing the previous one.
1767          * The issue can be worked around by issuing a TMDS software reset and
1768          * then write one of the FC registers several times.
1769          *
1770          * The number of iterations matters and depends on the HDMI TX revision
1771          * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
1772          * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
1773          * as needing the workaround, with 4 iterations for v1.30a and 1
1774          * iteration for others.
1775          * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
1776          * the workaround with a single iteration.
1777          */
1778
1779         switch (hdmi->version) {
1780         case 0x130a:
1781                 count = 4;
1782                 break;
1783         case 0x131a:
1784         case 0x132a:
1785         case 0x201a:
1786         case 0x212a:
1787                 count = 1;
1788                 break;
1789         default:
1790                 return;
1791         }
1792
1793         /* TMDS software reset */
1794         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1795
1796         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1797         for (i = 0; i < count; i++)
1798                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1799 }
1800
1801 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1802 {
1803         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1804                     HDMI_IH_MUTE_FC_STAT2);
1805 }
1806
1807 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1808 {
1809         int ret;
1810
1811         hdmi_disable_overflow_interrupts(hdmi);
1812
1813         hdmi->vic = drm_match_cea_mode(mode);
1814
1815         if (!hdmi->vic) {
1816                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1817         } else {
1818                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1819         }
1820
1821         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1822             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1823             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1824             (hdmi->vic == 17) || (hdmi->vic == 18))
1825                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1826         else
1827                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1828
1829         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1830         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1831
1832         /* TOFIX: Get input format from plat data or fallback to RGB888 */
1833         if (hdmi->plat_data->input_bus_format)
1834                 hdmi->hdmi_data.enc_in_bus_format =
1835                         hdmi->plat_data->input_bus_format;
1836         else
1837                 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1838
1839         /* TOFIX: Get input encoding from plat data or fallback to none */
1840         if (hdmi->plat_data->input_bus_encoding)
1841                 hdmi->hdmi_data.enc_in_encoding =
1842                         hdmi->plat_data->input_bus_encoding;
1843         else
1844                 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1845
1846         /* TOFIX: Default to RGB888 output format */
1847         hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1848
1849         hdmi->hdmi_data.pix_repet_factor = 0;
1850         hdmi->hdmi_data.hdcp_enable = 0;
1851         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1852
1853         /* HDMI Initialization Step B.1 */
1854         hdmi_av_composer(hdmi, mode);
1855
1856         /* HDMI Initializateion Step B.2 */
1857         ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1858         if (ret)
1859                 return ret;
1860         hdmi->phy.enabled = true;
1861
1862         /* HDMI Initialization Step B.3 */
1863         dw_hdmi_enable_video_path(hdmi);
1864
1865         if (hdmi->sink_has_audio) {
1866                 dev_dbg(hdmi->dev, "sink has audio support\n");
1867
1868                 /* HDMI Initialization Step E - Configure audio */
1869                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1870                 hdmi_enable_audio_clk(hdmi, true);
1871         }
1872
1873         /* not for DVI mode */
1874         if (hdmi->sink_is_hdmi) {
1875                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1876
1877                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1878                 hdmi_config_AVI(hdmi, mode);
1879                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1880         } else {
1881                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1882         }
1883
1884         hdmi_video_packetize(hdmi);
1885         hdmi_video_csc(hdmi);
1886         hdmi_video_sample(hdmi);
1887         hdmi_tx_hdcp_config(hdmi);
1888
1889         dw_hdmi_clear_overflow(hdmi);
1890
1891         return 0;
1892 }
1893
1894 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
1895 {
1896         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1897                     HDMI_PHY_I2CM_INT_ADDR);
1898
1899         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1900                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1901                     HDMI_PHY_I2CM_CTLINT_ADDR);
1902 }
1903
1904 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1905 {
1906         u8 ih_mute;
1907
1908         /*
1909          * Boot up defaults are:
1910          * HDMI_IH_MUTE   = 0x03 (disabled)
1911          * HDMI_IH_MUTE_* = 0x00 (enabled)
1912          *
1913          * Disable top level interrupt bits in HDMI block
1914          */
1915         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1916                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1917                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1918
1919         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1920
1921         /* by default mask all interrupts */
1922         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1923         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1924         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1925         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1926         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1927         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1928         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1929         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1930         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1931         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1932         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1933         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1934         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1935         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1936
1937         /* Disable interrupts in the IH_MUTE_* registers */
1938         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1939         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1940         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1941         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1942         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1943         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1944         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1945         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1946         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1947         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1948
1949         /* Enable top level interrupt bits in HDMI block */
1950         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1951                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1952         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1953 }
1954
1955 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1956 {
1957         hdmi->bridge_is_on = true;
1958         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1959 }
1960
1961 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1962 {
1963         if (hdmi->phy.enabled) {
1964                 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
1965                 hdmi->phy.enabled = false;
1966         }
1967
1968         hdmi->bridge_is_on = false;
1969 }
1970
1971 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1972 {
1973         int force = hdmi->force;
1974
1975         if (hdmi->disabled) {
1976                 force = DRM_FORCE_OFF;
1977         } else if (force == DRM_FORCE_UNSPECIFIED) {
1978                 if (hdmi->rxsense)
1979                         force = DRM_FORCE_ON;
1980                 else
1981                         force = DRM_FORCE_OFF;
1982         }
1983
1984         if (force == DRM_FORCE_OFF) {
1985                 if (hdmi->bridge_is_on)
1986                         dw_hdmi_poweroff(hdmi);
1987         } else {
1988                 if (!hdmi->bridge_is_on)
1989                         dw_hdmi_poweron(hdmi);
1990         }
1991 }
1992
1993 /*
1994  * Adjust the detection of RXSENSE according to whether we have a forced
1995  * connection mode enabled, or whether we have been disabled.  There is
1996  * no point processing RXSENSE interrupts if we have a forced connection
1997  * state, or DRM has us disabled.
1998  *
1999  * We also disable rxsense interrupts when we think we're disconnected
2000  * to avoid floating TDMS signals giving false rxsense interrupts.
2001  *
2002  * Note: we still need to listen for HPD interrupts even when DRM has us
2003  * disabled so that we can detect a connect event.
2004  */
2005 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2006 {
2007         if (hdmi->phy.ops->update_hpd)
2008                 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2009                                           hdmi->force, hdmi->disabled,
2010                                           hdmi->rxsense);
2011 }
2012
2013 static enum drm_connector_status
2014 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2015 {
2016         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2017                                              connector);
2018
2019         mutex_lock(&hdmi->mutex);
2020         hdmi->force = DRM_FORCE_UNSPECIFIED;
2021         dw_hdmi_update_power(hdmi);
2022         dw_hdmi_update_phy_mask(hdmi);
2023         mutex_unlock(&hdmi->mutex);
2024
2025         return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2026 }
2027
2028 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2029 {
2030         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2031                                              connector);
2032         struct edid *edid;
2033         int ret = 0;
2034
2035         if (!hdmi->ddc)
2036                 return 0;
2037
2038         edid = drm_get_edid(connector, hdmi->ddc);
2039         if (edid) {
2040                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2041                         edid->width_cm, edid->height_cm);
2042
2043                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2044                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2045                 drm_connector_update_edid_property(connector, edid);
2046                 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2047                 ret = drm_add_edid_modes(connector, edid);
2048                 kfree(edid);
2049         } else {
2050                 dev_dbg(hdmi->dev, "failed to get edid\n");
2051         }
2052
2053         return ret;
2054 }
2055
2056 static void dw_hdmi_connector_force(struct drm_connector *connector)
2057 {
2058         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2059                                              connector);
2060
2061         mutex_lock(&hdmi->mutex);
2062         hdmi->force = connector->force;
2063         dw_hdmi_update_power(hdmi);
2064         dw_hdmi_update_phy_mask(hdmi);
2065         mutex_unlock(&hdmi->mutex);
2066 }
2067
2068 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2069         .fill_modes = drm_helper_probe_single_connector_modes,
2070         .detect = dw_hdmi_connector_detect,
2071         .destroy = drm_connector_cleanup,
2072         .force = dw_hdmi_connector_force,
2073         .reset = drm_atomic_helper_connector_reset,
2074         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2075         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2076 };
2077
2078 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2079         .get_modes = dw_hdmi_connector_get_modes,
2080 };
2081
2082 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
2083 {
2084         struct dw_hdmi *hdmi = bridge->driver_private;
2085         struct drm_encoder *encoder = bridge->encoder;
2086         struct drm_connector *connector = &hdmi->connector;
2087
2088         connector->interlace_allowed = 1;
2089         connector->polled = DRM_CONNECTOR_POLL_HPD;
2090
2091         drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2092
2093         drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
2094                            DRM_MODE_CONNECTOR_HDMIA);
2095
2096         drm_connector_attach_encoder(connector, encoder);
2097
2098         return 0;
2099 }
2100
2101 static enum drm_mode_status
2102 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2103                           const struct drm_display_mode *mode)
2104 {
2105         struct dw_hdmi *hdmi = bridge->driver_private;
2106         struct drm_connector *connector = &hdmi->connector;
2107         enum drm_mode_status mode_status = MODE_OK;
2108
2109         /* We don't support double-clocked modes */
2110         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2111                 return MODE_BAD;
2112
2113         if (hdmi->plat_data->mode_valid)
2114                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2115
2116         return mode_status;
2117 }
2118
2119 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2120                                     const struct drm_display_mode *orig_mode,
2121                                     const struct drm_display_mode *mode)
2122 {
2123         struct dw_hdmi *hdmi = bridge->driver_private;
2124
2125         mutex_lock(&hdmi->mutex);
2126
2127         /* Store the display mode for plugin/DKMS poweron events */
2128         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2129
2130         mutex_unlock(&hdmi->mutex);
2131 }
2132
2133 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2134 {
2135         struct dw_hdmi *hdmi = bridge->driver_private;
2136
2137         mutex_lock(&hdmi->mutex);
2138         hdmi->disabled = true;
2139         dw_hdmi_update_power(hdmi);
2140         dw_hdmi_update_phy_mask(hdmi);
2141         mutex_unlock(&hdmi->mutex);
2142 }
2143
2144 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2145 {
2146         struct dw_hdmi *hdmi = bridge->driver_private;
2147
2148         mutex_lock(&hdmi->mutex);
2149         hdmi->disabled = false;
2150         dw_hdmi_update_power(hdmi);
2151         dw_hdmi_update_phy_mask(hdmi);
2152         mutex_unlock(&hdmi->mutex);
2153 }
2154
2155 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2156         .attach = dw_hdmi_bridge_attach,
2157         .enable = dw_hdmi_bridge_enable,
2158         .disable = dw_hdmi_bridge_disable,
2159         .mode_set = dw_hdmi_bridge_mode_set,
2160         .mode_valid = dw_hdmi_bridge_mode_valid,
2161 };
2162
2163 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2164 {
2165         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2166         unsigned int stat;
2167
2168         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2169         if (!stat)
2170                 return IRQ_NONE;
2171
2172         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2173
2174         i2c->stat = stat;
2175
2176         complete(&i2c->cmp);
2177
2178         return IRQ_HANDLED;
2179 }
2180
2181 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2182 {
2183         struct dw_hdmi *hdmi = dev_id;
2184         u8 intr_stat;
2185         irqreturn_t ret = IRQ_NONE;
2186
2187         if (hdmi->i2c)
2188                 ret = dw_hdmi_i2c_irq(hdmi);
2189
2190         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2191         if (intr_stat) {
2192                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2193                 return IRQ_WAKE_THREAD;
2194         }
2195
2196         return ret;
2197 }
2198
2199 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2200 {
2201         mutex_lock(&hdmi->mutex);
2202
2203         if (!hdmi->force) {
2204                 /*
2205                  * If the RX sense status indicates we're disconnected,
2206                  * clear the software rxsense status.
2207                  */
2208                 if (!rx_sense)
2209                         hdmi->rxsense = false;
2210
2211                 /*
2212                  * Only set the software rxsense status when both
2213                  * rxsense and hpd indicates we're connected.
2214                  * This avoids what seems to be bad behaviour in
2215                  * at least iMX6S versions of the phy.
2216                  */
2217                 if (hpd)
2218                         hdmi->rxsense = true;
2219
2220                 dw_hdmi_update_power(hdmi);
2221                 dw_hdmi_update_phy_mask(hdmi);
2222         }
2223         mutex_unlock(&hdmi->mutex);
2224 }
2225 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2226
2227 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2228 {
2229         struct dw_hdmi *hdmi = dev_id;
2230         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2231
2232         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2233         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2234         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2235
2236         phy_pol_mask = 0;
2237         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2238                 phy_pol_mask |= HDMI_PHY_HPD;
2239         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2240                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2241         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2242                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2243         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2244                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2245         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2246                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2247
2248         if (phy_pol_mask)
2249                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2250
2251         /*
2252          * RX sense tells us whether the TDMS transmitters are detecting
2253          * load - in other words, there's something listening on the
2254          * other end of the link.  Use this to decide whether we should
2255          * power on the phy as HPD may be toggled by the sink to merely
2256          * ask the source to re-read the EDID.
2257          */
2258         if (intr_stat &
2259             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2260                 dw_hdmi_setup_rx_sense(hdmi,
2261                                        phy_stat & HDMI_PHY_HPD,
2262                                        phy_stat & HDMI_PHY_RX_SENSE);
2263
2264                 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
2265                         cec_notifier_set_phys_addr(hdmi->cec_notifier,
2266                                                    CEC_PHYS_ADDR_INVALID);
2267         }
2268
2269         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2270                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2271                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2272                 if (hdmi->bridge.dev)
2273                         drm_helper_hpd_irq_event(hdmi->bridge.dev);
2274         }
2275
2276         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2277         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2278                     HDMI_IH_MUTE_PHY_STAT0);
2279
2280         return IRQ_HANDLED;
2281 }
2282
2283 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2284         {
2285                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2286                 .name = "DWC HDMI TX PHY",
2287                 .gen = 1,
2288         }, {
2289                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2290                 .name = "DWC MHL PHY + HEAC PHY",
2291                 .gen = 2,
2292                 .has_svsret = true,
2293                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2294         }, {
2295                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2296                 .name = "DWC MHL PHY",
2297                 .gen = 2,
2298                 .has_svsret = true,
2299                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2300         }, {
2301                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2302                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2303                 .gen = 2,
2304                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2305         }, {
2306                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2307                 .name = "DWC HDMI 3D TX PHY",
2308                 .gen = 2,
2309                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2310         }, {
2311                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2312                 .name = "DWC HDMI 2.0 TX PHY",
2313                 .gen = 2,
2314                 .has_svsret = true,
2315                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2316         }, {
2317                 .type = DW_HDMI_PHY_VENDOR_PHY,
2318                 .name = "Vendor PHY",
2319         }
2320 };
2321
2322 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2323 {
2324         unsigned int i;
2325         u8 phy_type;
2326
2327         phy_type = hdmi->plat_data->phy_force_vendor ?
2328                                 DW_HDMI_PHY_VENDOR_PHY :
2329                                 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2330
2331         if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2332                 /* Vendor PHYs require support from the glue layer. */
2333                 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2334                         dev_err(hdmi->dev,
2335                                 "Vendor HDMI PHY not supported by glue layer\n");
2336                         return -ENODEV;
2337                 }
2338
2339                 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2340                 hdmi->phy.data = hdmi->plat_data->phy_data;
2341                 hdmi->phy.name = hdmi->plat_data->phy_name;
2342                 return 0;
2343         }
2344
2345         /* Synopsys PHYs are handled internally. */
2346         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2347                 if (dw_hdmi_phys[i].type == phy_type) {
2348                         hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2349                         hdmi->phy.name = dw_hdmi_phys[i].name;
2350                         hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2351
2352                         if (!dw_hdmi_phys[i].configure &&
2353                             !hdmi->plat_data->configure_phy) {
2354                                 dev_err(hdmi->dev, "%s requires platform support\n",
2355                                         hdmi->phy.name);
2356                                 return -ENODEV;
2357                         }
2358
2359                         return 0;
2360                 }
2361         }
2362
2363         dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2364         return -ENODEV;
2365 }
2366
2367 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2368 {
2369         mutex_lock(&hdmi->mutex);
2370         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2371         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2372         mutex_unlock(&hdmi->mutex);
2373 }
2374
2375 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2376 {
2377         mutex_lock(&hdmi->mutex);
2378         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2379         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2380         mutex_unlock(&hdmi->mutex);
2381 }
2382
2383 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2384         .write = hdmi_writeb,
2385         .read = hdmi_readb,
2386         .enable = dw_hdmi_cec_enable,
2387         .disable = dw_hdmi_cec_disable,
2388 };
2389
2390 static const struct regmap_config hdmi_regmap_8bit_config = {
2391         .reg_bits       = 32,
2392         .val_bits       = 8,
2393         .reg_stride     = 1,
2394         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2395 };
2396
2397 static const struct regmap_config hdmi_regmap_32bit_config = {
2398         .reg_bits       = 32,
2399         .val_bits       = 32,
2400         .reg_stride     = 4,
2401         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2402 };
2403
2404 static struct dw_hdmi *
2405 __dw_hdmi_probe(struct platform_device *pdev,
2406                 const struct dw_hdmi_plat_data *plat_data)
2407 {
2408         struct device *dev = &pdev->dev;
2409         struct device_node *np = dev->of_node;
2410         struct platform_device_info pdevinfo;
2411         struct device_node *ddc_node;
2412         struct dw_hdmi_cec_data cec;
2413         struct dw_hdmi *hdmi;
2414         struct resource *iores = NULL;
2415         int irq;
2416         int ret;
2417         u32 val = 1;
2418         u8 prod_id0;
2419         u8 prod_id1;
2420         u8 config0;
2421         u8 config3;
2422
2423         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2424         if (!hdmi)
2425                 return ERR_PTR(-ENOMEM);
2426
2427         hdmi->plat_data = plat_data;
2428         hdmi->dev = dev;
2429         hdmi->sample_rate = 48000;
2430         hdmi->disabled = true;
2431         hdmi->rxsense = true;
2432         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2433         hdmi->mc_clkdis = 0x7f;
2434
2435         mutex_init(&hdmi->mutex);
2436         mutex_init(&hdmi->audio_mutex);
2437         spin_lock_init(&hdmi->audio_lock);
2438
2439         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2440         if (ddc_node) {
2441                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2442                 of_node_put(ddc_node);
2443                 if (!hdmi->ddc) {
2444                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2445                         return ERR_PTR(-EPROBE_DEFER);
2446                 }
2447
2448         } else {
2449                 dev_dbg(hdmi->dev, "no ddc property found\n");
2450         }
2451
2452         if (!plat_data->regm) {
2453                 const struct regmap_config *reg_config;
2454
2455                 of_property_read_u32(np, "reg-io-width", &val);
2456                 switch (val) {
2457                 case 4:
2458                         reg_config = &hdmi_regmap_32bit_config;
2459                         hdmi->reg_shift = 2;
2460                         break;
2461                 case 1:
2462                         reg_config = &hdmi_regmap_8bit_config;
2463                         break;
2464                 default:
2465                         dev_err(dev, "reg-io-width must be 1 or 4\n");
2466                         return ERR_PTR(-EINVAL);
2467                 }
2468
2469                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2470                 hdmi->regs = devm_ioremap_resource(dev, iores);
2471                 if (IS_ERR(hdmi->regs)) {
2472                         ret = PTR_ERR(hdmi->regs);
2473                         goto err_res;
2474                 }
2475
2476                 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2477                 if (IS_ERR(hdmi->regm)) {
2478                         dev_err(dev, "Failed to configure regmap\n");
2479                         ret = PTR_ERR(hdmi->regm);
2480                         goto err_res;
2481                 }
2482         } else {
2483                 hdmi->regm = plat_data->regm;
2484         }
2485
2486         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2487         if (IS_ERR(hdmi->isfr_clk)) {
2488                 ret = PTR_ERR(hdmi->isfr_clk);
2489                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2490                 goto err_res;
2491         }
2492
2493         ret = clk_prepare_enable(hdmi->isfr_clk);
2494         if (ret) {
2495                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2496                 goto err_res;
2497         }
2498
2499         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2500         if (IS_ERR(hdmi->iahb_clk)) {
2501                 ret = PTR_ERR(hdmi->iahb_clk);
2502                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2503                 goto err_isfr;
2504         }
2505
2506         ret = clk_prepare_enable(hdmi->iahb_clk);
2507         if (ret) {
2508                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2509                 goto err_isfr;
2510         }
2511
2512         hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2513         if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2514                 hdmi->cec_clk = NULL;
2515         } else if (IS_ERR(hdmi->cec_clk)) {
2516                 ret = PTR_ERR(hdmi->cec_clk);
2517                 if (ret != -EPROBE_DEFER)
2518                         dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2519                                 ret);
2520
2521                 hdmi->cec_clk = NULL;
2522                 goto err_iahb;
2523         } else {
2524                 ret = clk_prepare_enable(hdmi->cec_clk);
2525                 if (ret) {
2526                         dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2527                                 ret);
2528                         goto err_iahb;
2529                 }
2530         }
2531
2532         /* Product and revision IDs */
2533         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2534                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2535         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2536         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2537
2538         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2539             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2540                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2541                         hdmi->version, prod_id0, prod_id1);
2542                 ret = -ENODEV;
2543                 goto err_iahb;
2544         }
2545
2546         ret = dw_hdmi_detect_phy(hdmi);
2547         if (ret < 0)
2548                 goto err_iahb;
2549
2550         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2551                  hdmi->version >> 12, hdmi->version & 0xfff,
2552                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2553                  hdmi->phy.name);
2554
2555         initialize_hdmi_ih_mutes(hdmi);
2556
2557         irq = platform_get_irq(pdev, 0);
2558         if (irq < 0) {
2559                 ret = irq;
2560                 goto err_iahb;
2561         }
2562
2563         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2564                                         dw_hdmi_irq, IRQF_SHARED,
2565                                         dev_name(dev), hdmi);
2566         if (ret)
2567                 goto err_iahb;
2568
2569         hdmi->cec_notifier = cec_notifier_get(dev);
2570         if (!hdmi->cec_notifier) {
2571                 ret = -ENOMEM;
2572                 goto err_iahb;
2573         }
2574
2575         /*
2576          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2577          * N and cts values before enabling phy
2578          */
2579         hdmi_init_clk_regenerator(hdmi);
2580
2581         /* If DDC bus is not specified, try to register HDMI I2C bus */
2582         if (!hdmi->ddc) {
2583                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2584                 if (IS_ERR(hdmi->ddc))
2585                         hdmi->ddc = NULL;
2586         }
2587
2588         hdmi->bridge.driver_private = hdmi;
2589         hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2590 #ifdef CONFIG_OF
2591         hdmi->bridge.of_node = pdev->dev.of_node;
2592 #endif
2593
2594         dw_hdmi_setup_i2c(hdmi);
2595         if (hdmi->phy.ops->setup_hpd)
2596                 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2597
2598         memset(&pdevinfo, 0, sizeof(pdevinfo));
2599         pdevinfo.parent = dev;
2600         pdevinfo.id = PLATFORM_DEVID_AUTO;
2601
2602         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2603         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2604
2605         if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2606                 struct dw_hdmi_audio_data audio;
2607
2608                 audio.phys = iores->start;
2609                 audio.base = hdmi->regs;
2610                 audio.irq = irq;
2611                 audio.hdmi = hdmi;
2612                 audio.eld = hdmi->connector.eld;
2613                 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2614                 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2615
2616                 pdevinfo.name = "dw-hdmi-ahb-audio";
2617                 pdevinfo.data = &audio;
2618                 pdevinfo.size_data = sizeof(audio);
2619                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2620                 hdmi->audio = platform_device_register_full(&pdevinfo);
2621         } else if (config0 & HDMI_CONFIG0_I2S) {
2622                 struct dw_hdmi_i2s_audio_data audio;
2623
2624                 audio.hdmi      = hdmi;
2625                 audio.write     = hdmi_writeb;
2626                 audio.read      = hdmi_readb;
2627                 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2628                 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2629
2630                 pdevinfo.name = "dw-hdmi-i2s-audio";
2631                 pdevinfo.data = &audio;
2632                 pdevinfo.size_data = sizeof(audio);
2633                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2634                 hdmi->audio = platform_device_register_full(&pdevinfo);
2635         }
2636
2637         if (config0 & HDMI_CONFIG0_CEC) {
2638                 cec.hdmi = hdmi;
2639                 cec.ops = &dw_hdmi_cec_ops;
2640                 cec.irq = irq;
2641
2642                 pdevinfo.name = "dw-hdmi-cec";
2643                 pdevinfo.data = &cec;
2644                 pdevinfo.size_data = sizeof(cec);
2645                 pdevinfo.dma_mask = 0;
2646
2647                 hdmi->cec = platform_device_register_full(&pdevinfo);
2648         }
2649
2650         /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2651         if (hdmi->i2c)
2652                 dw_hdmi_i2c_init(hdmi);
2653
2654         return hdmi;
2655
2656 err_iahb:
2657         if (hdmi->i2c) {
2658                 i2c_del_adapter(&hdmi->i2c->adap);
2659                 hdmi->ddc = NULL;
2660         }
2661
2662         if (hdmi->cec_notifier)
2663                 cec_notifier_put(hdmi->cec_notifier);
2664
2665         clk_disable_unprepare(hdmi->iahb_clk);
2666         if (hdmi->cec_clk)
2667                 clk_disable_unprepare(hdmi->cec_clk);
2668 err_isfr:
2669         clk_disable_unprepare(hdmi->isfr_clk);
2670 err_res:
2671         i2c_put_adapter(hdmi->ddc);
2672
2673         return ERR_PTR(ret);
2674 }
2675
2676 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2677 {
2678         if (hdmi->audio && !IS_ERR(hdmi->audio))
2679                 platform_device_unregister(hdmi->audio);
2680         if (!IS_ERR(hdmi->cec))
2681                 platform_device_unregister(hdmi->cec);
2682
2683         /* Disable all interrupts */
2684         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2685
2686         if (hdmi->cec_notifier)
2687                 cec_notifier_put(hdmi->cec_notifier);
2688
2689         clk_disable_unprepare(hdmi->iahb_clk);
2690         clk_disable_unprepare(hdmi->isfr_clk);
2691         if (hdmi->cec_clk)
2692                 clk_disable_unprepare(hdmi->cec_clk);
2693
2694         if (hdmi->i2c)
2695                 i2c_del_adapter(&hdmi->i2c->adap);
2696         else
2697                 i2c_put_adapter(hdmi->ddc);
2698 }
2699
2700 /* -----------------------------------------------------------------------------
2701  * Probe/remove API, used from platforms based on the DRM bridge API.
2702  */
2703 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
2704                               const struct dw_hdmi_plat_data *plat_data)
2705 {
2706         struct dw_hdmi *hdmi;
2707
2708         hdmi = __dw_hdmi_probe(pdev, plat_data);
2709         if (IS_ERR(hdmi))
2710                 return hdmi;
2711
2712         drm_bridge_add(&hdmi->bridge);
2713
2714         return hdmi;
2715 }
2716 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2717
2718 void dw_hdmi_remove(struct dw_hdmi *hdmi)
2719 {
2720         drm_bridge_remove(&hdmi->bridge);
2721
2722         __dw_hdmi_remove(hdmi);
2723 }
2724 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2725
2726 /* -----------------------------------------------------------------------------
2727  * Bind/unbind API, used from platforms based on the component framework.
2728  */
2729 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
2730                              struct drm_encoder *encoder,
2731                              const struct dw_hdmi_plat_data *plat_data)
2732 {
2733         struct dw_hdmi *hdmi;
2734         int ret;
2735
2736         hdmi = __dw_hdmi_probe(pdev, plat_data);
2737         if (IS_ERR(hdmi))
2738                 return hdmi;
2739
2740         ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2741         if (ret) {
2742                 dw_hdmi_remove(hdmi);
2743                 DRM_ERROR("Failed to initialize bridge with drm\n");
2744                 return ERR_PTR(ret);
2745         }
2746
2747         return hdmi;
2748 }
2749 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2750
2751 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
2752 {
2753         __dw_hdmi_remove(hdmi);
2754 }
2755 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2756
2757 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2758 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2759 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2760 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2761 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2762 MODULE_LICENSE("GPL");
2763 MODULE_ALIAS("platform:dw-hdmi");