drivers/gpu/drm/bridge/ti-sn65dsi86.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  * datasheet: http://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/gpio/consumer.h>
  10 #include <linux/i2c.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/module.h>
  13 #include <linux/of_graph.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_dp_helper.h>
  21 #include <drm/drm_mipi_dsi.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drm_print.h>
  25 #include <drm/drm_probe_helper.h>
  26
  27 #define SN_DEVICE_REV_REG                       0x08
  28 #define SN_DPPLL_SRC_REG                        0x0A
  29 #define  DPPLL_CLK_SRC_DSICLK                   BIT(0)
  30 #define  REFCLK_FREQ_MASK                       GENMASK(3, 1)
  31 #define  REFCLK_FREQ(x)                         ((x) << 1)
  32 #define  DPPLL_SRC_DP_PLL_LOCK                  BIT(7)
  33 #define SN_PLL_ENABLE_REG                       0x0D
  34 #define SN_DSI_LANES_REG                        0x10
  35 #define  CHA_DSI_LANES_MASK                     GENMASK(4, 3)
  36 #define  CHA_DSI_LANES(x)                       ((x) << 3)
  37 #define SN_DSIA_CLK_FREQ_REG                    0x12
  38 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG       0x20
  39 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG    0x24
  40 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG        0x2C
  41 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG       0x2D
  42 #define  CHA_HSYNC_POLARITY                     BIT(7)
  43 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG        0x30
  44 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG       0x31
  45 #define  CHA_VSYNC_POLARITY                     BIT(7)
  46 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG        0x34
  47 #define SN_CHA_VERTICAL_BACK_PORCH_REG          0x36
  48 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG       0x38
  49 #define SN_CHA_VERTICAL_FRONT_PORCH_REG         0x3A
  50 #define SN_ENH_FRAME_REG                        0x5A
  51 #define  VSTREAM_ENABLE                         BIT(3)
  52 #define SN_DATA_FORMAT_REG                      0x5B
  53 #define SN_HPD_DISABLE_REG                      0x5C
  54 #define  HPD_DISABLE                            BIT(0)
  55 #define SN_AUX_WDATA_REG(x)                     (0x64 + (x))
  56 #define SN_AUX_ADDR_19_16_REG                   0x74
  57 #define SN_AUX_ADDR_15_8_REG                    0x75
  58 #define SN_AUX_ADDR_7_0_REG                     0x76
  59 #define SN_AUX_LENGTH_REG                       0x77
  60 #define SN_AUX_CMD_REG                          0x78
  61 #define  AUX_CMD_SEND                           BIT(0)
  62 #define  AUX_CMD_REQ(x)                         ((x) << 4)
  63 #define SN_AUX_RDATA_REG(x)                     (0x79 + (x))
  64 #define SN_SSC_CONFIG_REG                       0x93
  65 #define  DP_NUM_LANES_MASK                      GENMASK(5, 4)
  66 #define  DP_NUM_LANES(x)                        ((x) << 4)
  67 #define SN_DATARATE_CONFIG_REG                  0x94
  68 #define  DP_DATARATE_MASK                       GENMASK(7, 5)
  69 #define  DP_DATARATE(x)                         ((x) << 5)
  70 #define SN_ML_TX_MODE_REG                       0x96
  71 #define  ML_TX_MAIN_LINK_OFF                    0
  72 #define  ML_TX_NORMAL_MODE                      BIT(0)
  73 #define SN_AUX_CMD_STATUS_REG                   0xF4
  74 #define  AUX_IRQ_STATUS_AUX_RPLY_TOUT           BIT(3)
  75 #define  AUX_IRQ_STATUS_AUX_SHORT               BIT(5)
  76 #define  AUX_IRQ_STATUS_NAT_I2C_FAIL            BIT(6)
  77
  78 #define MIN_DSI_CLK_FREQ_MHZ    40
  79
  80 /* fudge factor required to account for 8b/10b encoding */
  81 #define DP_CLK_FUDGE_NUM        10
  82 #define DP_CLK_FUDGE_DEN        8
  83
  84 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
  85 #define SN_AUX_MAX_PAYLOAD_BYTES        16
  86
  87 #define SN_REGULATOR_SUPPLY_NUM         4
  88
  89 struct ti_sn_bridge {
  90         struct device                   *dev;
  91         struct regmap                   *regmap;
  92         struct drm_dp_aux               aux;
  93         struct drm_bridge               bridge;
  94         struct drm_connector            connector;
  95         struct dentry                   *debugfs;
  96         struct device_node              *host_node;
  97         struct mipi_dsi_device          *dsi;
  98         struct clk                      *refclk;
  99         struct drm_panel                *panel;
 100         struct gpio_desc                *enable_gpio;
 101         struct regulator_bulk_data      supplies[SN_REGULATOR_SUPPLY_NUM];
 102 };
 103
 104 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
 105         { .range_min = 0, .range_max = 0xFF },
 106 };
 107
 108 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
 109         .yes_ranges = ti_sn_bridge_volatile_ranges,
 110         .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
 111 };
 112
 113 static const struct regmap_config ti_sn_bridge_regmap_config = {
 114         .reg_bits = 8,
 115         .val_bits = 8,
 116         .volatile_table = &ti_sn_bridge_volatile_table,
 117         .cache_type = REGCACHE_NONE,
 118 };
 119
 120 static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
 121                                    unsigned int reg, u16 val)
 122 {
 123         regmap_write(pdata->regmap, reg, val & 0xFF);
 124         regmap_write(pdata->regmap, reg + 1, val >> 8);
 125 }
 126
 127 static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
 128 {
 129         struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
 130         int ret;
 131
 132         ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 133         if (ret) {
 134                 DRM_ERROR("failed to enable supplies %d\n", ret);
 135                 return ret;
 136         }
 137
 138         gpiod_set_value(pdata->enable_gpio, 1);
 139
 140         return ret;
 141 }
 142
 143 static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
 144 {
 145         struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
 146         int ret;
 147
 148         gpiod_set_value(pdata->enable_gpio, 0);
 149
 150         ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 151         if (ret)
 152                 DRM_ERROR("failed to disable supplies %d\n", ret);
 153
 154         return ret;
 155 }
 156
 157 static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
 158         SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
 159 };
 160
 161 static int status_show(struct seq_file *s, void *data)
 162 {
 163         struct ti_sn_bridge *pdata = s->private;
 164         unsigned int reg, val;
 165
 166         seq_puts(s, "STATUS REGISTERS:\n");
 167
 168         pm_runtime_get_sync(pdata->dev);
 169
 170         /* IRQ Status Registers, see Table 31 in datasheet */
 171         for (reg = 0xf0; reg <= 0xf8; reg++) {
 172                 regmap_read(pdata->regmap, reg, &val);
 173                 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
 174         }
 175
 176         pm_runtime_put(pdata->dev);
 177
 178         return 0;
 179 }
 180
 181 DEFINE_SHOW_ATTRIBUTE(status);
 182
 183 static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
 184 {
 185         pdata->debugfs = debugfs_create_dir("ti_sn65dsi86", NULL);
 186
 187         debugfs_create_file("status", 0600, pdata->debugfs, pdata,
 188                         &status_fops);
 189 }
 190
 191 static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
 192 {
 193         debugfs_remove_recursive(pdata->debugfs);
 194         pdata->debugfs = NULL;
 195 }
 196
 197 /* Connector funcs */
 198 static struct ti_sn_bridge *
 199 connector_to_ti_sn_bridge(struct drm_connector *connector)
 200 {
 201         return container_of(connector, struct ti_sn_bridge, connector);
 202 }
 203
 204 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
 205 {
 206         struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
 207
 208         return drm_panel_get_modes(pdata->panel);
 209 }
 210
 211 static enum drm_mode_status
 212 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
 213                                   struct drm_display_mode *mode)
 214 {
 215         /* maximum supported resolution is 4K at 60 fps */
 216         if (mode->clock > 594000)
 217                 return MODE_CLOCK_HIGH;
 218
 219         return MODE_OK;
 220 }
 221
 222 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
 223         .get_modes = ti_sn_bridge_connector_get_modes,
 224         .mode_valid = ti_sn_bridge_connector_mode_valid,
 225 };
 226
 227 static enum drm_connector_status
 228 ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
 229 {
 230         /**
 231          * TODO: Currently if drm_panel is present, then always
 232          * return the status as connected. Need to add support to detect
 233          * device state for hot pluggable scenarios.
 234          */
 235         return connector_status_connected;
 236 }
 237
 238 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
 239         .fill_modes = drm_helper_probe_single_connector_modes,
 240         .detect = ti_sn_bridge_connector_detect,
 241         .destroy = drm_connector_cleanup,
 242         .reset = drm_atomic_helper_connector_reset,
 243         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 244         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 245 };
 246
 247 static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
 248 {
 249         return container_of(bridge, struct ti_sn_bridge, bridge);
 250 }
 251
 252 static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
 253 {
 254         unsigned int i;
 255         const char * const ti_sn_bridge_supply_names[] = {
 256                 "vcca", "vcc", "vccio", "vpll",
 257         };
 258
 259         for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
 260                 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
 261
 262         return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
 263                                        pdata->supplies);
 264 }
 265
 266 static int ti_sn_bridge_attach(struct drm_bridge *bridge)
 267 {
 268         int ret, val;
 269         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 270         struct mipi_dsi_host *host;
 271         struct mipi_dsi_device *dsi;
 272         const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
 273                                                    .channel = 0,
 274                                                    .node = NULL,
 275                                                  };
 276
 277         ret = drm_connector_init(bridge->dev, &pdata->connector,
 278                                  &ti_sn_bridge_connector_funcs,
 279                                  DRM_MODE_CONNECTOR_eDP);
 280         if (ret) {
 281                 DRM_ERROR("Failed to initialize connector with drm\n");
 282                 return ret;
 283         }
 284
 285         drm_connector_helper_add(&pdata->connector,
 286                                  &ti_sn_bridge_connector_helper_funcs);
 287         drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
 288
 289         /*
 290          * TODO: ideally finding host resource and dsi dev registration needs
 291          * to be done in bridge probe. But some existing DSI host drivers will
 292          * wait for any of the drm_bridge/drm_panel to get added to the global
 293          * bridge/panel list, before completing their probe. So if we do the
 294          * dsi dev registration part in bridge probe, before populating in
 295          * the global bridge list, then it will cause deadlock as dsi host probe
 296          * will never complete, neither our bridge probe. So keeping it here
 297          * will satisfy most of the existing host drivers. Once the host driver
 298          * is fixed we can move the below code to bridge probe safely.
 299          */
 300         host = of_find_mipi_dsi_host_by_node(pdata->host_node);
 301         if (!host) {
 302                 DRM_ERROR("failed to find dsi host\n");
 303                 ret = -ENODEV;
 304                 goto err_dsi_host;
 305         }
 306
 307         dsi = mipi_dsi_device_register_full(host, &info);
 308         if (IS_ERR(dsi)) {
 309                 DRM_ERROR("failed to create dsi device\n");
 310                 ret = PTR_ERR(dsi);
 311                 goto err_dsi_host;
 312         }
 313
 314         /* TODO: setting to 4 lanes always for now */
 315         dsi->lanes = 4;
 316         dsi->format = MIPI_DSI_FMT_RGB888;
 317         dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 318                           MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
 319
 320         /* check if continuous dsi clock is required or not */
 321         pm_runtime_get_sync(pdata->dev);
 322         regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
 323         pm_runtime_put(pdata->dev);
 324         if (!(val & DPPLL_CLK_SRC_DSICLK))
 325                 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
 326
 327         ret = mipi_dsi_attach(dsi);
 328         if (ret < 0) {
 329                 DRM_ERROR("failed to attach dsi to host\n");
 330                 goto err_dsi_attach;
 331         }
 332         pdata->dsi = dsi;
 333
 334         /* attach panel to bridge */
 335         drm_panel_attach(pdata->panel, &pdata->connector);
 336
 337         return 0;
 338
 339 err_dsi_attach:
 340         mipi_dsi_device_unregister(dsi);
 341 err_dsi_host:
 342         drm_connector_cleanup(&pdata->connector);
 343         return ret;
 344 }
 345
 346 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
 347 {
 348         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 349
 350         drm_panel_disable(pdata->panel);
 351
 352         /* disable video stream */
 353         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
 354         /* semi auto link training mode OFF */
 355         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
 356         /* disable DP PLL */
 357         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
 358
 359         drm_panel_unprepare(pdata->panel);
 360 }
 361
 362 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
 363 {
 364         u32 bit_rate_khz, clk_freq_khz;
 365         struct drm_display_mode *mode =
 366                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 367
 368         bit_rate_khz = mode->clock *
 369                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 370         clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
 371
 372         return clk_freq_khz;
 373 }
 374
 375 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
 376 static const u32 ti_sn_bridge_refclk_lut[] = {
 377         12000000,
 378         19200000,
 379         26000000,
 380         27000000,
 381         38400000,
 382 };
 383
 384 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
 385 static const u32 ti_sn_bridge_dsiclk_lut[] = {
 386         468000000,
 387         384000000,
 388         416000000,
 389         486000000,
 390         460800000,
 391 };
 392
 393 static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
 394 {
 395         int i;
 396         u32 refclk_rate;
 397         const u32 *refclk_lut;
 398         size_t refclk_lut_size;
 399
 400         if (pdata->refclk) {
 401                 refclk_rate = clk_get_rate(pdata->refclk);
 402                 refclk_lut = ti_sn_bridge_refclk_lut;
 403                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
 404                 clk_prepare_enable(pdata->refclk);
 405         } else {
 406                 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
 407                 refclk_lut = ti_sn_bridge_dsiclk_lut;
 408                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
 409         }
 410
 411         /* for i equals to refclk_lut_size means default frequency */
 412         for (i = 0; i < refclk_lut_size; i++)
 413                 if (refclk_lut[i] == refclk_rate)
 414                         break;
 415
 416         regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
 417                            REFCLK_FREQ(i));
 418 }
 419
 420 /**
 421  * LUT index corresponds to register value and
 422  * LUT values corresponds to dp data rate supported
 423  * by the bridge in Mbps unit.
 424  */
 425 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
 426         0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 427 };
 428
 429 static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
 430 {
 431         unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz;
 432         unsigned int val, i;
 433         struct drm_display_mode *mode =
 434                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 435
 436         /* set DSIA clk frequency */
 437         bit_rate_mhz = (mode->clock / 1000) *
 438                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 439         clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
 440
 441         /* for each increment in val, frequency increases by 5MHz */
 442         val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
 443                 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
 444         regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 445
 446         /* set DP data rate */
 447         dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
 448                                                         DP_CLK_FUDGE_DEN;
 449         for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 450                 if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
 451                         break;
 452
 453         regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
 454                            DP_DATARATE_MASK, DP_DATARATE(i));
 455 }
 456
 457 static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
 458 {
 459         struct drm_display_mode *mode =
 460                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 461         u8 hsync_polarity = 0, vsync_polarity = 0;
 462
 463         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 464                 hsync_polarity = CHA_HSYNC_POLARITY;
 465         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 466                 vsync_polarity = CHA_VSYNC_POLARITY;
 467
 468         ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
 469                                mode->hdisplay);
 470         ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
 471                                mode->vdisplay);
 472         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
 473                      (mode->hsync_end - mode->hsync_start) & 0xFF);
 474         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
 475                      (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
 476                      hsync_polarity);
 477         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
 478                      (mode->vsync_end - mode->vsync_start) & 0xFF);
 479         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
 480                      (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
 481                      vsync_polarity);
 482
 483         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
 484                      (mode->htotal - mode->hsync_end) & 0xFF);
 485         regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
 486                      (mode->vtotal - mode->vsync_end) & 0xFF);
 487
 488         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
 489                      (mode->hsync_start - mode->hdisplay) & 0xFF);
 490         regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
 491                      (mode->vsync_start - mode->vdisplay) & 0xFF);
 492
 493         usleep_range(10000, 10500); /* 10ms delay recommended by spec */
 494 }
 495
 496 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
 497 {
 498         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 499         unsigned int val;
 500         int ret;
 501
 502         /* DSI_A lane config */
 503         val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
 504         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
 505                            CHA_DSI_LANES_MASK, val);
 506
 507         /* DP lane config */
 508         val = DP_NUM_LANES(pdata->dsi->lanes - 1);
 509         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
 510                            val);
 511
 512         /* set dsi/dp clk frequency value */
 513         ti_sn_bridge_set_dsi_dp_rate(pdata);
 514
 515         /* enable DP PLL */
 516         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
 517
 518         ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
 519                                        val & DPPLL_SRC_DP_PLL_LOCK, 1000,
 520                                        50 * 1000);
 521         if (ret) {
 522                 DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret);
 523                 return;
 524         }
 525
 526         /**
 527          * The SN65DSI86 only supports ASSR Display Authentication method and
 528          * this method is enabled by default. An eDP panel must support this
 529          * authentication method. We need to enable this method in the eDP panel
 530          * at DisplayPort address 0x0010A prior to link training.
 531          */
 532         drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
 533                            DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
 534
 535         /* Semi auto link training mode */
 536         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
 537         ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
 538                                        val == ML_TX_MAIN_LINK_OFF ||
 539                                        val == ML_TX_NORMAL_MODE, 1000,
 540                                        500 * 1000);
 541         if (ret) {
 542                 DRM_ERROR("Training complete polling failed (%d)\n", ret);
 543                 return;
 544         } else if (val == ML_TX_MAIN_LINK_OFF) {
 545                 DRM_ERROR("Link training failed, link is off\n");
 546                 return;
 547         }
 548
 549         /* config video parameters */
 550         ti_sn_bridge_set_video_timings(pdata);
 551
 552         /* enable video stream */
 553         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
 554                            VSTREAM_ENABLE);
 555
 556         drm_panel_enable(pdata->panel);
 557 }
 558
 559 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
 560 {
 561         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 562
 563         pm_runtime_get_sync(pdata->dev);
 564
 565         /* configure bridge ref_clk */
 566         ti_sn_bridge_set_refclk_freq(pdata);
 567
 568         /*
 569          * HPD on this bridge chip is a bit useless.  This is an eDP bridge
 570          * so the HPD is an internal signal that's only there to signal that
 571          * the panel is done powering up.  ...but the bridge chip debounces
 572          * this signal by between 100 ms and 400 ms (depending on process,
 573          * voltage, and temperate--I measured it at about 200 ms).  One
 574          * particular panel asserted HPD 84 ms after it was powered on meaning
 575          * that we saw HPD 284 ms after power on.  ...but the same panel said
 576          * that instead of looking at HPD you could just hardcode a delay of
 577          * 200 ms.  We'll assume that the panel driver will have the hardcoded
 578          * delay in its prepare and always disable HPD.
 579          *
 580          * If HPD somehow makes sense on some future panel we'll have to
 581          * change this to be conditional on someone specifying that HPD should
 582          * be used.
 583          */
 584         regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
 585                            HPD_DISABLE);
 586
 587         drm_panel_prepare(pdata->panel);
 588 }
 589
 590 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
 591 {
 592         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 593
 594         if (pdata->refclk)
 595                 clk_disable_unprepare(pdata->refclk);
 596
 597         pm_runtime_put_sync(pdata->dev);
 598 }
 599
 600 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
 601         .attach = ti_sn_bridge_attach,
 602         .pre_enable = ti_sn_bridge_pre_enable,
 603         .enable = ti_sn_bridge_enable,
 604         .disable = ti_sn_bridge_disable,
 605         .post_disable = ti_sn_bridge_post_disable,
 606 };
 607
 608 static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
 609 {
 610         return container_of(aux, struct ti_sn_bridge, aux);
 611 }
 612
 613 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
 614                                   struct drm_dp_aux_msg *msg)
 615 {
 616         struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
 617         u32 request = msg->request & ~DP_AUX_I2C_MOT;
 618         u32 request_val = AUX_CMD_REQ(msg->request);
 619         u8 *buf = (u8 *)msg->buffer;
 620         unsigned int val;
 621         int ret, i;
 622
 623         if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
 624                 return -EINVAL;
 625
 626         switch (request) {
 627         case DP_AUX_NATIVE_WRITE:
 628         case DP_AUX_I2C_WRITE:
 629         case DP_AUX_NATIVE_READ:
 630         case DP_AUX_I2C_READ:
 631                 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
 632                 break;
 633         default:
 634                 return -EINVAL;
 635         }
 636
 637         regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
 638                      (msg->address >> 16) & 0xF);
 639         regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
 640                      (msg->address >> 8) & 0xFF);
 641         regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
 642
 643         regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
 644
 645         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
 646                 for (i = 0; i < msg->size; i++)
 647                         regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
 648                                      buf[i]);
 649         }
 650
 651         regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
 652
 653         ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
 654                                        !(val & AUX_CMD_SEND), 200,
 655                                        50 * 1000);
 656         if (ret)
 657                 return ret;
 658
 659         ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
 660         if (ret)
 661                 return ret;
 662         else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
 663                  || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
 664                  || (val & AUX_IRQ_STATUS_AUX_SHORT))
 665                 return -ENXIO;
 666
 667         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
 668                 return msg->size;
 669
 670         for (i = 0; i < msg->size; i++) {
 671                 unsigned int val;
 672                 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
 673                                   &val);
 674                 if (ret)
 675                         return ret;
 676
 677                 WARN_ON(val & ~0xFF);
 678                 buf[i] = (u8)(val & 0xFF);
 679         }
 680
 681         return msg->size;
 682 }
 683
 684 static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
 685 {
 686         struct device_node *np = pdata->dev->of_node;
 687
 688         pdata->host_node = of_graph_get_remote_node(np, 0, 0);
 689
 690         if (!pdata->host_node) {
 691                 DRM_ERROR("remote dsi host node not found\n");
 692                 return -ENODEV;
 693         }
 694
 695         return 0;
 696 }
 697
 698 static int ti_sn_bridge_probe(struct i2c_client *client,
 699                               const struct i2c_device_id *id)
 700 {
 701         struct ti_sn_bridge *pdata;
 702         int ret;
 703
 704         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
 705                 DRM_ERROR("device doesn't support I2C\n");
 706                 return -ENODEV;
 707         }
 708
 709         pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
 710                              GFP_KERNEL);
 711         if (!pdata)
 712                 return -ENOMEM;
 713
 714         pdata->regmap = devm_regmap_init_i2c(client,
 715                                              &ti_sn_bridge_regmap_config);
 716         if (IS_ERR(pdata->regmap)) {
 717                 DRM_ERROR("regmap i2c init failed\n");
 718                 return PTR_ERR(pdata->regmap);
 719         }
 720
 721         pdata->dev = &client->dev;
 722
 723         ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
 724                                           &pdata->panel, NULL);
 725         if (ret) {
 726                 DRM_ERROR("could not find any panel node\n");
 727                 return ret;
 728         }
 729
 730         dev_set_drvdata(&client->dev, pdata);
 731
 732         pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
 733                                             GPIOD_OUT_LOW);
 734         if (IS_ERR(pdata->enable_gpio)) {
 735                 DRM_ERROR("failed to get enable gpio from DT\n");
 736                 ret = PTR_ERR(pdata->enable_gpio);
 737                 return ret;
 738         }
 739
 740         ret = ti_sn_bridge_parse_regulators(pdata);
 741         if (ret) {
 742                 DRM_ERROR("failed to parse regulators\n");
 743                 return ret;
 744         }
 745
 746         pdata->refclk = devm_clk_get(pdata->dev, "refclk");
 747         if (IS_ERR(pdata->refclk)) {
 748                 ret = PTR_ERR(pdata->refclk);
 749                 if (ret == -EPROBE_DEFER)
 750                         return ret;
 751                 DRM_DEBUG_KMS("refclk not found\n");
 752                 pdata->refclk = NULL;
 753         }
 754
 755         ret = ti_sn_bridge_parse_dsi_host(pdata);
 756         if (ret)
 757                 return ret;
 758
 759         pm_runtime_enable(pdata->dev);
 760
 761         i2c_set_clientdata(client, pdata);
 762
 763         pdata->aux.name = "ti-sn65dsi86-aux";
 764         pdata->aux.dev = pdata->dev;
 765         pdata->aux.transfer = ti_sn_aux_transfer;
 766         drm_dp_aux_register(&pdata->aux);
 767
 768         pdata->bridge.funcs = &ti_sn_bridge_funcs;
 769         pdata->bridge.of_node = client->dev.of_node;
 770
 771         drm_bridge_add(&pdata->bridge);
 772
 773         ti_sn_debugfs_init(pdata);
 774
 775         return 0;
 776 }
 777
 778 static int ti_sn_bridge_remove(struct i2c_client *client)
 779 {
 780         struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
 781
 782         if (!pdata)
 783                 return -EINVAL;
 784
 785         ti_sn_debugfs_remove(pdata);
 786
 787         of_node_put(pdata->host_node);
 788
 789         pm_runtime_disable(pdata->dev);
 790
 791         if (pdata->dsi) {
 792                 mipi_dsi_detach(pdata->dsi);
 793                 mipi_dsi_device_unregister(pdata->dsi);
 794         }
 795
 796         drm_bridge_remove(&pdata->bridge);
 797
 798         return 0;
 799 }
 800
 801 static struct i2c_device_id ti_sn_bridge_id[] = {
 802         { "ti,sn65dsi86", 0},
 803         {},
 804 };
 805 MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
 806
 807 static const struct of_device_id ti_sn_bridge_match_table[] = {
 808         {.compatible = "ti,sn65dsi86"},
 809         {},
 810 };
 811 MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
 812
 813 static struct i2c_driver ti_sn_bridge_driver = {
 814         .driver = {
 815                 .name = "ti_sn65dsi86",
 816                 .of_match_table = ti_sn_bridge_match_table,
 817                 .pm = &ti_sn_bridge_pm_ops,
 818         },
 819         .probe = ti_sn_bridge_probe,
 820         .remove = ti_sn_bridge_remove,
 821         .id_table = ti_sn_bridge_id,
 822 };
 823 module_i2c_driver(ti_sn_bridge_driver);
 824
 825 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
 826 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
 827 MODULE_LICENSE("GPL v2");