1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: http://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
8 #include <linux/debugfs.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/i2c.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/of_graph.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_dp_helper.h>
21 #include <drm/drm_mipi_dsi.h>
22 #include <drm/drm_of.h>
23 #include <drm/drm_panel.h>
24 #include <drm/drm_print.h>
25 #include <drm/drm_probe_helper.h>
27 #define SN_DEVICE_REV_REG 0x08
28 #define SN_DPPLL_SRC_REG 0x0A
29 #define DPPLL_CLK_SRC_DSICLK BIT(0)
30 #define REFCLK_FREQ_MASK GENMASK(3, 1)
31 #define REFCLK_FREQ(x) ((x) << 1)
32 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
33 #define SN_PLL_ENABLE_REG 0x0D
34 #define SN_DSI_LANES_REG 0x10
35 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
36 #define CHA_DSI_LANES(x) ((x) << 3)
37 #define SN_DSIA_CLK_FREQ_REG 0x12
38 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
39 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
40 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
41 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
42 #define CHA_HSYNC_POLARITY BIT(7)
43 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
44 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
45 #define CHA_VSYNC_POLARITY BIT(7)
46 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
47 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
48 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
49 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
50 #define SN_ENH_FRAME_REG 0x5A
51 #define VSTREAM_ENABLE BIT(3)
52 #define SN_DATA_FORMAT_REG 0x5B
53 #define SN_HPD_DISABLE_REG 0x5C
54 #define HPD_DISABLE BIT(0)
55 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
56 #define SN_AUX_ADDR_19_16_REG 0x74
57 #define SN_AUX_ADDR_15_8_REG 0x75
58 #define SN_AUX_ADDR_7_0_REG 0x76
59 #define SN_AUX_LENGTH_REG 0x77
60 #define SN_AUX_CMD_REG 0x78
61 #define AUX_CMD_SEND BIT(0)
62 #define AUX_CMD_REQ(x) ((x) << 4)
63 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
64 #define SN_SSC_CONFIG_REG 0x93
65 #define DP_NUM_LANES_MASK GENMASK(5, 4)
66 #define DP_NUM_LANES(x) ((x) << 4)
67 #define SN_DATARATE_CONFIG_REG 0x94
68 #define DP_DATARATE_MASK GENMASK(7, 5)
69 #define DP_DATARATE(x) ((x) << 5)
70 #define SN_ML_TX_MODE_REG 0x96
71 #define ML_TX_MAIN_LINK_OFF 0
72 #define ML_TX_NORMAL_MODE BIT(0)
73 #define SN_AUX_CMD_STATUS_REG 0xF4
74 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
75 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
76 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
78 #define MIN_DSI_CLK_FREQ_MHZ 40
80 /* fudge factor required to account for 8b/10b encoding */
81 #define DP_CLK_FUDGE_NUM 10
82 #define DP_CLK_FUDGE_DEN 8
84 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
85 #define SN_AUX_MAX_PAYLOAD_BYTES 16
87 #define SN_REGULATOR_SUPPLY_NUM 4
91 struct regmap *regmap;
92 struct drm_dp_aux aux;
93 struct drm_bridge bridge;
94 struct drm_connector connector;
95 struct dentry *debugfs;
96 struct device_node *host_node;
97 struct mipi_dsi_device *dsi;
99 struct drm_panel *panel;
100 struct gpio_desc *enable_gpio;
101 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
104 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
105 { .range_min = 0, .range_max = 0xFF },
108 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
109 .yes_ranges = ti_sn_bridge_volatile_ranges,
110 .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
113 static const struct regmap_config ti_sn_bridge_regmap_config = {
116 .volatile_table = &ti_sn_bridge_volatile_table,
117 .cache_type = REGCACHE_NONE,
120 static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
121 unsigned int reg, u16 val)
123 regmap_write(pdata->regmap, reg, val & 0xFF);
124 regmap_write(pdata->regmap, reg + 1, val >> 8);
127 static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
129 struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
132 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
134 DRM_ERROR("failed to enable supplies %d\n", ret);
138 gpiod_set_value(pdata->enable_gpio, 1);
143 static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
145 struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
148 gpiod_set_value(pdata->enable_gpio, 0);
150 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
152 DRM_ERROR("failed to disable supplies %d\n", ret);
157 static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
158 SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
161 static int status_show(struct seq_file *s, void *data)
163 struct ti_sn_bridge *pdata = s->private;
164 unsigned int reg, val;
166 seq_puts(s, "STATUS REGISTERS:\n");
168 pm_runtime_get_sync(pdata->dev);
170 /* IRQ Status Registers, see Table 31 in datasheet */
171 for (reg = 0xf0; reg <= 0xf8; reg++) {
172 regmap_read(pdata->regmap, reg, &val);
173 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
176 pm_runtime_put(pdata->dev);
181 DEFINE_SHOW_ATTRIBUTE(status);
183 static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
185 pdata->debugfs = debugfs_create_dir("ti_sn65dsi86", NULL);
187 debugfs_create_file("status", 0600, pdata->debugfs, pdata,
191 static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
193 debugfs_remove_recursive(pdata->debugfs);
194 pdata->debugfs = NULL;
197 /* Connector funcs */
198 static struct ti_sn_bridge *
199 connector_to_ti_sn_bridge(struct drm_connector *connector)
201 return container_of(connector, struct ti_sn_bridge, connector);
204 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
206 struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
208 return drm_panel_get_modes(pdata->panel);
211 static enum drm_mode_status
212 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
213 struct drm_display_mode *mode)
215 /* maximum supported resolution is 4K at 60 fps */
216 if (mode->clock > 594000)
217 return MODE_CLOCK_HIGH;
222 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
223 .get_modes = ti_sn_bridge_connector_get_modes,
224 .mode_valid = ti_sn_bridge_connector_mode_valid,
227 static enum drm_connector_status
228 ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
231 * TODO: Currently if drm_panel is present, then always
232 * return the status as connected. Need to add support to detect
233 * device state for hot pluggable scenarios.
235 return connector_status_connected;
238 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
239 .fill_modes = drm_helper_probe_single_connector_modes,
240 .detect = ti_sn_bridge_connector_detect,
241 .destroy = drm_connector_cleanup,
242 .reset = drm_atomic_helper_connector_reset,
243 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
244 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
247 static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
249 return container_of(bridge, struct ti_sn_bridge, bridge);
252 static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
255 const char * const ti_sn_bridge_supply_names[] = {
256 "vcca", "vcc", "vccio", "vpll",
259 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
260 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
262 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
266 static int ti_sn_bridge_attach(struct drm_bridge *bridge)
269 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
270 struct mipi_dsi_host *host;
271 struct mipi_dsi_device *dsi;
272 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
277 ret = drm_connector_init(bridge->dev, &pdata->connector,
278 &ti_sn_bridge_connector_funcs,
279 DRM_MODE_CONNECTOR_eDP);
281 DRM_ERROR("Failed to initialize connector with drm\n");
285 drm_connector_helper_add(&pdata->connector,
286 &ti_sn_bridge_connector_helper_funcs);
287 drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
290 * TODO: ideally finding host resource and dsi dev registration needs
291 * to be done in bridge probe. But some existing DSI host drivers will
292 * wait for any of the drm_bridge/drm_panel to get added to the global
293 * bridge/panel list, before completing their probe. So if we do the
294 * dsi dev registration part in bridge probe, before populating in
295 * the global bridge list, then it will cause deadlock as dsi host probe
296 * will never complete, neither our bridge probe. So keeping it here
297 * will satisfy most of the existing host drivers. Once the host driver
298 * is fixed we can move the below code to bridge probe safely.
300 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
302 DRM_ERROR("failed to find dsi host\n");
307 dsi = mipi_dsi_device_register_full(host, &info);
309 DRM_ERROR("failed to create dsi device\n");
314 /* TODO: setting to 4 lanes always for now */
316 dsi->format = MIPI_DSI_FMT_RGB888;
317 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
319 /* check if continuous dsi clock is required or not */
320 pm_runtime_get_sync(pdata->dev);
321 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
322 pm_runtime_put(pdata->dev);
323 if (!(val & DPPLL_CLK_SRC_DSICLK))
324 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
326 ret = mipi_dsi_attach(dsi);
328 DRM_ERROR("failed to attach dsi to host\n");
333 /* attach panel to bridge */
334 drm_panel_attach(pdata->panel, &pdata->connector);
339 mipi_dsi_device_unregister(dsi);
341 drm_connector_cleanup(&pdata->connector);
345 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
347 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
349 drm_panel_disable(pdata->panel);
351 /* disable video stream */
352 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
353 /* semi auto link training mode OFF */
354 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
356 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
358 drm_panel_unprepare(pdata->panel);
361 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
363 u32 bit_rate_khz, clk_freq_khz;
364 struct drm_display_mode *mode =
365 &pdata->bridge.encoder->crtc->state->adjusted_mode;
367 bit_rate_khz = mode->clock *
368 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
369 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
374 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
375 static const u32 ti_sn_bridge_refclk_lut[] = {
383 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
384 static const u32 ti_sn_bridge_dsiclk_lut[] = {
392 static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
396 const u32 *refclk_lut;
397 size_t refclk_lut_size;
400 refclk_rate = clk_get_rate(pdata->refclk);
401 refclk_lut = ti_sn_bridge_refclk_lut;
402 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
403 clk_prepare_enable(pdata->refclk);
405 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
406 refclk_lut = ti_sn_bridge_dsiclk_lut;
407 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
410 /* for i equals to refclk_lut_size means default frequency */
411 for (i = 0; i < refclk_lut_size; i++)
412 if (refclk_lut[i] == refclk_rate)
415 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
420 * LUT index corresponds to register value and
421 * LUT values corresponds to dp data rate supported
422 * by the bridge in Mbps unit.
424 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
425 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
428 static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
430 unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz;
432 struct drm_display_mode *mode =
433 &pdata->bridge.encoder->crtc->state->adjusted_mode;
435 /* set DSIA clk frequency */
436 bit_rate_mhz = (mode->clock / 1000) *
437 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
438 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
440 /* for each increment in val, frequency increases by 5MHz */
441 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
442 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
443 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
445 /* set DP data rate */
446 dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
448 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
449 if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
452 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
453 DP_DATARATE_MASK, DP_DATARATE(i));
456 static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
458 struct drm_display_mode *mode =
459 &pdata->bridge.encoder->crtc->state->adjusted_mode;
460 u8 hsync_polarity = 0, vsync_polarity = 0;
462 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
463 hsync_polarity = CHA_HSYNC_POLARITY;
464 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
465 vsync_polarity = CHA_VSYNC_POLARITY;
467 ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
469 ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
471 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
472 (mode->hsync_end - mode->hsync_start) & 0xFF);
473 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
474 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
476 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
477 (mode->vsync_end - mode->vsync_start) & 0xFF);
478 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
479 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
482 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
483 (mode->htotal - mode->hsync_end) & 0xFF);
484 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
485 (mode->vtotal - mode->vsync_end) & 0xFF);
487 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
488 (mode->hsync_start - mode->hdisplay) & 0xFF);
489 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
490 (mode->vsync_start - mode->vdisplay) & 0xFF);
492 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
495 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
497 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
501 /* DSI_A lane config */
502 val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
503 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
504 CHA_DSI_LANES_MASK, val);
507 val = DP_NUM_LANES(pdata->dsi->lanes - 1);
508 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
511 /* set dsi/dp clk frequency value */
512 ti_sn_bridge_set_dsi_dp_rate(pdata);
515 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
517 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
518 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
521 DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret);
526 * The SN65DSI86 only supports ASSR Display Authentication method and
527 * this method is enabled by default. An eDP panel must support this
528 * authentication method. We need to enable this method in the eDP panel
529 * at DisplayPort address 0x0010A prior to link training.
531 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
532 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
534 /* Semi auto link training mode */
535 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
536 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
537 val == ML_TX_MAIN_LINK_OFF ||
538 val == ML_TX_NORMAL_MODE, 1000,
541 DRM_ERROR("Training complete polling failed (%d)\n", ret);
543 } else if (val == ML_TX_MAIN_LINK_OFF) {
544 DRM_ERROR("Link training failed, link is off\n");
548 /* config video parameters */
549 ti_sn_bridge_set_video_timings(pdata);
551 /* enable video stream */
552 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
555 drm_panel_enable(pdata->panel);
558 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
560 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
562 pm_runtime_get_sync(pdata->dev);
564 /* configure bridge ref_clk */
565 ti_sn_bridge_set_refclk_freq(pdata);
568 * HPD on this bridge chip is a bit useless. This is an eDP bridge
569 * so the HPD is an internal signal that's only there to signal that
570 * the panel is done powering up. ...but the bridge chip debounces
571 * this signal by between 100 ms and 400 ms (depending on process,
572 * voltage, and temperate--I measured it at about 200 ms). One
573 * particular panel asserted HPD 84 ms after it was powered on meaning
574 * that we saw HPD 284 ms after power on. ...but the same panel said
575 * that instead of looking at HPD you could just hardcode a delay of
576 * 200 ms. We'll assume that the panel driver will have the hardcoded
577 * delay in its prepare and always disable HPD.
579 * If HPD somehow makes sense on some future panel we'll have to
580 * change this to be conditional on someone specifying that HPD should
583 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
586 drm_panel_prepare(pdata->panel);
589 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
591 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
594 clk_disable_unprepare(pdata->refclk);
596 pm_runtime_put_sync(pdata->dev);
599 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
600 .attach = ti_sn_bridge_attach,
601 .pre_enable = ti_sn_bridge_pre_enable,
602 .enable = ti_sn_bridge_enable,
603 .disable = ti_sn_bridge_disable,
604 .post_disable = ti_sn_bridge_post_disable,
607 static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
609 return container_of(aux, struct ti_sn_bridge, aux);
612 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
613 struct drm_dp_aux_msg *msg)
615 struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
616 u32 request = msg->request & ~DP_AUX_I2C_MOT;
617 u32 request_val = AUX_CMD_REQ(msg->request);
618 u8 *buf = (u8 *)msg->buffer;
622 if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
626 case DP_AUX_NATIVE_WRITE:
627 case DP_AUX_I2C_WRITE:
628 case DP_AUX_NATIVE_READ:
629 case DP_AUX_I2C_READ:
630 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
636 regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
637 (msg->address >> 16) & 0xF);
638 regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
639 (msg->address >> 8) & 0xFF);
640 regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
642 regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
644 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
645 for (i = 0; i < msg->size; i++)
646 regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
650 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
652 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
653 !(val & AUX_CMD_SEND), 200,
658 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
661 else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
662 || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
663 || (val & AUX_IRQ_STATUS_AUX_SHORT))
666 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
669 for (i = 0; i < msg->size; i++) {
671 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
676 WARN_ON(val & ~0xFF);
677 buf[i] = (u8)(val & 0xFF);
683 static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
685 struct device_node *np = pdata->dev->of_node;
687 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
689 if (!pdata->host_node) {
690 DRM_ERROR("remote dsi host node not found\n");
697 static int ti_sn_bridge_probe(struct i2c_client *client,
698 const struct i2c_device_id *id)
700 struct ti_sn_bridge *pdata;
703 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
704 DRM_ERROR("device doesn't support I2C\n");
708 pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
713 pdata->regmap = devm_regmap_init_i2c(client,
714 &ti_sn_bridge_regmap_config);
715 if (IS_ERR(pdata->regmap)) {
716 DRM_ERROR("regmap i2c init failed\n");
717 return PTR_ERR(pdata->regmap);
720 pdata->dev = &client->dev;
722 ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
723 &pdata->panel, NULL);
725 DRM_ERROR("could not find any panel node\n");
729 dev_set_drvdata(&client->dev, pdata);
731 pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
733 if (IS_ERR(pdata->enable_gpio)) {
734 DRM_ERROR("failed to get enable gpio from DT\n");
735 ret = PTR_ERR(pdata->enable_gpio);
739 ret = ti_sn_bridge_parse_regulators(pdata);
741 DRM_ERROR("failed to parse regulators\n");
745 pdata->refclk = devm_clk_get(pdata->dev, "refclk");
746 if (IS_ERR(pdata->refclk)) {
747 ret = PTR_ERR(pdata->refclk);
748 if (ret == -EPROBE_DEFER)
750 DRM_DEBUG_KMS("refclk not found\n");
751 pdata->refclk = NULL;
754 ret = ti_sn_bridge_parse_dsi_host(pdata);
758 pm_runtime_enable(pdata->dev);
760 i2c_set_clientdata(client, pdata);
762 pdata->aux.name = "ti-sn65dsi86-aux";
763 pdata->aux.dev = pdata->dev;
764 pdata->aux.transfer = ti_sn_aux_transfer;
765 drm_dp_aux_register(&pdata->aux);
767 pdata->bridge.funcs = &ti_sn_bridge_funcs;
768 pdata->bridge.of_node = client->dev.of_node;
770 drm_bridge_add(&pdata->bridge);
772 ti_sn_debugfs_init(pdata);
777 static int ti_sn_bridge_remove(struct i2c_client *client)
779 struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
784 ti_sn_debugfs_remove(pdata);
786 of_node_put(pdata->host_node);
788 pm_runtime_disable(pdata->dev);
791 mipi_dsi_detach(pdata->dsi);
792 mipi_dsi_device_unregister(pdata->dsi);
795 drm_bridge_remove(&pdata->bridge);
800 static struct i2c_device_id ti_sn_bridge_id[] = {
801 { "ti,sn65dsi86", 0},
804 MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
806 static const struct of_device_id ti_sn_bridge_match_table[] = {
807 {.compatible = "ti,sn65dsi86"},
810 MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
812 static struct i2c_driver ti_sn_bridge_driver = {
814 .name = "ti_sn65dsi86",
815 .of_match_table = ti_sn_bridge_match_table,
816 .pm = &ti_sn_bridge_pm_ops,
818 .probe = ti_sn_bridge_probe,
819 .remove = ti_sn_bridge_remove,
820 .id_table = ti_sn_bridge_id,
822 module_i2c_driver(ti_sn_bridge_driver);
824 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
825 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
826 MODULE_LICENSE("GPL v2");