drivers/gpu/drm/bridge/ti-sn65dsi86.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  * datasheet: http://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/gpio/consumer.h>
   9 #include <linux/i2c.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/module.h>
  12 #include <linux/of_graph.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/regmap.h>
  15 #include <linux/regulator/consumer.h>
  16
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_dp_helper.h>
  20 #include <drm/drm_mipi_dsi.h>
  21 #include <drm/drm_of.h>
  22 #include <drm/drm_panel.h>
  23 #include <drm/drm_print.h>
  24 #include <drm/drm_probe_helper.h>
  25
  26 #define SN_DEVICE_REV_REG                       0x08
  27 #define SN_DPPLL_SRC_REG                        0x0A
  28 #define  DPPLL_CLK_SRC_DSICLK                   BIT(0)
  29 #define  REFCLK_FREQ_MASK                       GENMASK(3, 1)
  30 #define  REFCLK_FREQ(x)                         ((x) << 1)
  31 #define  DPPLL_SRC_DP_PLL_LOCK                  BIT(7)
  32 #define SN_PLL_ENABLE_REG                       0x0D
  33 #define SN_DSI_LANES_REG                        0x10
  34 #define  CHA_DSI_LANES_MASK                     GENMASK(4, 3)
  35 #define  CHA_DSI_LANES(x)                       ((x) << 3)
  36 #define SN_DSIA_CLK_FREQ_REG                    0x12
  37 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG       0x20
  38 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG    0x24
  39 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG        0x2C
  40 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG       0x2D
  41 #define  CHA_HSYNC_POLARITY                     BIT(7)
  42 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG        0x30
  43 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG       0x31
  44 #define  CHA_VSYNC_POLARITY                     BIT(7)
  45 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG        0x34
  46 #define SN_CHA_VERTICAL_BACK_PORCH_REG          0x36
  47 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG       0x38
  48 #define SN_CHA_VERTICAL_FRONT_PORCH_REG         0x3A
  49 #define SN_ENH_FRAME_REG                        0x5A
  50 #define  VSTREAM_ENABLE                         BIT(3)
  51 #define SN_DATA_FORMAT_REG                      0x5B
  52 #define SN_HPD_DISABLE_REG                      0x5C
  53 #define  HPD_DISABLE                            BIT(0)
  54 #define SN_AUX_WDATA_REG(x)                     (0x64 + (x))
  55 #define SN_AUX_ADDR_19_16_REG                   0x74
  56 #define SN_AUX_ADDR_15_8_REG                    0x75
  57 #define SN_AUX_ADDR_7_0_REG                     0x76
  58 #define SN_AUX_LENGTH_REG                       0x77
  59 #define SN_AUX_CMD_REG                          0x78
  60 #define  AUX_CMD_SEND                           BIT(0)
  61 #define  AUX_CMD_REQ(x)                         ((x) << 4)
  62 #define SN_AUX_RDATA_REG(x)                     (0x79 + (x))
  63 #define SN_SSC_CONFIG_REG                       0x93
  64 #define  DP_NUM_LANES_MASK                      GENMASK(5, 4)
  65 #define  DP_NUM_LANES(x)                        ((x) << 4)
  66 #define SN_DATARATE_CONFIG_REG                  0x94
  67 #define  DP_DATARATE_MASK                       GENMASK(7, 5)
  68 #define  DP_DATARATE(x)                         ((x) << 5)
  69 #define SN_ML_TX_MODE_REG                       0x96
  70 #define  ML_TX_MAIN_LINK_OFF                    0
  71 #define  ML_TX_NORMAL_MODE                      BIT(0)
  72 #define SN_AUX_CMD_STATUS_REG                   0xF4
  73 #define  AUX_IRQ_STATUS_AUX_RPLY_TOUT           BIT(3)
  74 #define  AUX_IRQ_STATUS_AUX_SHORT               BIT(5)
  75 #define  AUX_IRQ_STATUS_NAT_I2C_FAIL            BIT(6)
  76
  77 #define MIN_DSI_CLK_FREQ_MHZ    40
  78
  79 /* fudge factor required to account for 8b/10b encoding */
  80 #define DP_CLK_FUDGE_NUM        10
  81 #define DP_CLK_FUDGE_DEN        8
  82
  83 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
  84 #define SN_AUX_MAX_PAYLOAD_BYTES        16
  85
  86 #define SN_REGULATOR_SUPPLY_NUM         4
  87
  88 struct ti_sn_bridge {
  89         struct device                   *dev;
  90         struct regmap                   *regmap;
  91         struct drm_dp_aux               aux;
  92         struct drm_bridge               bridge;
  93         struct drm_connector            connector;
  94         struct device_node              *host_node;
  95         struct mipi_dsi_device          *dsi;
  96         struct clk                      *refclk;
  97         struct drm_panel                *panel;
  98         struct gpio_desc                *enable_gpio;
  99         struct regulator_bulk_data      supplies[SN_REGULATOR_SUPPLY_NUM];
 100 };
 101
 102 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
 103         { .range_min = 0, .range_max = 0xFF },
 104 };
 105
 106 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
 107         .yes_ranges = ti_sn_bridge_volatile_ranges,
 108         .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
 109 };
 110
 111 static const struct regmap_config ti_sn_bridge_regmap_config = {
 112         .reg_bits = 8,
 113         .val_bits = 8,
 114         .volatile_table = &ti_sn_bridge_volatile_table,
 115         .cache_type = REGCACHE_NONE,
 116 };
 117
 118 static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
 119                                    unsigned int reg, u16 val)
 120 {
 121         regmap_write(pdata->regmap, reg, val & 0xFF);
 122         regmap_write(pdata->regmap, reg + 1, val >> 8);
 123 }
 124
 125 static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
 126 {
 127         struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
 128         int ret;
 129
 130         ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 131         if (ret) {
 132                 DRM_ERROR("failed to enable supplies %d\n", ret);
 133                 return ret;
 134         }
 135
 136         gpiod_set_value(pdata->enable_gpio, 1);
 137
 138         return ret;
 139 }
 140
 141 static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
 142 {
 143         struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
 144         int ret;
 145
 146         gpiod_set_value(pdata->enable_gpio, 0);
 147
 148         ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 149         if (ret)
 150                 DRM_ERROR("failed to disable supplies %d\n", ret);
 151
 152         return ret;
 153 }
 154
 155 static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
 156         SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
 157 };
 158
 159 /* Connector funcs */
 160 static struct ti_sn_bridge *
 161 connector_to_ti_sn_bridge(struct drm_connector *connector)
 162 {
 163         return container_of(connector, struct ti_sn_bridge, connector);
 164 }
 165
 166 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
 167 {
 168         struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
 169
 170         return drm_panel_get_modes(pdata->panel);
 171 }
 172
 173 static enum drm_mode_status
 174 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
 175                                   struct drm_display_mode *mode)
 176 {
 177         /* maximum supported resolution is 4K at 60 fps */
 178         if (mode->clock > 594000)
 179                 return MODE_CLOCK_HIGH;
 180
 181         return MODE_OK;
 182 }
 183
 184 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
 185         .get_modes = ti_sn_bridge_connector_get_modes,
 186         .mode_valid = ti_sn_bridge_connector_mode_valid,
 187 };
 188
 189 static enum drm_connector_status
 190 ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
 191 {
 192         /**
 193          * TODO: Currently if drm_panel is present, then always
 194          * return the status as connected. Need to add support to detect
 195          * device state for hot pluggable scenarios.
 196          */
 197         return connector_status_connected;
 198 }
 199
 200 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
 201         .fill_modes = drm_helper_probe_single_connector_modes,
 202         .detect = ti_sn_bridge_connector_detect,
 203         .destroy = drm_connector_cleanup,
 204         .reset = drm_atomic_helper_connector_reset,
 205         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 206         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 207 };
 208
 209 static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
 210 {
 211         return container_of(bridge, struct ti_sn_bridge, bridge);
 212 }
 213
 214 static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
 215 {
 216         unsigned int i;
 217         const char * const ti_sn_bridge_supply_names[] = {
 218                 "vcca", "vcc", "vccio", "vpll",
 219         };
 220
 221         for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
 222                 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
 223
 224         return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
 225                                        pdata->supplies);
 226 }
 227
 228 static int ti_sn_bridge_attach(struct drm_bridge *bridge)
 229 {
 230         int ret, val;
 231         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 232         struct mipi_dsi_host *host;
 233         struct mipi_dsi_device *dsi;
 234         const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
 235                                                    .channel = 0,
 236                                                    .node = NULL,
 237                                                  };
 238
 239         ret = drm_connector_init(bridge->dev, &pdata->connector,
 240                                  &ti_sn_bridge_connector_funcs,
 241                                  DRM_MODE_CONNECTOR_eDP);
 242         if (ret) {
 243                 DRM_ERROR("Failed to initialize connector with drm\n");
 244                 return ret;
 245         }
 246
 247         drm_connector_helper_add(&pdata->connector,
 248                                  &ti_sn_bridge_connector_helper_funcs);
 249         drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
 250
 251         /*
 252          * TODO: ideally finding host resource and dsi dev registration needs
 253          * to be done in bridge probe. But some existing DSI host drivers will
 254          * wait for any of the drm_bridge/drm_panel to get added to the global
 255          * bridge/panel list, before completing their probe. So if we do the
 256          * dsi dev registration part in bridge probe, before populating in
 257          * the global bridge list, then it will cause deadlock as dsi host probe
 258          * will never complete, neither our bridge probe. So keeping it here
 259          * will satisfy most of the existing host drivers. Once the host driver
 260          * is fixed we can move the below code to bridge probe safely.
 261          */
 262         host = of_find_mipi_dsi_host_by_node(pdata->host_node);
 263         if (!host) {
 264                 DRM_ERROR("failed to find dsi host\n");
 265                 ret = -ENODEV;
 266                 goto err_dsi_host;
 267         }
 268
 269         dsi = mipi_dsi_device_register_full(host, &info);
 270         if (IS_ERR(dsi)) {
 271                 DRM_ERROR("failed to create dsi device\n");
 272                 ret = PTR_ERR(dsi);
 273                 goto err_dsi_host;
 274         }
 275
 276         /* TODO: setting to 4 lanes always for now */
 277         dsi->lanes = 4;
 278         dsi->format = MIPI_DSI_FMT_RGB888;
 279         dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
 280                           MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
 281
 282         /* check if continuous dsi clock is required or not */
 283         pm_runtime_get_sync(pdata->dev);
 284         regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
 285         pm_runtime_put(pdata->dev);
 286         if (!(val & DPPLL_CLK_SRC_DSICLK))
 287                 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
 288
 289         ret = mipi_dsi_attach(dsi);
 290         if (ret < 0) {
 291                 DRM_ERROR("failed to attach dsi to host\n");
 292                 goto err_dsi_attach;
 293         }
 294         pdata->dsi = dsi;
 295
 296         /* attach panel to bridge */
 297         drm_panel_attach(pdata->panel, &pdata->connector);
 298
 299         return 0;
 300
 301 err_dsi_attach:
 302         mipi_dsi_device_unregister(dsi);
 303 err_dsi_host:
 304         drm_connector_cleanup(&pdata->connector);
 305         return ret;
 306 }
 307
 308 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
 309 {
 310         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 311
 312         drm_panel_disable(pdata->panel);
 313
 314         /* disable video stream */
 315         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
 316         /* semi auto link training mode OFF */
 317         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
 318         /* disable DP PLL */
 319         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
 320
 321         drm_panel_unprepare(pdata->panel);
 322 }
 323
 324 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
 325 {
 326         u32 bit_rate_khz, clk_freq_khz;
 327         struct drm_display_mode *mode =
 328                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 329
 330         bit_rate_khz = mode->clock *
 331                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 332         clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
 333
 334         return clk_freq_khz;
 335 }
 336
 337 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
 338 static const u32 ti_sn_bridge_refclk_lut[] = {
 339         12000000,
 340         19200000,
 341         26000000,
 342         27000000,
 343         38400000,
 344 };
 345
 346 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
 347 static const u32 ti_sn_bridge_dsiclk_lut[] = {
 348         468000000,
 349         384000000,
 350         416000000,
 351         486000000,
 352         460800000,
 353 };
 354
 355 static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
 356 {
 357         int i;
 358         u32 refclk_rate;
 359         const u32 *refclk_lut;
 360         size_t refclk_lut_size;
 361
 362         if (pdata->refclk) {
 363                 refclk_rate = clk_get_rate(pdata->refclk);
 364                 refclk_lut = ti_sn_bridge_refclk_lut;
 365                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
 366                 clk_prepare_enable(pdata->refclk);
 367         } else {
 368                 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
 369                 refclk_lut = ti_sn_bridge_dsiclk_lut;
 370                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
 371         }
 372
 373         /* for i equals to refclk_lut_size means default frequency */
 374         for (i = 0; i < refclk_lut_size; i++)
 375                 if (refclk_lut[i] == refclk_rate)
 376                         break;
 377
 378         regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
 379                            REFCLK_FREQ(i));
 380 }
 381
 382 /**
 383  * LUT index corresponds to register value and
 384  * LUT values corresponds to dp data rate supported
 385  * by the bridge in Mbps unit.
 386  */
 387 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
 388         0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 389 };
 390
 391 static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
 392 {
 393         unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz;
 394         unsigned int val, i;
 395         struct drm_display_mode *mode =
 396                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 397
 398         /* set DSIA clk frequency */
 399         bit_rate_mhz = (mode->clock / 1000) *
 400                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 401         clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
 402
 403         /* for each increment in val, frequency increases by 5MHz */
 404         val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
 405                 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
 406         regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 407
 408         /* set DP data rate */
 409         dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
 410                                                         DP_CLK_FUDGE_DEN;
 411         for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 412                 if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
 413                         break;
 414
 415         regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
 416                            DP_DATARATE_MASK, DP_DATARATE(i));
 417 }
 418
 419 static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
 420 {
 421         struct drm_display_mode *mode =
 422                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 423         u8 hsync_polarity = 0, vsync_polarity = 0;
 424
 425         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 426                 hsync_polarity = CHA_HSYNC_POLARITY;
 427         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 428                 vsync_polarity = CHA_VSYNC_POLARITY;
 429
 430         ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
 431                                mode->hdisplay);
 432         ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
 433                                mode->vdisplay);
 434         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
 435                      (mode->hsync_end - mode->hsync_start) & 0xFF);
 436         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
 437                      (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
 438                      hsync_polarity);
 439         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
 440                      (mode->vsync_end - mode->vsync_start) & 0xFF);
 441         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
 442                      (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
 443                      vsync_polarity);
 444
 445         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
 446                      (mode->htotal - mode->hsync_end) & 0xFF);
 447         regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
 448                      (mode->vtotal - mode->vsync_end) & 0xFF);
 449
 450         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
 451                      (mode->hsync_start - mode->hdisplay) & 0xFF);
 452         regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
 453                      (mode->vsync_start - mode->vdisplay) & 0xFF);
 454
 455         usleep_range(10000, 10500); /* 10ms delay recommended by spec */
 456 }
 457
 458 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
 459 {
 460         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 461         unsigned int val;
 462         int ret;
 463
 464         /* DSI_A lane config */
 465         val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
 466         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
 467                            CHA_DSI_LANES_MASK, val);
 468
 469         /* DP lane config */
 470         val = DP_NUM_LANES(pdata->dsi->lanes - 1);
 471         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
 472                            val);
 473
 474         /* set dsi/dp clk frequency value */
 475         ti_sn_bridge_set_dsi_dp_rate(pdata);
 476
 477         /* enable DP PLL */
 478         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
 479
 480         ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
 481                                        val & DPPLL_SRC_DP_PLL_LOCK, 1000,
 482                                        50 * 1000);
 483         if (ret) {
 484                 DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret);
 485                 return;
 486         }
 487
 488         /**
 489          * The SN65DSI86 only supports ASSR Display Authentication method and
 490          * this method is enabled by default. An eDP panel must support this
 491          * authentication method. We need to enable this method in the eDP panel
 492          * at DisplayPort address 0x0010A prior to link training.
 493          */
 494         drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
 495                            DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
 496
 497         /* Semi auto link training mode */
 498         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
 499         ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
 500                                        val == ML_TX_MAIN_LINK_OFF ||
 501                                        val == ML_TX_NORMAL_MODE, 1000,
 502                                        500 * 1000);
 503         if (ret) {
 504                 DRM_ERROR("Training complete polling failed (%d)\n", ret);
 505                 return;
 506         } else if (val == ML_TX_MAIN_LINK_OFF) {
 507                 DRM_ERROR("Link training failed, link is off\n");
 508                 return;
 509         }
 510
 511         /* config video parameters */
 512         ti_sn_bridge_set_video_timings(pdata);
 513
 514         /* enable video stream */
 515         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
 516                            VSTREAM_ENABLE);
 517
 518         drm_panel_enable(pdata->panel);
 519 }
 520
 521 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
 522 {
 523         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 524
 525         pm_runtime_get_sync(pdata->dev);
 526
 527         /* configure bridge ref_clk */
 528         ti_sn_bridge_set_refclk_freq(pdata);
 529
 530         /*
 531          * HPD on this bridge chip is a bit useless.  This is an eDP bridge
 532          * so the HPD is an internal signal that's only there to signal that
 533          * the panel is done powering up.  ...but the bridge chip debounces
 534          * this signal by between 100 ms and 400 ms (depending on process,
 535          * voltage, and temperate--I measured it at about 200 ms).  One
 536          * particular panel asserted HPD 84 ms after it was powered on meaning
 537          * that we saw HPD 284 ms after power on.  ...but the same panel said
 538          * that instead of looking at HPD you could just hardcode a delay of
 539          * 200 ms.  We'll assume that the panel driver will have the hardcoded
 540          * delay in its prepare and always disable HPD.
 541          *
 542          * If HPD somehow makes sense on some future panel we'll have to
 543          * change this to be conditional on someone specifying that HPD should
 544          * be used.
 545          */
 546         regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
 547                            HPD_DISABLE);
 548
 549         drm_panel_prepare(pdata->panel);
 550 }
 551
 552 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
 553 {
 554         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 555
 556         if (pdata->refclk)
 557                 clk_disable_unprepare(pdata->refclk);
 558
 559         pm_runtime_put_sync(pdata->dev);
 560 }
 561
 562 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
 563         .attach = ti_sn_bridge_attach,
 564         .pre_enable = ti_sn_bridge_pre_enable,
 565         .enable = ti_sn_bridge_enable,
 566         .disable = ti_sn_bridge_disable,
 567         .post_disable = ti_sn_bridge_post_disable,
 568 };
 569
 570 static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
 571 {
 572         return container_of(aux, struct ti_sn_bridge, aux);
 573 }
 574
 575 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
 576                                   struct drm_dp_aux_msg *msg)
 577 {
 578         struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
 579         u32 request = msg->request & ~DP_AUX_I2C_MOT;
 580         u32 request_val = AUX_CMD_REQ(msg->request);
 581         u8 *buf = (u8 *)msg->buffer;
 582         unsigned int val;
 583         int ret, i;
 584
 585         if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
 586                 return -EINVAL;
 587
 588         switch (request) {
 589         case DP_AUX_NATIVE_WRITE:
 590         case DP_AUX_I2C_WRITE:
 591         case DP_AUX_NATIVE_READ:
 592         case DP_AUX_I2C_READ:
 593                 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
 594                 break;
 595         default:
 596                 return -EINVAL;
 597         }
 598
 599         regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
 600                      (msg->address >> 16) & 0xF);
 601         regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
 602                      (msg->address >> 8) & 0xFF);
 603         regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
 604
 605         regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
 606
 607         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
 608                 for (i = 0; i < msg->size; i++)
 609                         regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
 610                                      buf[i]);
 611         }
 612
 613         regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
 614
 615         ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
 616                                        !(val & AUX_CMD_SEND), 200,
 617                                        50 * 1000);
 618         if (ret)
 619                 return ret;
 620
 621         ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
 622         if (ret)
 623                 return ret;
 624         else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
 625                  || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
 626                  || (val & AUX_IRQ_STATUS_AUX_SHORT))
 627                 return -ENXIO;
 628
 629         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
 630                 return msg->size;
 631
 632         for (i = 0; i < msg->size; i++) {
 633                 unsigned int val;
 634                 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
 635                                   &val);
 636                 if (ret)
 637                         return ret;
 638
 639                 WARN_ON(val & ~0xFF);
 640                 buf[i] = (u8)(val & 0xFF);
 641         }
 642
 643         return msg->size;
 644 }
 645
 646 static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
 647 {
 648         struct device_node *np = pdata->dev->of_node;
 649
 650         pdata->host_node = of_graph_get_remote_node(np, 0, 0);
 651
 652         if (!pdata->host_node) {
 653                 DRM_ERROR("remote dsi host node not found\n");
 654                 return -ENODEV;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static int ti_sn_bridge_probe(struct i2c_client *client,
 661                               const struct i2c_device_id *id)
 662 {
 663         struct ti_sn_bridge *pdata;
 664         int ret;
 665
 666         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
 667                 DRM_ERROR("device doesn't support I2C\n");
 668                 return -ENODEV;
 669         }
 670
 671         pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
 672                              GFP_KERNEL);
 673         if (!pdata)
 674                 return -ENOMEM;
 675
 676         pdata->regmap = devm_regmap_init_i2c(client,
 677                                              &ti_sn_bridge_regmap_config);
 678         if (IS_ERR(pdata->regmap)) {
 679                 DRM_ERROR("regmap i2c init failed\n");
 680                 return PTR_ERR(pdata->regmap);
 681         }
 682
 683         pdata->dev = &client->dev;
 684
 685         ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
 686                                           &pdata->panel, NULL);
 687         if (ret) {
 688                 DRM_ERROR("could not find any panel node\n");
 689                 return ret;
 690         }
 691
 692         dev_set_drvdata(&client->dev, pdata);
 693
 694         pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
 695                                             GPIOD_OUT_LOW);
 696         if (IS_ERR(pdata->enable_gpio)) {
 697                 DRM_ERROR("failed to get enable gpio from DT\n");
 698                 ret = PTR_ERR(pdata->enable_gpio);
 699                 return ret;
 700         }
 701
 702         ret = ti_sn_bridge_parse_regulators(pdata);
 703         if (ret) {
 704                 DRM_ERROR("failed to parse regulators\n");
 705                 return ret;
 706         }
 707
 708         pdata->refclk = devm_clk_get(pdata->dev, "refclk");
 709         if (IS_ERR(pdata->refclk)) {
 710                 ret = PTR_ERR(pdata->refclk);
 711                 if (ret == -EPROBE_DEFER)
 712                         return ret;
 713                 DRM_DEBUG_KMS("refclk not found\n");
 714                 pdata->refclk = NULL;
 715         }
 716
 717         ret = ti_sn_bridge_parse_dsi_host(pdata);
 718         if (ret)
 719                 return ret;
 720
 721         pm_runtime_enable(pdata->dev);
 722
 723         i2c_set_clientdata(client, pdata);
 724
 725         pdata->aux.name = "ti-sn65dsi86-aux";
 726         pdata->aux.dev = pdata->dev;
 727         pdata->aux.transfer = ti_sn_aux_transfer;
 728         drm_dp_aux_register(&pdata->aux);
 729
 730         pdata->bridge.funcs = &ti_sn_bridge_funcs;
 731         pdata->bridge.of_node = client->dev.of_node;
 732
 733         drm_bridge_add(&pdata->bridge);
 734
 735         return 0;
 736 }
 737
 738 static int ti_sn_bridge_remove(struct i2c_client *client)
 739 {
 740         struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
 741
 742         if (!pdata)
 743                 return -EINVAL;
 744
 745         of_node_put(pdata->host_node);
 746
 747         pm_runtime_disable(pdata->dev);
 748
 749         if (pdata->dsi) {
 750                 mipi_dsi_detach(pdata->dsi);
 751                 mipi_dsi_device_unregister(pdata->dsi);
 752         }
 753
 754         drm_bridge_remove(&pdata->bridge);
 755
 756         return 0;
 757 }
 758
 759 static struct i2c_device_id ti_sn_bridge_id[] = {
 760         { "ti,sn65dsi86", 0},
 761         {},
 762 };
 763 MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
 764
 765 static const struct of_device_id ti_sn_bridge_match_table[] = {
 766         {.compatible = "ti,sn65dsi86"},
 767         {},
 768 };
 769 MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
 770
 771 static struct i2c_driver ti_sn_bridge_driver = {
 772         .driver = {
 773                 .name = "ti_sn65dsi86",
 774                 .of_match_table = ti_sn_bridge_match_table,
 775                 .pm = &ti_sn_bridge_pm_ops,
 776         },
 777         .probe = ti_sn_bridge_probe,
 778         .remove = ti_sn_bridge_remove,
 779         .id_table = ti_sn_bridge_id,
 780 };
 781 module_i2c_driver(ti_sn_bridge_driver);
 782
 783 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
 784 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
 785 MODULE_LICENSE("GPL v2");