2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
101 static const struct edid_quirk {
105 } edid_quirk_list[] = {
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
128 /* Belinea 10 15 55 */
129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
132 /* Envision Peripherals, Inc. EN-7100e */
133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
134 /* Envision EN2028 */
135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
137 /* Funai Electronics PM36B */
138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
139 EDID_QUIRK_DETAILED_IN_CM },
141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
144 /* LG Philips LCD LP154W01-A5 */
145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
148 /* Philips 107p5 CRT */
149 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
152 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
154 /* Samsung SyncMaster 205BW. Note: irony */
155 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
156 /* Samsung SyncMaster 22[5-6]BW */
157 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
158 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
160 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
161 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
163 /* ViewSonic VA2026w */
164 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
166 /* Medion MD 30217 PG */
167 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
169 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
170 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
172 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
173 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
175 /* HTC Vive and Vive Pro VR Headsets */
176 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
177 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
179 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
180 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
181 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
182 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
184 /* Windows Mixed Reality Headsets */
185 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
186 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
187 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
188 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
189 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
190 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
191 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
192 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
194 /* Sony PlayStation VR Headset */
195 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
197 /* Sensics VR Headsets */
198 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
200 /* OSVR HDK and HDK2 VR Headsets */
201 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
205 * Autogenerated from the DMT spec.
206 * This table is copied from xfree86/modes/xf86EdidModes.c.
208 static const struct drm_display_mode drm_dmt_modes[] = {
209 /* 0x01 - 640x350@85Hz */
210 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
211 736, 832, 0, 350, 382, 385, 445, 0,
212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
213 /* 0x02 - 640x400@85Hz */
214 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
215 736, 832, 0, 400, 401, 404, 445, 0,
216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
217 /* 0x03 - 720x400@85Hz */
218 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
219 828, 936, 0, 400, 401, 404, 446, 0,
220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
221 /* 0x04 - 640x480@60Hz */
222 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
223 752, 800, 0, 480, 490, 492, 525, 0,
224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
225 /* 0x05 - 640x480@72Hz */
226 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
227 704, 832, 0, 480, 489, 492, 520, 0,
228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
229 /* 0x06 - 640x480@75Hz */
230 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
231 720, 840, 0, 480, 481, 484, 500, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
233 /* 0x07 - 640x480@85Hz */
234 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
235 752, 832, 0, 480, 481, 484, 509, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x08 - 800x600@56Hz */
238 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
239 896, 1024, 0, 600, 601, 603, 625, 0,
240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x09 - 800x600@60Hz */
242 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
243 968, 1056, 0, 600, 601, 605, 628, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x0a - 800x600@72Hz */
246 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
247 976, 1040, 0, 600, 637, 643, 666, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 0x0b - 800x600@75Hz */
250 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
251 896, 1056, 0, 600, 601, 604, 625, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x0c - 800x600@85Hz */
254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
255 896, 1048, 0, 600, 601, 604, 631, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x0d - 800x600@120Hz RB */
258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
259 880, 960, 0, 600, 603, 607, 636, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x0e - 848x480@60Hz */
262 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
263 976, 1088, 0, 480, 486, 494, 517, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x0f - 1024x768@43Hz, interlace */
266 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
267 1208, 1264, 0, 768, 768, 776, 817, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
269 DRM_MODE_FLAG_INTERLACE) },
270 /* 0x10 - 1024x768@60Hz */
271 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
272 1184, 1344, 0, 768, 771, 777, 806, 0,
273 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
274 /* 0x11 - 1024x768@70Hz */
275 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
276 1184, 1328, 0, 768, 771, 777, 806, 0,
277 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
278 /* 0x12 - 1024x768@75Hz */
279 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
280 1136, 1312, 0, 768, 769, 772, 800, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x13 - 1024x768@85Hz */
283 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
284 1168, 1376, 0, 768, 769, 772, 808, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x14 - 1024x768@120Hz RB */
287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
288 1104, 1184, 0, 768, 771, 775, 813, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x15 - 1152x864@75Hz */
291 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
292 1344, 1600, 0, 864, 865, 868, 900, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x55 - 1280x720@60Hz */
295 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
296 1430, 1650, 0, 720, 725, 730, 750, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x16 - 1280x768@60Hz RB */
299 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
300 1360, 1440, 0, 768, 771, 778, 790, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x17 - 1280x768@60Hz */
303 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
304 1472, 1664, 0, 768, 771, 778, 798, 0,
305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x18 - 1280x768@75Hz */
307 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
308 1488, 1696, 0, 768, 771, 778, 805, 0,
309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x19 - 1280x768@85Hz */
311 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
312 1496, 1712, 0, 768, 771, 778, 809, 0,
313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x1a - 1280x768@120Hz RB */
315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
316 1360, 1440, 0, 768, 771, 778, 813, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
318 /* 0x1b - 1280x800@60Hz RB */
319 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
320 1360, 1440, 0, 800, 803, 809, 823, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
322 /* 0x1c - 1280x800@60Hz */
323 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
324 1480, 1680, 0, 800, 803, 809, 831, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x1d - 1280x800@75Hz */
327 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
328 1488, 1696, 0, 800, 803, 809, 838, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x1e - 1280x800@85Hz */
331 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
332 1496, 1712, 0, 800, 803, 809, 843, 0,
333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x1f - 1280x800@120Hz RB */
335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
336 1360, 1440, 0, 800, 803, 809, 847, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x20 - 1280x960@60Hz */
339 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
340 1488, 1800, 0, 960, 961, 964, 1000, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x21 - 1280x960@85Hz */
343 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
344 1504, 1728, 0, 960, 961, 964, 1011, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x22 - 1280x960@120Hz RB */
347 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
348 1360, 1440, 0, 960, 963, 967, 1017, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 0x23 - 1280x1024@60Hz */
351 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
352 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x24 - 1280x1024@75Hz */
355 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
356 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x25 - 1280x1024@85Hz */
359 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
360 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x26 - 1280x1024@120Hz RB */
363 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
364 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
366 /* 0x27 - 1360x768@60Hz */
367 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
368 1536, 1792, 0, 768, 771, 777, 795, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x28 - 1360x768@120Hz RB */
371 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
372 1440, 1520, 0, 768, 771, 776, 813, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x51 - 1366x768@60Hz */
375 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
376 1579, 1792, 0, 768, 771, 774, 798, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x56 - 1366x768@60Hz */
379 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
380 1436, 1500, 0, 768, 769, 772, 800, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x29 - 1400x1050@60Hz RB */
383 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
384 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
386 /* 0x2a - 1400x1050@60Hz */
387 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
388 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
389 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x2b - 1400x1050@75Hz */
391 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
392 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x2c - 1400x1050@85Hz */
395 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
396 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x2d - 1400x1050@120Hz RB */
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
400 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x2e - 1440x900@60Hz RB */
403 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
404 1520, 1600, 0, 900, 903, 909, 926, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
406 /* 0x2f - 1440x900@60Hz */
407 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
408 1672, 1904, 0, 900, 903, 909, 934, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x30 - 1440x900@75Hz */
411 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
412 1688, 1936, 0, 900, 903, 909, 942, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x31 - 1440x900@85Hz */
415 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
416 1696, 1952, 0, 900, 903, 909, 948, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x32 - 1440x900@120Hz RB */
419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
420 1520, 1600, 0, 900, 903, 909, 953, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x53 - 1600x900@60Hz */
423 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
424 1704, 1800, 0, 900, 901, 904, 1000, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x33 - 1600x1200@60Hz */
427 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
428 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x34 - 1600x1200@65Hz */
431 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
432 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x35 - 1600x1200@70Hz */
435 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
436 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x36 - 1600x1200@75Hz */
439 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
440 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x37 - 1600x1200@85Hz */
443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x38 - 1600x1200@120Hz RB */
447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
448 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
450 /* 0x39 - 1680x1050@60Hz RB */
451 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
452 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 0x3a - 1680x1050@60Hz */
455 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
456 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x3b - 1680x1050@75Hz */
459 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
460 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x3c - 1680x1050@85Hz */
463 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
464 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x3d - 1680x1050@120Hz RB */
467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
468 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 0x3e - 1792x1344@60Hz */
471 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
472 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x3f - 1792x1344@75Hz */
475 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
476 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x40 - 1792x1344@120Hz RB */
479 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
480 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x41 - 1856x1392@60Hz */
483 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
484 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x42 - 1856x1392@75Hz */
487 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
488 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x43 - 1856x1392@120Hz RB */
491 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
492 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
494 /* 0x52 - 1920x1080@60Hz */
495 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
496 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
498 /* 0x44 - 1920x1200@60Hz RB */
499 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
500 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
502 /* 0x45 - 1920x1200@60Hz */
503 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
504 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x46 - 1920x1200@75Hz */
507 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
508 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x47 - 1920x1200@85Hz */
511 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
512 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x48 - 1920x1200@120Hz RB */
515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
516 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x49 - 1920x1440@60Hz */
519 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
520 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x4a - 1920x1440@75Hz */
523 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
524 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x4b - 1920x1440@120Hz RB */
527 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
528 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
530 /* 0x54 - 2048x1152@60Hz */
531 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
532 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x4c - 2560x1600@60Hz RB */
535 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
536 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
538 /* 0x4d - 2560x1600@60Hz */
539 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
540 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x4e - 2560x1600@75Hz */
543 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
544 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x4f - 2560x1600@85Hz */
547 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
548 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x50 - 2560x1600@120Hz RB */
551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
552 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x57 - 4096x2160@60Hz RB */
555 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
556 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
558 /* 0x58 - 4096x2160@59.94Hz RB */
559 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
560 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
565 * These more or less come from the DMT spec. The 720x400 modes are
566 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
567 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
568 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
571 * The DMT modes have been fact-checked; the rest are mild guesses.
573 static const struct drm_display_mode edid_est_modes[] = {
574 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
575 968, 1056, 0, 600, 601, 605, 628, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
577 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
578 896, 1024, 0, 600, 601, 603, 625, 0,
579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
580 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
581 720, 840, 0, 480, 481, 484, 500, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
583 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
584 704, 832, 0, 480, 489, 492, 520, 0,
585 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
586 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
587 768, 864, 0, 480, 483, 486, 525, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
589 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
590 752, 800, 0, 480, 490, 492, 525, 0,
591 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
592 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
593 846, 900, 0, 400, 421, 423, 449, 0,
594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
595 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
596 846, 900, 0, 400, 412, 414, 449, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
598 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
599 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
601 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
602 1136, 1312, 0, 768, 769, 772, 800, 0,
603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
604 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
605 1184, 1328, 0, 768, 771, 777, 806, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
607 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
608 1184, 1344, 0, 768, 771, 777, 806, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
610 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
611 1208, 1264, 0, 768, 768, 776, 817, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
613 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
614 928, 1152, 0, 624, 625, 628, 667, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
616 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
617 896, 1056, 0, 600, 601, 604, 625, 0,
618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
619 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
620 976, 1040, 0, 600, 637, 643, 666, 0,
621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
622 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
623 1344, 1600, 0, 864, 865, 868, 900, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
634 static const struct minimode est3_modes[] = {
642 { 1024, 768, 85, 0 },
643 { 1152, 864, 75, 0 },
645 { 1280, 768, 60, 1 },
646 { 1280, 768, 60, 0 },
647 { 1280, 768, 75, 0 },
648 { 1280, 768, 85, 0 },
649 { 1280, 960, 60, 0 },
650 { 1280, 960, 85, 0 },
651 { 1280, 1024, 60, 0 },
652 { 1280, 1024, 85, 0 },
654 { 1360, 768, 60, 0 },
655 { 1440, 900, 60, 1 },
656 { 1440, 900, 60, 0 },
657 { 1440, 900, 75, 0 },
658 { 1440, 900, 85, 0 },
659 { 1400, 1050, 60, 1 },
660 { 1400, 1050, 60, 0 },
661 { 1400, 1050, 75, 0 },
663 { 1400, 1050, 85, 0 },
664 { 1680, 1050, 60, 1 },
665 { 1680, 1050, 60, 0 },
666 { 1680, 1050, 75, 0 },
667 { 1680, 1050, 85, 0 },
668 { 1600, 1200, 60, 0 },
669 { 1600, 1200, 65, 0 },
670 { 1600, 1200, 70, 0 },
672 { 1600, 1200, 75, 0 },
673 { 1600, 1200, 85, 0 },
674 { 1792, 1344, 60, 0 },
675 { 1792, 1344, 75, 0 },
676 { 1856, 1392, 60, 0 },
677 { 1856, 1392, 75, 0 },
678 { 1920, 1200, 60, 1 },
679 { 1920, 1200, 60, 0 },
681 { 1920, 1200, 75, 0 },
682 { 1920, 1200, 85, 0 },
683 { 1920, 1440, 60, 0 },
684 { 1920, 1440, 75, 0 },
687 static const struct minimode extra_modes[] = {
688 { 1024, 576, 60, 0 },
689 { 1366, 768, 60, 0 },
690 { 1600, 900, 60, 0 },
691 { 1680, 945, 60, 0 },
692 { 1920, 1080, 60, 0 },
693 { 2048, 1152, 60, 0 },
694 { 2048, 1536, 60, 0 },
698 * Probably taken from CEA-861 spec.
699 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
701 * Index using the VIC.
703 static const struct drm_display_mode edid_cea_modes[] = {
704 /* 0 - dummy, VICs start at 1 */
706 /* 1 - 640x480@60Hz 4:3 */
707 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
708 752, 800, 0, 480, 490, 492, 525, 0,
709 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
711 /* 2 - 720x480@60Hz 4:3 */
712 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
713 798, 858, 0, 480, 489, 495, 525, 0,
714 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
716 /* 3 - 720x480@60Hz 16:9 */
717 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
718 798, 858, 0, 480, 489, 495, 525, 0,
719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
721 /* 4 - 1280x720@60Hz 16:9 */
722 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
723 1430, 1650, 0, 720, 725, 730, 750, 0,
724 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
726 /* 5 - 1920x1080i@60Hz 16:9 */
727 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
728 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
729 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
730 DRM_MODE_FLAG_INTERLACE),
731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
732 /* 6 - 720(1440)x480i@60Hz 4:3 */
733 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
734 801, 858, 0, 480, 488, 494, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
736 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
738 /* 7 - 720(1440)x480i@60Hz 16:9 */
739 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
740 801, 858, 0, 480, 488, 494, 525, 0,
741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
742 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
744 /* 8 - 720(1440)x240@60Hz 4:3 */
745 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
746 801, 858, 0, 240, 244, 247, 262, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
748 DRM_MODE_FLAG_DBLCLK),
749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
750 /* 9 - 720(1440)x240@60Hz 16:9 */
751 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
752 801, 858, 0, 240, 244, 247, 262, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
754 DRM_MODE_FLAG_DBLCLK),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 10 - 2880x480i@60Hz 4:3 */
757 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
758 3204, 3432, 0, 480, 488, 494, 525, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
760 DRM_MODE_FLAG_INTERLACE),
761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
762 /* 11 - 2880x480i@60Hz 16:9 */
763 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
764 3204, 3432, 0, 480, 488, 494, 525, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
766 DRM_MODE_FLAG_INTERLACE),
767 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
768 /* 12 - 2880x240@60Hz 4:3 */
769 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
770 3204, 3432, 0, 240, 244, 247, 262, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
772 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
773 /* 13 - 2880x240@60Hz 16:9 */
774 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
775 3204, 3432, 0, 240, 244, 247, 262, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
777 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
778 /* 14 - 1440x480@60Hz 4:3 */
779 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
780 1596, 1716, 0, 480, 489, 495, 525, 0,
781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
782 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
783 /* 15 - 1440x480@60Hz 16:9 */
784 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
785 1596, 1716, 0, 480, 489, 495, 525, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
787 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788 /* 16 - 1920x1080@60Hz 16:9 */
789 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
790 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
791 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
792 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
793 /* 17 - 720x576@50Hz 4:3 */
794 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
795 796, 864, 0, 576, 581, 586, 625, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
798 /* 18 - 720x576@50Hz 16:9 */
799 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
800 796, 864, 0, 576, 581, 586, 625, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 19 - 1280x720@50Hz 16:9 */
804 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
805 1760, 1980, 0, 720, 725, 730, 750, 0,
806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
808 /* 20 - 1920x1080i@50Hz 16:9 */
809 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
810 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
812 DRM_MODE_FLAG_INTERLACE),
813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 21 - 720(1440)x576i@50Hz 4:3 */
815 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
816 795, 864, 0, 576, 580, 586, 625, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
818 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
820 /* 22 - 720(1440)x576i@50Hz 16:9 */
821 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
822 795, 864, 0, 576, 580, 586, 625, 0,
823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
824 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 23 - 720(1440)x288@50Hz 4:3 */
827 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
828 795, 864, 0, 288, 290, 293, 312, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
830 DRM_MODE_FLAG_DBLCLK),
831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
832 /* 24 - 720(1440)x288@50Hz 16:9 */
833 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
834 795, 864, 0, 288, 290, 293, 312, 0,
835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
836 DRM_MODE_FLAG_DBLCLK),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 25 - 2880x576i@50Hz 4:3 */
839 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
840 3180, 3456, 0, 576, 580, 586, 625, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
842 DRM_MODE_FLAG_INTERLACE),
843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
844 /* 26 - 2880x576i@50Hz 16:9 */
845 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
846 3180, 3456, 0, 576, 580, 586, 625, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
848 DRM_MODE_FLAG_INTERLACE),
849 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
850 /* 27 - 2880x288@50Hz 4:3 */
851 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
852 3180, 3456, 0, 288, 290, 293, 312, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
854 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
855 /* 28 - 2880x288@50Hz 16:9 */
856 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
857 3180, 3456, 0, 288, 290, 293, 312, 0,
858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
859 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
860 /* 29 - 1440x576@50Hz 4:3 */
861 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
862 1592, 1728, 0, 576, 581, 586, 625, 0,
863 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
865 /* 30 - 1440x576@50Hz 16:9 */
866 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
867 1592, 1728, 0, 576, 581, 586, 625, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
869 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 31 - 1920x1080@50Hz 16:9 */
871 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
872 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
874 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
875 /* 32 - 1920x1080@24Hz 16:9 */
876 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
877 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
879 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
880 /* 33 - 1920x1080@25Hz 16:9 */
881 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
882 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
883 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
884 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
885 /* 34 - 1920x1080@30Hz 16:9 */
886 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
887 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
889 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 35 - 2880x480@60Hz 4:3 */
891 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
892 3192, 3432, 0, 480, 489, 495, 525, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
894 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
895 /* 36 - 2880x480@60Hz 16:9 */
896 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
897 3192, 3432, 0, 480, 489, 495, 525, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
899 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 37 - 2880x576@50Hz 4:3 */
901 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
902 3184, 3456, 0, 576, 581, 586, 625, 0,
903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
904 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
905 /* 38 - 2880x576@50Hz 16:9 */
906 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
907 3184, 3456, 0, 576, 581, 586, 625, 0,
908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
909 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 39 - 1920x1080i@50Hz 16:9 */
911 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
912 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
914 DRM_MODE_FLAG_INTERLACE),
915 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
916 /* 40 - 1920x1080i@100Hz 16:9 */
917 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
918 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
919 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
920 DRM_MODE_FLAG_INTERLACE),
921 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 41 - 1280x720@100Hz 16:9 */
923 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
924 1760, 1980, 0, 720, 725, 730, 750, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
926 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
927 /* 42 - 720x576@100Hz 4:3 */
928 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
929 796, 864, 0, 576, 581, 586, 625, 0,
930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
931 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
932 /* 43 - 720x576@100Hz 16:9 */
933 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
934 796, 864, 0, 576, 581, 586, 625, 0,
935 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
936 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
937 /* 44 - 720(1440)x576i@100Hz 4:3 */
938 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
939 795, 864, 0, 576, 580, 586, 625, 0,
940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
941 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
942 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
943 /* 45 - 720(1440)x576i@100Hz 16:9 */
944 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
945 795, 864, 0, 576, 580, 586, 625, 0,
946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
947 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949 /* 46 - 1920x1080i@120Hz 16:9 */
950 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
951 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
953 DRM_MODE_FLAG_INTERLACE),
954 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 /* 47 - 1280x720@120Hz 16:9 */
956 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
957 1430, 1650, 0, 720, 725, 730, 750, 0,
958 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
959 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
960 /* 48 - 720x480@120Hz 4:3 */
961 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
962 798, 858, 0, 480, 489, 495, 525, 0,
963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
964 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
965 /* 49 - 720x480@120Hz 16:9 */
966 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
967 798, 858, 0, 480, 489, 495, 525, 0,
968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
969 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 50 - 720(1440)x480i@120Hz 4:3 */
971 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
972 801, 858, 0, 480, 488, 494, 525, 0,
973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
974 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
975 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
976 /* 51 - 720(1440)x480i@120Hz 16:9 */
977 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
978 801, 858, 0, 480, 488, 494, 525, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
980 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
981 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982 /* 52 - 720x576@200Hz 4:3 */
983 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
984 796, 864, 0, 576, 581, 586, 625, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
986 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
987 /* 53 - 720x576@200Hz 16:9 */
988 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
989 796, 864, 0, 576, 581, 586, 625, 0,
990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
991 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
992 /* 54 - 720(1440)x576i@200Hz 4:3 */
993 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
994 795, 864, 0, 576, 580, 586, 625, 0,
995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
996 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
997 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
998 /* 55 - 720(1440)x576i@200Hz 16:9 */
999 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1000 795, 864, 0, 576, 580, 586, 625, 0,
1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1002 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1003 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 56 - 720x480@240Hz 4:3 */
1005 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1006 798, 858, 0, 480, 489, 495, 525, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1008 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1009 /* 57 - 720x480@240Hz 16:9 */
1010 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1011 798, 858, 0, 480, 489, 495, 525, 0,
1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1013 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 58 - 720(1440)x480i@240Hz 4:3 */
1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1016 801, 858, 0, 480, 488, 494, 525, 0,
1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1019 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1020 /* 59 - 720(1440)x480i@240Hz 16:9 */
1021 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1022 801, 858, 0, 480, 488, 494, 525, 0,
1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1025 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026 /* 60 - 1280x720@24Hz 16:9 */
1027 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1028 3080, 3300, 0, 720, 725, 730, 750, 0,
1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1030 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1031 /* 61 - 1280x720@25Hz 16:9 */
1032 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1033 3740, 3960, 0, 720, 725, 730, 750, 0,
1034 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1035 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1036 /* 62 - 1280x720@30Hz 16:9 */
1037 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1038 3080, 3300, 0, 720, 725, 730, 750, 0,
1039 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1040 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1041 /* 63 - 1920x1080@120Hz 16:9 */
1042 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1043 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1045 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1046 /* 64 - 1920x1080@100Hz 16:9 */
1047 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1048 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1050 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1051 /* 65 - 1280x720@24Hz 64:27 */
1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1053 3080, 3300, 0, 720, 725, 730, 750, 0,
1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1055 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1056 /* 66 - 1280x720@25Hz 64:27 */
1057 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1058 3740, 3960, 0, 720, 725, 730, 750, 0,
1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1061 /* 67 - 1280x720@30Hz 64:27 */
1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1063 3080, 3300, 0, 720, 725, 730, 750, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1066 /* 68 - 1280x720@50Hz 64:27 */
1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1068 1760, 1980, 0, 720, 725, 730, 750, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1071 /* 69 - 1280x720@60Hz 64:27 */
1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1073 1430, 1650, 0, 720, 725, 730, 750, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1076 /* 70 - 1280x720@100Hz 64:27 */
1077 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1078 1760, 1980, 0, 720, 725, 730, 750, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1081 /* 71 - 1280x720@120Hz 64:27 */
1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1083 1430, 1650, 0, 720, 725, 730, 750, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1086 /* 72 - 1920x1080@24Hz 64:27 */
1087 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1088 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 73 - 1920x1080@25Hz 64:27 */
1092 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1093 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 74 - 1920x1080@30Hz 64:27 */
1097 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1098 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 75 - 1920x1080@50Hz 64:27 */
1102 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1103 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 76 - 1920x1080@60Hz 64:27 */
1107 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1108 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 77 - 1920x1080@100Hz 64:27 */
1112 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1113 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 78 - 1920x1080@120Hz 64:27 */
1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1118 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 79 - 1680x720@24Hz 64:27 */
1122 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1123 3080, 3300, 0, 720, 725, 730, 750, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 80 - 1680x720@25Hz 64:27 */
1127 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1128 2948, 3168, 0, 720, 725, 730, 750, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 81 - 1680x720@30Hz 64:27 */
1132 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1133 2420, 2640, 0, 720, 725, 730, 750, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 82 - 1680x720@50Hz 64:27 */
1137 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1138 1980, 2200, 0, 720, 725, 730, 750, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 83 - 1680x720@60Hz 64:27 */
1142 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1143 1980, 2200, 0, 720, 725, 730, 750, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 84 - 1680x720@100Hz 64:27 */
1147 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1148 1780, 2000, 0, 720, 725, 730, 825, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 85 - 1680x720@120Hz 64:27 */
1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1153 1780, 2000, 0, 720, 725, 730, 825, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156 /* 86 - 2560x1080@24Hz 64:27 */
1157 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1158 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161 /* 87 - 2560x1080@25Hz 64:27 */
1162 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1163 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166 /* 88 - 2560x1080@30Hz 64:27 */
1167 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1168 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171 /* 89 - 2560x1080@50Hz 64:27 */
1172 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1173 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176 /* 90 - 2560x1080@60Hz 64:27 */
1177 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1178 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181 /* 91 - 2560x1080@100Hz 64:27 */
1182 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1183 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186 /* 92 - 2560x1080@120Hz 64:27 */
1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1188 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191 /* 93 - 3840x2160@24Hz 16:9 */
1192 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1193 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1196 /* 94 - 3840x2160@25Hz 16:9 */
1197 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1198 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1201 /* 95 - 3840x2160@30Hz 16:9 */
1202 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1203 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1206 /* 96 - 3840x2160@50Hz 16:9 */
1207 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1208 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1211 /* 97 - 3840x2160@60Hz 16:9 */
1212 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1213 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1216 /* 98 - 4096x2160@24Hz 256:135 */
1217 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1218 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1221 /* 99 - 4096x2160@25Hz 256:135 */
1222 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1223 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1226 /* 100 - 4096x2160@30Hz 256:135 */
1227 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1228 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1231 /* 101 - 4096x2160@50Hz 256:135 */
1232 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1233 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1236 /* 102 - 4096x2160@60Hz 256:135 */
1237 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1238 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1241 /* 103 - 3840x2160@24Hz 64:27 */
1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1243 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1246 /* 104 - 3840x2160@25Hz 64:27 */
1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1248 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1251 /* 105 - 3840x2160@30Hz 64:27 */
1252 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1253 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1256 /* 106 - 3840x2160@50Hz 64:27 */
1257 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1258 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1261 /* 107 - 3840x2160@60Hz 64:27 */
1262 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1263 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1269 * HDMI 1.4 4k modes. Index using the VIC.
1271 static const struct drm_display_mode edid_4k_modes[] = {
1272 /* 0 - dummy, VICs start at 1 */
1274 /* 1 - 3840x2160@30Hz */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1276 3840, 4016, 4104, 4400, 0,
1277 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 /* 2 - 3840x2160@25Hz */
1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1282 3840, 4896, 4984, 5280, 0,
1283 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1286 /* 3 - 3840x2160@24Hz */
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1288 3840, 5116, 5204, 5500, 0,
1289 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1292 /* 4 - 4096x2160@24Hz (SMPTE) */
1293 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1294 4096, 5116, 5204, 5500, 0,
1295 2160, 2168, 2178, 2250, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 /*** DDC fetch and block validation ***/
1302 static const u8 edid_header[] = {
1303 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1307 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1308 * @raw_edid: pointer to raw base EDID block
1310 * Sanity check the header of the base EDID block.
1312 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1314 int drm_edid_header_is_valid(const u8 *raw_edid)
1318 for (i = 0; i < sizeof(edid_header); i++)
1319 if (raw_edid[i] == edid_header[i])
1324 EXPORT_SYMBOL(drm_edid_header_is_valid);
1326 static int edid_fixup __read_mostly = 6;
1327 module_param_named(edid_fixup, edid_fixup, int, 0400);
1328 MODULE_PARM_DESC(edid_fixup,
1329 "Minimum number of valid EDID header bytes (0-8, default 6)");
1331 static void drm_get_displayid(struct drm_connector *connector,
1334 static int drm_edid_block_checksum(const u8 *raw_edid)
1338 for (i = 0; i < EDID_LENGTH; i++)
1339 csum += raw_edid[i];
1344 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1346 if (memchr_inv(in_edid, 0, length))
1353 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1354 * @raw_edid: pointer to raw EDID block
1355 * @block: type of block to validate (0 for base, extension otherwise)
1356 * @print_bad_edid: if true, dump bad EDID blocks to the console
1357 * @edid_corrupt: if true, the header or checksum is invalid
1359 * Validate a base or extension EDID block and optionally dump bad blocks to
1362 * Return: True if the block is valid, false otherwise.
1364 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1368 struct edid *edid = (struct edid *)raw_edid;
1370 if (WARN_ON(!raw_edid))
1373 if (edid_fixup > 8 || edid_fixup < 0)
1377 int score = drm_edid_header_is_valid(raw_edid);
1380 *edid_corrupt = false;
1381 } else if (score >= edid_fixup) {
1382 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1383 * The corrupt flag needs to be set here otherwise, the
1384 * fix-up code here will correct the problem, the
1385 * checksum is correct and the test fails
1388 *edid_corrupt = true;
1389 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1390 memcpy(raw_edid, edid_header, sizeof(edid_header));
1393 *edid_corrupt = true;
1398 csum = drm_edid_block_checksum(raw_edid);
1401 *edid_corrupt = true;
1403 /* allow CEA to slide through, switches mangle this */
1404 if (raw_edid[0] == CEA_EXT) {
1405 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1406 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1409 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1415 /* per-block-type checks */
1416 switch (raw_edid[0]) {
1418 if (edid->version != 1) {
1419 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1423 if (edid->revision > 4)
1424 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1434 if (print_bad_edid) {
1435 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1436 pr_notice("EDID block is all zeroes\n");
1438 pr_notice("Raw EDID:\n");
1439 print_hex_dump(KERN_NOTICE,
1440 " \t", DUMP_PREFIX_NONE, 16, 1,
1441 raw_edid, EDID_LENGTH, false);
1446 EXPORT_SYMBOL(drm_edid_block_valid);
1449 * drm_edid_is_valid - sanity check EDID data
1452 * Sanity-check an entire EDID record (including extensions)
1454 * Return: True if the EDID data is valid, false otherwise.
1456 bool drm_edid_is_valid(struct edid *edid)
1459 u8 *raw = (u8 *)edid;
1464 for (i = 0; i <= edid->extensions; i++)
1465 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1470 EXPORT_SYMBOL(drm_edid_is_valid);
1472 #define DDC_SEGMENT_ADDR 0x30
1474 * drm_do_probe_ddc_edid() - get EDID information via I2C
1475 * @data: I2C device adapter
1476 * @buf: EDID data buffer to be filled
1477 * @block: 128 byte EDID block to start fetching from
1478 * @len: EDID data buffer length to fetch
1480 * Try to fetch EDID information by calling I2C driver functions.
1482 * Return: 0 on success or -1 on failure.
1485 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1487 struct i2c_adapter *adapter = data;
1488 unsigned char start = block * EDID_LENGTH;
1489 unsigned char segment = block >> 1;
1490 unsigned char xfers = segment ? 3 : 2;
1491 int ret, retries = 5;
1494 * The core I2C driver will automatically retry the transfer if the
1495 * adapter reports EAGAIN. However, we find that bit-banging transfers
1496 * are susceptible to errors under a heavily loaded machine and
1497 * generate spurious NAKs and timeouts. Retrying the transfer
1498 * of the individual block a few times seems to overcome this.
1501 struct i2c_msg msgs[] = {
1503 .addr = DDC_SEGMENT_ADDR,
1521 * Avoid sending the segment addr to not upset non-compliant
1524 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1526 if (ret == -ENXIO) {
1527 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1531 } while (ret != xfers && --retries);
1533 return ret == xfers ? 0 : -1;
1536 static void connector_bad_edid(struct drm_connector *connector,
1537 u8 *edid, int num_blocks)
1541 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1544 dev_warn(connector->dev->dev,
1545 "%s: EDID is invalid:\n",
1547 for (i = 0; i < num_blocks; i++) {
1548 u8 *block = edid + i * EDID_LENGTH;
1551 if (drm_edid_is_zero(block, EDID_LENGTH))
1552 sprintf(prefix, "\t[%02x] ZERO ", i);
1553 else if (!drm_edid_block_valid(block, i, false, NULL))
1554 sprintf(prefix, "\t[%02x] BAD ", i);
1556 sprintf(prefix, "\t[%02x] GOOD ", i);
1558 print_hex_dump(KERN_WARNING,
1559 prefix, DUMP_PREFIX_NONE, 16, 1,
1560 block, EDID_LENGTH, false);
1565 * drm_do_get_edid - get EDID data using a custom EDID block read function
1566 * @connector: connector we're probing
1567 * @get_edid_block: EDID block read function
1568 * @data: private data passed to the block read function
1570 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1571 * exposes a different interface to read EDID blocks this function can be used
1572 * to get EDID data using a custom block read function.
1574 * As in the general case the DDC bus is accessible by the kernel at the I2C
1575 * level, drivers must make all reasonable efforts to expose it as an I2C
1576 * adapter and use drm_get_edid() instead of abusing this function.
1578 * The EDID may be overridden using debugfs override_edid or firmare EDID
1579 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1580 * order. Having either of them bypasses actual EDID reads.
1582 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1584 struct edid *drm_do_get_edid(struct drm_connector *connector,
1585 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1589 int i, j = 0, valid_extensions = 0;
1591 struct edid *override = NULL;
1593 if (connector->override_edid)
1594 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1597 override = drm_load_edid_firmware(connector);
1599 if (!IS_ERR_OR_NULL(override))
1602 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1605 /* base block fetch */
1606 for (i = 0; i < 4; i++) {
1607 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1609 if (drm_edid_block_valid(edid, 0, false,
1610 &connector->edid_corrupt))
1612 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1613 connector->null_edid_counter++;
1620 /* if there's no extensions, we're done */
1621 valid_extensions = edid[0x7e];
1622 if (valid_extensions == 0)
1623 return (struct edid *)edid;
1625 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1630 for (j = 1; j <= edid[0x7e]; j++) {
1631 u8 *block = edid + j * EDID_LENGTH;
1633 for (i = 0; i < 4; i++) {
1634 if (get_edid_block(data, block, j, EDID_LENGTH))
1636 if (drm_edid_block_valid(block, j, false, NULL))
1644 if (valid_extensions != edid[0x7e]) {
1647 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1649 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1650 edid[0x7e] = valid_extensions;
1652 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1658 for (i = 0; i <= edid[0x7e]; i++) {
1659 u8 *block = edid + i * EDID_LENGTH;
1661 if (!drm_edid_block_valid(block, i, false, NULL))
1664 memcpy(base, block, EDID_LENGTH);
1665 base += EDID_LENGTH;
1672 return (struct edid *)edid;
1675 connector_bad_edid(connector, edid, 1);
1680 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1683 * drm_probe_ddc() - probe DDC presence
1684 * @adapter: I2C adapter to probe
1686 * Return: True on success, false on failure.
1689 drm_probe_ddc(struct i2c_adapter *adapter)
1693 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1695 EXPORT_SYMBOL(drm_probe_ddc);
1698 * drm_get_edid - get EDID data, if available
1699 * @connector: connector we're probing
1700 * @adapter: I2C adapter to use for DDC
1702 * Poke the given I2C channel to grab EDID data if possible. If found,
1703 * attach it to the connector.
1705 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1707 struct edid *drm_get_edid(struct drm_connector *connector,
1708 struct i2c_adapter *adapter)
1712 if (connector->force == DRM_FORCE_OFF)
1715 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1718 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1720 drm_get_displayid(connector, edid);
1723 EXPORT_SYMBOL(drm_get_edid);
1726 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1727 * @connector: connector we're probing
1728 * @adapter: I2C adapter to use for DDC
1730 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1731 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1732 * switch DDC to the GPU which is retrieving EDID.
1734 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1736 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1737 struct i2c_adapter *adapter)
1739 struct pci_dev *pdev = connector->dev->pdev;
1742 vga_switcheroo_lock_ddc(pdev);
1743 edid = drm_get_edid(connector, adapter);
1744 vga_switcheroo_unlock_ddc(pdev);
1748 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1751 * drm_edid_duplicate - duplicate an EDID and the extensions
1752 * @edid: EDID to duplicate
1754 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1756 struct edid *drm_edid_duplicate(const struct edid *edid)
1758 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1760 EXPORT_SYMBOL(drm_edid_duplicate);
1762 /*** EDID parsing ***/
1765 * edid_vendor - match a string against EDID's obfuscated vendor field
1766 * @edid: EDID to match
1767 * @vendor: vendor string
1769 * Returns true if @vendor is in @edid, false otherwise
1771 static bool edid_vendor(const struct edid *edid, const char *vendor)
1773 char edid_vendor[3];
1775 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1776 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1777 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1778 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1780 return !strncmp(edid_vendor, vendor, 3);
1784 * edid_get_quirks - return quirk flags for a given EDID
1785 * @edid: EDID to process
1787 * This tells subsequent routines what fixes they need to apply.
1789 static u32 edid_get_quirks(const struct edid *edid)
1791 const struct edid_quirk *quirk;
1794 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1795 quirk = &edid_quirk_list[i];
1797 if (edid_vendor(edid, quirk->vendor) &&
1798 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1799 return quirk->quirks;
1805 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1806 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1809 * edid_fixup_preferred - set preferred modes based on quirk list
1810 * @connector: has mode list to fix up
1811 * @quirks: quirks list
1813 * Walk the mode list for @connector, clearing the preferred status
1814 * on existing modes and setting it anew for the right mode ala @quirks.
1816 static void edid_fixup_preferred(struct drm_connector *connector,
1819 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1820 int target_refresh = 0;
1821 int cur_vrefresh, preferred_vrefresh;
1823 if (list_empty(&connector->probed_modes))
1826 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1827 target_refresh = 60;
1828 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1829 target_refresh = 75;
1831 preferred_mode = list_first_entry(&connector->probed_modes,
1832 struct drm_display_mode, head);
1834 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1835 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1837 if (cur_mode == preferred_mode)
1840 /* Largest mode is preferred */
1841 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1842 preferred_mode = cur_mode;
1844 cur_vrefresh = cur_mode->vrefresh ?
1845 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1846 preferred_vrefresh = preferred_mode->vrefresh ?
1847 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1848 /* At a given size, try to get closest to target refresh */
1849 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1850 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1851 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1852 preferred_mode = cur_mode;
1856 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1860 mode_is_rb(const struct drm_display_mode *mode)
1862 return (mode->htotal - mode->hdisplay == 160) &&
1863 (mode->hsync_end - mode->hdisplay == 80) &&
1864 (mode->hsync_end - mode->hsync_start == 32) &&
1865 (mode->vsync_start - mode->vdisplay == 3);
1869 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1870 * @dev: Device to duplicate against
1871 * @hsize: Mode width
1872 * @vsize: Mode height
1873 * @fresh: Mode refresh rate
1874 * @rb: Mode reduced-blanking-ness
1876 * Walk the DMT mode list looking for a match for the given parameters.
1878 * Return: A newly allocated copy of the mode, or NULL if not found.
1880 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1881 int hsize, int vsize, int fresh,
1886 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1887 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1888 if (hsize != ptr->hdisplay)
1890 if (vsize != ptr->vdisplay)
1892 if (fresh != drm_mode_vrefresh(ptr))
1894 if (rb != mode_is_rb(ptr))
1897 return drm_mode_duplicate(dev, ptr);
1902 EXPORT_SYMBOL(drm_mode_find_dmt);
1904 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1907 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1911 u8 *det_base = ext + d;
1914 for (i = 0; i < n; i++)
1915 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1919 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1921 unsigned int i, n = min((int)ext[0x02], 6);
1922 u8 *det_base = ext + 5;
1925 return; /* unknown version */
1927 for (i = 0; i < n; i++)
1928 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1932 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1935 struct edid *edid = (struct edid *)raw_edid;
1940 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1941 cb(&(edid->detailed_timings[i]), closure);
1943 for (i = 1; i <= raw_edid[0x7e]; i++) {
1944 u8 *ext = raw_edid + (i * EDID_LENGTH);
1947 cea_for_each_detailed_block(ext, cb, closure);
1950 vtb_for_each_detailed_block(ext, cb, closure);
1959 is_rb(struct detailed_timing *t, void *data)
1962 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1964 *(bool *)data = true;
1967 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1969 drm_monitor_supports_rb(struct edid *edid)
1971 if (edid->revision >= 4) {
1973 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1977 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1981 find_gtf2(struct detailed_timing *t, void *data)
1984 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1988 /* Secondary GTF curve kicks in above some break frequency */
1990 drm_gtf2_hbreak(struct edid *edid)
1993 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1994 return r ? (r[12] * 2) : 0;
1998 drm_gtf2_2c(struct edid *edid)
2001 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2002 return r ? r[13] : 0;
2006 drm_gtf2_m(struct edid *edid)
2009 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2010 return r ? (r[15] << 8) + r[14] : 0;
2014 drm_gtf2_k(struct edid *edid)
2017 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2018 return r ? r[16] : 0;
2022 drm_gtf2_2j(struct edid *edid)
2025 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2026 return r ? r[17] : 0;
2030 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2031 * @edid: EDID block to scan
2033 static int standard_timing_level(struct edid *edid)
2035 if (edid->revision >= 2) {
2036 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2038 if (drm_gtf2_hbreak(edid))
2046 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2047 * monitors fill with ascii space (0x20) instead.
2050 bad_std_timing(u8 a, u8 b)
2052 return (a == 0x00 && b == 0x00) ||
2053 (a == 0x01 && b == 0x01) ||
2054 (a == 0x20 && b == 0x20);
2058 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2059 * @connector: connector of for the EDID block
2060 * @edid: EDID block to scan
2061 * @t: standard timing params
2063 * Take the standard timing params (in this case width, aspect, and refresh)
2064 * and convert them into a real mode using CVT/GTF/DMT.
2066 static struct drm_display_mode *
2067 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2068 struct std_timing *t)
2070 struct drm_device *dev = connector->dev;
2071 struct drm_display_mode *m, *mode = NULL;
2074 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2075 >> EDID_TIMING_ASPECT_SHIFT;
2076 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2077 >> EDID_TIMING_VFREQ_SHIFT;
2078 int timing_level = standard_timing_level(edid);
2080 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2083 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2084 hsize = t->hsize * 8 + 248;
2085 /* vrefresh_rate = vfreq + 60 */
2086 vrefresh_rate = vfreq + 60;
2087 /* the vdisplay is calculated based on the aspect ratio */
2088 if (aspect_ratio == 0) {
2089 if (edid->revision < 3)
2092 vsize = (hsize * 10) / 16;
2093 } else if (aspect_ratio == 1)
2094 vsize = (hsize * 3) / 4;
2095 else if (aspect_ratio == 2)
2096 vsize = (hsize * 4) / 5;
2098 vsize = (hsize * 9) / 16;
2100 /* HDTV hack, part 1 */
2101 if (vrefresh_rate == 60 &&
2102 ((hsize == 1360 && vsize == 765) ||
2103 (hsize == 1368 && vsize == 769))) {
2109 * If this connector already has a mode for this size and refresh
2110 * rate (because it came from detailed or CVT info), use that
2111 * instead. This way we don't have to guess at interlace or
2114 list_for_each_entry(m, &connector->probed_modes, head)
2115 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2116 drm_mode_vrefresh(m) == vrefresh_rate)
2119 /* HDTV hack, part 2 */
2120 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2121 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2125 mode->hdisplay = 1366;
2126 mode->hsync_start = mode->hsync_start - 1;
2127 mode->hsync_end = mode->hsync_end - 1;
2131 /* check whether it can be found in default mode table */
2132 if (drm_monitor_supports_rb(edid)) {
2133 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2138 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2142 /* okay, generate it */
2143 switch (timing_level) {
2147 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2151 * This is potentially wrong if there's ever a monitor with
2152 * more than one ranges section, each claiming a different
2153 * secondary GTF curve. Please don't do that.
2155 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2158 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2159 drm_mode_destroy(dev, mode);
2160 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2161 vrefresh_rate, 0, 0,
2169 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2177 * EDID is delightfully ambiguous about how interlaced modes are to be
2178 * encoded. Our internal representation is of frame height, but some
2179 * HDTV detailed timings are encoded as field height.
2181 * The format list here is from CEA, in frame size. Technically we
2182 * should be checking refresh rate too. Whatever.
2185 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2186 struct detailed_pixel_timing *pt)
2189 static const struct {
2191 } cea_interlaced[] = {
2201 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2204 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2205 if ((mode->hdisplay == cea_interlaced[i].w) &&
2206 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2207 mode->vdisplay *= 2;
2208 mode->vsync_start *= 2;
2209 mode->vsync_end *= 2;
2215 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2219 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2220 * @dev: DRM device (needed to create new mode)
2222 * @timing: EDID detailed timing info
2223 * @quirks: quirks to apply
2225 * An EDID detailed timing block contains enough info for us to create and
2226 * return a new struct drm_display_mode.
2228 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2230 struct detailed_timing *timing,
2233 struct drm_display_mode *mode;
2234 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2235 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2236 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2237 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2238 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2239 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2240 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2241 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2242 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2244 /* ignore tiny modes */
2245 if (hactive < 64 || vactive < 64)
2248 if (pt->misc & DRM_EDID_PT_STEREO) {
2249 DRM_DEBUG_KMS("stereo mode not supported\n");
2252 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2253 DRM_DEBUG_KMS("composite sync not supported\n");
2256 /* it is incorrect if hsync/vsync width is zero */
2257 if (!hsync_pulse_width || !vsync_pulse_width) {
2258 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2259 "Wrong Hsync/Vsync pulse width\n");
2263 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2264 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2271 mode = drm_mode_create(dev);
2275 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2276 timing->pixel_clock = cpu_to_le16(1088);
2278 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2280 mode->hdisplay = hactive;
2281 mode->hsync_start = mode->hdisplay + hsync_offset;
2282 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2283 mode->htotal = mode->hdisplay + hblank;
2285 mode->vdisplay = vactive;
2286 mode->vsync_start = mode->vdisplay + vsync_offset;
2287 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2288 mode->vtotal = mode->vdisplay + vblank;
2290 /* Some EDIDs have bogus h/vtotal values */
2291 if (mode->hsync_end > mode->htotal)
2292 mode->htotal = mode->hsync_end + 1;
2293 if (mode->vsync_end > mode->vtotal)
2294 mode->vtotal = mode->vsync_end + 1;
2296 drm_mode_do_interlace_quirk(mode, pt);
2298 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2299 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2302 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2303 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2304 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2305 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2308 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2309 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2311 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2312 mode->width_mm *= 10;
2313 mode->height_mm *= 10;
2316 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2317 mode->width_mm = edid->width_cm * 10;
2318 mode->height_mm = edid->height_cm * 10;
2321 mode->type = DRM_MODE_TYPE_DRIVER;
2322 mode->vrefresh = drm_mode_vrefresh(mode);
2323 drm_mode_set_name(mode);
2329 mode_in_hsync_range(const struct drm_display_mode *mode,
2330 struct edid *edid, u8 *t)
2332 int hsync, hmin, hmax;
2335 if (edid->revision >= 4)
2336 hmin += ((t[4] & 0x04) ? 255 : 0);
2338 if (edid->revision >= 4)
2339 hmax += ((t[4] & 0x08) ? 255 : 0);
2340 hsync = drm_mode_hsync(mode);
2342 return (hsync <= hmax && hsync >= hmin);
2346 mode_in_vsync_range(const struct drm_display_mode *mode,
2347 struct edid *edid, u8 *t)
2349 int vsync, vmin, vmax;
2352 if (edid->revision >= 4)
2353 vmin += ((t[4] & 0x01) ? 255 : 0);
2355 if (edid->revision >= 4)
2356 vmax += ((t[4] & 0x02) ? 255 : 0);
2357 vsync = drm_mode_vrefresh(mode);
2359 return (vsync <= vmax && vsync >= vmin);
2363 range_pixel_clock(struct edid *edid, u8 *t)
2366 if (t[9] == 0 || t[9] == 255)
2369 /* 1.4 with CVT support gives us real precision, yay */
2370 if (edid->revision >= 4 && t[10] == 0x04)
2371 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2373 /* 1.3 is pathetic, so fuzz up a bit */
2374 return t[9] * 10000 + 5001;
2378 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2379 struct detailed_timing *timing)
2382 u8 *t = (u8 *)timing;
2384 if (!mode_in_hsync_range(mode, edid, t))
2387 if (!mode_in_vsync_range(mode, edid, t))
2390 if ((max_clock = range_pixel_clock(edid, t)))
2391 if (mode->clock > max_clock)
2394 /* 1.4 max horizontal check */
2395 if (edid->revision >= 4 && t[10] == 0x04)
2396 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2399 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2405 static bool valid_inferred_mode(const struct drm_connector *connector,
2406 const struct drm_display_mode *mode)
2408 const struct drm_display_mode *m;
2411 list_for_each_entry(m, &connector->probed_modes, head) {
2412 if (mode->hdisplay == m->hdisplay &&
2413 mode->vdisplay == m->vdisplay &&
2414 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2415 return false; /* duplicated */
2416 if (mode->hdisplay <= m->hdisplay &&
2417 mode->vdisplay <= m->vdisplay)
2424 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2425 struct detailed_timing *timing)
2428 struct drm_display_mode *newmode;
2429 struct drm_device *dev = connector->dev;
2431 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2432 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2433 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2434 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2436 drm_mode_probed_add(connector, newmode);
2445 /* fix up 1366x768 mode from 1368x768;
2446 * GFT/CVT can't express 1366 width which isn't dividable by 8
2448 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2450 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2451 mode->hdisplay = 1366;
2452 mode->hsync_start--;
2454 drm_mode_set_name(mode);
2459 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2460 struct detailed_timing *timing)
2463 struct drm_display_mode *newmode;
2464 struct drm_device *dev = connector->dev;
2466 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2467 const struct minimode *m = &extra_modes[i];
2468 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2472 drm_mode_fixup_1366x768(newmode);
2473 if (!mode_in_range(newmode, edid, timing) ||
2474 !valid_inferred_mode(connector, newmode)) {
2475 drm_mode_destroy(dev, newmode);
2479 drm_mode_probed_add(connector, newmode);
2487 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2488 struct detailed_timing *timing)
2491 struct drm_display_mode *newmode;
2492 struct drm_device *dev = connector->dev;
2493 bool rb = drm_monitor_supports_rb(edid);
2495 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2496 const struct minimode *m = &extra_modes[i];
2497 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2501 drm_mode_fixup_1366x768(newmode);
2502 if (!mode_in_range(newmode, edid, timing) ||
2503 !valid_inferred_mode(connector, newmode)) {
2504 drm_mode_destroy(dev, newmode);
2508 drm_mode_probed_add(connector, newmode);
2516 do_inferred_modes(struct detailed_timing *timing, void *c)
2518 struct detailed_mode_closure *closure = c;
2519 struct detailed_non_pixel *data = &timing->data.other_data;
2520 struct detailed_data_monitor_range *range = &data->data.range;
2522 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2525 closure->modes += drm_dmt_modes_for_range(closure->connector,
2529 if (!version_greater(closure->edid, 1, 1))
2530 return; /* GTF not defined yet */
2532 switch (range->flags) {
2533 case 0x02: /* secondary gtf, XXX could do more */
2534 case 0x00: /* default gtf */
2535 closure->modes += drm_gtf_modes_for_range(closure->connector,
2539 case 0x04: /* cvt, only in 1.4+ */
2540 if (!version_greater(closure->edid, 1, 3))
2543 closure->modes += drm_cvt_modes_for_range(closure->connector,
2547 case 0x01: /* just the ranges, no formula */
2554 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2556 struct detailed_mode_closure closure = {
2557 .connector = connector,
2561 if (version_greater(edid, 1, 0))
2562 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2565 return closure.modes;
2569 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2571 int i, j, m, modes = 0;
2572 struct drm_display_mode *mode;
2573 u8 *est = ((u8 *)timing) + 6;
2575 for (i = 0; i < 6; i++) {
2576 for (j = 7; j >= 0; j--) {
2577 m = (i * 8) + (7 - j);
2578 if (m >= ARRAY_SIZE(est3_modes))
2580 if (est[i] & (1 << j)) {
2581 mode = drm_mode_find_dmt(connector->dev,
2587 drm_mode_probed_add(connector, mode);
2598 do_established_modes(struct detailed_timing *timing, void *c)
2600 struct detailed_mode_closure *closure = c;
2601 struct detailed_non_pixel *data = &timing->data.other_data;
2603 if (data->type == EDID_DETAIL_EST_TIMINGS)
2604 closure->modes += drm_est3_modes(closure->connector, timing);
2608 * add_established_modes - get est. modes from EDID and add them
2609 * @connector: connector to add mode(s) to
2610 * @edid: EDID block to scan
2612 * Each EDID block contains a bitmap of the supported "established modes" list
2613 * (defined above). Tease them out and add them to the global modes list.
2616 add_established_modes(struct drm_connector *connector, struct edid *edid)
2618 struct drm_device *dev = connector->dev;
2619 unsigned long est_bits = edid->established_timings.t1 |
2620 (edid->established_timings.t2 << 8) |
2621 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2623 struct detailed_mode_closure closure = {
2624 .connector = connector,
2628 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2629 if (est_bits & (1<<i)) {
2630 struct drm_display_mode *newmode;
2631 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2633 drm_mode_probed_add(connector, newmode);
2639 if (version_greater(edid, 1, 0))
2640 drm_for_each_detailed_block((u8 *)edid,
2641 do_established_modes, &closure);
2643 return modes + closure.modes;
2647 do_standard_modes(struct detailed_timing *timing, void *c)
2649 struct detailed_mode_closure *closure = c;
2650 struct detailed_non_pixel *data = &timing->data.other_data;
2651 struct drm_connector *connector = closure->connector;
2652 struct edid *edid = closure->edid;
2654 if (data->type == EDID_DETAIL_STD_MODES) {
2656 for (i = 0; i < 6; i++) {
2657 struct std_timing *std;
2658 struct drm_display_mode *newmode;
2660 std = &data->data.timings[i];
2661 newmode = drm_mode_std(connector, edid, std);
2663 drm_mode_probed_add(connector, newmode);
2671 * add_standard_modes - get std. modes from EDID and add them
2672 * @connector: connector to add mode(s) to
2673 * @edid: EDID block to scan
2675 * Standard modes can be calculated using the appropriate standard (DMT,
2676 * GTF or CVT. Grab them from @edid and add them to the list.
2679 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2682 struct detailed_mode_closure closure = {
2683 .connector = connector,
2687 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2688 struct drm_display_mode *newmode;
2690 newmode = drm_mode_std(connector, edid,
2691 &edid->standard_timings[i]);
2693 drm_mode_probed_add(connector, newmode);
2698 if (version_greater(edid, 1, 0))
2699 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2702 /* XXX should also look for standard codes in VTB blocks */
2704 return modes + closure.modes;
2707 static int drm_cvt_modes(struct drm_connector *connector,
2708 struct detailed_timing *timing)
2710 int i, j, modes = 0;
2711 struct drm_display_mode *newmode;
2712 struct drm_device *dev = connector->dev;
2713 struct cvt_timing *cvt;
2714 const int rates[] = { 60, 85, 75, 60, 50 };
2715 const u8 empty[3] = { 0, 0, 0 };
2717 for (i = 0; i < 4; i++) {
2718 int uninitialized_var(width), height;
2719 cvt = &(timing->data.other_data.data.cvt[i]);
2721 if (!memcmp(cvt->code, empty, 3))
2724 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2725 switch (cvt->code[1] & 0x0c) {
2727 width = height * 4 / 3;
2730 width = height * 16 / 9;
2733 width = height * 16 / 10;
2736 width = height * 15 / 9;
2740 for (j = 1; j < 5; j++) {
2741 if (cvt->code[2] & (1 << j)) {
2742 newmode = drm_cvt_mode(dev, width, height,
2746 drm_mode_probed_add(connector, newmode);
2757 do_cvt_mode(struct detailed_timing *timing, void *c)
2759 struct detailed_mode_closure *closure = c;
2760 struct detailed_non_pixel *data = &timing->data.other_data;
2762 if (data->type == EDID_DETAIL_CVT_3BYTE)
2763 closure->modes += drm_cvt_modes(closure->connector, timing);
2767 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2769 struct detailed_mode_closure closure = {
2770 .connector = connector,
2774 if (version_greater(edid, 1, 2))
2775 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2777 /* XXX should also look for CVT codes in VTB blocks */
2779 return closure.modes;
2782 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2785 do_detailed_mode(struct detailed_timing *timing, void *c)
2787 struct detailed_mode_closure *closure = c;
2788 struct drm_display_mode *newmode;
2790 if (timing->pixel_clock) {
2791 newmode = drm_mode_detailed(closure->connector->dev,
2792 closure->edid, timing,
2797 if (closure->preferred)
2798 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2801 * Detailed modes are limited to 10kHz pixel clock resolution,
2802 * so fix up anything that looks like CEA/HDMI mode, but the clock
2803 * is just slightly off.
2805 fixup_detailed_cea_mode_clock(newmode);
2807 drm_mode_probed_add(closure->connector, newmode);
2809 closure->preferred = false;
2814 * add_detailed_modes - Add modes from detailed timings
2815 * @connector: attached connector
2816 * @edid: EDID block to scan
2817 * @quirks: quirks to apply
2820 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2823 struct detailed_mode_closure closure = {
2824 .connector = connector,
2830 if (closure.preferred && !version_greater(edid, 1, 3))
2832 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2834 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2836 return closure.modes;
2839 #define AUDIO_BLOCK 0x01
2840 #define VIDEO_BLOCK 0x02
2841 #define VENDOR_BLOCK 0x03
2842 #define SPEAKER_BLOCK 0x04
2843 #define USE_EXTENDED_TAG 0x07
2844 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2845 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2846 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2847 #define EDID_BASIC_AUDIO (1 << 6)
2848 #define EDID_CEA_YCRCB444 (1 << 5)
2849 #define EDID_CEA_YCRCB422 (1 << 4)
2850 #define EDID_CEA_VCDB_QS (1 << 6)
2853 * Search EDID for CEA extension block.
2855 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2857 u8 *edid_ext = NULL;
2860 /* No EDID or EDID extensions */
2861 if (edid == NULL || edid->extensions == 0)
2864 /* Find CEA extension */
2865 for (i = 0; i < edid->extensions; i++) {
2866 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2867 if (edid_ext[0] == ext_id)
2871 if (i == edid->extensions)
2877 static u8 *drm_find_cea_extension(const struct edid *edid)
2879 return drm_find_edid_extension(edid, CEA_EXT);
2882 static u8 *drm_find_displayid_extension(const struct edid *edid)
2884 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2888 * Calculate the alternate clock for the CEA mode
2889 * (60Hz vs. 59.94Hz etc.)
2892 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2894 unsigned int clock = cea_mode->clock;
2896 if (cea_mode->vrefresh % 6 != 0)
2900 * edid_cea_modes contains the 59.94Hz
2901 * variant for 240 and 480 line modes,
2902 * and the 60Hz variant otherwise.
2904 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2905 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2907 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2913 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2916 * For certain VICs the spec allows the vertical
2917 * front porch to vary by one or two lines.
2919 * cea_modes[] stores the variant with the shortest
2920 * vertical front porch. We can adjust the mode to
2921 * get the other variants by simply increasing the
2922 * vertical front porch length.
2924 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2925 edid_cea_modes[9].vtotal != 262 ||
2926 edid_cea_modes[12].vtotal != 262 ||
2927 edid_cea_modes[13].vtotal != 262 ||
2928 edid_cea_modes[23].vtotal != 312 ||
2929 edid_cea_modes[24].vtotal != 312 ||
2930 edid_cea_modes[27].vtotal != 312 ||
2931 edid_cea_modes[28].vtotal != 312);
2933 if (((vic == 8 || vic == 9 ||
2934 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2935 ((vic == 23 || vic == 24 ||
2936 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2937 mode->vsync_start++;
2947 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2948 unsigned int clock_tolerance)
2950 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2953 if (!to_match->clock)
2956 if (to_match->picture_aspect_ratio)
2957 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2959 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2960 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2961 unsigned int clock1, clock2;
2963 /* Check both 60Hz and 59.94Hz */
2964 clock1 = cea_mode.clock;
2965 clock2 = cea_mode_alternate_clock(&cea_mode);
2967 if (abs(to_match->clock - clock1) > clock_tolerance &&
2968 abs(to_match->clock - clock2) > clock_tolerance)
2972 if (drm_mode_match(to_match, &cea_mode, match_flags))
2974 } while (cea_mode_alternate_timings(vic, &cea_mode));
2981 * drm_match_cea_mode - look for a CEA mode matching given mode
2982 * @to_match: display mode
2984 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2987 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2989 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2992 if (!to_match->clock)
2995 if (to_match->picture_aspect_ratio)
2996 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2998 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2999 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3000 unsigned int clock1, clock2;
3002 /* Check both 60Hz and 59.94Hz */
3003 clock1 = cea_mode.clock;
3004 clock2 = cea_mode_alternate_clock(&cea_mode);
3006 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3007 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3011 if (drm_mode_match(to_match, &cea_mode, match_flags))
3013 } while (cea_mode_alternate_timings(vic, &cea_mode));
3018 EXPORT_SYMBOL(drm_match_cea_mode);
3020 static bool drm_valid_cea_vic(u8 vic)
3022 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3026 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3027 * the input VIC from the CEA mode list
3028 * @video_code: ID given to each of the CEA modes
3030 * Returns picture aspect ratio
3032 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3034 return edid_cea_modes[video_code].picture_aspect_ratio;
3036 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3039 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3042 * It's almost like cea_mode_alternate_clock(), we just need to add an
3043 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3047 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3049 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3050 return hdmi_mode->clock;
3052 return cea_mode_alternate_clock(hdmi_mode);
3055 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3056 unsigned int clock_tolerance)
3058 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3061 if (!to_match->clock)
3064 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3065 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3066 unsigned int clock1, clock2;
3068 /* Make sure to also match alternate clocks */
3069 clock1 = hdmi_mode->clock;
3070 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3072 if (abs(to_match->clock - clock1) > clock_tolerance &&
3073 abs(to_match->clock - clock2) > clock_tolerance)
3076 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3084 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3085 * @to_match: display mode
3087 * An HDMI mode is one defined in the HDMI vendor specific block.
3089 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3091 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3093 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3096 if (!to_match->clock)
3099 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3100 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3101 unsigned int clock1, clock2;
3103 /* Make sure to also match alternate clocks */
3104 clock1 = hdmi_mode->clock;
3105 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3107 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3108 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3109 drm_mode_match(to_match, hdmi_mode, match_flags))
3115 static bool drm_valid_hdmi_vic(u8 vic)
3117 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3121 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3123 struct drm_device *dev = connector->dev;
3124 struct drm_display_mode *mode, *tmp;
3128 /* Don't add CEA modes if the CEA extension block is missing */
3129 if (!drm_find_cea_extension(edid))
3133 * Go through all probed modes and create a new mode
3134 * with the alternate clock for certain CEA modes.
3136 list_for_each_entry(mode, &connector->probed_modes, head) {
3137 const struct drm_display_mode *cea_mode = NULL;
3138 struct drm_display_mode *newmode;
3139 u8 vic = drm_match_cea_mode(mode);
3140 unsigned int clock1, clock2;
3142 if (drm_valid_cea_vic(vic)) {
3143 cea_mode = &edid_cea_modes[vic];
3144 clock2 = cea_mode_alternate_clock(cea_mode);
3146 vic = drm_match_hdmi_mode(mode);
3147 if (drm_valid_hdmi_vic(vic)) {
3148 cea_mode = &edid_4k_modes[vic];
3149 clock2 = hdmi_mode_alternate_clock(cea_mode);
3156 clock1 = cea_mode->clock;
3158 if (clock1 == clock2)
3161 if (mode->clock != clock1 && mode->clock != clock2)
3164 newmode = drm_mode_duplicate(dev, cea_mode);
3168 /* Carry over the stereo flags */
3169 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3172 * The current mode could be either variant. Make
3173 * sure to pick the "other" clock for the new mode.
3175 if (mode->clock != clock1)
3176 newmode->clock = clock1;
3178 newmode->clock = clock2;
3180 list_add_tail(&newmode->head, &list);
3183 list_for_each_entry_safe(mode, tmp, &list, head) {
3184 list_del(&mode->head);
3185 drm_mode_probed_add(connector, mode);
3192 static u8 svd_to_vic(u8 svd)
3194 /* 0-6 bit vic, 7th bit native mode indicator */
3195 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3201 static struct drm_display_mode *
3202 drm_display_mode_from_vic_index(struct drm_connector *connector,
3203 const u8 *video_db, u8 video_len,
3206 struct drm_device *dev = connector->dev;
3207 struct drm_display_mode *newmode;
3210 if (video_db == NULL || video_index >= video_len)
3213 /* CEA modes are numbered 1..127 */
3214 vic = svd_to_vic(video_db[video_index]);
3215 if (!drm_valid_cea_vic(vic))
3218 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3222 newmode->vrefresh = 0;
3228 * do_y420vdb_modes - Parse YCBCR 420 only modes
3229 * @connector: connector corresponding to the HDMI sink
3230 * @svds: start of the data block of CEA YCBCR 420 VDB
3231 * @len: length of the CEA YCBCR 420 VDB
3233 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3234 * which contains modes which can be supported in YCBCR 420
3235 * output format only.
3237 static int do_y420vdb_modes(struct drm_connector *connector,
3238 const u8 *svds, u8 svds_len)
3241 struct drm_device *dev = connector->dev;
3242 struct drm_display_info *info = &connector->display_info;
3243 struct drm_hdmi_info *hdmi = &info->hdmi;
3245 for (i = 0; i < svds_len; i++) {
3246 u8 vic = svd_to_vic(svds[i]);
3247 struct drm_display_mode *newmode;
3249 if (!drm_valid_cea_vic(vic))
3252 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3255 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3256 drm_mode_probed_add(connector, newmode);
3261 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3266 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3267 * @connector: connector corresponding to the HDMI sink
3268 * @vic: CEA vic for the video mode to be added in the map
3270 * Makes an entry for a videomode in the YCBCR 420 bitmap
3273 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3275 u8 vic = svd_to_vic(svd);
3276 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3278 if (!drm_valid_cea_vic(vic))
3281 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3285 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3288 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3290 for (i = 0; i < len; i++) {
3291 struct drm_display_mode *mode;
3292 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3295 * YCBCR420 capability block contains a bitmap which
3296 * gives the index of CEA modes from CEA VDB, which
3297 * can support YCBCR 420 sampling output also (apart
3298 * from RGB/YCBCR444 etc).
3299 * For example, if the bit 0 in bitmap is set,
3300 * first mode in VDB can support YCBCR420 output too.
3301 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3303 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3304 drm_add_cmdb_modes(connector, db[i]);
3306 drm_mode_probed_add(connector, mode);
3314 struct stereo_mandatory_mode {
3315 int width, height, vrefresh;
3319 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3320 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3321 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3323 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3325 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3326 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3327 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3328 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3329 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3333 stereo_match_mandatory(const struct drm_display_mode *mode,
3334 const struct stereo_mandatory_mode *stereo_mode)
3336 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3338 return mode->hdisplay == stereo_mode->width &&
3339 mode->vdisplay == stereo_mode->height &&
3340 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3341 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3344 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3346 struct drm_device *dev = connector->dev;
3347 const struct drm_display_mode *mode;
3348 struct list_head stereo_modes;
3351 INIT_LIST_HEAD(&stereo_modes);
3353 list_for_each_entry(mode, &connector->probed_modes, head) {
3354 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3355 const struct stereo_mandatory_mode *mandatory;
3356 struct drm_display_mode *new_mode;
3358 if (!stereo_match_mandatory(mode,
3359 &stereo_mandatory_modes[i]))
3362 mandatory = &stereo_mandatory_modes[i];
3363 new_mode = drm_mode_duplicate(dev, mode);
3367 new_mode->flags |= mandatory->flags;
3368 list_add_tail(&new_mode->head, &stereo_modes);
3373 list_splice_tail(&stereo_modes, &connector->probed_modes);
3378 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3380 struct drm_device *dev = connector->dev;
3381 struct drm_display_mode *newmode;
3383 if (!drm_valid_hdmi_vic(vic)) {
3384 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3388 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3392 drm_mode_probed_add(connector, newmode);
3397 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3398 const u8 *video_db, u8 video_len, u8 video_index)
3400 struct drm_display_mode *newmode;
3403 if (structure & (1 << 0)) {
3404 newmode = drm_display_mode_from_vic_index(connector, video_db,
3408 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3409 drm_mode_probed_add(connector, newmode);
3413 if (structure & (1 << 6)) {
3414 newmode = drm_display_mode_from_vic_index(connector, video_db,
3418 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3419 drm_mode_probed_add(connector, newmode);
3423 if (structure & (1 << 8)) {
3424 newmode = drm_display_mode_from_vic_index(connector, video_db,
3428 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3429 drm_mode_probed_add(connector, newmode);
3438 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3439 * @connector: connector corresponding to the HDMI sink
3440 * @db: start of the CEA vendor specific block
3441 * @len: length of the CEA block payload, ie. one can access up to db[len]
3443 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3444 * also adds the stereo 3d modes when applicable.
3447 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3448 const u8 *video_db, u8 video_len)
3450 struct drm_display_info *info = &connector->display_info;
3451 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3452 u8 vic_len, hdmi_3d_len = 0;
3459 /* no HDMI_Video_Present */
3460 if (!(db[8] & (1 << 5)))
3463 /* Latency_Fields_Present */
3464 if (db[8] & (1 << 7))
3467 /* I_Latency_Fields_Present */
3468 if (db[8] & (1 << 6))
3471 /* the declared length is not long enough for the 2 first bytes
3472 * of additional video format capabilities */
3473 if (len < (8 + offset + 2))
3478 if (db[8 + offset] & (1 << 7)) {
3479 modes += add_hdmi_mandatory_stereo_modes(connector);
3481 /* 3D_Multi_present */
3482 multi_present = (db[8 + offset] & 0x60) >> 5;
3486 vic_len = db[8 + offset] >> 5;
3487 hdmi_3d_len = db[8 + offset] & 0x1f;
3489 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3492 vic = db[9 + offset + i];
3493 modes += add_hdmi_mode(connector, vic);
3495 offset += 1 + vic_len;
3497 if (multi_present == 1)
3499 else if (multi_present == 2)
3504 if (len < (8 + offset + hdmi_3d_len - 1))
3507 if (hdmi_3d_len < multi_len)
3510 if (multi_present == 1 || multi_present == 2) {
3511 /* 3D_Structure_ALL */
3512 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3514 /* check if 3D_MASK is present */
3515 if (multi_present == 2)
3516 mask = (db[10 + offset] << 8) | db[11 + offset];
3520 for (i = 0; i < 16; i++) {
3521 if (mask & (1 << i))
3522 modes += add_3d_struct_modes(connector,
3529 offset += multi_len;
3531 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3533 struct drm_display_mode *newmode = NULL;
3534 unsigned int newflag = 0;
3535 bool detail_present;
3537 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3539 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3542 /* 2D_VIC_order_X */
3543 vic_index = db[8 + offset + i] >> 4;
3545 /* 3D_Structure_X */
3546 switch (db[8 + offset + i] & 0x0f) {
3548 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3551 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3555 if ((db[9 + offset + i] >> 4) == 1)
3556 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3561 newmode = drm_display_mode_from_vic_index(connector,
3567 newmode->flags |= newflag;
3568 drm_mode_probed_add(connector, newmode);
3579 info->has_hdmi_infoframe = true;
3584 cea_db_payload_len(const u8 *db)
3586 return db[0] & 0x1f;
3590 cea_db_extended_tag(const u8 *db)
3596 cea_db_tag(const u8 *db)
3602 cea_revision(const u8 *cea)
3608 cea_db_offsets(const u8 *cea, int *start, int *end)
3610 /* Data block offset in CEA extension block */
3615 if (*end < 4 || *end > 127)
3620 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3624 if (cea_db_tag(db) != VENDOR_BLOCK)
3627 if (cea_db_payload_len(db) < 5)
3630 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3632 return hdmi_id == HDMI_IEEE_OUI;
3635 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3639 if (cea_db_tag(db) != VENDOR_BLOCK)
3642 if (cea_db_payload_len(db) < 7)
3645 oui = db[3] << 16 | db[2] << 8 | db[1];
3647 return oui == HDMI_FORUM_IEEE_OUI;
3650 static bool cea_db_is_vcdb(const u8 *db)
3652 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3655 if (cea_db_payload_len(db) != 2)
3658 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3664 static bool cea_db_is_y420cmdb(const u8 *db)
3666 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3669 if (!cea_db_payload_len(db))
3672 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3678 static bool cea_db_is_y420vdb(const u8 *db)
3680 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3683 if (!cea_db_payload_len(db))
3686 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3692 #define for_each_cea_db(cea, i, start, end) \
3693 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3695 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3698 struct drm_display_info *info = &connector->display_info;
3699 struct drm_hdmi_info *hdmi = &info->hdmi;
3700 u8 map_len = cea_db_payload_len(db) - 1;
3705 /* All CEA modes support ycbcr420 sampling also.*/
3706 hdmi->y420_cmdb_map = U64_MAX;
3707 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3712 * This map indicates which of the existing CEA block modes
3713 * from VDB can support YCBCR420 output too. So if bit=0 is
3714 * set, first mode from VDB can support YCBCR420 output too.
3715 * We will parse and keep this map, before parsing VDB itself
3716 * to avoid going through the same block again and again.
3718 * Spec is not clear about max possible size of this block.
3719 * Clamping max bitmap block size at 8 bytes. Every byte can
3720 * address 8 CEA modes, in this way this map can address
3721 * 8*8 = first 64 SVDs.
3723 if (WARN_ON_ONCE(map_len > 8))
3726 for (count = 0; count < map_len; count++)
3727 map |= (u64)db[2 + count] << (8 * count);
3730 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3732 hdmi->y420_cmdb_map = map;
3736 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3738 const u8 *cea = drm_find_cea_extension(edid);
3739 const u8 *db, *hdmi = NULL, *video = NULL;
3740 u8 dbl, hdmi_len, video_len = 0;
3743 if (cea && cea_revision(cea) >= 3) {
3746 if (cea_db_offsets(cea, &start, &end))
3749 for_each_cea_db(cea, i, start, end) {
3751 dbl = cea_db_payload_len(db);
3753 if (cea_db_tag(db) == VIDEO_BLOCK) {
3756 modes += do_cea_modes(connector, video, dbl);
3757 } else if (cea_db_is_hdmi_vsdb(db)) {
3760 } else if (cea_db_is_y420vdb(db)) {
3761 const u8 *vdb420 = &db[2];
3763 /* Add 4:2:0(only) modes present in EDID */
3764 modes += do_y420vdb_modes(connector,
3772 * We parse the HDMI VSDB after having added the cea modes as we will
3773 * be patching their flags when the sink supports stereo 3D.
3776 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3782 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3784 const struct drm_display_mode *cea_mode;
3785 int clock1, clock2, clock;
3790 * allow 5kHz clock difference either way to account for
3791 * the 10kHz clock resolution limit of detailed timings.
3793 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3794 if (drm_valid_cea_vic(vic)) {
3796 cea_mode = &edid_cea_modes[vic];
3797 clock1 = cea_mode->clock;
3798 clock2 = cea_mode_alternate_clock(cea_mode);
3800 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3801 if (drm_valid_hdmi_vic(vic)) {
3803 cea_mode = &edid_4k_modes[vic];
3804 clock1 = cea_mode->clock;
3805 clock2 = hdmi_mode_alternate_clock(cea_mode);
3811 /* pick whichever is closest */
3812 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3817 if (mode->clock == clock)
3820 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3821 type, vic, mode->clock, clock);
3822 mode->clock = clock;
3826 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3828 u8 len = cea_db_payload_len(db);
3830 if (len >= 6 && (db[6] & (1 << 7)))
3831 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3833 connector->latency_present[0] = db[8] >> 7;
3834 connector->latency_present[1] = (db[8] >> 6) & 1;
3837 connector->video_latency[0] = db[9];
3839 connector->audio_latency[0] = db[10];
3841 connector->video_latency[1] = db[11];
3843 connector->audio_latency[1] = db[12];
3845 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3846 "video latency %d %d, "
3847 "audio latency %d %d\n",
3848 connector->latency_present[0],
3849 connector->latency_present[1],
3850 connector->video_latency[0],
3851 connector->video_latency[1],
3852 connector->audio_latency[0],
3853 connector->audio_latency[1]);
3857 monitor_name(struct detailed_timing *t, void *data)
3859 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3860 *(u8 **)data = t->data.other_data.data.str.str;
3863 static int get_monitor_name(struct edid *edid, char name[13])
3865 char *edid_name = NULL;
3871 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3872 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3873 if (edid_name[mnl] == 0x0a)
3876 name[mnl] = edid_name[mnl];
3883 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3884 * @edid: monitor EDID information
3885 * @name: pointer to a character array to hold the name of the monitor
3886 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3889 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3897 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3898 memcpy(name, buf, name_length);
3899 name[name_length] = '\0';
3901 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3903 static void clear_eld(struct drm_connector *connector)
3905 memset(connector->eld, 0, sizeof(connector->eld));
3907 connector->latency_present[0] = false;
3908 connector->latency_present[1] = false;
3909 connector->video_latency[0] = 0;
3910 connector->audio_latency[0] = 0;
3911 connector->video_latency[1] = 0;
3912 connector->audio_latency[1] = 0;
3916 * drm_edid_to_eld - build ELD from EDID
3917 * @connector: connector corresponding to the HDMI/DP sink
3918 * @edid: EDID to parse
3920 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3921 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3923 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3925 uint8_t *eld = connector->eld;
3928 int total_sad_count = 0;
3932 clear_eld(connector);
3937 cea = drm_find_cea_extension(edid);
3939 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3943 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3944 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
3946 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3947 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
3949 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
3951 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3952 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3953 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3954 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
3956 if (cea_revision(cea) >= 3) {
3959 if (cea_db_offsets(cea, &start, &end)) {
3964 for_each_cea_db(cea, i, start, end) {
3966 dbl = cea_db_payload_len(db);
3968 switch (cea_db_tag(db)) {
3972 /* Audio Data Block, contains SADs */
3973 sad_count = min(dbl / 3, 15 - total_sad_count);
3975 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
3976 &db[1], sad_count * 3);
3977 total_sad_count += sad_count;
3980 /* Speaker Allocation Data Block */
3982 eld[DRM_ELD_SPEAKER] = db[1];
3985 /* HDMI Vendor-Specific Data Block */
3986 if (cea_db_is_hdmi_vsdb(db))
3987 drm_parse_hdmi_vsdb_audio(connector, db);
3994 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
3996 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3997 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3998 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4000 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4002 eld[DRM_ELD_BASELINE_ELD_LEN] =
4003 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4005 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4006 drm_eld_size(eld), total_sad_count);
4010 * drm_edid_to_sad - extracts SADs from EDID
4011 * @edid: EDID to parse
4012 * @sads: pointer that will be set to the extracted SADs
4014 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4016 * Note: The returned pointer needs to be freed using kfree().
4018 * Return: The number of found SADs or negative number on error.
4020 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4023 int i, start, end, dbl;
4026 cea = drm_find_cea_extension(edid);
4028 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4032 if (cea_revision(cea) < 3) {
4033 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4037 if (cea_db_offsets(cea, &start, &end)) {
4038 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4042 for_each_cea_db(cea, i, start, end) {
4045 if (cea_db_tag(db) == AUDIO_BLOCK) {
4047 dbl = cea_db_payload_len(db);
4049 count = dbl / 3; /* SAD is 3B */
4050 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4053 for (j = 0; j < count; j++) {
4054 u8 *sad = &db[1 + j * 3];
4056 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4057 (*sads)[j].channels = sad[0] & 0x7;
4058 (*sads)[j].freq = sad[1] & 0x7F;
4059 (*sads)[j].byte2 = sad[2];
4067 EXPORT_SYMBOL(drm_edid_to_sad);
4070 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4071 * @edid: EDID to parse
4072 * @sadb: pointer to the speaker block
4074 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4076 * Note: The returned pointer needs to be freed using kfree().
4078 * Return: The number of found Speaker Allocation Blocks or negative number on
4081 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4084 int i, start, end, dbl;
4087 cea = drm_find_cea_extension(edid);
4089 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4093 if (cea_revision(cea) < 3) {
4094 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4098 if (cea_db_offsets(cea, &start, &end)) {
4099 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4103 for_each_cea_db(cea, i, start, end) {
4104 const u8 *db = &cea[i];
4106 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4107 dbl = cea_db_payload_len(db);
4109 /* Speaker Allocation Data Block */
4111 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4122 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4125 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4126 * @connector: connector associated with the HDMI/DP sink
4127 * @mode: the display mode
4129 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4130 * the sink doesn't support audio or video.
4132 int drm_av_sync_delay(struct drm_connector *connector,
4133 const struct drm_display_mode *mode)
4135 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4138 if (!connector->latency_present[0])
4140 if (!connector->latency_present[1])
4143 a = connector->audio_latency[i];
4144 v = connector->video_latency[i];
4147 * HDMI/DP sink doesn't support audio or video?
4149 if (a == 255 || v == 255)
4153 * Convert raw EDID values to millisecond.
4154 * Treat unknown latency as 0ms.
4157 a = min(2 * (a - 1), 500);
4159 v = min(2 * (v - 1), 500);
4161 return max(v - a, 0);
4163 EXPORT_SYMBOL(drm_av_sync_delay);
4166 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4167 * @edid: monitor EDID information
4169 * Parse the CEA extension according to CEA-861-B.
4171 * Return: True if the monitor is HDMI, false if not or unknown.
4173 bool drm_detect_hdmi_monitor(struct edid *edid)
4177 int start_offset, end_offset;
4179 edid_ext = drm_find_cea_extension(edid);
4183 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4187 * Because HDMI identifier is in Vendor Specific Block,
4188 * search it from all data blocks of CEA extension.
4190 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4191 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4197 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4200 * drm_detect_monitor_audio - check monitor audio capability
4201 * @edid: EDID block to scan
4203 * Monitor should have CEA extension block.
4204 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4205 * audio' only. If there is any audio extension block and supported
4206 * audio format, assume at least 'basic audio' support, even if 'basic
4207 * audio' is not defined in EDID.
4209 * Return: True if the monitor supports audio, false otherwise.
4211 bool drm_detect_monitor_audio(struct edid *edid)
4215 bool has_audio = false;
4216 int start_offset, end_offset;
4218 edid_ext = drm_find_cea_extension(edid);
4222 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4225 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4229 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4232 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4233 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4235 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4236 DRM_DEBUG_KMS("CEA audio format %d\n",
4237 (edid_ext[i + j] >> 3) & 0xf);
4244 EXPORT_SYMBOL(drm_detect_monitor_audio);
4248 * drm_default_rgb_quant_range - default RGB quantization range
4249 * @mode: display mode
4251 * Determine the default RGB quantization range for the mode,
4252 * as specified in CEA-861.
4254 * Return: The default RGB quantization range for the mode
4256 enum hdmi_quantization_range
4257 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4259 /* All CEA modes other than VIC 1 use limited quantization range. */
4260 return drm_match_cea_mode(mode) > 1 ?
4261 HDMI_QUANTIZATION_RANGE_LIMITED :
4262 HDMI_QUANTIZATION_RANGE_FULL;
4264 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4266 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4268 struct drm_display_info *info = &connector->display_info;
4270 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4272 if (db[2] & EDID_CEA_VCDB_QS)
4273 info->rgb_quant_range_selectable = true;
4276 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4280 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4282 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4283 hdmi->y420_dc_modes = dc_mask;
4286 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4289 struct drm_display_info *display = &connector->display_info;
4290 struct drm_hdmi_info *hdmi = &display->hdmi;
4292 display->has_hdmi_infoframe = true;
4294 if (hf_vsdb[6] & 0x80) {
4295 hdmi->scdc.supported = true;
4296 if (hf_vsdb[6] & 0x40)
4297 hdmi->scdc.read_request = true;
4301 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4302 * And as per the spec, three factors confirm this:
4303 * * Availability of a HF-VSDB block in EDID (check)
4304 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4305 * * SCDC support available (let's check)
4306 * Lets check it out.
4310 /* max clock is 5000 KHz times block value */
4311 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4312 struct drm_scdc *scdc = &hdmi->scdc;
4314 if (max_tmds_clock > 340000) {
4315 display->max_tmds_clock = max_tmds_clock;
4316 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4317 display->max_tmds_clock);
4320 if (scdc->supported) {
4321 scdc->scrambling.supported = true;
4323 /* Few sinks support scrambling for cloks < 340M */
4324 if ((hf_vsdb[6] & 0x8))
4325 scdc->scrambling.low_rates = true;
4329 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4332 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4335 struct drm_display_info *info = &connector->display_info;
4336 unsigned int dc_bpc = 0;
4338 /* HDMI supports at least 8 bpc */
4341 if (cea_db_payload_len(hdmi) < 6)
4344 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4346 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4347 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4351 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4353 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4354 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4358 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4360 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4361 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4366 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4371 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4372 connector->name, dc_bpc);
4376 * Deep color support mandates RGB444 support for all video
4377 * modes and forbids YCRCB422 support for all video modes per
4380 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4382 /* YCRCB444 is optional according to spec. */
4383 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4384 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4385 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4390 * Spec says that if any deep color mode is supported at all,
4391 * then deep color 36 bit must be supported.
4393 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4394 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4400 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4402 struct drm_display_info *info = &connector->display_info;
4403 u8 len = cea_db_payload_len(db);
4406 info->dvi_dual = db[6] & 1;
4408 info->max_tmds_clock = db[7] * 5000;
4410 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4411 "max TMDS clock %d kHz\n",
4413 info->max_tmds_clock);
4415 drm_parse_hdmi_deep_color_info(connector, db);
4418 static void drm_parse_cea_ext(struct drm_connector *connector,
4419 const struct edid *edid)
4421 struct drm_display_info *info = &connector->display_info;
4425 edid_ext = drm_find_cea_extension(edid);
4429 info->cea_rev = edid_ext[1];
4431 /* The existence of a CEA block should imply RGB support */
4432 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4433 if (edid_ext[3] & EDID_CEA_YCRCB444)
4434 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4435 if (edid_ext[3] & EDID_CEA_YCRCB422)
4436 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4438 if (cea_db_offsets(edid_ext, &start, &end))
4441 for_each_cea_db(edid_ext, i, start, end) {
4442 const u8 *db = &edid_ext[i];
4444 if (cea_db_is_hdmi_vsdb(db))
4445 drm_parse_hdmi_vsdb_video(connector, db);
4446 if (cea_db_is_hdmi_forum_vsdb(db))
4447 drm_parse_hdmi_forum_vsdb(connector, db);
4448 if (cea_db_is_y420cmdb(db))
4449 drm_parse_y420cmdb_bitmap(connector, db);
4450 if (cea_db_is_vcdb(db))
4451 drm_parse_vcdb(connector, db);
4455 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4456 * all of the values which would have been set from EDID
4459 drm_reset_display_info(struct drm_connector *connector)
4461 struct drm_display_info *info = &connector->display_info;
4464 info->height_mm = 0;
4467 info->color_formats = 0;
4469 info->max_tmds_clock = 0;
4470 info->dvi_dual = false;
4471 info->has_hdmi_infoframe = false;
4472 info->rgb_quant_range_selectable = false;
4473 memset(&info->hdmi, 0, sizeof(info->hdmi));
4475 info->non_desktop = 0;
4478 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4480 struct drm_display_info *info = &connector->display_info;
4482 u32 quirks = edid_get_quirks(edid);
4484 drm_reset_display_info(connector);
4486 info->width_mm = edid->width_cm * 10;
4487 info->height_mm = edid->height_cm * 10;
4489 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4491 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4493 if (edid->revision < 3)
4496 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4499 drm_parse_cea_ext(connector, edid);
4502 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4504 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4505 * tells us to assume 8 bpc color depth if the EDID doesn't have
4506 * extensions which tell otherwise.
4508 if ((info->bpc == 0) && (edid->revision < 4) &&
4509 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4511 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4512 connector->name, info->bpc);
4515 /* Only defined for 1.4 with digital displays */
4516 if (edid->revision < 4)
4519 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4520 case DRM_EDID_DIGITAL_DEPTH_6:
4523 case DRM_EDID_DIGITAL_DEPTH_8:
4526 case DRM_EDID_DIGITAL_DEPTH_10:
4529 case DRM_EDID_DIGITAL_DEPTH_12:
4532 case DRM_EDID_DIGITAL_DEPTH_14:
4535 case DRM_EDID_DIGITAL_DEPTH_16:
4538 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4544 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4545 connector->name, info->bpc);
4547 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4548 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4549 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4550 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4551 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4555 static int validate_displayid(u8 *displayid, int length, int idx)
4559 struct displayid_hdr *base;
4561 base = (struct displayid_hdr *)&displayid[idx];
4563 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4564 base->rev, base->bytes, base->prod_id, base->ext_count);
4566 if (base->bytes + 5 > length - idx)
4568 for (i = idx; i <= base->bytes + 5; i++) {
4569 csum += displayid[i];
4572 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4578 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4579 struct displayid_detailed_timings_1 *timings)
4581 struct drm_display_mode *mode;
4582 unsigned pixel_clock = (timings->pixel_clock[0] |
4583 (timings->pixel_clock[1] << 8) |
4584 (timings->pixel_clock[2] << 16));
4585 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4586 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4587 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4588 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4589 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4590 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4591 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4592 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4593 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4594 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4595 mode = drm_mode_create(dev);
4599 mode->clock = pixel_clock * 10;
4600 mode->hdisplay = hactive;
4601 mode->hsync_start = mode->hdisplay + hsync;
4602 mode->hsync_end = mode->hsync_start + hsync_width;
4603 mode->htotal = mode->hdisplay + hblank;
4605 mode->vdisplay = vactive;
4606 mode->vsync_start = mode->vdisplay + vsync;
4607 mode->vsync_end = mode->vsync_start + vsync_width;
4608 mode->vtotal = mode->vdisplay + vblank;
4611 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4612 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4613 mode->type = DRM_MODE_TYPE_DRIVER;
4615 if (timings->flags & 0x80)
4616 mode->type |= DRM_MODE_TYPE_PREFERRED;
4617 mode->vrefresh = drm_mode_vrefresh(mode);
4618 drm_mode_set_name(mode);
4623 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4624 struct displayid_block *block)
4626 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4629 struct drm_display_mode *newmode;
4631 /* blocks must be multiple of 20 bytes length */
4632 if (block->num_bytes % 20)
4635 num_timings = block->num_bytes / 20;
4636 for (i = 0; i < num_timings; i++) {
4637 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4639 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4643 drm_mode_probed_add(connector, newmode);
4649 static int add_displayid_detailed_modes(struct drm_connector *connector,
4655 int length = EDID_LENGTH;
4656 struct displayid_block *block;
4659 displayid = drm_find_displayid_extension(edid);
4663 ret = validate_displayid(displayid, length, idx);
4667 idx += sizeof(struct displayid_hdr);
4668 while (block = (struct displayid_block *)&displayid[idx],
4669 idx + sizeof(struct displayid_block) <= length &&
4670 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4671 block->num_bytes > 0) {
4672 idx += block->num_bytes + sizeof(struct displayid_block);
4673 switch (block->tag) {
4674 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4675 num_modes += add_displayid_detailed_1_modes(connector, block);
4683 * drm_add_edid_modes - add modes from EDID data, if available
4684 * @connector: connector we're probing
4687 * Add the specified modes to the connector's mode list. Also fills out the
4688 * &drm_display_info structure and ELD in @connector with any information which
4689 * can be derived from the edid.
4691 * Return: The number of modes added or 0 if we couldn't find any.
4693 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4699 clear_eld(connector);
4702 if (!drm_edid_is_valid(edid)) {
4703 clear_eld(connector);
4704 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4709 drm_edid_to_eld(connector, edid);
4712 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4713 * To avoid multiple parsing of same block, lets parse that map
4714 * from sink info, before parsing CEA modes.
4716 quirks = drm_add_display_info(connector, edid);
4719 * EDID spec says modes should be preferred in this order:
4720 * - preferred detailed mode
4721 * - other detailed modes from base block
4722 * - detailed modes from extension blocks
4723 * - CVT 3-byte code modes
4724 * - standard timing codes
4725 * - established timing codes
4726 * - modes inferred from GTF or CVT range information
4728 * We get this pretty much right.
4730 * XXX order for additional mode types in extension blocks?
4732 num_modes += add_detailed_modes(connector, edid, quirks);
4733 num_modes += add_cvt_modes(connector, edid);
4734 num_modes += add_standard_modes(connector, edid);
4735 num_modes += add_established_modes(connector, edid);
4736 num_modes += add_cea_modes(connector, edid);
4737 num_modes += add_alternate_cea_modes(connector, edid);
4738 num_modes += add_displayid_detailed_modes(connector, edid);
4739 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4740 num_modes += add_inferred_modes(connector, edid);
4742 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4743 edid_fixup_preferred(connector, quirks);
4745 if (quirks & EDID_QUIRK_FORCE_6BPC)
4746 connector->display_info.bpc = 6;
4748 if (quirks & EDID_QUIRK_FORCE_8BPC)
4749 connector->display_info.bpc = 8;
4751 if (quirks & EDID_QUIRK_FORCE_10BPC)
4752 connector->display_info.bpc = 10;
4754 if (quirks & EDID_QUIRK_FORCE_12BPC)
4755 connector->display_info.bpc = 12;
4759 EXPORT_SYMBOL(drm_add_edid_modes);
4762 * drm_add_modes_noedid - add modes for the connectors without EDID
4763 * @connector: connector we're probing
4764 * @hdisplay: the horizontal display limit
4765 * @vdisplay: the vertical display limit
4767 * Add the specified modes to the connector's mode list. Only when the
4768 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4770 * Return: The number of modes added or 0 if we couldn't find any.
4772 int drm_add_modes_noedid(struct drm_connector *connector,
4773 int hdisplay, int vdisplay)
4775 int i, count, num_modes = 0;
4776 struct drm_display_mode *mode;
4777 struct drm_device *dev = connector->dev;
4779 count = ARRAY_SIZE(drm_dmt_modes);
4785 for (i = 0; i < count; i++) {
4786 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4787 if (hdisplay && vdisplay) {
4789 * Only when two are valid, they will be used to check
4790 * whether the mode should be added to the mode list of
4793 if (ptr->hdisplay > hdisplay ||
4794 ptr->vdisplay > vdisplay)
4797 if (drm_mode_vrefresh(ptr) > 61)
4799 mode = drm_mode_duplicate(dev, ptr);
4801 drm_mode_probed_add(connector, mode);
4807 EXPORT_SYMBOL(drm_add_modes_noedid);
4810 * drm_set_preferred_mode - Sets the preferred mode of a connector
4811 * @connector: connector whose mode list should be processed
4812 * @hpref: horizontal resolution of preferred mode
4813 * @vpref: vertical resolution of preferred mode
4815 * Marks a mode as preferred if it matches the resolution specified by @hpref
4818 void drm_set_preferred_mode(struct drm_connector *connector,
4819 int hpref, int vpref)
4821 struct drm_display_mode *mode;
4823 list_for_each_entry(mode, &connector->probed_modes, head) {
4824 if (mode->hdisplay == hpref &&
4825 mode->vdisplay == vpref)
4826 mode->type |= DRM_MODE_TYPE_PREFERRED;
4829 EXPORT_SYMBOL(drm_set_preferred_mode);
4831 static bool is_hdmi2_sink(struct drm_connector *connector)
4834 * FIXME: sil-sii8620 doesn't have a connector around when
4835 * we need one, so we have to be prepared for a NULL connector.
4840 return connector->display_info.hdmi.scdc.supported ||
4841 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
4845 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4846 * data from a DRM display mode
4847 * @frame: HDMI AVI infoframe
4848 * @connector: the connector
4849 * @mode: DRM display mode
4851 * Return: 0 on success or a negative error code on failure.
4854 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4855 struct drm_connector *connector,
4856 const struct drm_display_mode *mode)
4858 enum hdmi_picture_aspect picture_aspect;
4861 if (!frame || !mode)
4864 err = hdmi_avi_infoframe_init(frame);
4868 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4869 frame->pixel_repeat = 1;
4871 frame->video_code = drm_match_cea_mode(mode);
4874 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4875 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4876 * have to make sure we dont break HDMI 1.4 sinks.
4878 if (!is_hdmi2_sink(connector) && frame->video_code > 64)
4879 frame->video_code = 0;
4882 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4883 * we should send its VIC in vendor infoframes, else send the
4884 * VIC in AVI infoframes. Lets check if this mode is present in
4885 * HDMI 1.4b 4K modes
4887 if (frame->video_code) {
4888 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4889 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4891 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4892 frame->video_code = 0;
4895 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4898 * As some drivers don't support atomic, we can't use connector state.
4899 * So just initialize the frame with default values, just the same way
4900 * as it's done with other properties here.
4902 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
4906 * Populate picture aspect ratio from either
4907 * user input (if specified) or from the CEA mode list.
4909 picture_aspect = mode->picture_aspect_ratio;
4910 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
4911 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
4914 * The infoframe can't convey anything but none, 4:3
4915 * and 16:9, so if the user has asked for anything else
4916 * we can only satisfy it by specifying the right VIC.
4918 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
4919 if (picture_aspect !=
4920 drm_get_cea_aspect_ratio(frame->video_code))
4922 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4925 frame->picture_aspect = picture_aspect;
4926 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4927 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4931 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4933 /* HDMI Colorspace Spec Definitions */
4934 #define FULL_COLORIMETRY_MASK 0x1FF
4935 #define NORMAL_COLORIMETRY_MASK 0x3
4936 #define EXTENDED_COLORIMETRY_MASK 0x7
4937 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
4939 #define C(x) ((x) << 0)
4940 #define EC(x) ((x) << 2)
4941 #define ACE(x) ((x) << 5)
4943 #define HDMI_COLORIMETRY_NO_DATA 0x0
4944 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
4945 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
4946 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
4947 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
4948 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
4949 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
4950 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
4951 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
4952 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
4953 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
4954 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
4955 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
4957 static const u32 hdmi_colorimetry_val[] = {
4958 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
4959 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
4960 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
4961 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
4962 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
4963 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
4964 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
4965 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
4966 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
4967 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
4968 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
4976 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
4977 * colorspace information
4978 * @frame: HDMI AVI infoframe
4979 * @conn_state: connector state
4982 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
4983 const struct drm_connector_state *conn_state)
4985 u32 colorimetry_val;
4986 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
4988 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
4989 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
4991 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
4993 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
4995 * ToDo: Extend it for ACE formats as well. Modify the infoframe
4996 * structure and extend it in drivers/video/hdmi
4998 frame->extended_colorimetry = (colorimetry_val >> 2) &
4999 EXTENDED_COLORIMETRY_MASK;
5001 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5004 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5005 * quantization range information
5006 * @frame: HDMI AVI infoframe
5007 * @connector: the connector
5008 * @mode: DRM display mode
5009 * @rgb_quant_range: RGB quantization range (Q)
5012 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5013 struct drm_connector *connector,
5014 const struct drm_display_mode *mode,
5015 enum hdmi_quantization_range rgb_quant_range)
5017 const struct drm_display_info *info = &connector->display_info;
5021 * "A Source shall not send a non-zero Q value that does not correspond
5022 * to the default RGB Quantization Range for the transmitted Picture
5023 * unless the Sink indicates support for the Q bit in a Video
5024 * Capabilities Data Block."
5026 * HDMI 2.0 recommends sending non-zero Q when it does match the
5027 * default RGB quantization range for the mode, even when QS=0.
5029 if (info->rgb_quant_range_selectable ||
5030 rgb_quant_range == drm_default_rgb_quant_range(mode))
5031 frame->quantization_range = rgb_quant_range;
5033 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5037 * "When transmitting any RGB colorimetry, the Source should set the
5038 * YQ-field to match the RGB Quantization Range being transmitted
5039 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5040 * set YQ=1) and the Sink shall ignore the YQ-field."
5042 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5043 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5044 * good way to tell which version of CEA-861 the sink supports, so
5045 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5048 if (!is_hdmi2_sink(connector) ||
5049 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5050 frame->ycc_quantization_range =
5051 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5053 frame->ycc_quantization_range =
5054 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5056 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5058 static enum hdmi_3d_structure
5059 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5061 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5064 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5065 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5066 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5067 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5068 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5069 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5070 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5071 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5072 case DRM_MODE_FLAG_3D_L_DEPTH:
5073 return HDMI_3D_STRUCTURE_L_DEPTH;
5074 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5075 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5076 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5077 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5078 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5079 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5081 return HDMI_3D_STRUCTURE_INVALID;
5086 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5087 * data from a DRM display mode
5088 * @frame: HDMI vendor infoframe
5089 * @connector: the connector
5090 * @mode: DRM display mode
5092 * Note that there's is a need to send HDMI vendor infoframes only when using a
5093 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5094 * function will return -EINVAL, error that can be safely ignored.
5096 * Return: 0 on success or a negative error code on failure.
5099 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5100 struct drm_connector *connector,
5101 const struct drm_display_mode *mode)
5104 * FIXME: sil-sii8620 doesn't have a connector around when
5105 * we need one, so we have to be prepared for a NULL connector.
5107 bool has_hdmi_infoframe = connector ?
5108 connector->display_info.has_hdmi_infoframe : false;
5113 if (!frame || !mode)
5116 if (!has_hdmi_infoframe)
5119 vic = drm_match_hdmi_mode(mode);
5120 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5123 * Even if it's not absolutely necessary to send the infoframe
5124 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5125 * know that the sink can handle it. This is based on a
5126 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5127 * have trouble realizing that they shuld switch from 3D to 2D
5128 * mode if the source simply stops sending the infoframe when
5129 * it wants to switch from 3D to 2D.
5132 if (vic && s3d_flags)
5135 err = hdmi_vendor_infoframe_init(frame);
5140 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5144 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5146 static int drm_parse_tiled_block(struct drm_connector *connector,
5147 struct displayid_block *block)
5149 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5151 u8 tile_v_loc, tile_h_loc;
5152 u8 num_v_tile, num_h_tile;
5153 struct drm_tile_group *tg;
5155 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5156 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5158 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5159 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5160 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5161 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5163 connector->has_tile = true;
5164 if (tile->tile_cap & 0x80)
5165 connector->tile_is_single_monitor = true;
5167 connector->num_h_tile = num_h_tile + 1;
5168 connector->num_v_tile = num_v_tile + 1;
5169 connector->tile_h_loc = tile_h_loc;
5170 connector->tile_v_loc = tile_v_loc;
5171 connector->tile_h_size = w + 1;
5172 connector->tile_v_size = h + 1;
5174 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5175 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5176 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5177 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5178 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5180 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5182 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5187 if (connector->tile_group != tg) {
5188 /* if we haven't got a pointer,
5189 take the reference, drop ref to old tile group */
5190 if (connector->tile_group) {
5191 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5193 connector->tile_group = tg;
5195 /* if same tile group, then release the ref we just took. */
5196 drm_mode_put_tile_group(connector->dev, tg);
5200 static int drm_parse_display_id(struct drm_connector *connector,
5201 u8 *displayid, int length,
5202 bool is_edid_extension)
5204 /* if this is an EDID extension the first byte will be 0x70 */
5206 struct displayid_block *block;
5209 if (is_edid_extension)
5212 ret = validate_displayid(displayid, length, idx);
5216 idx += sizeof(struct displayid_hdr);
5217 while (block = (struct displayid_block *)&displayid[idx],
5218 idx + sizeof(struct displayid_block) <= length &&
5219 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5220 block->num_bytes > 0) {
5221 idx += block->num_bytes + sizeof(struct displayid_block);
5222 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5223 block->tag, block->rev, block->num_bytes);
5225 switch (block->tag) {
5226 case DATA_BLOCK_TILED_DISPLAY:
5227 ret = drm_parse_tiled_block(connector, block);
5231 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5232 /* handled in mode gathering code. */
5235 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5242 static void drm_get_displayid(struct drm_connector *connector,
5245 void *displayid = NULL;
5247 connector->has_tile = false;
5248 displayid = drm_find_displayid_extension(edid);
5250 /* drop reference to any tile group we had */
5254 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5257 if (!connector->has_tile)
5261 if (connector->tile_group) {
5262 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5263 connector->tile_group = NULL;
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