drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #include <video/exynos5433_decon.h>
  21
  22 #include "exynos_drm_drv.h"
  23 #include "exynos_drm_crtc.h"
  24 #include "exynos_drm_fb.h"
  25 #include "exynos_drm_plane.h"
  26 #include "exynos_drm_iommu.h"
  27
  28 #define WINDOWS_NR      3
  29 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  30
  31 static const char * const decon_clks_name[] = {
  32         "pclk",
  33         "aclk_decon",
  34         "aclk_smmu_decon0x",
  35         "aclk_xiu_decon0x",
  36         "pclk_smmu_decon0x",
  37         "sclk_decon_vclk",
  38         "sclk_decon_eclk",
  39 };
  40
  41 enum decon_iftype {
  42         IFTYPE_RGB,
  43         IFTYPE_I80,
  44         IFTYPE_HDMI
  45 };
  46
  47 enum decon_flag_bits {
  48         BIT_CLKS_ENABLED,
  49         BIT_IRQS_ENABLED,
  50         BIT_WIN_UPDATED,
  51         BIT_SUSPENDED
  52 };
  53
  54 struct decon_context {
  55         struct device                   *dev;
  56         struct drm_device               *drm_dev;
  57         struct exynos_drm_crtc          *crtc;
  58         struct exynos_drm_plane         planes[WINDOWS_NR];
  59         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  60         void __iomem                    *addr;
  61         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  62         int                             pipe;
  63         unsigned long                   flags;
  64         enum decon_iftype               out_type;
  65         int                             first_win;
  66 };
  67
  68 static const uint32_t decon_formats[] = {
  69         DRM_FORMAT_XRGB1555,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_ARGB8888,
  73 };
  74
  75 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  76         DRM_PLANE_TYPE_PRIMARY,
  77         DRM_PLANE_TYPE_OVERLAY,
  78         DRM_PLANE_TYPE_CURSOR,
  79 };
  80
  81 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  82                                   u32 val)
  83 {
  84         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  85         writel(val, ctx->addr + reg);
  86 }
  87
  88 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  89 {
  90         struct decon_context *ctx = crtc->ctx;
  91         u32 val;
  92
  93         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  94                 return -EPERM;
  95
  96         if (test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
  97                 val = VIDINTCON0_INTEN;
  98                 if (ctx->out_type == IFTYPE_I80)
  99                         val |= VIDINTCON0_FRAMEDONE;
 100                 else
 101                         val |= VIDINTCON0_INTFRMEN;
 102
 103                 writel(val, ctx->addr + DECON_VIDINTCON0);
 104         }
 105
 106         return 0;
 107 }
 108
 109 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 110 {
 111         struct decon_context *ctx = crtc->ctx;
 112
 113         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 114                 return;
 115
 116         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 117                 writel(0, ctx->addr + DECON_VIDINTCON0);
 118 }
 119
 120 static void decon_setup_trigger(struct decon_context *ctx)
 121 {
 122         u32 val = (ctx->out_type != IFTYPE_HDMI)
 123                 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 124                   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
 125                 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 126                   TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
 127         writel(val, ctx->addr + DECON_TRIGCON);
 128 }
 129
 130 static void decon_commit(struct exynos_drm_crtc *crtc)
 131 {
 132         struct decon_context *ctx = crtc->ctx;
 133         struct drm_display_mode *m = &crtc->base.mode;
 134         u32 val;
 135
 136         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 137                 return;
 138
 139         if (ctx->out_type == IFTYPE_HDMI) {
 140                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 141                 m->crtc_hsync_end = m->crtc_htotal - 92;
 142                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 143                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 144         }
 145
 146         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
 147
 148         /* enable clock gate */
 149         val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
 150         writel(val, ctx->addr + DECON_CMU);
 151
 152         /* lcd on and use command if */
 153         val = VIDOUT_LCD_ON;
 154         if (ctx->out_type == IFTYPE_I80)
 155                 val |= VIDOUT_COMMAND_IF;
 156         else
 157                 val |= VIDOUT_RGB_IF;
 158         writel(val, ctx->addr + DECON_VIDOUTCON0);
 159
 160         val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 161                 VIDTCON2_HOZVAL(m->hdisplay - 1);
 162         writel(val, ctx->addr + DECON_VIDTCON2);
 163
 164         if (ctx->out_type != IFTYPE_I80) {
 165                 val = VIDTCON00_VBPD_F(
 166                                 m->crtc_vtotal - m->crtc_vsync_end - 1) |
 167                         VIDTCON00_VFPD_F(
 168                                 m->crtc_vsync_start - m->crtc_vdisplay - 1);
 169                 writel(val, ctx->addr + DECON_VIDTCON00);
 170
 171                 val = VIDTCON01_VSPW_F(
 172                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 173                 writel(val, ctx->addr + DECON_VIDTCON01);
 174
 175                 val = VIDTCON10_HBPD_F(
 176                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 177                         VIDTCON10_HFPD_F(
 178                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 179                 writel(val, ctx->addr + DECON_VIDTCON10);
 180
 181                 val = VIDTCON11_HSPW_F(
 182                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 183                 writel(val, ctx->addr + DECON_VIDTCON11);
 184         }
 185
 186         decon_setup_trigger(ctx);
 187
 188         /* enable output and display signal */
 189         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 190 }
 191
 192 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 193                                  struct drm_framebuffer *fb)
 194 {
 195         unsigned long val;
 196
 197         val = readl(ctx->addr + DECON_WINCONx(win));
 198         val &= ~WINCONx_BPPMODE_MASK;
 199
 200         switch (fb->pixel_format) {
 201         case DRM_FORMAT_XRGB1555:
 202                 val |= WINCONx_BPPMODE_16BPP_I1555;
 203                 val |= WINCONx_HAWSWP_F;
 204                 val |= WINCONx_BURSTLEN_16WORD;
 205                 break;
 206         case DRM_FORMAT_RGB565:
 207                 val |= WINCONx_BPPMODE_16BPP_565;
 208                 val |= WINCONx_HAWSWP_F;
 209                 val |= WINCONx_BURSTLEN_16WORD;
 210                 break;
 211         case DRM_FORMAT_XRGB8888:
 212                 val |= WINCONx_BPPMODE_24BPP_888;
 213                 val |= WINCONx_WSWP_F;
 214                 val |= WINCONx_BURSTLEN_16WORD;
 215                 break;
 216         case DRM_FORMAT_ARGB8888:
 217                 val |= WINCONx_BPPMODE_32BPP_A8888;
 218                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 219                 val |= WINCONx_BURSTLEN_16WORD;
 220                 break;
 221         default:
 222                 DRM_ERROR("Proper pixel format is not set\n");
 223                 return;
 224         }
 225
 226         DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
 227
 228         /*
 229          * In case of exynos, setting dma-burst to 16Word causes permanent
 230          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 231          * switching which is based on plane size is not recommended as
 232          * plane size varies a lot towards the end of the screen and rapid
 233          * movement causes unstable DMA which results into iommu crash/tear.
 234          */
 235
 236         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 237                 val &= ~WINCONx_BURSTLEN_MASK;
 238                 val |= WINCONx_BURSTLEN_8WORD;
 239         }
 240
 241         writel(val, ctx->addr + DECON_WINCONx(win));
 242 }
 243
 244 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 245                                         bool protect)
 246 {
 247         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 248                        protect ? ~0 : 0);
 249 }
 250
 251 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 252 {
 253         struct decon_context *ctx = crtc->ctx;
 254         int i;
 255
 256         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 257                 return;
 258
 259         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 260                 decon_shadow_protect_win(ctx, i, true);
 261 }
 262
 263 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 264 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 265 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 266
 267 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 268                                struct exynos_drm_plane *plane)
 269 {
 270         struct exynos_drm_plane_state *state =
 271                                 to_exynos_plane_state(plane->base.state);
 272         struct decon_context *ctx = crtc->ctx;
 273         struct drm_framebuffer *fb = state->base.fb;
 274         unsigned int win = plane->index;
 275         unsigned int bpp = fb->bits_per_pixel >> 3;
 276         unsigned int pitch = fb->pitches[0];
 277         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 278         u32 val;
 279
 280         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 281                 return;
 282
 283         val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 284         writel(val, ctx->addr + DECON_VIDOSDxA(win));
 285
 286         val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 287                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 288         writel(val, ctx->addr + DECON_VIDOSDxB(win));
 289
 290         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 291                 VIDOSD_Wx_ALPHA_B_F(0x0);
 292         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 293
 294         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 295                 VIDOSD_Wx_ALPHA_B_F(0x0);
 296         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 297
 298         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 299
 300         val = dma_addr + pitch * state->src.h;
 301         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 302
 303         if (ctx->out_type != IFTYPE_HDMI)
 304                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 305                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 306         else
 307                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 308                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 309         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 310
 311         decon_win_set_pixfmt(ctx, win, fb);
 312
 313         /* window enable */
 314         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 315
 316         /* standalone update */
 317         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 318 }
 319
 320 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 321                                 struct exynos_drm_plane *plane)
 322 {
 323         struct decon_context *ctx = crtc->ctx;
 324         unsigned int win = plane->index;
 325
 326         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 327                 return;
 328
 329         decon_shadow_protect_win(ctx, win, true);
 330
 331         /* window disable */
 332         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 333
 334         decon_shadow_protect_win(ctx, win, false);
 335
 336         /* standalone update */
 337         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 338 }
 339
 340 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 341 {
 342         struct decon_context *ctx = crtc->ctx;
 343         int i;
 344
 345         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 346                 return;
 347
 348         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 349                 decon_shadow_protect_win(ctx, i, false);
 350
 351         if (ctx->out_type == IFTYPE_I80)
 352                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 353 }
 354
 355 static void decon_swreset(struct decon_context *ctx)
 356 {
 357         unsigned int tries;
 358
 359         writel(0, ctx->addr + DECON_VIDCON0);
 360         for (tries = 2000; tries; --tries) {
 361                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 362                         break;
 363                 udelay(10);
 364         }
 365
 366         WARN(tries == 0, "failed to disable DECON\n");
 367
 368         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 369         for (tries = 2000; tries; --tries) {
 370                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 371                         break;
 372                 udelay(10);
 373         }
 374
 375         WARN(tries == 0, "failed to software reset DECON\n");
 376
 377         if (ctx->out_type != IFTYPE_HDMI)
 378                 return;
 379
 380         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 381         decon_set_bits(ctx, DECON_CMU,
 382                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 383         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 384         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 385                ctx->addr + DECON_CRCCTRL);
 386         decon_setup_trigger(ctx);
 387 }
 388
 389 static void decon_enable(struct exynos_drm_crtc *crtc)
 390 {
 391         struct decon_context *ctx = crtc->ctx;
 392
 393         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 394                 return;
 395
 396         pm_runtime_get_sync(ctx->dev);
 397
 398         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 399
 400         /* if vblank was enabled status, enable it again. */
 401         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 402                 decon_enable_vblank(ctx->crtc);
 403
 404         decon_commit(ctx->crtc);
 405
 406         set_bit(BIT_SUSPENDED, &ctx->flags);
 407 }
 408
 409 static void decon_disable(struct exynos_drm_crtc *crtc)
 410 {
 411         struct decon_context *ctx = crtc->ctx;
 412         int i;
 413
 414         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 415                 return;
 416
 417         /*
 418          * We need to make sure that all windows are disabled before we
 419          * suspend that connector. Otherwise we might try to scan from
 420          * a destroyed buffer later.
 421          */
 422         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 423                 decon_disable_plane(crtc, &ctx->planes[i]);
 424
 425         decon_swreset(ctx);
 426
 427         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 428
 429         pm_runtime_put_sync(ctx->dev);
 430
 431         set_bit(BIT_SUSPENDED, &ctx->flags);
 432 }
 433
 434 void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 435 {
 436         struct decon_context *ctx = crtc->ctx;
 437
 438         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 439                 return;
 440
 441         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 442                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 443
 444         drm_crtc_handle_vblank(&ctx->crtc->base);
 445 }
 446
 447 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 448 {
 449         struct decon_context *ctx = crtc->ctx;
 450         int win, i, ret;
 451
 452         DRM_DEBUG_KMS("%s\n", __FILE__);
 453
 454         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 455                 ret = clk_prepare_enable(ctx->clks[i]);
 456                 if (ret < 0)
 457                         goto err;
 458         }
 459
 460         for (win = 0; win < WINDOWS_NR; win++) {
 461                 decon_shadow_protect_win(ctx, win, true);
 462                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 463                 decon_shadow_protect_win(ctx, win, false);
 464                 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 465         }
 466         /* TODO: wait for possible vsync */
 467         msleep(50);
 468
 469 err:
 470         while (--i >= 0)
 471                 clk_disable_unprepare(ctx->clks[i]);
 472 }
 473
 474 static struct exynos_drm_crtc_ops decon_crtc_ops = {
 475         .enable                 = decon_enable,
 476         .disable                = decon_disable,
 477         .enable_vblank          = decon_enable_vblank,
 478         .disable_vblank         = decon_disable_vblank,
 479         .atomic_begin           = decon_atomic_begin,
 480         .update_plane           = decon_update_plane,
 481         .disable_plane          = decon_disable_plane,
 482         .atomic_flush           = decon_atomic_flush,
 483         .te_handler             = decon_te_irq_handler,
 484 };
 485
 486 static int decon_bind(struct device *dev, struct device *master, void *data)
 487 {
 488         struct decon_context *ctx = dev_get_drvdata(dev);
 489         struct drm_device *drm_dev = data;
 490         struct exynos_drm_private *priv = drm_dev->dev_private;
 491         struct exynos_drm_plane *exynos_plane;
 492         enum exynos_drm_output_type out_type;
 493         unsigned int win;
 494         int ret;
 495
 496         ctx->drm_dev = drm_dev;
 497         ctx->pipe = priv->pipe++;
 498
 499         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 500                 int tmp = (win == ctx->first_win) ? 0 : win;
 501
 502                 ctx->configs[win].pixel_formats = decon_formats;
 503                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 504                 ctx->configs[win].zpos = win;
 505                 ctx->configs[win].type = decon_win_types[tmp];
 506
 507                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 508                                         1 << ctx->pipe, &ctx->configs[win]);
 509                 if (ret)
 510                         return ret;
 511         }
 512
 513         exynos_plane = &ctx->planes[ctx->first_win];
 514         out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 515                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 516         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 517                                         ctx->pipe, out_type,
 518                                         &decon_crtc_ops, ctx);
 519         if (IS_ERR(ctx->crtc)) {
 520                 ret = PTR_ERR(ctx->crtc);
 521                 goto err;
 522         }
 523
 524         decon_clear_channels(ctx->crtc);
 525
 526         ret = drm_iommu_attach_device(drm_dev, dev);
 527         if (ret)
 528                 goto err;
 529
 530         return ret;
 531 err:
 532         priv->pipe--;
 533         return ret;
 534 }
 535
 536 static void decon_unbind(struct device *dev, struct device *master, void *data)
 537 {
 538         struct decon_context *ctx = dev_get_drvdata(dev);
 539
 540         decon_disable(ctx->crtc);
 541
 542         /* detach this sub driver from iommu mapping if supported. */
 543         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 544 }
 545
 546 static const struct component_ops decon_component_ops = {
 547         .bind   = decon_bind,
 548         .unbind = decon_unbind,
 549 };
 550
 551 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 552 {
 553         struct decon_context *ctx = dev_id;
 554         u32 val;
 555         int win;
 556
 557         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 558                 goto out;
 559
 560         val = readl(ctx->addr + DECON_VIDINTCON1);
 561         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 562
 563         if (val) {
 564                 for (win = ctx->first_win; win < WINDOWS_NR ; win++) {
 565                         struct exynos_drm_plane *plane = &ctx->planes[win];
 566
 567                         if (!plane->pending_fb)
 568                                 continue;
 569
 570                         exynos_drm_crtc_finish_update(ctx->crtc, plane);
 571                 }
 572
 573                 /* clear */
 574                 writel(val, ctx->addr + DECON_VIDINTCON1);
 575         }
 576
 577 out:
 578         return IRQ_HANDLED;
 579 }
 580
 581 #ifdef CONFIG_PM
 582 static int exynos5433_decon_suspend(struct device *dev)
 583 {
 584         struct decon_context *ctx = dev_get_drvdata(dev);
 585         int i;
 586
 587         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++)
 588                 clk_disable_unprepare(ctx->clks[i]);
 589
 590         return 0;
 591 }
 592
 593 static int exynos5433_decon_resume(struct device *dev)
 594 {
 595         struct decon_context *ctx = dev_get_drvdata(dev);
 596         int i, ret;
 597
 598         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 599                 ret = clk_prepare_enable(ctx->clks[i]);
 600                 if (ret < 0)
 601                         goto err;
 602         }
 603
 604         return 0;
 605
 606 err:
 607         while (--i >= 0)
 608                 clk_disable_unprepare(ctx->clks[i]);
 609
 610         return ret;
 611 }
 612 #endif
 613
 614 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 615         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 616                            NULL)
 617 };
 618
 619 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 620         {
 621                 .compatible = "samsung,exynos5433-decon",
 622                 .data = (void *)IFTYPE_RGB
 623         },
 624         {
 625                 .compatible = "samsung,exynos5433-decon-tv",
 626                 .data = (void *)IFTYPE_HDMI
 627         },
 628         {},
 629 };
 630 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 631
 632 static int exynos5433_decon_probe(struct platform_device *pdev)
 633 {
 634         const struct of_device_id *of_id;
 635         struct device *dev = &pdev->dev;
 636         struct decon_context *ctx;
 637         struct resource *res;
 638         int ret;
 639         int i;
 640
 641         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 642         if (!ctx)
 643                 return -ENOMEM;
 644
 645         __set_bit(BIT_SUSPENDED, &ctx->flags);
 646         ctx->dev = dev;
 647
 648         of_id = of_match_device(exynos5433_decon_driver_dt_match, &pdev->dev);
 649         ctx->out_type = (enum decon_iftype)of_id->data;
 650
 651         if (ctx->out_type == IFTYPE_HDMI)
 652                 ctx->first_win = 1;
 653         else if (of_get_child_by_name(dev->of_node, "i80-if-timings"))
 654                 ctx->out_type = IFTYPE_I80;
 655
 656         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 657                 struct clk *clk;
 658
 659                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 660                 if (IS_ERR(clk))
 661                         return PTR_ERR(clk);
 662
 663                 ctx->clks[i] = clk;
 664         }
 665
 666         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 667         if (!res) {
 668                 dev_err(dev, "cannot find IO resource\n");
 669                 return -ENXIO;
 670         }
 671
 672         ctx->addr = devm_ioremap_resource(dev, res);
 673         if (IS_ERR(ctx->addr)) {
 674                 dev_err(dev, "ioremap failed\n");
 675                 return PTR_ERR(ctx->addr);
 676         }
 677
 678         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 679                         (ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync");
 680         if (!res) {
 681                 dev_err(dev, "cannot find IRQ resource\n");
 682                 return -ENXIO;
 683         }
 684
 685         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 686                                "drm_decon", ctx);
 687         if (ret < 0) {
 688                 dev_err(dev, "lcd_sys irq request failed\n");
 689                 return ret;
 690         }
 691
 692         platform_set_drvdata(pdev, ctx);
 693
 694         pm_runtime_enable(dev);
 695
 696         ret = component_add(dev, &decon_component_ops);
 697         if (ret)
 698                 goto err_disable_pm_runtime;
 699
 700         return 0;
 701
 702 err_disable_pm_runtime:
 703         pm_runtime_disable(dev);
 704
 705         return ret;
 706 }
 707
 708 static int exynos5433_decon_remove(struct platform_device *pdev)
 709 {
 710         pm_runtime_disable(&pdev->dev);
 711
 712         component_del(&pdev->dev, &decon_component_ops);
 713
 714         return 0;
 715 }
 716
 717 struct platform_driver exynos5433_decon_driver = {
 718         .probe          = exynos5433_decon_probe,
 719         .remove         = exynos5433_decon_remove,
 720         .driver         = {
 721                 .name   = "exynos5433-decon",
 722                 .pm     = &exynos5433_decon_pm_ops,
 723                 .of_match_table = exynos5433_decon_driver_dt_match,
 724         },
 725 };