drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* exynos_drm_fimd.c
   3  *
   4  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   5  * Authors:
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *      Inki Dae <inki.dae@samsung.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/component.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19
  20 #include <video/of_display_timing.h>
  21 #include <video/of_videomode.h>
  22 #include <video/samsung_fimd.h>
  23
  24 #include <drm/drm_fourcc.h>
  25 #include <drm/drm_vblank.h>
  26 #include <drm/exynos_drm.h>
  27
  28 #include "exynos_drm_crtc.h"
  29 #include "exynos_drm_drv.h"
  30 #include "exynos_drm_fb.h"
  31 #include "exynos_drm_plane.h"
  32
  33 /*
  34  * FIMD stands for Fully Interactive Mobile Display and
  35  * as a display controller, it transfers contents drawn on memory
  36  * to a LCD Panel through Display Interfaces such as RGB or
  37  * CPU Interface.
  38  */
  39
  40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  41
  42 /* position control register for hardware window 0, 2 ~ 4.*/
  43 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  44 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  45 /*
  46  * size control register for hardware windows 0 and alpha control register
  47  * for hardware windows 1 ~ 4
  48  */
  49 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  50 /* size control register for hardware windows 1 ~ 2. */
  51 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  52
  53 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  54 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  55
  56 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  57 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  58 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  59 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  60
  61 /* color key control register for hardware window 1 ~ 4. */
  62 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  63 /* color key value register for hardware window 1 ~ 4. */
  64 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  65
  66 /* I80 trigger control register */
  67 #define TRIGCON                         0x1A4
  68 #define TRGMODE_ENABLE                  (1 << 0)
  69 #define SWTRGCMD_ENABLE                 (1 << 1)
  70 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
  71 #define HWTRGEN_ENABLE                  (1 << 3)
  72 #define HWTRGMASK_ENABLE                (1 << 4)
  73 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
  74 #define HWTRIGEN_PER_ENABLE             (1 << 31)
  75
  76 /* display mode change control register except exynos4 */
  77 #define VIDOUT_CON                      0x000
  78 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  79
  80 /* I80 interface control for main LDI register */
  81 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  82 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  83 #define LCD_CS_SETUP(x)                 ((x) << 16)
  84 #define LCD_WR_SETUP(x)                 ((x) << 12)
  85 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  86 #define LCD_WR_HOLD(x)                  ((x) << 4)
  87 #define I80IFEN_ENABLE                  (1 << 0)
  88
  89 /* FIMD has totally five hardware windows. */
  90 #define WINDOWS_NR      5
  91
  92 /* HW trigger flag on i80 panel. */
  93 #define I80_HW_TRG     (1 << 1)
  94
  95 struct fimd_driver_data {
  96         unsigned int timing_base;
  97         unsigned int lcdblk_offset;
  98         unsigned int lcdblk_vt_shift;
  99         unsigned int lcdblk_bypass_shift;
 100         unsigned int lcdblk_mic_bypass_shift;
 101         unsigned int trg_type;
 102
 103         unsigned int has_shadowcon:1;
 104         unsigned int has_clksel:1;
 105         unsigned int has_limited_fmt:1;
 106         unsigned int has_vidoutcon:1;
 107         unsigned int has_vtsel:1;
 108         unsigned int has_mic_bypass:1;
 109         unsigned int has_dp_clk:1;
 110         unsigned int has_hw_trigger:1;
 111         unsigned int has_trigger_per_te:1;
 112 };
 113
 114 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 115         .timing_base = 0x0,
 116         .has_clksel = 1,
 117         .has_limited_fmt = 1,
 118 };
 119
 120 static struct fimd_driver_data s5pv210_fimd_driver_data = {
 121         .timing_base = 0x0,
 122         .has_shadowcon = 1,
 123         .has_clksel = 1,
 124 };
 125
 126 static struct fimd_driver_data exynos3_fimd_driver_data = {
 127         .timing_base = 0x20000,
 128         .lcdblk_offset = 0x210,
 129         .lcdblk_bypass_shift = 1,
 130         .has_shadowcon = 1,
 131         .has_vidoutcon = 1,
 132 };
 133
 134 static struct fimd_driver_data exynos4_fimd_driver_data = {
 135         .timing_base = 0x0,
 136         .lcdblk_offset = 0x210,
 137         .lcdblk_vt_shift = 10,
 138         .lcdblk_bypass_shift = 1,
 139         .has_shadowcon = 1,
 140         .has_vtsel = 1,
 141 };
 142
 143 static struct fimd_driver_data exynos5_fimd_driver_data = {
 144         .timing_base = 0x20000,
 145         .lcdblk_offset = 0x214,
 146         .lcdblk_vt_shift = 24,
 147         .lcdblk_bypass_shift = 15,
 148         .has_shadowcon = 1,
 149         .has_vidoutcon = 1,
 150         .has_vtsel = 1,
 151         .has_dp_clk = 1,
 152 };
 153
 154 static struct fimd_driver_data exynos5420_fimd_driver_data = {
 155         .timing_base = 0x20000,
 156         .lcdblk_offset = 0x214,
 157         .lcdblk_vt_shift = 24,
 158         .lcdblk_bypass_shift = 15,
 159         .lcdblk_mic_bypass_shift = 11,
 160         .has_shadowcon = 1,
 161         .has_vidoutcon = 1,
 162         .has_vtsel = 1,
 163         .has_mic_bypass = 1,
 164         .has_dp_clk = 1,
 165 };
 166
 167 struct fimd_context {
 168         struct device                   *dev;
 169         struct drm_device               *drm_dev;
 170         struct exynos_drm_crtc          *crtc;
 171         struct exynos_drm_plane         planes[WINDOWS_NR];
 172         struct exynos_drm_plane_config  configs[WINDOWS_NR];
 173         struct clk                      *bus_clk;
 174         struct clk                      *lcd_clk;
 175         void __iomem                    *regs;
 176         struct regmap                   *sysreg;
 177         unsigned long                   irq_flags;
 178         u32                             vidcon0;
 179         u32                             vidcon1;
 180         u32                             vidout_con;
 181         u32                             i80ifcon;
 182         bool                            i80_if;
 183         bool                            suspended;
 184         wait_queue_head_t               wait_vsync_queue;
 185         atomic_t                        wait_vsync_event;
 186         atomic_t                        win_updated;
 187         atomic_t                        triggering;
 188         u32                             clkdiv;
 189
 190         const struct fimd_driver_data *driver_data;
 191         struct drm_encoder *encoder;
 192         struct exynos_drm_clk           dp_clk;
 193 };
 194
 195 static const struct of_device_id fimd_driver_dt_match[] = {
 196         { .compatible = "samsung,s3c6400-fimd",
 197           .data = &s3c64xx_fimd_driver_data },
 198         { .compatible = "samsung,s5pv210-fimd",
 199           .data = &s5pv210_fimd_driver_data },
 200         { .compatible = "samsung,exynos3250-fimd",
 201           .data = &exynos3_fimd_driver_data },
 202         { .compatible = "samsung,exynos4210-fimd",
 203           .data = &exynos4_fimd_driver_data },
 204         { .compatible = "samsung,exynos5250-fimd",
 205           .data = &exynos5_fimd_driver_data },
 206         { .compatible = "samsung,exynos5420-fimd",
 207           .data = &exynos5420_fimd_driver_data },
 208         {},
 209 };
 210 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 211
 212 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
 213         DRM_PLANE_TYPE_PRIMARY,
 214         DRM_PLANE_TYPE_OVERLAY,
 215         DRM_PLANE_TYPE_OVERLAY,
 216         DRM_PLANE_TYPE_OVERLAY,
 217         DRM_PLANE_TYPE_CURSOR,
 218 };
 219
 220 static const uint32_t fimd_formats[] = {
 221         DRM_FORMAT_C8,
 222         DRM_FORMAT_XRGB1555,
 223         DRM_FORMAT_RGB565,
 224         DRM_FORMAT_XRGB8888,
 225         DRM_FORMAT_ARGB8888,
 226 };
 227
 228 static const unsigned int capabilities[WINDOWS_NR] = {
 229         0,
 230         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 231         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 232         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 233         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 234 };
 235
 236 static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
 237                                  u32 val)
 238 {
 239         val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
 240         writel(val, ctx->regs + reg);
 241 }
 242
 243 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 244 {
 245         struct fimd_context *ctx = crtc->ctx;
 246         u32 val;
 247
 248         if (ctx->suspended)
 249                 return -EPERM;
 250
 251         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 252                 val = readl(ctx->regs + VIDINTCON0);
 253
 254                 val |= VIDINTCON0_INT_ENABLE;
 255
 256                 if (ctx->i80_if) {
 257                         val |= VIDINTCON0_INT_I80IFDONE;
 258                         val |= VIDINTCON0_INT_SYSMAINCON;
 259                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 260                 } else {
 261                         val |= VIDINTCON0_INT_FRAME;
 262
 263                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 264                         val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
 265                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 266                         val |= VIDINTCON0_FRAMESEL1_NONE;
 267                 }
 268
 269                 writel(val, ctx->regs + VIDINTCON0);
 270         }
 271
 272         return 0;
 273 }
 274
 275 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 276 {
 277         struct fimd_context *ctx = crtc->ctx;
 278         u32 val;
 279
 280         if (ctx->suspended)
 281                 return;
 282
 283         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 284                 val = readl(ctx->regs + VIDINTCON0);
 285
 286                 val &= ~VIDINTCON0_INT_ENABLE;
 287
 288                 if (ctx->i80_if) {
 289                         val &= ~VIDINTCON0_INT_I80IFDONE;
 290                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 291                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 292                 } else
 293                         val &= ~VIDINTCON0_INT_FRAME;
 294
 295                 writel(val, ctx->regs + VIDINTCON0);
 296         }
 297 }
 298
 299 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 300 {
 301         struct fimd_context *ctx = crtc->ctx;
 302
 303         if (ctx->suspended)
 304                 return;
 305
 306         atomic_set(&ctx->wait_vsync_event, 1);
 307
 308         /*
 309          * wait for FIMD to signal VSYNC interrupt or return after
 310          * timeout which is set to 50ms (refresh rate of 20).
 311          */
 312         if (!wait_event_timeout(ctx->wait_vsync_queue,
 313                                 !atomic_read(&ctx->wait_vsync_event),
 314                                 HZ/20))
 315                 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
 316 }
 317
 318 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 319                                         bool enable)
 320 {
 321         u32 val = readl(ctx->regs + WINCON(win));
 322
 323         if (enable)
 324                 val |= WINCONx_ENWIN;
 325         else
 326                 val &= ~WINCONx_ENWIN;
 327
 328         writel(val, ctx->regs + WINCON(win));
 329 }
 330
 331 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 332                                                 unsigned int win,
 333                                                 bool enable)
 334 {
 335         u32 val = readl(ctx->regs + SHADOWCON);
 336
 337         if (enable)
 338                 val |= SHADOWCON_CHx_ENABLE(win);
 339         else
 340                 val &= ~SHADOWCON_CHx_ENABLE(win);
 341
 342         writel(val, ctx->regs + SHADOWCON);
 343 }
 344
 345 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 346 {
 347         struct fimd_context *ctx = crtc->ctx;
 348         unsigned int win, ch_enabled = 0;
 349
 350         /* Hardware is in unknown state, so ensure it gets enabled properly */
 351         pm_runtime_get_sync(ctx->dev);
 352
 353         clk_prepare_enable(ctx->bus_clk);
 354         clk_prepare_enable(ctx->lcd_clk);
 355
 356         /* Check if any channel is enabled. */
 357         for (win = 0; win < WINDOWS_NR; win++) {
 358                 u32 val = readl(ctx->regs + WINCON(win));
 359
 360                 if (val & WINCONx_ENWIN) {
 361                         fimd_enable_video_output(ctx, win, false);
 362
 363                         if (ctx->driver_data->has_shadowcon)
 364                                 fimd_enable_shadow_channel_path(ctx, win,
 365                                                                 false);
 366
 367                         ch_enabled = 1;
 368                 }
 369         }
 370
 371         /* Wait for vsync, as disable channel takes effect at next vsync */
 372         if (ch_enabled) {
 373                 ctx->suspended = false;
 374
 375                 fimd_enable_vblank(ctx->crtc);
 376                 fimd_wait_for_vblank(ctx->crtc);
 377                 fimd_disable_vblank(ctx->crtc);
 378
 379                 ctx->suspended = true;
 380         }
 381
 382         clk_disable_unprepare(ctx->lcd_clk);
 383         clk_disable_unprepare(ctx->bus_clk);
 384
 385         pm_runtime_put(ctx->dev);
 386 }
 387
 388
 389 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
 390                 struct drm_crtc_state *state)
 391 {
 392         struct drm_display_mode *mode = &state->adjusted_mode;
 393         struct fimd_context *ctx = crtc->ctx;
 394         unsigned long ideal_clk, lcd_rate;
 395         u32 clkdiv;
 396
 397         if (mode->clock == 0) {
 398                 DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n");
 399                 return -EINVAL;
 400         }
 401
 402         ideal_clk = mode->clock * 1000;
 403
 404         if (ctx->i80_if) {
 405                 /*
 406                  * The frame done interrupt should be occurred prior to the
 407                  * next TE signal.
 408                  */
 409                 ideal_clk *= 2;
 410         }
 411
 412         lcd_rate = clk_get_rate(ctx->lcd_clk);
 413         if (2 * lcd_rate < ideal_clk) {
 414                 DRM_DEV_ERROR(ctx->dev,
 415                               "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
 416                               lcd_rate, ideal_clk);
 417                 return -EINVAL;
 418         }
 419
 420         /* Find the clock divider value that gets us closest to ideal_clk */
 421         clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
 422         if (clkdiv >= 0x200) {
 423                 DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n",
 424                               ideal_clk);
 425                 return -EINVAL;
 426         }
 427
 428         ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
 429
 430         return 0;
 431 }
 432
 433 static void fimd_setup_trigger(struct fimd_context *ctx)
 434 {
 435         void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
 436         u32 trg_type = ctx->driver_data->trg_type;
 437         u32 val = readl(timing_base + TRIGCON);
 438
 439         val &= ~(TRGMODE_ENABLE);
 440
 441         if (trg_type == I80_HW_TRG) {
 442                 if (ctx->driver_data->has_hw_trigger)
 443                         val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
 444                 if (ctx->driver_data->has_trigger_per_te)
 445                         val |= HWTRIGEN_PER_ENABLE;
 446         } else {
 447                 val |= TRGMODE_ENABLE;
 448         }
 449
 450         writel(val, timing_base + TRIGCON);
 451 }
 452
 453 static void fimd_commit(struct exynos_drm_crtc *crtc)
 454 {
 455         struct fimd_context *ctx = crtc->ctx;
 456         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 457         const struct fimd_driver_data *driver_data = ctx->driver_data;
 458         void *timing_base = ctx->regs + driver_data->timing_base;
 459         u32 val;
 460
 461         if (ctx->suspended)
 462                 return;
 463
 464         /* nothing to do if we haven't set the mode yet */
 465         if (mode->htotal == 0 || mode->vtotal == 0)
 466                 return;
 467
 468         if (ctx->i80_if) {
 469                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 470                 writel(val, timing_base + I80IFCONFAx(0));
 471
 472                 /* disable auto frame rate */
 473                 writel(0, timing_base + I80IFCONFBx(0));
 474
 475                 /* set video type selection to I80 interface */
 476                 if (driver_data->has_vtsel && ctx->sysreg &&
 477                                 regmap_update_bits(ctx->sysreg,
 478                                         driver_data->lcdblk_offset,
 479                                         0x3 << driver_data->lcdblk_vt_shift,
 480                                         0x1 << driver_data->lcdblk_vt_shift)) {
 481                         DRM_DEV_ERROR(ctx->dev,
 482                                       "Failed to update sysreg for I80 i/f.\n");
 483                         return;
 484                 }
 485         } else {
 486                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 487                 u32 vidcon1;
 488
 489                 /* setup polarity values */
 490                 vidcon1 = ctx->vidcon1;
 491                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 492                         vidcon1 |= VIDCON1_INV_VSYNC;
 493                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 494                         vidcon1 |= VIDCON1_INV_HSYNC;
 495                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 496
 497                 /* setup vertical timing values. */
 498                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 499                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 500                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 501
 502                 val = VIDTCON0_VBPD(vbpd - 1) |
 503                         VIDTCON0_VFPD(vfpd - 1) |
 504                         VIDTCON0_VSPW(vsync_len - 1);
 505                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 506
 507                 /* setup horizontal timing values.  */
 508                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 509                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 510                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 511
 512                 val = VIDTCON1_HBPD(hbpd - 1) |
 513                         VIDTCON1_HFPD(hfpd - 1) |
 514                         VIDTCON1_HSPW(hsync_len - 1);
 515                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 516         }
 517
 518         if (driver_data->has_vidoutcon)
 519                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 520
 521         /* set bypass selection */
 522         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 523                                 driver_data->lcdblk_offset,
 524                                 0x1 << driver_data->lcdblk_bypass_shift,
 525                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 526                 DRM_DEV_ERROR(ctx->dev,
 527                               "Failed to update sysreg for bypass setting.\n");
 528                 return;
 529         }
 530
 531         /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
 532          * bit should be cleared.
 533          */
 534         if (driver_data->has_mic_bypass && ctx->sysreg &&
 535             regmap_update_bits(ctx->sysreg,
 536                                 driver_data->lcdblk_offset,
 537                                 0x1 << driver_data->lcdblk_mic_bypass_shift,
 538                                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
 539                 DRM_DEV_ERROR(ctx->dev,
 540                               "Failed to update sysreg for bypass mic.\n");
 541                 return;
 542         }
 543
 544         /* setup horizontal and vertical display size. */
 545         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 546                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 547                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 548                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 549         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 550
 551         fimd_setup_trigger(ctx);
 552
 553         /*
 554          * fields of register with prefix '_F' would be updated
 555          * at vsync(same as dma start)
 556          */
 557         val = ctx->vidcon0;
 558         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 559
 560         if (ctx->driver_data->has_clksel)
 561                 val |= VIDCON0_CLKSEL_LCD;
 562
 563         if (ctx->clkdiv > 1)
 564                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 565
 566         writel(val, ctx->regs + VIDCON0);
 567 }
 568
 569 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
 570                                unsigned int alpha, unsigned int pixel_alpha)
 571 {
 572         u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
 573         u32 val = 0;
 574
 575         switch (pixel_alpha) {
 576         case DRM_MODE_BLEND_PIXEL_NONE:
 577         case DRM_MODE_BLEND_COVERAGE:
 578                 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
 579                 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 580                 break;
 581         case DRM_MODE_BLEND_PREMULTI:
 582         default:
 583                 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
 584                         val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
 585                         val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 586                 } else {
 587                         val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
 588                         val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 589                 }
 590                 break;
 591         }
 592         fimd_set_bits(ctx, BLENDEQx(win), mask, val);
 593 }
 594
 595 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
 596                                 unsigned int alpha, unsigned int pixel_alpha)
 597 {
 598         u32 win_alpha_l = (alpha >> 8) & 0xf;
 599         u32 win_alpha_h = alpha >> 12;
 600         u32 val = 0;
 601
 602         switch (pixel_alpha) {
 603         case DRM_MODE_BLEND_PIXEL_NONE:
 604                 break;
 605         case DRM_MODE_BLEND_COVERAGE:
 606         case DRM_MODE_BLEND_PREMULTI:
 607         default:
 608                 val |= WINCON1_ALPHA_SEL;
 609                 val |= WINCON1_BLD_PIX;
 610                 val |= WINCON1_ALPHA_MUL;
 611                 break;
 612         }
 613         fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
 614
 615         /* OSD alpha */
 616         val = VIDISD14C_ALPHA0_R(win_alpha_h) |
 617                 VIDISD14C_ALPHA0_G(win_alpha_h) |
 618                 VIDISD14C_ALPHA0_B(win_alpha_h) |
 619                 VIDISD14C_ALPHA1_R(0x0) |
 620                 VIDISD14C_ALPHA1_G(0x0) |
 621                 VIDISD14C_ALPHA1_B(0x0);
 622         writel(val, ctx->regs + VIDOSD_C(win));
 623
 624         val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
 625                 VIDW_ALPHA_B(win_alpha_l);
 626         writel(val, ctx->regs + VIDWnALPHA0(win));
 627
 628         val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
 629                 VIDW_ALPHA_B(0x0);
 630         writel(val, ctx->regs + VIDWnALPHA1(win));
 631
 632         fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
 633                         BLENDCON_NEW_8BIT_ALPHA_VALUE);
 634 }
 635
 636 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 637                                 struct drm_framebuffer *fb, int width)
 638 {
 639         struct exynos_drm_plane plane = ctx->planes[win];
 640         struct exynos_drm_plane_state *state =
 641                 to_exynos_plane_state(plane.base.state);
 642         uint32_t pixel_format = fb->format->format;
 643         unsigned int alpha = state->base.alpha;
 644         u32 val = WINCONx_ENWIN;
 645         unsigned int pixel_alpha;
 646
 647         if (fb->format->has_alpha)
 648                 pixel_alpha = state->base.pixel_blend_mode;
 649         else
 650                 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
 651
 652         /*
 653          * In case of s3c64xx, window 0 doesn't support alpha channel.
 654          * So the request format is ARGB8888 then change it to XRGB8888.
 655          */
 656         if (ctx->driver_data->has_limited_fmt && !win) {
 657                 if (pixel_format == DRM_FORMAT_ARGB8888)
 658                         pixel_format = DRM_FORMAT_XRGB8888;
 659         }
 660
 661         switch (pixel_format) {
 662         case DRM_FORMAT_C8:
 663                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 664                 val |= WINCONx_BURSTLEN_8WORD;
 665                 val |= WINCONx_BYTSWP;
 666                 break;
 667         case DRM_FORMAT_XRGB1555:
 668                 val |= WINCON0_BPPMODE_16BPP_1555;
 669                 val |= WINCONx_HAWSWP;
 670                 val |= WINCONx_BURSTLEN_16WORD;
 671                 break;
 672         case DRM_FORMAT_RGB565:
 673                 val |= WINCON0_BPPMODE_16BPP_565;
 674                 val |= WINCONx_HAWSWP;
 675                 val |= WINCONx_BURSTLEN_16WORD;
 676                 break;
 677         case DRM_FORMAT_XRGB8888:
 678                 val |= WINCON0_BPPMODE_24BPP_888;
 679                 val |= WINCONx_WSWP;
 680                 val |= WINCONx_BURSTLEN_16WORD;
 681                 break;
 682         case DRM_FORMAT_ARGB8888:
 683         default:
 684                 val |= WINCON1_BPPMODE_25BPP_A1888;
 685                 val |= WINCONx_WSWP;
 686                 val |= WINCONx_BURSTLEN_16WORD;
 687                 break;
 688         }
 689
 690         /*
 691          * Setting dma-burst to 16Word causes permanent tearing for very small
 692          * buffers, e.g. cursor buffer. Burst Mode switching which based on
 693          * plane size is not recommended as plane size varies alot towards the
 694          * end of the screen and rapid movement causes unstable DMA, but it is
 695          * still better to change dma-burst than displaying garbage.
 696          */
 697
 698         if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 699                 val &= ~WINCONx_BURSTLEN_MASK;
 700                 val |= WINCONx_BURSTLEN_4WORD;
 701         }
 702         fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
 703
 704         /* hardware window 0 doesn't support alpha channel. */
 705         if (win != 0) {
 706                 fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
 707                 fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
 708         }
 709 }
 710
 711 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 712 {
 713         unsigned int keycon0 = 0, keycon1 = 0;
 714
 715         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 716                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 717
 718         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 719
 720         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 721         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 722 }
 723
 724 /**
 725  * shadow_protect_win() - disable updating values from shadow registers at vsync
 726  *
 727  * @win: window to protect registers for
 728  * @protect: 1 to protect (disable updates)
 729  */
 730 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 731                                     unsigned int win, bool protect)
 732 {
 733         u32 reg, bits, val;
 734
 735         /*
 736          * SHADOWCON/PRTCON register is used for enabling timing.
 737          *
 738          * for example, once only width value of a register is set,
 739          * if the dma is started then fimd hardware could malfunction so
 740          * with protect window setting, the register fields with prefix '_F'
 741          * wouldn't be updated at vsync also but updated once unprotect window
 742          * is set.
 743          */
 744
 745         if (ctx->driver_data->has_shadowcon) {
 746                 reg = SHADOWCON;
 747                 bits = SHADOWCON_WINx_PROTECT(win);
 748         } else {
 749                 reg = PRTCON;
 750                 bits = PRTCON_PROTECT;
 751         }
 752
 753         val = readl(ctx->regs + reg);
 754         if (protect)
 755                 val |= bits;
 756         else
 757                 val &= ~bits;
 758         writel(val, ctx->regs + reg);
 759 }
 760
 761 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
 762 {
 763         struct fimd_context *ctx = crtc->ctx;
 764         int i;
 765
 766         if (ctx->suspended)
 767                 return;
 768
 769         for (i = 0; i < WINDOWS_NR; i++)
 770                 fimd_shadow_protect_win(ctx, i, true);
 771 }
 772
 773 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
 774 {
 775         struct fimd_context *ctx = crtc->ctx;
 776         int i;
 777
 778         if (ctx->suspended)
 779                 return;
 780
 781         for (i = 0; i < WINDOWS_NR; i++)
 782                 fimd_shadow_protect_win(ctx, i, false);
 783
 784         exynos_crtc_handle_event(crtc);
 785 }
 786
 787 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 788                               struct exynos_drm_plane *plane)
 789 {
 790         struct exynos_drm_plane_state *state =
 791                                 to_exynos_plane_state(plane->base.state);
 792         struct fimd_context *ctx = crtc->ctx;
 793         struct drm_framebuffer *fb = state->base.fb;
 794         dma_addr_t dma_addr;
 795         unsigned long val, size, offset;
 796         unsigned int last_x, last_y, buf_offsize, line_size;
 797         unsigned int win = plane->index;
 798         unsigned int cpp = fb->format->cpp[0];
 799         unsigned int pitch = fb->pitches[0];
 800
 801         if (ctx->suspended)
 802                 return;
 803
 804         offset = state->src.x * cpp;
 805         offset += state->src.y * pitch;
 806
 807         /* buffer start address */
 808         dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
 809         val = (unsigned long)dma_addr;
 810         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 811
 812         /* buffer end address */
 813         size = pitch * state->crtc.h;
 814         val = (unsigned long)(dma_addr + size);
 815         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 816
 817         DRM_DEV_DEBUG_KMS(ctx->dev,
 818                           "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 819                           (unsigned long)dma_addr, val, size);
 820         DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
 821                           state->crtc.w, state->crtc.h);
 822
 823         /* buffer size */
 824         buf_offsize = pitch - (state->crtc.w * cpp);
 825         line_size = state->crtc.w * cpp;
 826         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 827                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 828                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 829                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 830         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 831
 832         /* OSD position */
 833         val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
 834                 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
 835                 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
 836                 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
 837         writel(val, ctx->regs + VIDOSD_A(win));
 838
 839         last_x = state->crtc.x + state->crtc.w;
 840         if (last_x)
 841                 last_x--;
 842         last_y = state->crtc.y + state->crtc.h;
 843         if (last_y)
 844                 last_y--;
 845
 846         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 847                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 848
 849         writel(val, ctx->regs + VIDOSD_B(win));
 850
 851         DRM_DEV_DEBUG_KMS(ctx->dev,
 852                           "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 853                           state->crtc.x, state->crtc.y, last_x, last_y);
 854
 855         /* OSD size */
 856         if (win != 3 && win != 4) {
 857                 u32 offset = VIDOSD_D(win);
 858                 if (win == 0)
 859                         offset = VIDOSD_C(win);
 860                 val = state->crtc.w * state->crtc.h;
 861                 writel(val, ctx->regs + offset);
 862
 863                 DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n",
 864                                   (unsigned int)val);
 865         }
 866
 867         fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
 868
 869         /* hardware window 0 doesn't support color key. */
 870         if (win != 0)
 871                 fimd_win_set_colkey(ctx, win);
 872
 873         fimd_enable_video_output(ctx, win, true);
 874
 875         if (ctx->driver_data->has_shadowcon)
 876                 fimd_enable_shadow_channel_path(ctx, win, true);
 877
 878         if (ctx->i80_if)
 879                 atomic_set(&ctx->win_updated, 1);
 880 }
 881
 882 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 883                                struct exynos_drm_plane *plane)
 884 {
 885         struct fimd_context *ctx = crtc->ctx;
 886         unsigned int win = plane->index;
 887
 888         if (ctx->suspended)
 889                 return;
 890
 891         fimd_enable_video_output(ctx, win, false);
 892
 893         if (ctx->driver_data->has_shadowcon)
 894                 fimd_enable_shadow_channel_path(ctx, win, false);
 895 }
 896
 897 static void fimd_enable(struct exynos_drm_crtc *crtc)
 898 {
 899         struct fimd_context *ctx = crtc->ctx;
 900
 901         if (!ctx->suspended)
 902                 return;
 903
 904         ctx->suspended = false;
 905
 906         pm_runtime_get_sync(ctx->dev);
 907
 908         /* if vblank was enabled status, enable it again. */
 909         if (test_and_clear_bit(0, &ctx->irq_flags))
 910                 fimd_enable_vblank(ctx->crtc);
 911
 912         fimd_commit(ctx->crtc);
 913 }
 914
 915 static void fimd_disable(struct exynos_drm_crtc *crtc)
 916 {
 917         struct fimd_context *ctx = crtc->ctx;
 918         int i;
 919
 920         if (ctx->suspended)
 921                 return;
 922
 923         /*
 924          * We need to make sure that all windows are disabled before we
 925          * suspend that connector. Otherwise we might try to scan from
 926          * a destroyed buffer later.
 927          */
 928         for (i = 0; i < WINDOWS_NR; i++)
 929                 fimd_disable_plane(crtc, &ctx->planes[i]);
 930
 931         fimd_enable_vblank(crtc);
 932         fimd_wait_for_vblank(crtc);
 933         fimd_disable_vblank(crtc);
 934
 935         writel(0, ctx->regs + VIDCON0);
 936
 937         pm_runtime_put_sync(ctx->dev);
 938         ctx->suspended = true;
 939 }
 940
 941 static void fimd_trigger(struct device *dev)
 942 {
 943         struct fimd_context *ctx = dev_get_drvdata(dev);
 944         const struct fimd_driver_data *driver_data = ctx->driver_data;
 945         void *timing_base = ctx->regs + driver_data->timing_base;
 946         u32 reg;
 947
 948          /*
 949           * Skips triggering if in triggering state, because multiple triggering
 950           * requests can cause panel reset.
 951           */
 952         if (atomic_read(&ctx->triggering))
 953                 return;
 954
 955         /* Enters triggering mode */
 956         atomic_set(&ctx->triggering, 1);
 957
 958         reg = readl(timing_base + TRIGCON);
 959         reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
 960         writel(reg, timing_base + TRIGCON);
 961
 962         /*
 963          * Exits triggering mode if vblank is not enabled yet, because when the
 964          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 965          */
 966         if (!test_bit(0, &ctx->irq_flags))
 967                 atomic_set(&ctx->triggering, 0);
 968 }
 969
 970 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 971 {
 972         struct fimd_context *ctx = crtc->ctx;
 973         u32 trg_type = ctx->driver_data->trg_type;
 974
 975         /* Checks the crtc is detached already from encoder */
 976         if (!ctx->drm_dev)
 977                 return;
 978
 979         if (trg_type == I80_HW_TRG)
 980                 goto out;
 981
 982         /*
 983          * If there is a page flip request, triggers and handles the page flip
 984          * event so that current fb can be updated into panel GRAM.
 985          */
 986         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 987                 fimd_trigger(ctx->dev);
 988
 989 out:
 990         /* Wakes up vsync event queue */
 991         if (atomic_read(&ctx->wait_vsync_event)) {
 992                 atomic_set(&ctx->wait_vsync_event, 0);
 993                 wake_up(&ctx->wait_vsync_queue);
 994         }
 995
 996         if (test_bit(0, &ctx->irq_flags))
 997                 drm_crtc_handle_vblank(&ctx->crtc->base);
 998 }
 999
1000 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
1001 {
1002         struct fimd_context *ctx = container_of(clk, struct fimd_context,
1003                                                 dp_clk);
1004         u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
1005         writel(val, ctx->regs + DP_MIE_CLKCON);
1006 }
1007
1008 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
1009         .enable = fimd_enable,
1010         .disable = fimd_disable,
1011         .enable_vblank = fimd_enable_vblank,
1012         .disable_vblank = fimd_disable_vblank,
1013         .atomic_begin = fimd_atomic_begin,
1014         .update_plane = fimd_update_plane,
1015         .disable_plane = fimd_disable_plane,
1016         .atomic_flush = fimd_atomic_flush,
1017         .atomic_check = fimd_atomic_check,
1018         .te_handler = fimd_te_handler,
1019 };
1020
1021 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1022 {
1023         struct fimd_context *ctx = (struct fimd_context *)dev_id;
1024         u32 val, clear_bit;
1025
1026         val = readl(ctx->regs + VIDINTCON1);
1027
1028         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1029         if (val & clear_bit)
1030                 writel(clear_bit, ctx->regs + VIDINTCON1);
1031
1032         /* check the crtc is detached already from encoder */
1033         if (!ctx->drm_dev)
1034                 goto out;
1035
1036         if (!ctx->i80_if)
1037                 drm_crtc_handle_vblank(&ctx->crtc->base);
1038
1039         if (ctx->i80_if) {
1040                 /* Exits triggering mode */
1041                 atomic_set(&ctx->triggering, 0);
1042         } else {
1043                 /* set wait vsync event to zero and wake up queue. */
1044                 if (atomic_read(&ctx->wait_vsync_event)) {
1045                         atomic_set(&ctx->wait_vsync_event, 0);
1046                         wake_up(&ctx->wait_vsync_queue);
1047                 }
1048         }
1049
1050 out:
1051         return IRQ_HANDLED;
1052 }
1053
1054 static int fimd_bind(struct device *dev, struct device *master, void *data)
1055 {
1056         struct fimd_context *ctx = dev_get_drvdata(dev);
1057         struct drm_device *drm_dev = data;
1058         struct exynos_drm_plane *exynos_plane;
1059         unsigned int i;
1060         int ret;
1061
1062         ctx->drm_dev = drm_dev;
1063
1064         for (i = 0; i < WINDOWS_NR; i++) {
1065                 ctx->configs[i].pixel_formats = fimd_formats;
1066                 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1067                 ctx->configs[i].zpos = i;
1068                 ctx->configs[i].type = fimd_win_types[i];
1069                 ctx->configs[i].capabilities = capabilities[i];
1070                 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1071                                         &ctx->configs[i]);
1072                 if (ret)
1073                         return ret;
1074         }
1075
1076         exynos_plane = &ctx->planes[DEFAULT_WIN];
1077         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1078                         EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
1079         if (IS_ERR(ctx->crtc))
1080                 return PTR_ERR(ctx->crtc);
1081
1082         if (ctx->driver_data->has_dp_clk) {
1083                 ctx->dp_clk.enable = fimd_dp_clock_enable;
1084                 ctx->crtc->pipe_clk = &ctx->dp_clk;
1085         }
1086
1087         if (ctx->encoder)
1088                 exynos_dpi_bind(drm_dev, ctx->encoder);
1089
1090         if (is_drm_iommu_supported(drm_dev))
1091                 fimd_clear_channels(ctx->crtc);
1092
1093         return exynos_drm_register_dma(drm_dev, dev);
1094 }
1095
1096 static void fimd_unbind(struct device *dev, struct device *master,
1097                         void *data)
1098 {
1099         struct fimd_context *ctx = dev_get_drvdata(dev);
1100
1101         fimd_disable(ctx->crtc);
1102
1103         exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
1104
1105         if (ctx->encoder)
1106                 exynos_dpi_remove(ctx->encoder);
1107 }
1108
1109 static const struct component_ops fimd_component_ops = {
1110         .bind   = fimd_bind,
1111         .unbind = fimd_unbind,
1112 };
1113
1114 static int fimd_probe(struct platform_device *pdev)
1115 {
1116         struct device *dev = &pdev->dev;
1117         struct fimd_context *ctx;
1118         struct device_node *i80_if_timings;
1119         struct resource *res;
1120         int ret;
1121
1122         if (!dev->of_node)
1123                 return -ENODEV;
1124
1125         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1126         if (!ctx)
1127                 return -ENOMEM;
1128
1129         ctx->dev = dev;
1130         ctx->suspended = true;
1131         ctx->driver_data = of_device_get_match_data(dev);
1132
1133         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1134                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1135         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1136                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1137
1138         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1139         if (i80_if_timings) {
1140                 u32 val;
1141
1142                 ctx->i80_if = true;
1143
1144                 if (ctx->driver_data->has_vidoutcon)
1145                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1146                 else
1147                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1148                 /*
1149                  * The user manual describes that this "DSI_EN" bit is required
1150                  * to enable I80 24-bit data interface.
1151                  */
1152                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1153
1154                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1155                         val = 0;
1156                 ctx->i80ifcon = LCD_CS_SETUP(val);
1157                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1158                         val = 0;
1159                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1160                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1161                         val = 1;
1162                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1163                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1164                         val = 0;
1165                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1166         }
1167         of_node_put(i80_if_timings);
1168
1169         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1170                                                         "samsung,sysreg");
1171         if (IS_ERR(ctx->sysreg)) {
1172                 dev_warn(dev, "failed to get system register.\n");
1173                 ctx->sysreg = NULL;
1174         }
1175
1176         ctx->bus_clk = devm_clk_get(dev, "fimd");
1177         if (IS_ERR(ctx->bus_clk)) {
1178                 dev_err(dev, "failed to get bus clock\n");
1179                 return PTR_ERR(ctx->bus_clk);
1180         }
1181
1182         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1183         if (IS_ERR(ctx->lcd_clk)) {
1184                 dev_err(dev, "failed to get lcd clock\n");
1185                 return PTR_ERR(ctx->lcd_clk);
1186         }
1187
1188         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1189
1190         ctx->regs = devm_ioremap_resource(dev, res);
1191         if (IS_ERR(ctx->regs))
1192                 return PTR_ERR(ctx->regs);
1193
1194         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1195                                            ctx->i80_if ? "lcd_sys" : "vsync");
1196         if (!res) {
1197                 dev_err(dev, "irq request failed.\n");
1198                 return -ENXIO;
1199         }
1200
1201         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1202                                                         0, "drm_fimd", ctx);
1203         if (ret) {
1204                 dev_err(dev, "irq request failed.\n");
1205                 return ret;
1206         }
1207
1208         init_waitqueue_head(&ctx->wait_vsync_queue);
1209         atomic_set(&ctx->wait_vsync_event, 0);
1210
1211         platform_set_drvdata(pdev, ctx);
1212
1213         ctx->encoder = exynos_dpi_probe(dev);
1214         if (IS_ERR(ctx->encoder))
1215                 return PTR_ERR(ctx->encoder);
1216
1217         pm_runtime_enable(dev);
1218
1219         ret = component_add(dev, &fimd_component_ops);
1220         if (ret)
1221                 goto err_disable_pm_runtime;
1222
1223         return ret;
1224
1225 err_disable_pm_runtime:
1226         pm_runtime_disable(dev);
1227
1228         return ret;
1229 }
1230
1231 static int fimd_remove(struct platform_device *pdev)
1232 {
1233         pm_runtime_disable(&pdev->dev);
1234
1235         component_del(&pdev->dev, &fimd_component_ops);
1236
1237         return 0;
1238 }
1239
1240 #ifdef CONFIG_PM
1241 static int exynos_fimd_suspend(struct device *dev)
1242 {
1243         struct fimd_context *ctx = dev_get_drvdata(dev);
1244
1245         clk_disable_unprepare(ctx->lcd_clk);
1246         clk_disable_unprepare(ctx->bus_clk);
1247
1248         return 0;
1249 }
1250
1251 static int exynos_fimd_resume(struct device *dev)
1252 {
1253         struct fimd_context *ctx = dev_get_drvdata(dev);
1254         int ret;
1255
1256         ret = clk_prepare_enable(ctx->bus_clk);
1257         if (ret < 0) {
1258                 DRM_DEV_ERROR(dev,
1259                               "Failed to prepare_enable the bus clk [%d]\n",
1260                               ret);
1261                 return ret;
1262         }
1263
1264         ret = clk_prepare_enable(ctx->lcd_clk);
1265         if  (ret < 0) {
1266                 DRM_DEV_ERROR(dev,
1267                               "Failed to prepare_enable the lcd clk [%d]\n",
1268                               ret);
1269                 return ret;
1270         }
1271
1272         return 0;
1273 }
1274 #endif
1275
1276 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1277         SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1278         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1279                                 pm_runtime_force_resume)
1280 };
1281
1282 struct platform_driver fimd_driver = {
1283         .probe          = fimd_probe,
1284         .remove         = fimd_remove,
1285         .driver         = {
1286                 .name   = "exynos4-fb",
1287                 .owner  = THIS_MODULE,
1288                 .pm     = &exynos_fimd_pm_ops,
1289                 .of_match_table = fimd_driver_dt_match,
1290         },
1291 };