1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments
4 * Author: Rob Clark <robdclark@gmail.com>
7 #include <linux/component.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/hdmi.h>
10 #include <linux/module.h>
11 #include <linux/platform_data/tda9950.h>
12 #include <linux/irq.h>
13 #include <sound/asoundef.h>
14 #include <sound/hdmi-codec.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_edid.h>
19 #include <drm/drm_of.h>
20 #include <drm/drm_probe_helper.h>
21 #include <drm/i2c/tda998x.h>
23 #include <media/cec-notifier.h>
25 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
27 struct tda998x_audio_port {
28 u8 format; /* AFMT_xxx */
29 u8 config; /* AP value */
33 struct i2c_client *cec;
34 struct i2c_client *hdmi;
40 bool supports_infoframes;
45 unsigned long tmds_clock;
46 struct tda998x_audio_params audio_params;
48 struct platform_device *audio_pdev;
49 struct mutex audio_mutex;
51 struct mutex edid_mutex;
52 wait_queue_head_t wq_edid;
53 volatile int wq_edid_wait;
55 struct work_struct detect_work;
56 struct timer_list edid_delay_timer;
57 wait_queue_head_t edid_delay_waitq;
58 bool edid_delay_active;
60 struct drm_encoder encoder;
61 struct drm_bridge bridge;
62 struct drm_connector connector;
64 struct tda998x_audio_port audio_port[2];
65 struct tda9950_glue cec_glue;
66 struct gpio_desc *calib;
67 struct cec_notifier *cec_notify;
70 #define conn_to_tda998x_priv(x) \
71 container_of(x, struct tda998x_priv, connector)
72 #define enc_to_tda998x_priv(x) \
73 container_of(x, struct tda998x_priv, encoder)
74 #define bridge_to_tda998x_priv(x) \
75 container_of(x, struct tda998x_priv, bridge)
77 /* The TDA9988 series of devices use a paged register scheme.. to simplify
78 * things we encode the page # in upper bits of the register #. To read/
79 * write a given register, we need to make sure CURPAGE register is set
80 * appropriately. Which implies reads/writes are not atomic. Fun!
83 #define REG(page, addr) (((page) << 8) | (addr))
84 #define REG2ADDR(reg) ((reg) & 0xff)
85 #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
87 #define REG_CURPAGE 0xff /* write */
90 /* Page 00h: General Control */
91 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
92 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
93 # define MAIN_CNTRL0_SR (1 << 0)
94 # define MAIN_CNTRL0_DECS (1 << 1)
95 # define MAIN_CNTRL0_DEHS (1 << 2)
96 # define MAIN_CNTRL0_CECS (1 << 3)
97 # define MAIN_CNTRL0_CEHS (1 << 4)
98 # define MAIN_CNTRL0_SCALER (1 << 7)
99 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
100 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
101 # define SOFTRESET_AUDIO (1 << 0)
102 # define SOFTRESET_I2C_MASTER (1 << 1)
103 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
104 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
105 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
106 # define I2C_MASTER_DIS_MM (1 << 0)
107 # define I2C_MASTER_DIS_FILT (1 << 1)
108 # define I2C_MASTER_APP_STRT_LAT (1 << 2)
109 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
110 # define FEAT_POWERDOWN_PREFILT BIT(0)
111 # define FEAT_POWERDOWN_CSC BIT(1)
112 # define FEAT_POWERDOWN_SPDIF (1 << 3)
113 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
114 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
115 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
116 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
117 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
118 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
119 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
120 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
121 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
122 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
123 # define VIP_CNTRL_0_MIRR_A (1 << 7)
124 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
125 # define VIP_CNTRL_0_MIRR_B (1 << 3)
126 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
127 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
128 # define VIP_CNTRL_1_MIRR_C (1 << 7)
129 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
130 # define VIP_CNTRL_1_MIRR_D (1 << 3)
131 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
132 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
133 # define VIP_CNTRL_2_MIRR_E (1 << 7)
134 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
135 # define VIP_CNTRL_2_MIRR_F (1 << 3)
136 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
137 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
138 # define VIP_CNTRL_3_X_TGL (1 << 0)
139 # define VIP_CNTRL_3_H_TGL (1 << 1)
140 # define VIP_CNTRL_3_V_TGL (1 << 2)
141 # define VIP_CNTRL_3_EMB (1 << 3)
142 # define VIP_CNTRL_3_SYNC_DE (1 << 4)
143 # define VIP_CNTRL_3_SYNC_HS (1 << 5)
144 # define VIP_CNTRL_3_DE_INT (1 << 6)
145 # define VIP_CNTRL_3_EDGE (1 << 7)
146 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
147 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
148 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
149 # define VIP_CNTRL_4_CCIR656 (1 << 4)
150 # define VIP_CNTRL_4_656_ALT (1 << 5)
151 # define VIP_CNTRL_4_TST_656 (1 << 6)
152 # define VIP_CNTRL_4_TST_PAT (1 << 7)
153 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
154 # define VIP_CNTRL_5_CKCASE (1 << 0)
155 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
156 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
157 # define MUX_AP_SELECT_I2S 0x64
158 # define MUX_AP_SELECT_SPDIF 0x40
159 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
160 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
161 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
162 # define MAT_CONTRL_MAT_BP (1 << 2)
163 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
164 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
165 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
166 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
167 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
168 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
169 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
170 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
171 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
172 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
173 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
174 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
175 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
176 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
177 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
178 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
179 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
180 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
181 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
182 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
183 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
184 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
185 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
186 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
187 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
188 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
189 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
190 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
191 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
192 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
193 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
194 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
195 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
196 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
197 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
198 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
199 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
200 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
201 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
202 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
203 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
204 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
205 # define TBG_CNTRL_0_TOP_TGL (1 << 0)
206 # define TBG_CNTRL_0_TOP_SEL (1 << 1)
207 # define TBG_CNTRL_0_DE_EXT (1 << 2)
208 # define TBG_CNTRL_0_TOP_EXT (1 << 3)
209 # define TBG_CNTRL_0_FRAME_DIS (1 << 5)
210 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
211 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
212 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
213 # define TBG_CNTRL_1_H_TGL (1 << 0)
214 # define TBG_CNTRL_1_V_TGL (1 << 1)
215 # define TBG_CNTRL_1_TGL_EN (1 << 2)
216 # define TBG_CNTRL_1_X_EXT (1 << 3)
217 # define TBG_CNTRL_1_H_EXT (1 << 4)
218 # define TBG_CNTRL_1_V_EXT (1 << 5)
219 # define TBG_CNTRL_1_DWIN_DIS (1 << 6)
220 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
221 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
222 # define HVF_CNTRL_0_SM (1 << 7)
223 # define HVF_CNTRL_0_RWB (1 << 6)
224 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
225 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
226 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
227 # define HVF_CNTRL_1_FOR (1 << 0)
228 # define HVF_CNTRL_1_YUVBLK (1 << 1)
229 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
230 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
231 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
232 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
233 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
234 # define I2S_FORMAT(x) (((x) & 3) << 0)
235 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
236 # define AIP_CLKSEL_AIP_SPDIF (0 << 3)
237 # define AIP_CLKSEL_AIP_I2S (1 << 3)
238 # define AIP_CLKSEL_FS_ACLK (0 << 0)
239 # define AIP_CLKSEL_FS_MCLK (1 << 0)
240 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
242 /* Page 02h: PLL settings */
243 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
244 # define PLL_SERIAL_1_SRL_FDN (1 << 0)
245 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
246 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
247 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
248 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
249 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
250 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
251 # define PLL_SERIAL_3_SRL_CCIR (1 << 0)
252 # define PLL_SERIAL_3_SRL_DE (1 << 2)
253 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
254 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
255 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
256 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
257 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
258 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
259 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
260 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
261 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
262 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
263 # define AUDIO_DIV_SERCLK_1 0
264 # define AUDIO_DIV_SERCLK_2 1
265 # define AUDIO_DIV_SERCLK_4 2
266 # define AUDIO_DIV_SERCLK_8 3
267 # define AUDIO_DIV_SERCLK_16 4
268 # define AUDIO_DIV_SERCLK_32 5
269 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
270 # define SEL_CLK_SEL_CLK1 (1 << 0)
271 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
272 # define SEL_CLK_ENA_SC_CLK (1 << 3)
273 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
276 /* Page 09h: EDID Control */
277 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
278 /* next 127 successive registers are the EDID block */
279 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
280 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
281 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
282 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
283 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
286 /* Page 10h: information frames and packets */
287 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
288 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
289 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
290 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
291 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
294 /* Page 11h: audio settings and content info packets */
295 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
296 # define AIP_CNTRL_0_RST_FIFO (1 << 0)
297 # define AIP_CNTRL_0_SWAP (1 << 1)
298 # define AIP_CNTRL_0_LAYOUT (1 << 2)
299 # define AIP_CNTRL_0_ACR_MAN (1 << 5)
300 # define AIP_CNTRL_0_RST_CTS (1 << 6)
301 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
302 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
303 # define CA_I2S_HBR_CHSTAT (1 << 6)
304 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
305 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
306 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
307 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
308 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
309 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
310 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
311 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
312 # define CTS_N_K(x) (((x) & 7) << 0)
313 # define CTS_N_M(x) (((x) & 3) << 4)
314 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
315 # define ENC_CNTRL_RST_ENC (1 << 0)
316 # define ENC_CNTRL_RST_SEL (1 << 1)
317 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
318 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
319 # define DIP_FLAGS_ACR (1 << 0)
320 # define DIP_FLAGS_GC (1 << 1)
321 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
322 # define DIP_IF_FLAGS_IF1 (1 << 1)
323 # define DIP_IF_FLAGS_IF2 (1 << 2)
324 # define DIP_IF_FLAGS_IF3 (1 << 3)
325 # define DIP_IF_FLAGS_IF4 (1 << 4)
326 # define DIP_IF_FLAGS_IF5 (1 << 5)
327 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
330 /* Page 12h: HDCP and OTP */
331 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
332 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
333 # define TX4_PD_RAM (1 << 1)
334 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
335 # define TX33_HDMI (1 << 1)
338 /* Page 13h: Gamut related metadata packets */
342 /* CEC registers: (not paged)
344 #define REG_CEC_INTSTATUS 0xee /* read */
345 # define CEC_INTSTATUS_CEC (1 << 0)
346 # define CEC_INTSTATUS_HDMI (1 << 1)
347 #define REG_CEC_CAL_XOSC_CTRL1 0xf2
348 # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0)
349 #define REG_CEC_DES_FREQ2 0xf5
350 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
351 #define REG_CEC_CLK 0xf6
352 # define CEC_CLK_FRO 0x11
353 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
354 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
355 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
356 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
357 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
358 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
359 #define REG_CEC_RXSHPDINT 0xfd /* read */
360 # define CEC_RXSHPDINT_RXSENS BIT(0)
361 # define CEC_RXSHPDINT_HPD BIT(1)
362 #define REG_CEC_RXSHPDLEV 0xfe /* read */
363 # define CEC_RXSHPDLEV_RXSENS (1 << 0)
364 # define CEC_RXSHPDLEV_HPD (1 << 1)
366 #define REG_CEC_ENAMODS 0xff /* read/write */
367 # define CEC_ENAMODS_EN_CEC_CLK (1 << 7)
368 # define CEC_ENAMODS_DIS_FRO (1 << 6)
369 # define CEC_ENAMODS_DIS_CCLK (1 << 5)
370 # define CEC_ENAMODS_EN_RXSENS (1 << 2)
371 # define CEC_ENAMODS_EN_HDMI (1 << 1)
372 # define CEC_ENAMODS_EN_CEC (1 << 0)
375 /* Device versions: */
376 #define TDA9989N2 0x0101
377 #define TDA19989 0x0201
378 #define TDA19989N2 0x0202
379 #define TDA19988 0x0301
382 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
384 u8 buf[] = {addr, val};
385 struct i2c_msg msg = {
386 .addr = priv->cec_addr,
392 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
394 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
399 cec_read(struct tda998x_priv *priv, u8 addr)
402 struct i2c_msg msg[2] = {
404 .addr = priv->cec_addr,
408 .addr = priv->cec_addr,
416 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
418 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
426 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
428 int val = cec_read(priv, REG_CEC_ENAMODS);
438 cec_write(priv, REG_CEC_ENAMODS, val);
441 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
446 cec_write(priv, 0xf3, 0xc0);
447 cec_write(priv, 0xf4, 0xd4);
449 /* Enable automatic calibration mode */
450 val = cec_read(priv, REG_CEC_DES_FREQ2);
451 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
452 cec_write(priv, REG_CEC_DES_FREQ2, val);
454 /* Enable free running oscillator */
455 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
456 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
458 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
459 CEC_CAL_XOSC_CTRL1_ENA_CAL);
461 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
466 * Calibration for the internal oscillator: we need to set calibration mode,
467 * and then pulse the IRQ line low for a 10ms ± 1% period.
469 static void tda998x_cec_calibration(struct tda998x_priv *priv)
471 struct gpio_desc *calib = priv->calib;
473 mutex_lock(&priv->edid_mutex);
474 if (priv->hdmi->irq > 0)
475 disable_irq(priv->hdmi->irq);
476 gpiod_direction_output(calib, 1);
477 tda998x_cec_set_calibration(priv, true);
480 gpiod_set_value(calib, 0);
482 gpiod_set_value(calib, 1);
485 tda998x_cec_set_calibration(priv, false);
486 gpiod_direction_input(calib);
487 if (priv->hdmi->irq > 0)
488 enable_irq(priv->hdmi->irq);
489 mutex_unlock(&priv->edid_mutex);
492 static int tda998x_cec_hook_init(void *data)
494 struct tda998x_priv *priv = data;
495 struct gpio_desc *calib;
497 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
499 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
501 return PTR_ERR(calib);
509 static void tda998x_cec_hook_exit(void *data)
511 struct tda998x_priv *priv = data;
513 gpiod_put(priv->calib);
517 static int tda998x_cec_hook_open(void *data)
519 struct tda998x_priv *priv = data;
521 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
522 tda998x_cec_calibration(priv);
527 static void tda998x_cec_hook_release(void *data)
529 struct tda998x_priv *priv = data;
531 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
535 set_page(struct tda998x_priv *priv, u16 reg)
537 if (REG2PAGE(reg) != priv->current_page) {
538 struct i2c_client *client = priv->hdmi;
540 REG_CURPAGE, REG2PAGE(reg)
542 int ret = i2c_master_send(client, buf, sizeof(buf));
544 dev_err(&client->dev, "%s %04x err %d\n", __func__,
549 priv->current_page = REG2PAGE(reg);
555 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
557 struct i2c_client *client = priv->hdmi;
558 u8 addr = REG2ADDR(reg);
561 mutex_lock(&priv->mutex);
562 ret = set_page(priv, reg);
566 ret = i2c_master_send(client, &addr, sizeof(addr));
570 ret = i2c_master_recv(client, buf, cnt);
577 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
579 mutex_unlock(&priv->mutex);
583 #define MAX_WRITE_RANGE_BUF 32
586 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
588 struct i2c_client *client = priv->hdmi;
589 /* This is the maximum size of the buffer passed in */
590 u8 buf[MAX_WRITE_RANGE_BUF + 1];
593 if (cnt > MAX_WRITE_RANGE_BUF) {
594 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
595 MAX_WRITE_RANGE_BUF);
599 buf[0] = REG2ADDR(reg);
600 memcpy(&buf[1], p, cnt);
602 mutex_lock(&priv->mutex);
603 ret = set_page(priv, reg);
607 ret = i2c_master_send(client, buf, cnt + 1);
609 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
611 mutex_unlock(&priv->mutex);
615 reg_read(struct tda998x_priv *priv, u16 reg)
620 ret = reg_read_range(priv, reg, &val, sizeof(val));
627 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
629 struct i2c_client *client = priv->hdmi;
630 u8 buf[] = {REG2ADDR(reg), val};
633 mutex_lock(&priv->mutex);
634 ret = set_page(priv, reg);
638 ret = i2c_master_send(client, buf, sizeof(buf));
640 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
642 mutex_unlock(&priv->mutex);
646 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
648 struct i2c_client *client = priv->hdmi;
649 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
652 mutex_lock(&priv->mutex);
653 ret = set_page(priv, reg);
657 ret = i2c_master_send(client, buf, sizeof(buf));
659 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
661 mutex_unlock(&priv->mutex);
665 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
669 old_val = reg_read(priv, reg);
671 reg_write(priv, reg, old_val | val);
675 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
679 old_val = reg_read(priv, reg);
681 reg_write(priv, reg, old_val & ~val);
685 tda998x_reset(struct tda998x_priv *priv)
687 /* reset audio and i2c master: */
688 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
690 reg_write(priv, REG_SOFTRESET, 0);
693 /* reset transmitter: */
694 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
695 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
697 /* PLL registers common configuration */
698 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
699 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
700 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
701 reg_write(priv, REG_SERIALIZER, 0x00);
702 reg_write(priv, REG_BUFFER_OUT, 0x00);
703 reg_write(priv, REG_PLL_SCG1, 0x00);
704 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
705 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
706 reg_write(priv, REG_PLL_SCGN1, 0xfa);
707 reg_write(priv, REG_PLL_SCGN2, 0x00);
708 reg_write(priv, REG_PLL_SCGR1, 0x5b);
709 reg_write(priv, REG_PLL_SCGR2, 0x00);
710 reg_write(priv, REG_PLL_SCG2, 0x10);
712 /* Write the default value MUX register */
713 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
717 * The TDA998x has a problem when trying to read the EDID close to a
718 * HPD assertion: it needs a delay of 100ms to avoid timing out while
719 * trying to read EDID data.
721 * However, tda998x_connector_get_modes() may be called at any moment
722 * after tda998x_connector_detect() indicates that we are connected, so
723 * we need to delay probing modes in tda998x_connector_get_modes() after
724 * we have seen a HPD inactive->active transition. This code implements
727 static void tda998x_edid_delay_done(struct timer_list *t)
729 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
731 priv->edid_delay_active = false;
732 wake_up(&priv->edid_delay_waitq);
733 schedule_work(&priv->detect_work);
736 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
738 priv->edid_delay_active = true;
739 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
742 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
744 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
748 * We need to run the KMS hotplug event helper outside of our threaded
749 * interrupt routine as this can call back into our get_modes method,
750 * which will want to make use of interrupts.
752 static void tda998x_detect_work(struct work_struct *work)
754 struct tda998x_priv *priv =
755 container_of(work, struct tda998x_priv, detect_work);
756 struct drm_device *dev = priv->connector.dev;
759 drm_kms_helper_hotplug_event(dev);
763 * only 2 interrupts may occur: screen plug/unplug and EDID read
765 static irqreturn_t tda998x_irq_thread(int irq, void *data)
767 struct tda998x_priv *priv = data;
768 u8 sta, cec, lvl, flag0, flag1, flag2;
769 bool handled = false;
771 sta = cec_read(priv, REG_CEC_INTSTATUS);
772 if (sta & CEC_INTSTATUS_HDMI) {
773 cec = cec_read(priv, REG_CEC_RXSHPDINT);
774 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
775 flag0 = reg_read(priv, REG_INT_FLAGS_0);
776 flag1 = reg_read(priv, REG_INT_FLAGS_1);
777 flag2 = reg_read(priv, REG_INT_FLAGS_2);
779 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
780 sta, cec, lvl, flag0, flag1, flag2);
782 if (cec & CEC_RXSHPDINT_HPD) {
783 if (lvl & CEC_RXSHPDLEV_HPD) {
784 tda998x_edid_delay_start(priv);
786 schedule_work(&priv->detect_work);
787 cec_notifier_set_phys_addr(priv->cec_notify,
788 CEC_PHYS_ADDR_INVALID);
794 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
795 priv->wq_edid_wait = 0;
796 wake_up(&priv->wq_edid);
801 return IRQ_RETVAL(handled);
805 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
806 union hdmi_infoframe *frame)
808 u8 buf[MAX_WRITE_RANGE_BUF];
811 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
813 dev_err(&priv->hdmi->dev,
814 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
815 frame->any.type, len);
819 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
820 reg_write_range(priv, addr, buf, len);
821 reg_set(priv, REG_DIP_IF_FLAGS, bit);
824 static int tda998x_write_aif(struct tda998x_priv *priv,
825 struct hdmi_audio_infoframe *cea)
827 union hdmi_infoframe frame;
831 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
837 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
839 union hdmi_infoframe frame;
841 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
842 &priv->connector, mode);
843 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
845 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
850 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
853 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
854 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
855 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
857 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
862 tda998x_configure_audio(struct tda998x_priv *priv,
863 struct tda998x_audio_params *params)
865 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
868 /* Enable audio ports */
869 reg_write(priv, REG_ENA_AP, params->config);
871 /* Set audio input source */
872 switch (params->format) {
874 reg_write(priv, REG_ENA_ACLK, 0);
875 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
876 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
877 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
878 cts_n = CTS_N_M(3) | CTS_N_K(3);
882 reg_write(priv, REG_ENA_ACLK, 1);
883 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
884 clksel_aip = AIP_CLKSEL_AIP_I2S;
885 clksel_fs = AIP_CLKSEL_FS_ACLK;
886 switch (params->sample_width) {
888 cts_n = CTS_N_M(3) | CTS_N_K(1);
893 cts_n = CTS_N_M(3) | CTS_N_K(2);
897 cts_n = CTS_N_M(3) | CTS_N_K(3);
903 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
907 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
908 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
909 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
910 reg_write(priv, REG_CTS_N, cts_n);
913 * Audio input somehow depends on HDMI line rate which is
914 * related to pixclk. Testing showed that modes with pixclk
915 * >100MHz need a larger divider while <40MHz need the default.
916 * There is no detailed info in the datasheet, so we just
917 * assume 100MHz requires larger divider.
919 adiv = AUDIO_DIV_SERCLK_8;
920 if (priv->tmds_clock > 100000)
921 adiv++; /* AUDIO_DIV_SERCLK_16 */
923 /* S/PDIF asks for a larger divider */
924 if (params->format == AFMT_SPDIF)
925 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
927 reg_write(priv, REG_AUDIO_DIV, adiv);
930 * This is the approximate value of N, which happens to be
931 * the recommended values for non-coherent clocks.
933 n = 128 * params->sample_rate / 1000;
935 /* Write the CTS and N values */
942 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
944 /* Set CTS clock reference */
945 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
947 /* Reset CTS generator */
948 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
949 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
951 /* Write the channel status
952 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
953 * there is a separate register for each I2S wire.
955 buf[0] = params->status[0];
956 buf[1] = params->status[1];
957 buf[2] = params->status[3];
958 buf[3] = params->status[4];
959 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
961 tda998x_audio_mute(priv, true);
963 tda998x_audio_mute(priv, false);
965 return tda998x_write_aif(priv, ¶ms->cea);
968 static int tda998x_audio_hw_params(struct device *dev, void *data,
969 struct hdmi_codec_daifmt *daifmt,
970 struct hdmi_codec_params *params)
972 struct tda998x_priv *priv = dev_get_drvdata(dev);
974 struct tda998x_audio_params audio = {
975 .sample_width = params->sample_width,
976 .sample_rate = params->sample_rate,
980 memcpy(audio.status, params->iec.status,
981 min(sizeof(audio.status), sizeof(params->iec.status)));
983 switch (daifmt->fmt) {
985 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
986 daifmt->bit_clk_master || daifmt->frame_clk_master) {
987 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
988 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
989 daifmt->bit_clk_master,
990 daifmt->frame_clk_master);
993 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
994 if (priv->audio_port[i].format == AFMT_I2S)
995 audio.config = priv->audio_port[i].config;
996 audio.format = AFMT_I2S;
999 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
1000 if (priv->audio_port[i].format == AFMT_SPDIF)
1001 audio.config = priv->audio_port[i].config;
1002 audio.format = AFMT_SPDIF;
1005 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1009 if (audio.config == 0) {
1010 dev_err(dev, "%s: No audio configuration found\n", __func__);
1014 mutex_lock(&priv->audio_mutex);
1015 if (priv->supports_infoframes && priv->sink_has_audio)
1016 ret = tda998x_configure_audio(priv, &audio);
1021 priv->audio_params = audio;
1022 mutex_unlock(&priv->audio_mutex);
1027 static void tda998x_audio_shutdown(struct device *dev, void *data)
1029 struct tda998x_priv *priv = dev_get_drvdata(dev);
1031 mutex_lock(&priv->audio_mutex);
1033 reg_write(priv, REG_ENA_AP, 0);
1035 priv->audio_params.format = AFMT_UNUSED;
1037 mutex_unlock(&priv->audio_mutex);
1040 int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
1042 struct tda998x_priv *priv = dev_get_drvdata(dev);
1044 mutex_lock(&priv->audio_mutex);
1046 tda998x_audio_mute(priv, enable);
1048 mutex_unlock(&priv->audio_mutex);
1052 static int tda998x_audio_get_eld(struct device *dev, void *data,
1053 uint8_t *buf, size_t len)
1055 struct tda998x_priv *priv = dev_get_drvdata(dev);
1057 mutex_lock(&priv->audio_mutex);
1058 memcpy(buf, priv->connector.eld,
1059 min(sizeof(priv->connector.eld), len));
1060 mutex_unlock(&priv->audio_mutex);
1065 static const struct hdmi_codec_ops audio_codec_ops = {
1066 .hw_params = tda998x_audio_hw_params,
1067 .audio_shutdown = tda998x_audio_shutdown,
1068 .digital_mute = tda998x_audio_digital_mute,
1069 .get_eld = tda998x_audio_get_eld,
1072 static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1075 struct hdmi_codec_pdata codec_data = {
1076 .ops = &audio_codec_ops,
1077 .max_i2s_channels = 2,
1081 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
1082 if (priv->audio_port[i].format == AFMT_I2S &&
1083 priv->audio_port[i].config != 0)
1085 if (priv->audio_port[i].format == AFMT_SPDIF &&
1086 priv->audio_port[i].config != 0)
1087 codec_data.spdif = 1;
1090 priv->audio_pdev = platform_device_register_data(
1091 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1092 &codec_data, sizeof(codec_data));
1094 return PTR_ERR_OR_ZERO(priv->audio_pdev);
1097 /* DRM connector functions */
1099 static enum drm_connector_status
1100 tda998x_connector_detect(struct drm_connector *connector, bool force)
1102 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1103 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1105 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1106 connector_status_disconnected;
1109 static void tda998x_connector_destroy(struct drm_connector *connector)
1111 drm_connector_cleanup(connector);
1114 static const struct drm_connector_funcs tda998x_connector_funcs = {
1115 .reset = drm_atomic_helper_connector_reset,
1116 .fill_modes = drm_helper_probe_single_connector_modes,
1117 .detect = tda998x_connector_detect,
1118 .destroy = tda998x_connector_destroy,
1119 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1120 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1123 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1125 struct tda998x_priv *priv = data;
1129 offset = (blk & 1) ? 128 : 0;
1132 mutex_lock(&priv->edid_mutex);
1134 reg_write(priv, REG_DDC_ADDR, 0xa0);
1135 reg_write(priv, REG_DDC_OFFS, offset);
1136 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1137 reg_write(priv, REG_DDC_SEGM, segptr);
1139 /* enable reading EDID: */
1140 priv->wq_edid_wait = 1;
1141 reg_write(priv, REG_EDID_CTRL, 0x1);
1143 /* flag must be cleared by sw: */
1144 reg_write(priv, REG_EDID_CTRL, 0x0);
1146 /* wait for block read to complete: */
1147 if (priv->hdmi->irq) {
1148 i = wait_event_timeout(priv->wq_edid,
1149 !priv->wq_edid_wait,
1150 msecs_to_jiffies(100));
1152 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1157 for (i = 100; i > 0; i--) {
1159 ret = reg_read(priv, REG_INT_FLAGS_2);
1162 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1168 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1173 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1174 if (ret != length) {
1175 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1183 mutex_unlock(&priv->edid_mutex);
1187 static int tda998x_connector_get_modes(struct drm_connector *connector)
1189 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1194 * If we get killed while waiting for the HPD timeout, return
1195 * no modes found: we are not in a restartable path, so we
1196 * can't handle signals gracefully.
1198 if (tda998x_edid_delay_wait(priv))
1201 if (priv->rev == TDA19988)
1202 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1204 edid = drm_do_get_edid(connector, read_edid_block, priv);
1206 if (priv->rev == TDA19988)
1207 reg_set(priv, REG_TX4, TX4_PD_RAM);
1210 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1214 drm_connector_update_edid_property(connector, edid);
1215 cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1217 mutex_lock(&priv->audio_mutex);
1218 n = drm_add_edid_modes(connector, edid);
1219 priv->sink_has_audio = drm_detect_monitor_audio(edid);
1220 mutex_unlock(&priv->audio_mutex);
1227 static struct drm_encoder *
1228 tda998x_connector_best_encoder(struct drm_connector *connector)
1230 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1232 return priv->bridge.encoder;
1236 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1237 .get_modes = tda998x_connector_get_modes,
1238 .best_encoder = tda998x_connector_best_encoder,
1241 static int tda998x_connector_init(struct tda998x_priv *priv,
1242 struct drm_device *drm)
1244 struct drm_connector *connector = &priv->connector;
1247 connector->interlace_allowed = 1;
1249 if (priv->hdmi->irq)
1250 connector->polled = DRM_CONNECTOR_POLL_HPD;
1252 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1253 DRM_CONNECTOR_POLL_DISCONNECT;
1255 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1256 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1257 DRM_MODE_CONNECTOR_HDMIA);
1261 drm_connector_attach_encoder(&priv->connector,
1262 priv->bridge.encoder);
1267 /* DRM bridge functions */
1269 static int tda998x_bridge_attach(struct drm_bridge *bridge)
1271 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1273 return tda998x_connector_init(priv, bridge->dev);
1276 static void tda998x_bridge_detach(struct drm_bridge *bridge)
1278 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1280 drm_connector_cleanup(&priv->connector);
1283 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1284 const struct drm_display_mode *mode)
1286 /* TDA19988 dotclock can go up to 165MHz */
1287 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1289 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1290 return MODE_CLOCK_HIGH;
1291 if (mode->htotal >= BIT(13))
1292 return MODE_BAD_HVALUE;
1293 if (mode->vtotal >= BIT(11))
1294 return MODE_BAD_VVALUE;
1298 static void tda998x_bridge_enable(struct drm_bridge *bridge)
1300 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1303 /* enable video ports, audio will be enabled later */
1304 reg_write(priv, REG_ENA_VP_0, 0xff);
1305 reg_write(priv, REG_ENA_VP_1, 0xff);
1306 reg_write(priv, REG_ENA_VP_2, 0xff);
1307 /* set muxing after enabling ports: */
1308 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1309 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1310 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1316 static void tda998x_bridge_disable(struct drm_bridge *bridge)
1318 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1321 /* disable video ports */
1322 reg_write(priv, REG_ENA_VP_0, 0x00);
1323 reg_write(priv, REG_ENA_VP_1, 0x00);
1324 reg_write(priv, REG_ENA_VP_2, 0x00);
1326 priv->is_on = false;
1330 static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1331 const struct drm_display_mode *mode,
1332 const struct drm_display_mode *adjusted_mode)
1334 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1335 unsigned long tmds_clock;
1336 u16 ref_pix, ref_line, n_pix, n_line;
1337 u16 hs_pix_s, hs_pix_e;
1338 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1339 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1340 u16 vwin1_line_s, vwin1_line_e;
1341 u16 vwin2_line_s, vwin2_line_e;
1342 u16 de_pix_s, de_pix_e;
1346 * Internally TDA998x is using ITU-R BT.656 style sync but
1347 * we get VESA style sync. TDA998x is using a reference pixel
1348 * relative to ITU to sync to the input frame and for output
1349 * sync generation. Currently, we are using reference detection
1350 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1351 * which is position of rising VS with coincident rising HS.
1353 * Now there is some issues to take care of:
1354 * - HDMI data islands require sync-before-active
1355 * - TDA998x register values must be > 0 to be enabled
1356 * - REFLINE needs an additional offset of +1
1357 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1359 * So we add +1 to all horizontal and vertical register values,
1360 * plus an additional +3 for REFPIX as we are using RGB input only.
1362 n_pix = mode->htotal;
1363 n_line = mode->vtotal;
1365 hs_pix_e = mode->hsync_end - mode->hdisplay;
1366 hs_pix_s = mode->hsync_start - mode->hdisplay;
1367 de_pix_e = mode->htotal;
1368 de_pix_s = mode->htotal - mode->hdisplay;
1369 ref_pix = 3 + hs_pix_s;
1372 * Attached LCD controllers may generate broken sync. Allow
1373 * those to adjust the position of the rising VS edge by adding
1376 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1377 ref_pix += adjusted_mode->hskew;
1379 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1380 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1381 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1382 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1383 vs1_pix_s = vs1_pix_e = hs_pix_s;
1384 vs1_line_s = mode->vsync_start - mode->vdisplay;
1385 vs1_line_e = vs1_line_s +
1386 mode->vsync_end - mode->vsync_start;
1387 vwin2_line_s = vwin2_line_e = 0;
1388 vs2_pix_s = vs2_pix_e = 0;
1389 vs2_line_s = vs2_line_e = 0;
1391 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1392 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1393 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1394 vs1_pix_s = vs1_pix_e = hs_pix_s;
1395 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1396 vs1_line_e = vs1_line_s +
1397 (mode->vsync_end - mode->vsync_start)/2;
1398 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1399 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1400 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1401 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1402 vs2_line_e = vs2_line_s +
1403 (mode->vsync_end - mode->vsync_start)/2;
1406 tmds_clock = mode->clock;
1409 * The divisor is power-of-2. The TDA9983B datasheet gives
1410 * this as ranges of Msample/s, which is 10x the TMDS clock:
1411 * 0 - 800 to 1500 Msample/s
1412 * 1 - 400 to 800 Msample/s
1413 * 2 - 200 to 400 Msample/s
1416 for (div = 0; div < 3; div++)
1417 if (80000 >> div <= tmds_clock)
1420 mutex_lock(&priv->audio_mutex);
1422 /* mute the audio FIFO: */
1423 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1425 /* set HDMI HDCP mode off: */
1426 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1427 reg_clear(priv, REG_TX33, TX33_HDMI);
1428 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1430 /* no pre-filter or interpolator: */
1431 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1432 HVF_CNTRL_0_INTPOL(0));
1433 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1434 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1435 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1436 VIP_CNTRL_4_BLC(0));
1438 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1439 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1440 PLL_SERIAL_3_SRL_DE);
1441 reg_write(priv, REG_SERIALIZER, 0);
1442 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1444 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1446 reg_write(priv, REG_RPT_CNTRL, 0);
1447 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
1448 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1450 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1451 PLL_SERIAL_2_SRL_PR(rep));
1453 /* set color matrix bypass flag: */
1454 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1455 MAT_CONTRL_MAT_SC(1));
1456 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1458 /* set BIAS tmds value: */
1459 reg_write(priv, REG_ANA_GENERAL, 0x09);
1462 * Sync on rising HSYNC/VSYNC
1464 reg = VIP_CNTRL_3_SYNC_HS;
1467 * TDA19988 requires high-active sync at input stage,
1468 * so invert low-active sync provided by master encoder here
1470 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1471 reg |= VIP_CNTRL_3_H_TGL;
1472 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1473 reg |= VIP_CNTRL_3_V_TGL;
1474 reg_write(priv, REG_VIP_CNTRL_3, reg);
1476 reg_write(priv, REG_VIDFORMAT, 0x00);
1477 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1478 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1479 reg_write16(priv, REG_NPIX_MSB, n_pix);
1480 reg_write16(priv, REG_NLINE_MSB, n_line);
1481 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1482 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1483 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1484 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1485 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1486 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1487 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1488 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1489 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1490 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1491 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1492 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1493 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1494 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1495 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1496 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1498 if (priv->rev == TDA19988) {
1499 /* let incoming pixels fill the active space (if any) */
1500 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1504 * Always generate sync polarity relative to input sync and
1505 * revert input stage toggled sync at output stage
1507 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1508 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1509 reg |= TBG_CNTRL_1_H_TGL;
1510 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1511 reg |= TBG_CNTRL_1_V_TGL;
1512 reg_write(priv, REG_TBG_CNTRL_1, reg);
1514 /* must be last register set: */
1515 reg_write(priv, REG_TBG_CNTRL_0, 0);
1517 priv->tmds_clock = adjusted_mode->clock;
1519 /* CEA-861B section 6 says that:
1520 * CEA version 1 (CEA-861) has no support for infoframes.
1521 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1522 * and optional basic audio.
1523 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1524 * and optional digital audio, with audio infoframes.
1526 * Since we only support generation of version 2 AVI infoframes,
1527 * ignore CEA version 2 and below (iow, behave as if we're a
1530 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1532 if (priv->supports_infoframes) {
1533 /* We need to turn HDMI HDCP stuff on to get audio through */
1534 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1535 reg_write(priv, REG_TBG_CNTRL_1, reg);
1536 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1537 reg_set(priv, REG_TX33, TX33_HDMI);
1539 tda998x_write_avi(priv, adjusted_mode);
1541 if (priv->audio_params.format != AFMT_UNUSED &&
1542 priv->sink_has_audio)
1543 tda998x_configure_audio(priv, &priv->audio_params);
1546 mutex_unlock(&priv->audio_mutex);
1549 static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1550 .attach = tda998x_bridge_attach,
1551 .detach = tda998x_bridge_detach,
1552 .mode_valid = tda998x_bridge_mode_valid,
1553 .disable = tda998x_bridge_disable,
1554 .mode_set = tda998x_bridge_mode_set,
1555 .enable = tda998x_bridge_enable,
1558 /* I2C driver functions */
1560 static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1561 struct device_node *np)
1563 const u32 *port_data;
1567 port_data = of_get_property(np, "audio-ports", &size);
1571 size /= sizeof(u32);
1572 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1573 dev_err(&priv->hdmi->dev,
1574 "Bad number of elements in audio-ports dt-property\n");
1580 for (i = 0; i < size; i++) {
1581 u8 afmt = be32_to_cpup(&port_data[2*i]);
1582 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1584 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1585 dev_err(&priv->hdmi->dev,
1586 "Bad audio format %u\n", afmt);
1590 priv->audio_port[i].format = afmt;
1591 priv->audio_port[i].config = ena_ap;
1594 if (priv->audio_port[0].format == priv->audio_port[1].format) {
1595 dev_err(&priv->hdmi->dev,
1596 "There can only be on I2S port and one SPDIF port\n");
1602 static void tda998x_set_config(struct tda998x_priv *priv,
1603 const struct tda998x_encoder_params *p)
1605 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1606 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1607 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1608 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1609 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1610 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1611 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1612 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1613 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1614 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1615 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1616 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1618 priv->audio_params = p->audio_params;
1621 static void tda998x_destroy(struct device *dev)
1623 struct tda998x_priv *priv = dev_get_drvdata(dev);
1625 drm_bridge_remove(&priv->bridge);
1627 /* disable all IRQs and free the IRQ handler */
1628 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1629 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1631 if (priv->audio_pdev)
1632 platform_device_unregister(priv->audio_pdev);
1634 if (priv->hdmi->irq)
1635 free_irq(priv->hdmi->irq, priv);
1637 del_timer_sync(&priv->edid_delay_timer);
1638 cancel_work_sync(&priv->detect_work);
1640 i2c_unregister_device(priv->cec);
1642 if (priv->cec_notify)
1643 cec_notifier_put(priv->cec_notify);
1646 static int tda998x_create(struct device *dev)
1648 struct i2c_client *client = to_i2c_client(dev);
1649 struct device_node *np = client->dev.of_node;
1650 struct i2c_board_info cec_info;
1651 struct tda998x_priv *priv;
1653 int rev_lo, rev_hi, ret;
1655 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1659 dev_set_drvdata(dev, priv);
1661 mutex_init(&priv->mutex); /* protect the page access */
1662 mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1663 mutex_init(&priv->edid_mutex);
1664 INIT_LIST_HEAD(&priv->bridge.list);
1665 init_waitqueue_head(&priv->edid_delay_waitq);
1666 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1667 INIT_WORK(&priv->detect_work, tda998x_detect_work);
1669 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1670 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1671 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1673 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1674 priv->cec_addr = 0x34 + (client->addr & 0x03);
1675 priv->current_page = 0xff;
1676 priv->hdmi = client;
1678 /* wake up the device: */
1679 cec_write(priv, REG_CEC_ENAMODS,
1680 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1682 tda998x_reset(priv);
1685 rev_lo = reg_read(priv, REG_VERSION_LSB);
1687 dev_err(dev, "failed to read version: %d\n", rev_lo);
1691 rev_hi = reg_read(priv, REG_VERSION_MSB);
1693 dev_err(dev, "failed to read version: %d\n", rev_hi);
1697 priv->rev = rev_lo | rev_hi << 8;
1699 /* mask off feature bits: */
1700 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1702 switch (priv->rev) {
1704 dev_info(dev, "found TDA9989 n2");
1707 dev_info(dev, "found TDA19989");
1710 dev_info(dev, "found TDA19989 n2");
1713 dev_info(dev, "found TDA19988");
1716 dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1720 /* after reset, enable DDC: */
1721 reg_write(priv, REG_DDC_DISABLE, 0x00);
1723 /* set clock on DDC channel: */
1724 reg_write(priv, REG_TX3, 39);
1726 /* if necessary, disable multi-master: */
1727 if (priv->rev == TDA19989)
1728 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1730 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1731 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1733 /* ensure interrupts are disabled */
1734 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1736 /* clear pending interrupts */
1737 cec_read(priv, REG_CEC_RXSHPDINT);
1738 reg_read(priv, REG_INT_FLAGS_0);
1739 reg_read(priv, REG_INT_FLAGS_1);
1740 reg_read(priv, REG_INT_FLAGS_2);
1742 /* initialize the optional IRQ */
1744 unsigned long irq_flags;
1746 /* init read EDID waitqueue and HDP work */
1747 init_waitqueue_head(&priv->wq_edid);
1750 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1752 priv->cec_glue.irq_flags = irq_flags;
1754 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1755 ret = request_threaded_irq(client->irq, NULL,
1756 tda998x_irq_thread, irq_flags,
1759 dev_err(dev, "failed to request IRQ#%u: %d\n",
1764 /* enable HPD irq */
1765 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1768 priv->cec_notify = cec_notifier_get(dev);
1769 if (!priv->cec_notify) {
1774 priv->cec_glue.parent = dev;
1775 priv->cec_glue.data = priv;
1776 priv->cec_glue.init = tda998x_cec_hook_init;
1777 priv->cec_glue.exit = tda998x_cec_hook_exit;
1778 priv->cec_glue.open = tda998x_cec_hook_open;
1779 priv->cec_glue.release = tda998x_cec_hook_release;
1782 * Some TDA998x are actually two I2C devices merged onto one piece
1783 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1784 * with a slightly modified TDA9950 CEC device. The CEC device
1785 * is at the TDA9950 address, with the address pins strapped across
1786 * to the TDA998x address pins. Hence, it always has the same
1789 memset(&cec_info, 0, sizeof(cec_info));
1790 strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1791 cec_info.addr = priv->cec_addr;
1792 cec_info.platform_data = &priv->cec_glue;
1793 cec_info.irq = client->irq;
1795 priv->cec = i2c_new_device(client->adapter, &cec_info);
1801 /* enable EDID read irq: */
1802 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1805 /* get the device tree parameters */
1806 ret = of_property_read_u32(np, "video-ports", &video);
1808 priv->vip_cntrl_0 = video >> 16;
1809 priv->vip_cntrl_1 = video >> 8;
1810 priv->vip_cntrl_2 = video;
1813 ret = tda998x_get_audio_ports(priv, np);
1817 if (priv->audio_port[0].format != AFMT_UNUSED)
1818 tda998x_audio_codec_init(priv, &client->dev);
1819 } else if (dev->platform_data) {
1820 tda998x_set_config(priv, dev->platform_data);
1823 priv->bridge.funcs = &tda998x_bridge_funcs;
1825 priv->bridge.of_node = dev->of_node;
1828 drm_bridge_add(&priv->bridge);
1833 tda998x_destroy(dev);
1838 /* DRM encoder functions */
1840 static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1842 drm_encoder_cleanup(encoder);
1845 static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1846 .destroy = tda998x_encoder_destroy,
1849 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
1851 struct tda998x_priv *priv = dev_get_drvdata(dev);
1856 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1858 /* If no CRTCs were found, fall back to our old behaviour */
1860 dev_warn(dev, "Falling back to first CRTC\n");
1864 priv->encoder.possible_crtcs = crtcs;
1866 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1867 DRM_MODE_ENCODER_TMDS, NULL);
1871 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL);
1878 drm_encoder_cleanup(&priv->encoder);
1883 static int tda998x_bind(struct device *dev, struct device *master, void *data)
1885 struct drm_device *drm = data;
1887 return tda998x_encoder_init(dev, drm);
1890 static void tda998x_unbind(struct device *dev, struct device *master,
1893 struct tda998x_priv *priv = dev_get_drvdata(dev);
1895 drm_encoder_cleanup(&priv->encoder);
1898 static const struct component_ops tda998x_ops = {
1899 .bind = tda998x_bind,
1900 .unbind = tda998x_unbind,
1904 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1908 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1909 dev_warn(&client->dev, "adapter does not support I2C\n");
1913 ret = tda998x_create(&client->dev);
1917 ret = component_add(&client->dev, &tda998x_ops);
1919 tda998x_destroy(&client->dev);
1923 static int tda998x_remove(struct i2c_client *client)
1925 component_del(&client->dev, &tda998x_ops);
1926 tda998x_destroy(&client->dev);
1931 static const struct of_device_id tda998x_dt_ids[] = {
1932 { .compatible = "nxp,tda998x", },
1935 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1938 static const struct i2c_device_id tda998x_ids[] = {
1942 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1944 static struct i2c_driver tda998x_driver = {
1945 .probe = tda998x_probe,
1946 .remove = tda998x_remove,
1949 .of_match_table = of_match_ptr(tda998x_dt_ids),
1951 .id_table = tda998x_ids,
1954 module_i2c_driver(tda998x_driver);
1956 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1957 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1958 MODULE_LICENSE("GPL");