drivers/gpu/drm/i915/display/intel_color.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_color.h"
  26 #include "intel_display_types.h"
  27
  28 #define CTM_COEFF_SIGN  (1ULL << 63)
  29
  30 #define CTM_COEFF_1_0   (1ULL << 32)
  31 #define CTM_COEFF_2_0   (CTM_COEFF_1_0 << 1)
  32 #define CTM_COEFF_4_0   (CTM_COEFF_2_0 << 1)
  33 #define CTM_COEFF_8_0   (CTM_COEFF_4_0 << 1)
  34 #define CTM_COEFF_0_5   (CTM_COEFF_1_0 >> 1)
  35 #define CTM_COEFF_0_25  (CTM_COEFF_0_5 >> 1)
  36 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
  37
  38 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
  39
  40 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
  41 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
  42
  43 #define LEGACY_LUT_LENGTH               256
  44
  45 /*
  46  * ILK+ csc matrix:
  47  *
  48  * |R/Cr|   | c0 c1 c2 |   ( |R/Cr|   |preoff0| )   |postoff0|
  49  * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
  50  * |B/Cb|   | c6 c7 c8 |   ( |B/Cb|   |preoff2| )   |postoff2|
  51  *
  52  * ILK/SNB don't have explicit post offsets, and instead
  53  * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
  54  *  CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
  55  *  CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
  56  *  CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
  57  *  CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
  58  */
  59
  60 /*
  61  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  62  * format). This macro takes the coefficient we want transformed and the
  63  * number of fractional bits.
  64  *
  65  * We only have a 9 bits precision window which slides depending on the value
  66  * of the CTM coefficient and we write the value from bit 3. We also round the
  67  * value.
  68  */
  69 #define ILK_CSC_COEFF_FP(coeff, fbits)  \
  70         (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
  71
  72 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
  73 #define ILK_CSC_COEFF_1_0 0x7800
  74
  75 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
  76
  77 /* Nop pre/post offsets */
  78 static const u16 ilk_csc_off_zero[3] = {};
  79
  80 /* Identity matrix */
  81 static const u16 ilk_csc_coeff_identity[9] = {
  82         ILK_CSC_COEFF_1_0, 0, 0,
  83         0, ILK_CSC_COEFF_1_0, 0,
  84         0, 0, ILK_CSC_COEFF_1_0,
  85 };
  86
  87 /* Limited range RGB post offsets */
  88 static const u16 ilk_csc_postoff_limited_range[3] = {
  89         ILK_CSC_POSTOFF_LIMITED_RANGE,
  90         ILK_CSC_POSTOFF_LIMITED_RANGE,
  91         ILK_CSC_POSTOFF_LIMITED_RANGE,
  92 };
  93
  94 /* Full range RGB -> limited range RGB matrix */
  95 static const u16 ilk_csc_coeff_limited_range[9] = {
  96         ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
  97         0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
  98         0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
  99 };
 100
 101 /* BT.709 full range RGB -> limited range YCbCr matrix */
 102 static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
 103         0x1e08, 0x9cc0, 0xb528,
 104         0x2ba8, 0x09d8, 0x37e8,
 105         0xbce8, 0x9ad8, 0x1e08,
 106 };
 107
 108 /* Limited range YCbCr post offsets */
 109 static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
 110         0x0800, 0x0100, 0x0800,
 111 };
 112
 113 static bool lut_is_legacy(const struct drm_property_blob *lut)
 114 {
 115         return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
 116 }
 117
 118 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
 119 {
 120         return !crtc_state->base.degamma_lut &&
 121                 !crtc_state->base.ctm &&
 122                 crtc_state->base.gamma_lut &&
 123                 lut_is_legacy(crtc_state->base.gamma_lut);
 124 }
 125
 126 /*
 127  * When using limited range, multiply the matrix given by userspace by
 128  * the matrix that we would use for the limited range.
 129  */
 130 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 131 {
 132         int i;
 133
 134         for (i = 0; i < 9; i++) {
 135                 u64 user_coeff = input[i];
 136                 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
 137                 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
 138                                           CTM_COEFF_4_0 - 1) >> 2;
 139
 140                 /*
 141                  * By scaling every co-efficient with limited range (16-235)
 142                  * vs full range (0-255) the final o/p will be scaled down to
 143                  * fit in the limited range supported by the panel.
 144                  */
 145                 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
 146                 result[i] |= user_coeff & CTM_COEFF_SIGN;
 147         }
 148
 149         return result;
 150 }
 151
 152 static void ilk_update_pipe_csc(struct intel_crtc *crtc,
 153                                 const u16 preoff[3],
 154                                 const u16 coeff[9],
 155                                 const u16 postoff[3])
 156 {
 157         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 158         enum pipe pipe = crtc->pipe;
 159
 160         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
 161         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
 162         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
 163
 164         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
 165         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
 166
 167         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
 168         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
 169
 170         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
 171         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
 172
 173         if (INTEL_GEN(dev_priv) >= 7) {
 174                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]);
 175                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff[1]);
 176                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff[2]);
 177         }
 178 }
 179
 180 static void icl_update_output_csc(struct intel_crtc *crtc,
 181                                   const u16 preoff[3],
 182                                   const u16 coeff[9],
 183                                   const u16 postoff[3])
 184 {
 185         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 186         enum pipe pipe = crtc->pipe;
 187
 188         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
 189         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
 190         I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
 191
 192         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
 193         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2] << 16);
 194
 195         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
 196         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5] << 16);
 197
 198         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
 199         I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8] << 16);
 200
 201         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
 202         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
 203         I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
 204 }
 205
 206 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 207 {
 208         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 209
 210         /*
 211          * FIXME if there's a gamma LUT after the CSC, we should
 212          * do the range compression using the gamma LUT instead.
 213          */
 214         return crtc_state->limited_color_range &&
 215                 (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
 216                  IS_GEN_RANGE(dev_priv, 9, 10));
 217 }
 218
 219 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
 220                                 u16 coeffs[9])
 221 {
 222         const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 223         const u64 *input;
 224         u64 temp[9];
 225         int i;
 226
 227         if (ilk_csc_limited_range(crtc_state))
 228                 input = ctm_mult_by_limited(temp, ctm->matrix);
 229         else
 230                 input = ctm->matrix;
 231
 232         /*
 233          * Convert fixed point S31.32 input to format supported by the
 234          * hardware.
 235          */
 236         for (i = 0; i < 9; i++) {
 237                 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
 238
 239                 /*
 240                  * Clamp input value to min/max supported by
 241                  * hardware.
 242                  */
 243                 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
 244
 245                 coeffs[i] = 0;
 246
 247                 /* sign bit */
 248                 if (CTM_COEFF_NEGATIVE(input[i]))
 249                         coeffs[i] |= 1 << 15;
 250
 251                 if (abs_coeff < CTM_COEFF_0_125)
 252                         coeffs[i] |= (3 << 12) |
 253                                 ILK_CSC_COEFF_FP(abs_coeff, 12);
 254                 else if (abs_coeff < CTM_COEFF_0_25)
 255                         coeffs[i] |= (2 << 12) |
 256                                 ILK_CSC_COEFF_FP(abs_coeff, 11);
 257                 else if (abs_coeff < CTM_COEFF_0_5)
 258                         coeffs[i] |= (1 << 12) |
 259                                 ILK_CSC_COEFF_FP(abs_coeff, 10);
 260                 else if (abs_coeff < CTM_COEFF_1_0)
 261                         coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
 262                 else if (abs_coeff < CTM_COEFF_2_0)
 263                         coeffs[i] |= (7 << 12) |
 264                                 ILK_CSC_COEFF_FP(abs_coeff, 8);
 265                 else
 266                         coeffs[i] |= (6 << 12) |
 267                                 ILK_CSC_COEFF_FP(abs_coeff, 7);
 268         }
 269 }
 270
 271 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 272 {
 273         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 274         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 275         bool limited_color_range = ilk_csc_limited_range(crtc_state);
 276
 277         if (crtc_state->base.ctm) {
 278                 u16 coeff[9];
 279
 280                 ilk_csc_convert_ctm(crtc_state, coeff);
 281                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
 282                                     limited_color_range ?
 283                                     ilk_csc_postoff_limited_range :
 284                                     ilk_csc_off_zero);
 285         } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 286                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 287                                     ilk_csc_coeff_rgb_to_ycbcr,
 288                                     ilk_csc_postoff_rgb_to_ycbcr);
 289         } else if (limited_color_range) {
 290                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 291                                     ilk_csc_coeff_limited_range,
 292                                     ilk_csc_postoff_limited_range);
 293         } else if (crtc_state->csc_enable) {
 294                 /*
 295                  * On GLK+ both pipe CSC and degamma LUT are controlled
 296                  * by csc_enable. Hence for the cases where the degama
 297                  * LUT is needed but CSC is not we need to load an
 298                  * identity matrix.
 299                  */
 300                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_GEMINILAKE(dev_priv));
 301
 302                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 303                                     ilk_csc_coeff_identity,
 304                                     ilk_csc_off_zero);
 305         }
 306
 307         I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 308 }
 309
 310 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 311 {
 312         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 313         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 314
 315         if (crtc_state->base.ctm) {
 316                 u16 coeff[9];
 317
 318                 ilk_csc_convert_ctm(crtc_state, coeff);
 319                 ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 320                                     coeff, ilk_csc_off_zero);
 321         }
 322
 323         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
 324                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 325                                       ilk_csc_coeff_rgb_to_ycbcr,
 326                                       ilk_csc_postoff_rgb_to_ycbcr);
 327         } else if (crtc_state->limited_color_range) {
 328                 icl_update_output_csc(crtc, ilk_csc_off_zero,
 329                                       ilk_csc_coeff_limited_range,
 330                                       ilk_csc_postoff_limited_range);
 331         }
 332
 333         I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 334 }
 335
 336 /*
 337  * Set up the pipe CSC unit on CherryView.
 338  */
 339 static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 340 {
 341         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 342         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 343         enum pipe pipe = crtc->pipe;
 344
 345         if (crtc_state->base.ctm) {
 346                 const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 347                 u16 coeffs[9] = {};
 348                 int i;
 349
 350                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 351                         u64 abs_coeff =
 352                                 ((1ULL << 63) - 1) & ctm->matrix[i];
 353
 354                         /* Round coefficient. */
 355                         abs_coeff += 1 << (32 - 13);
 356                         /* Clamp to hardware limits. */
 357                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 358
 359                         /* Write coefficients in S3.12 format. */
 360                         if (ctm->matrix[i] & (1ULL << 63))
 361                                 coeffs[i] = 1 << 15;
 362                         coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
 363                         coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 364                 }
 365
 366                 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
 367                            coeffs[1] << 16 | coeffs[0]);
 368                 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
 369                            coeffs[3] << 16 | coeffs[2]);
 370                 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
 371                            coeffs[5] << 16 | coeffs[4]);
 372                 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
 373                            coeffs[7] << 16 | coeffs[6]);
 374                 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 375         }
 376
 377         I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
 378 }
 379
 380 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 381 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 382 {
 383         return (color->red & 0xff) << 16 |
 384                 (color->green & 0xff) << 8 |
 385                 (color->blue & 0xff);
 386 }
 387
 388 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
 389 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
 390 {
 391         return (color->red >> 8) << 16 |
 392                 (color->green >> 8) << 8 |
 393                 (color->blue >> 8);
 394 }
 395
 396 static u32 ilk_lut_10(const struct drm_color_lut *color)
 397 {
 398         return drm_color_lut_extract(color->red, 10) << 20 |
 399                 drm_color_lut_extract(color->green, 10) << 10 |
 400                 drm_color_lut_extract(color->blue, 10);
 401 }
 402
 403 /* Loads the legacy palette/gamma unit for the CRTC. */
 404 static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
 405                                     const struct drm_property_blob *blob)
 406 {
 407         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 408         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 409         enum pipe pipe = crtc->pipe;
 410         int i;
 411
 412         if (HAS_GMCH(dev_priv)) {
 413                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 414                         assert_dsi_pll_enabled(dev_priv);
 415                 else
 416                         assert_pll_enabled(dev_priv, pipe);
 417         }
 418
 419         if (blob) {
 420                 const struct drm_color_lut *lut = blob->data;
 421
 422                 for (i = 0; i < 256; i++) {
 423                         u32 word =
 424                                 (drm_color_lut_extract(lut[i].red, 8) << 16) |
 425                                 (drm_color_lut_extract(lut[i].green, 8) << 8) |
 426                                 drm_color_lut_extract(lut[i].blue, 8);
 427
 428                         if (HAS_GMCH(dev_priv))
 429                                 I915_WRITE(PALETTE(pipe, i), word);
 430                         else
 431                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 432                 }
 433         }
 434 }
 435
 436 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
 437 {
 438         i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 439 }
 440
 441 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 442 {
 443         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 444         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 445         enum pipe pipe = crtc->pipe;
 446         u32 val;
 447
 448         val = I915_READ(PIPECONF(pipe));
 449         val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
 450         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 451         I915_WRITE(PIPECONF(pipe), val);
 452 }
 453
 454 static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
 455 {
 456         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 458         enum pipe pipe = crtc->pipe;
 459         u32 val;
 460
 461         val = I915_READ(PIPECONF(pipe));
 462         val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
 463         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 464         I915_WRITE(PIPECONF(pipe), val);
 465
 466         ilk_load_csc_matrix(crtc_state);
 467 }
 468
 469 static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
 470 {
 471         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 472         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 473
 474         I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 475
 476         ilk_load_csc_matrix(crtc_state);
 477 }
 478
 479 static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 480 {
 481         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 482         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 483         enum pipe pipe = crtc->pipe;
 484         u32 val = 0;
 485
 486         /*
 487          * We don't (yet) allow userspace to control the pipe background color,
 488          * so force it to black, but apply pipe gamma and CSC appropriately
 489          * so that its handling will match how we program our planes.
 490          */
 491         if (crtc_state->gamma_enable)
 492                 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
 493         if (crtc_state->csc_enable)
 494                 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
 495         I915_WRITE(SKL_BOTTOM_COLOR(pipe), val);
 496
 497         I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 498
 499         if (INTEL_GEN(dev_priv) >= 11)
 500                 icl_load_csc_matrix(crtc_state);
 501         else
 502                 ilk_load_csc_matrix(crtc_state);
 503 }
 504
 505 static void i965_load_lut_10p6(struct intel_crtc *crtc,
 506                                const struct drm_property_blob *blob)
 507 {
 508         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 509         const struct drm_color_lut *lut = blob->data;
 510         int i, lut_size = drm_color_lut_size(blob);
 511         enum pipe pipe = crtc->pipe;
 512
 513         for (i = 0; i < lut_size - 1; i++) {
 514                 I915_WRITE(PALETTE(pipe, 2 * i + 0),
 515                            i965_lut_10p6_ldw(&lut[i]));
 516                 I915_WRITE(PALETTE(pipe, 2 * i + 1),
 517                            i965_lut_10p6_udw(&lut[i]));
 518         }
 519
 520         I915_WRITE(PIPEGCMAX(pipe, 0), lut[i].red);
 521         I915_WRITE(PIPEGCMAX(pipe, 1), lut[i].green);
 522         I915_WRITE(PIPEGCMAX(pipe, 2), lut[i].blue);
 523 }
 524
 525 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 526 {
 527         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 528         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 529
 530         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 531                 i9xx_load_luts(crtc_state);
 532         else
 533                 i965_load_lut_10p6(crtc, gamma_lut);
 534 }
 535
 536 static void ilk_load_lut_10(struct intel_crtc *crtc,
 537                             const struct drm_property_blob *blob)
 538 {
 539         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 540         const struct drm_color_lut *lut = blob->data;
 541         int i, lut_size = drm_color_lut_size(blob);
 542         enum pipe pipe = crtc->pipe;
 543
 544         for (i = 0; i < lut_size; i++)
 545                 I915_WRITE(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i]));
 546 }
 547
 548 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 549 {
 550         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 551         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 552
 553         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 554                 i9xx_load_luts(crtc_state);
 555         else
 556                 ilk_load_lut_10(crtc, gamma_lut);
 557 }
 558
 559 static int ivb_lut_10_size(u32 prec_index)
 560 {
 561         if (prec_index & PAL_PREC_SPLIT_MODE)
 562                 return 512;
 563         else
 564                 return 1024;
 565 }
 566
 567 /*
 568  * IVB/HSW Bspec / PAL_PREC_INDEX:
 569  * "Restriction : Index auto increment mode is not
 570  *  supported and must not be enabled."
 571  */
 572 static void ivb_load_lut_10(struct intel_crtc *crtc,
 573                             const struct drm_property_blob *blob,
 574                             u32 prec_index)
 575 {
 576         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 577         int hw_lut_size = ivb_lut_10_size(prec_index);
 578         const struct drm_color_lut *lut = blob->data;
 579         int i, lut_size = drm_color_lut_size(blob);
 580         enum pipe pipe = crtc->pipe;
 581
 582         for (i = 0; i < hw_lut_size; i++) {
 583                 /* We discard half the user entries in split gamma mode */
 584                 const struct drm_color_lut *entry =
 585                         &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 586
 587                 I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++);
 588                 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry));
 589         }
 590
 591         /*
 592          * Reset the index, otherwise it prevents the legacy palette to be
 593          * written properly.
 594          */
 595         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 596 }
 597
 598 /* On BDW+ the index auto increment mode actually works */
 599 static void bdw_load_lut_10(struct intel_crtc *crtc,
 600                             const struct drm_property_blob *blob,
 601                             u32 prec_index)
 602 {
 603         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 604         int hw_lut_size = ivb_lut_10_size(prec_index);
 605         const struct drm_color_lut *lut = blob->data;
 606         int i, lut_size = drm_color_lut_size(blob);
 607         enum pipe pipe = crtc->pipe;
 608
 609         I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
 610                    PAL_PREC_AUTO_INCREMENT);
 611
 612         for (i = 0; i < hw_lut_size; i++) {
 613                 /* We discard half the user entries in split gamma mode */
 614                 const struct drm_color_lut *entry =
 615                         &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
 616
 617                 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry));
 618         }
 619
 620         /*
 621          * Reset the index, otherwise it prevents the legacy palette to be
 622          * written properly.
 623          */
 624         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 625 }
 626
 627 static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
 628 {
 629         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 630         enum pipe pipe = crtc->pipe;
 631
 632         /* Program the max register to clamp values > 1.0. */
 633         I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
 634         I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
 635         I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
 636
 637         /*
 638          * Program the gc max 2 register to clamp values > 1.0.
 639          * ToDo: Extend the ABI to be able to program values
 640          * from 3.0 to 7.0
 641          */
 642         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 643                 I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
 644                 I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
 645                 I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
 646         }
 647 }
 648
 649 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 650 {
 651         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 652         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 653         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 654
 655         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 656                 i9xx_load_luts(crtc_state);
 657         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 658                 ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 659                                 PAL_PREC_INDEX_VALUE(0));
 660                 ivb_load_lut_ext_max(crtc);
 661                 ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 662                                 PAL_PREC_INDEX_VALUE(512));
 663         } else {
 664                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 665
 666                 ivb_load_lut_10(crtc, blob,
 667                                 PAL_PREC_INDEX_VALUE(0));
 668                 ivb_load_lut_ext_max(crtc);
 669         }
 670 }
 671
 672 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 673 {
 674         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 675         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 676         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 677
 678         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 679                 i9xx_load_luts(crtc_state);
 680         } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 681                 bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 682                                 PAL_PREC_INDEX_VALUE(0));
 683                 ivb_load_lut_ext_max(crtc);
 684                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 685                                 PAL_PREC_INDEX_VALUE(512));
 686         } else {
 687                 const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 688
 689                 bdw_load_lut_10(crtc, blob,
 690                                 PAL_PREC_INDEX_VALUE(0));
 691                 ivb_load_lut_ext_max(crtc);
 692         }
 693 }
 694
 695 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 696 {
 697         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 698         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 699         enum pipe pipe = crtc->pipe;
 700         const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 701         const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
 702         u32 i;
 703
 704         /*
 705          * When setting the auto-increment bit, the hardware seems to
 706          * ignore the index bits, so we need to reset it to index 0
 707          * separately.
 708          */
 709         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 710         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 711
 712         for (i = 0; i < lut_size; i++) {
 713                 /*
 714                  * First 33 entries represent range from 0 to 1.0
 715                  * 34th and 35th entry will represent extended range
 716                  * inputs 3.0 and 7.0 respectively, currently clamped
 717                  * at 1.0. Since the precision is 16bit, the user
 718                  * value can be directly filled to register.
 719                  * The pipe degamma table in GLK+ onwards doesn't
 720                  * support different values per channel, so this just
 721                  * programs green value which will be equal to Red and
 722                  * Blue into the lut registers.
 723                  * ToDo: Extend to max 7.0. Enable 32 bit input value
 724                  * as compared to just 16 to achieve this.
 725                  */
 726                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green);
 727         }
 728
 729         /* Clamp values > 1.0. */
 730         while (i++ < 35)
 731                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 732 }
 733
 734 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
 735 {
 736         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 737         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 738         enum pipe pipe = crtc->pipe;
 739         const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 740         u32 i;
 741
 742         /*
 743          * When setting the auto-increment bit, the hardware seems to
 744          * ignore the index bits, so we need to reset it to index 0
 745          * separately.
 746          */
 747         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 748         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 749
 750         for (i = 0; i < lut_size; i++) {
 751                 u32 v = (i << 16) / (lut_size - 1);
 752
 753                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
 754         }
 755
 756         /* Clamp values > 1.0. */
 757         while (i++ < 35)
 758                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), 1 << 16);
 759 }
 760
 761 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 762 {
 763         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 764         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 765
 766         /*
 767          * On GLK+ both pipe CSC and degamma LUT are controlled
 768          * by csc_enable. Hence for the cases where the CSC is
 769          * needed but degamma LUT is not we need to load a
 770          * linear degamma LUT. In fact we'll just always load
 771          * the degama LUT so that we don't have to reload
 772          * it every time the pipe CSC is being enabled.
 773          */
 774         if (crtc_state->base.degamma_lut)
 775                 glk_load_degamma_lut(crtc_state);
 776         else
 777                 glk_load_degamma_lut_linear(crtc_state);
 778
 779         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
 780                 i9xx_load_luts(crtc_state);
 781         } else {
 782                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 783                 ivb_load_lut_ext_max(crtc);
 784         }
 785 }
 786
 787 /* ilk+ "12.4" interpolated format (high 10 bits) */
 788 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
 789 {
 790         return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
 791                 (color->blue >> 6);
 792 }
 793
 794 /* ilk+ "12.4" interpolated format (low 6 bits) */
 795 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
 796 {
 797         return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
 798                 (color->blue & 0x3f) << 4;
 799 }
 800
 801 static void
 802 icl_load_gcmax(const struct intel_crtc_state *crtc_state,
 803                const struct drm_color_lut *color)
 804 {
 805         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 806         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 807         enum pipe pipe = crtc->pipe;
 808
 809         /* Fixme: LUT entries are 16 bit only, so we can prog 0xFFFF max */
 810         I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
 811         I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
 812         I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
 813 }
 814
 815 static void
 816 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 817 {
 818         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 819         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 820         const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
 821         const struct drm_color_lut *lut = blob->data;
 822         enum pipe pipe = crtc->pipe;
 823         u32 i;
 824
 825         /*
 826          * Program Super Fine segment (let's call it seg1)...
 827          *
 828          * Super Fine segment's step is 1/(8 * 128 * 256) and it has
 829          * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
 830          * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
 831          */
 832         I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
 833
 834         for (i = 0; i < 9; i++) {
 835                 const struct drm_color_lut *entry = &lut[i];
 836
 837                 I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
 838                            ilk_lut_12p4_ldw(entry));
 839                 I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
 840                            ilk_lut_12p4_udw(entry));
 841         }
 842 }
 843
 844 static void
 845 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 846 {
 847         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 848         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 849         const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
 850         const struct drm_color_lut *lut = blob->data;
 851         const struct drm_color_lut *entry;
 852         enum pipe pipe = crtc->pipe;
 853         u32 i;
 854
 855         /*
 856          * Program Fine segment (let's call it seg2)...
 857          *
 858          * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
 859          * ... 256/(128 * 256). So in order to program fine segment of LUT we
 860          * need to pick every 8th entry in the LUT, and program 256 indexes.
 861          *
 862          * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
 863          * seg2[0] being unused by the hardware.
 864          */
 865         I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
 866
 867         for (i = 1; i < 257; i++) {
 868                 entry = &lut[i * 8];
 869                 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry));
 870                 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry));
 871         }
 872
 873         /*
 874          * Program Coarse segment (let's call it seg3)...
 875          *
 876          * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
 877          * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
 878          * above, we need to pick every (8 * 128)th entry in LUT, and
 879          * program 256 of those.
 880          *
 881          * Spec is not very clear about if entries seg3[0] and seg3[1] are
 882          * being used or not, but we still need to program these to advance
 883          * the index.
 884          */
 885         for (i = 0; i < 256; i++) {
 886                 entry = &lut[i * 8 * 128];
 887                 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry));
 888                 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_udw(entry));
 889         }
 890
 891         /* The last entry in the LUT is to be programmed in GCMAX */
 892         entry = &lut[256 * 8 * 128];
 893         icl_load_gcmax(crtc_state, entry);
 894         ivb_load_lut_ext_max(crtc);
 895 }
 896
 897 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 898 {
 899         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 900         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 901
 902         if (crtc_state->base.degamma_lut)
 903                 glk_load_degamma_lut(crtc_state);
 904
 905         switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
 906         case GAMMA_MODE_MODE_8BIT:
 907                 i9xx_load_luts(crtc_state);
 908                 break;
 909         case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 910                 icl_program_gamma_superfine_segment(crtc_state);
 911                 icl_program_gamma_multi_segment(crtc_state);
 912                 break;
 913         default:
 914                 bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 915                 ivb_load_lut_ext_max(crtc);
 916         }
 917 }
 918
 919 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
 920 {
 921         return drm_color_lut_extract(color->green, 14) << 16 |
 922                 drm_color_lut_extract(color->blue, 14);
 923 }
 924
 925 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
 926 {
 927         return drm_color_lut_extract(color->red, 14);
 928 }
 929
 930 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
 931                                  const struct drm_property_blob *blob)
 932 {
 933         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 934         const struct drm_color_lut *lut = blob->data;
 935         int i, lut_size = drm_color_lut_size(blob);
 936         enum pipe pipe = crtc->pipe;
 937
 938         for (i = 0; i < lut_size; i++) {
 939                 I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0),
 940                            chv_cgm_degamma_ldw(&lut[i]));
 941                 I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1),
 942                            chv_cgm_degamma_udw(&lut[i]));
 943         }
 944 }
 945
 946 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
 947 {
 948         return drm_color_lut_extract(color->green, 10) << 16 |
 949                 drm_color_lut_extract(color->blue, 10);
 950 }
 951
 952 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
 953 {
 954         return drm_color_lut_extract(color->red, 10);
 955 }
 956
 957 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 958                                const struct drm_property_blob *blob)
 959 {
 960         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 961         const struct drm_color_lut *lut = blob->data;
 962         int i, lut_size = drm_color_lut_size(blob);
 963         enum pipe pipe = crtc->pipe;
 964
 965         for (i = 0; i < lut_size; i++) {
 966                 I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0),
 967                            chv_cgm_gamma_ldw(&lut[i]));
 968                 I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1),
 969                            chv_cgm_gamma_udw(&lut[i]));
 970         }
 971 }
 972
 973 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 974 {
 975         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 976         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
 977         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
 978
 979         cherryview_load_csc_matrix(crtc_state);
 980
 981         if (crtc_state_is_legacy_gamma(crtc_state)) {
 982                 i9xx_load_luts(crtc_state);
 983                 return;
 984         }
 985
 986         if (degamma_lut)
 987                 chv_load_cgm_degamma(crtc, degamma_lut);
 988
 989         if (gamma_lut)
 990                 chv_load_cgm_gamma(crtc, gamma_lut);
 991 }
 992
 993 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 994 {
 995         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 996
 997         dev_priv->display.load_luts(crtc_state);
 998 }
 999
1000 void intel_color_commit(const struct intel_crtc_state *crtc_state)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1003
1004         dev_priv->display.color_commit(crtc_state);
1005 }
1006
1007 int intel_color_check(struct intel_crtc_state *crtc_state)
1008 {
1009         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1010
1011         return dev_priv->display.color_check(crtc_state);
1012 }
1013
1014 void intel_color_get_config(struct intel_crtc_state *crtc_state)
1015 {
1016         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1017
1018         if (dev_priv->display.read_luts)
1019                 dev_priv->display.read_luts(crtc_state);
1020 }
1021
1022 static bool need_plane_update(struct intel_plane *plane,
1023                               const struct intel_crtc_state *crtc_state)
1024 {
1025         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1026
1027         /*
1028          * On pre-SKL the pipe gamma enable and pipe csc enable for
1029          * the pipe bottom color are configured via the primary plane.
1030          * We have to reconfigure that even if the plane is inactive.
1031          */
1032         return crtc_state->active_planes & BIT(plane->id) ||
1033                 (INTEL_GEN(dev_priv) < 9 &&
1034                  plane->id == PLANE_PRIMARY);
1035 }
1036
1037 static int
1038 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1039 {
1040         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1041         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1042         struct intel_atomic_state *state =
1043                 to_intel_atomic_state(new_crtc_state->base.state);
1044         const struct intel_crtc_state *old_crtc_state =
1045                 intel_atomic_get_old_crtc_state(state, crtc);
1046         struct intel_plane *plane;
1047
1048         if (!new_crtc_state->base.active ||
1049             drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
1050                 return 0;
1051
1052         if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1053             new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1054                 return 0;
1055
1056         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
1057                 struct intel_plane_state *plane_state;
1058
1059                 if (!need_plane_update(plane, new_crtc_state))
1060                         continue;
1061
1062                 plane_state = intel_atomic_get_plane_state(state, plane);
1063                 if (IS_ERR(plane_state))
1064                         return PTR_ERR(plane_state);
1065
1066                 new_crtc_state->update_planes |= BIT(plane->id);
1067         }
1068
1069         return 0;
1070 }
1071
1072 static int check_lut_size(const struct drm_property_blob *lut, int expected)
1073 {
1074         int len;
1075
1076         if (!lut)
1077                 return 0;
1078
1079         len = drm_color_lut_size(lut);
1080         if (len != expected) {
1081                 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1082                               len, expected);
1083                 return -EINVAL;
1084         }
1085
1086         return 0;
1087 }
1088
1089 static int check_luts(const struct intel_crtc_state *crtc_state)
1090 {
1091         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1092         const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
1093         const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
1094         int gamma_length, degamma_length;
1095         u32 gamma_tests, degamma_tests;
1096
1097         /* Always allow legacy gamma LUT with no further checking. */
1098         if (crtc_state_is_legacy_gamma(crtc_state))
1099                 return 0;
1100
1101         /* C8 relies on its palette being stored in the legacy LUT */
1102         if (crtc_state->c8_planes) {
1103                 DRM_DEBUG_KMS("C8 pixelformat requires the legacy LUT\n");
1104                 return -EINVAL;
1105         }
1106
1107         degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1108         gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1109         degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1110         gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1111
1112         if (check_lut_size(degamma_lut, degamma_length) ||
1113             check_lut_size(gamma_lut, gamma_length))
1114                 return -EINVAL;
1115
1116         if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1117             drm_color_lut_check(gamma_lut, gamma_tests))
1118                 return -EINVAL;
1119
1120         return 0;
1121 }
1122
1123 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1124 {
1125         if (!crtc_state->gamma_enable ||
1126             crtc_state_is_legacy_gamma(crtc_state))
1127                 return GAMMA_MODE_MODE_8BIT;
1128         else
1129                 return GAMMA_MODE_MODE_10BIT; /* i965+ only */
1130 }
1131
1132 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1133 {
1134         int ret;
1135
1136         ret = check_luts(crtc_state);
1137         if (ret)
1138                 return ret;
1139
1140         crtc_state->gamma_enable =
1141                 crtc_state->base.gamma_lut &&
1142                 !crtc_state->c8_planes;
1143
1144         crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
1145
1146         ret = intel_color_add_affected_planes(crtc_state);
1147         if (ret)
1148                 return ret;
1149
1150         return 0;
1151 }
1152
1153 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
1154 {
1155         u32 cgm_mode = 0;
1156
1157         if (crtc_state_is_legacy_gamma(crtc_state))
1158                 return 0;
1159
1160         if (crtc_state->base.degamma_lut)
1161                 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
1162         if (crtc_state->base.ctm)
1163                 cgm_mode |= CGM_PIPE_MODE_CSC;
1164         if (crtc_state->base.gamma_lut)
1165                 cgm_mode |= CGM_PIPE_MODE_GAMMA;
1166
1167         return cgm_mode;
1168 }
1169
1170 /*
1171  * CHV color pipeline:
1172  * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
1173  * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
1174  *
1175  * We always bypass the WGC csc and use the CGM csc
1176  * instead since it has degamma and better precision.
1177  */
1178 static int chv_color_check(struct intel_crtc_state *crtc_state)
1179 {
1180         int ret;
1181
1182         ret = check_luts(crtc_state);
1183         if (ret)
1184                 return ret;
1185
1186         /*
1187          * Pipe gamma will be used only for the legacy LUT.
1188          * Otherwise we bypass it and use the CGM gamma instead.
1189          */
1190         crtc_state->gamma_enable =
1191                 crtc_state_is_legacy_gamma(crtc_state) &&
1192                 !crtc_state->c8_planes;
1193
1194         crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
1195
1196         crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
1197
1198         ret = intel_color_add_affected_planes(crtc_state);
1199         if (ret)
1200                 return ret;
1201
1202         return 0;
1203 }
1204
1205 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
1206 {
1207         if (!crtc_state->gamma_enable ||
1208             crtc_state_is_legacy_gamma(crtc_state))
1209                 return GAMMA_MODE_MODE_8BIT;
1210         else
1211                 return GAMMA_MODE_MODE_10BIT;
1212 }
1213
1214 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
1215 {
1216         /*
1217          * CSC comes after the LUT in RGB->YCbCr mode.
1218          * RGB->YCbCr needs the limited range offsets added to
1219          * the output. RGB limited range output is handled by
1220          * the hw automagically elsewhere.
1221          */
1222         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1223                 return CSC_BLACK_SCREEN_OFFSET;
1224
1225         return CSC_MODE_YUV_TO_RGB |
1226                 CSC_POSITION_BEFORE_GAMMA;
1227 }
1228
1229 static int ilk_color_check(struct intel_crtc_state *crtc_state)
1230 {
1231         int ret;
1232
1233         ret = check_luts(crtc_state);
1234         if (ret)
1235                 return ret;
1236
1237         crtc_state->gamma_enable =
1238                 crtc_state->base.gamma_lut &&
1239                 !crtc_state->c8_planes;
1240
1241         /*
1242          * We don't expose the ctm on ilk/snb currently, also RGB
1243          * limited range output is handled by the hw automagically.
1244          */
1245         crtc_state->csc_enable =
1246                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
1247
1248         crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
1249
1250         crtc_state->csc_mode = ilk_csc_mode(crtc_state);
1251
1252         ret = intel_color_add_affected_planes(crtc_state);
1253         if (ret)
1254                 return ret;
1255
1256         return 0;
1257 }
1258
1259 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
1260 {
1261         if (!crtc_state->gamma_enable ||
1262             crtc_state_is_legacy_gamma(crtc_state))
1263                 return GAMMA_MODE_MODE_8BIT;
1264         else if (crtc_state->base.gamma_lut &&
1265                  crtc_state->base.degamma_lut)
1266                 return GAMMA_MODE_MODE_SPLIT;
1267         else
1268                 return GAMMA_MODE_MODE_10BIT;
1269 }
1270
1271 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
1272 {
1273         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1274
1275         /*
1276          * CSC comes after the LUT in degamma, RGB->YCbCr,
1277          * and RGB full->limited range mode.
1278          */
1279         if (crtc_state->base.degamma_lut ||
1280             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1281             limited_color_range)
1282                 return 0;
1283
1284         return CSC_POSITION_BEFORE_GAMMA;
1285 }
1286
1287 static int ivb_color_check(struct intel_crtc_state *crtc_state)
1288 {
1289         bool limited_color_range = ilk_csc_limited_range(crtc_state);
1290         int ret;
1291
1292         ret = check_luts(crtc_state);
1293         if (ret)
1294                 return ret;
1295
1296         crtc_state->gamma_enable =
1297                 (crtc_state->base.gamma_lut ||
1298                  crtc_state->base.degamma_lut) &&
1299                 !crtc_state->c8_planes;
1300
1301         crtc_state->csc_enable =
1302                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1303                 crtc_state->base.ctm || limited_color_range;
1304
1305         crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
1306
1307         crtc_state->csc_mode = ivb_csc_mode(crtc_state);
1308
1309         ret = intel_color_add_affected_planes(crtc_state);
1310         if (ret)
1311                 return ret;
1312
1313         return 0;
1314 }
1315
1316 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
1317 {
1318         if (!crtc_state->gamma_enable ||
1319             crtc_state_is_legacy_gamma(crtc_state))
1320                 return GAMMA_MODE_MODE_8BIT;
1321         else
1322                 return GAMMA_MODE_MODE_10BIT;
1323 }
1324
1325 static int glk_color_check(struct intel_crtc_state *crtc_state)
1326 {
1327         int ret;
1328
1329         ret = check_luts(crtc_state);
1330         if (ret)
1331                 return ret;
1332
1333         crtc_state->gamma_enable =
1334                 crtc_state->base.gamma_lut &&
1335                 !crtc_state->c8_planes;
1336
1337         /* On GLK+ degamma LUT is controlled by csc_enable */
1338         crtc_state->csc_enable =
1339                 crtc_state->base.degamma_lut ||
1340                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1341                 crtc_state->base.ctm || crtc_state->limited_color_range;
1342
1343         crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
1344
1345         crtc_state->csc_mode = 0;
1346
1347         ret = intel_color_add_affected_planes(crtc_state);
1348         if (ret)
1349                 return ret;
1350
1351         return 0;
1352 }
1353
1354 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
1355 {
1356         u32 gamma_mode = 0;
1357
1358         if (crtc_state->base.degamma_lut)
1359                 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
1360
1361         if (crtc_state->base.gamma_lut &&
1362             !crtc_state->c8_planes)
1363                 gamma_mode |= POST_CSC_GAMMA_ENABLE;
1364
1365         if (!crtc_state->base.gamma_lut ||
1366             crtc_state_is_legacy_gamma(crtc_state))
1367                 gamma_mode |= GAMMA_MODE_MODE_8BIT;
1368         else
1369                 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
1370
1371         return gamma_mode;
1372 }
1373
1374 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
1375 {
1376         u32 csc_mode = 0;
1377
1378         if (crtc_state->base.ctm)
1379                 csc_mode |= ICL_CSC_ENABLE;
1380
1381         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
1382             crtc_state->limited_color_range)
1383                 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
1384
1385         return csc_mode;
1386 }
1387
1388 static int icl_color_check(struct intel_crtc_state *crtc_state)
1389 {
1390         int ret;
1391
1392         ret = check_luts(crtc_state);
1393         if (ret)
1394                 return ret;
1395
1396         crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
1397
1398         crtc_state->csc_mode = icl_csc_mode(crtc_state);
1399
1400         return 0;
1401 }
1402
1403 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
1404 {
1405         switch (crtc_state->gamma_mode) {
1406         case GAMMA_MODE_MODE_8BIT:
1407                 return 8;
1408         case GAMMA_MODE_MODE_10BIT:
1409                 return 16;
1410         default:
1411                 MISSING_CASE(crtc_state->gamma_mode);
1412                 return 0;
1413         }
1414 }
1415
1416 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
1417 {
1418         if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
1419                 return 0;
1420
1421         switch (crtc_state->gamma_mode) {
1422         case GAMMA_MODE_MODE_8BIT:
1423                 return 8;
1424         case GAMMA_MODE_MODE_10BIT:
1425                 return 10;
1426         default:
1427                 MISSING_CASE(crtc_state->gamma_mode);
1428                 return 0;
1429         }
1430 }
1431
1432 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
1433 {
1434         if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1435                 return 10;
1436         else
1437                 return i9xx_gamma_precision(crtc_state);
1438 }
1439
1440 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
1441 {
1442         switch (crtc_state->gamma_mode) {
1443         case GAMMA_MODE_MODE_8BIT:
1444                 return 8;
1445         case GAMMA_MODE_MODE_10BIT:
1446                 return 10;
1447         default:
1448                 MISSING_CASE(crtc_state->gamma_mode);
1449                 return 0;
1450         }
1451 }
1452
1453 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
1454 {
1455         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1456         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1457
1458         if (!crtc_state->gamma_enable)
1459                 return 0;
1460
1461         if (HAS_GMCH(dev_priv)) {
1462                 if (IS_CHERRYVIEW(dev_priv))
1463                         return chv_gamma_precision(crtc_state);
1464                 else
1465                         return i9xx_gamma_precision(crtc_state);
1466         } else {
1467                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
1468                         return glk_gamma_precision(crtc_state);
1469                 else if (IS_IRONLAKE(dev_priv))
1470                         return ilk_gamma_precision(crtc_state);
1471         }
1472
1473         return 0;
1474 }
1475
1476 static bool err_check(struct drm_color_lut *lut1,
1477                       struct drm_color_lut *lut2, u32 err)
1478 {
1479         return ((abs((long)lut2->red - lut1->red)) <= err) &&
1480                 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
1481                 ((abs((long)lut2->green - lut1->green)) <= err);
1482 }
1483
1484 static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
1485                                         struct drm_color_lut *lut2,
1486                                         int lut_size, u32 err)
1487 {
1488         int i;
1489
1490         for (i = 0; i < lut_size; i++) {
1491                 if (!err_check(&lut1[i], &lut2[i], err))
1492                         return false;
1493         }
1494
1495         return true;
1496 }
1497
1498 bool intel_color_lut_equal(struct drm_property_blob *blob1,
1499                            struct drm_property_blob *blob2,
1500                            u32 gamma_mode, u32 bit_precision)
1501 {
1502         struct drm_color_lut *lut1, *lut2;
1503         int lut_size1, lut_size2;
1504         u32 err;
1505
1506         if (!blob1 != !blob2)
1507                 return false;
1508
1509         if (!blob1)
1510                 return true;
1511
1512         lut_size1 = drm_color_lut_size(blob1);
1513         lut_size2 = drm_color_lut_size(blob2);
1514
1515         /* check sw and hw lut size */
1516         switch (gamma_mode) {
1517         case GAMMA_MODE_MODE_8BIT:
1518         case GAMMA_MODE_MODE_10BIT:
1519                 if (lut_size1 != lut_size2)
1520                         return false;
1521                 break;
1522         default:
1523                 MISSING_CASE(gamma_mode);
1524                         return false;
1525         }
1526
1527         lut1 = blob1->data;
1528         lut2 = blob2->data;
1529
1530         err = 0xffff >> bit_precision;
1531
1532         /* check sw and hw lut entry to be equal */
1533         switch (gamma_mode) {
1534         case GAMMA_MODE_MODE_8BIT:
1535         case GAMMA_MODE_MODE_10BIT:
1536                 if (!intel_color_lut_entry_equal(lut1, lut2,
1537                                                  lut_size2, err))
1538                         return false;
1539                 break;
1540         default:
1541                 MISSING_CASE(gamma_mode);
1542                         return false;
1543         }
1544
1545         return true;
1546 }
1547
1548 /* convert hw value with given bit_precision to lut property val */
1549 static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
1550 {
1551         u32 max = 0xffff >> (16 - bit_precision);
1552
1553         val = clamp_val(val, 0, max);
1554
1555         if (bit_precision < 16)
1556                 val <<= 16 - bit_precision;
1557
1558         return val;
1559 }
1560
1561 static struct drm_property_blob *
1562 i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
1563 {
1564         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1565         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566         enum pipe pipe = crtc->pipe;
1567         struct drm_property_blob *blob;
1568         struct drm_color_lut *blob_data;
1569         u32 i, val;
1570
1571         blob = drm_property_create_blob(&dev_priv->drm,
1572                                         sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
1573                                         NULL);
1574         if (IS_ERR(blob))
1575                 return NULL;
1576
1577         blob_data = blob->data;
1578
1579         for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
1580                 if (HAS_GMCH(dev_priv))
1581                         val = I915_READ(PALETTE(pipe, i));
1582                 else
1583                         val = I915_READ(LGC_PALETTE(pipe, i));
1584
1585                 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1586                                                         LGC_PALETTE_RED_MASK, val), 8);
1587                 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1588                                                           LGC_PALETTE_GREEN_MASK, val), 8);
1589                 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1590                                                          LGC_PALETTE_BLUE_MASK, val), 8);
1591         }
1592
1593         return blob;
1594 }
1595
1596 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
1597 {
1598         crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1599 }
1600
1601 static struct drm_property_blob *
1602 i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
1603 {
1604         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1605         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1606         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1607         enum pipe pipe = crtc->pipe;
1608         struct drm_property_blob *blob;
1609         struct drm_color_lut *blob_data;
1610         u32 i, val1, val2;
1611
1612         blob = drm_property_create_blob(&dev_priv->drm,
1613                                         sizeof(struct drm_color_lut) * lut_size,
1614                                         NULL);
1615         if (IS_ERR(blob))
1616                 return NULL;
1617
1618         blob_data = blob->data;
1619
1620         for (i = 0; i < lut_size - 1; i++) {
1621                 val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
1622                 val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
1623
1624                 blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
1625                                                  REG_FIELD_GET(PALETTE_RED_MASK, val1);
1626                 blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
1627                                                    REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
1628                 blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
1629                                                   REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
1630         }
1631
1632         blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1633                                          I915_READ(PIPEGCMAX(pipe, 0)));
1634         blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1635                                            I915_READ(PIPEGCMAX(pipe, 1)));
1636         blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
1637                                           I915_READ(PIPEGCMAX(pipe, 2)));
1638
1639         return blob;
1640 }
1641
1642 static void i965_read_luts(struct intel_crtc_state *crtc_state)
1643 {
1644         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1645                 crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1646         else
1647                 crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
1648 }
1649
1650 static struct drm_property_blob *
1651 chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
1652 {
1653         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1654         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1655         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1656         enum pipe pipe = crtc->pipe;
1657         struct drm_property_blob *blob;
1658         struct drm_color_lut *blob_data;
1659         u32 i, val;
1660
1661         blob = drm_property_create_blob(&dev_priv->drm,
1662                                         sizeof(struct drm_color_lut) * lut_size,
1663                                         NULL);
1664         if (IS_ERR(blob))
1665                 return NULL;
1666
1667         blob_data = blob->data;
1668
1669         for (i = 0; i < lut_size; i++) {
1670                 val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0));
1671                 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1672                                                           CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
1673                 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1674                                                          CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
1675
1676                 val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1));
1677                 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1678                                                         CGM_PIPE_GAMMA_RED_MASK, val), 10);
1679         }
1680
1681         return blob;
1682 }
1683
1684 static void chv_read_luts(struct intel_crtc_state *crtc_state)
1685 {
1686         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1687                 crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1688         else
1689                 crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
1690 }
1691
1692 static struct drm_property_blob *
1693 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
1694 {
1695         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1696         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1697         u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1698         enum pipe pipe = crtc->pipe;
1699         struct drm_property_blob *blob;
1700         struct drm_color_lut *blob_data;
1701         u32 i, val;
1702
1703         blob = drm_property_create_blob(&dev_priv->drm,
1704                                         sizeof(struct drm_color_lut) * lut_size,
1705                                         NULL);
1706         if (IS_ERR(blob))
1707                 return NULL;
1708
1709         blob_data = blob->data;
1710
1711         for (i = 0; i < lut_size; i++) {
1712                 val = I915_READ(PREC_PALETTE(pipe, i));
1713
1714                 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1715                                                         PREC_PALETTE_RED_MASK, val), 10);
1716                 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1717                                                           PREC_PALETTE_GREEN_MASK, val), 10);
1718                 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1719                                                          PREC_PALETTE_BLUE_MASK, val), 10);
1720         }
1721
1722         return blob;
1723 }
1724
1725 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
1726 {
1727         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1728                 crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1729         else
1730                 crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
1731 }
1732
1733 static struct drm_property_blob *
1734 glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
1735 {
1736         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1737         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1738         int hw_lut_size = ivb_lut_10_size(prec_index);
1739         enum pipe pipe = crtc->pipe;
1740         struct drm_property_blob *blob;
1741         struct drm_color_lut *blob_data;
1742         u32 i, val;
1743
1744         blob = drm_property_create_blob(&dev_priv->drm,
1745                                         sizeof(struct drm_color_lut) * hw_lut_size,
1746                                         NULL);
1747         if (IS_ERR(blob))
1748                 return NULL;
1749
1750         blob_data = blob->data;
1751
1752         I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
1753                    PAL_PREC_AUTO_INCREMENT);
1754
1755         for (i = 0; i < hw_lut_size; i++) {
1756                 val = I915_READ(PREC_PAL_DATA(pipe));
1757
1758                 blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
1759                                                         PREC_PAL_DATA_RED_MASK, val), 10);
1760                 blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
1761                                                         PREC_PAL_DATA_GREEN_MASK, val), 10);
1762                 blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
1763                                                         PREC_PAL_DATA_BLUE_MASK, val), 10);
1764         }
1765
1766         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
1767
1768         return blob;
1769 }
1770
1771 static void glk_read_luts(struct intel_crtc_state *crtc_state)
1772 {
1773         if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
1774                 crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
1775         else
1776                 crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
1777 }
1778
1779 void intel_color_init(struct intel_crtc *crtc)
1780 {
1781         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1782         bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
1783
1784         drm_mode_crtc_set_gamma_size(&crtc->base, 256);
1785
1786         if (HAS_GMCH(dev_priv)) {
1787                 if (IS_CHERRYVIEW(dev_priv)) {
1788                         dev_priv->display.color_check = chv_color_check;
1789                         dev_priv->display.color_commit = i9xx_color_commit;
1790                         dev_priv->display.load_luts = chv_load_luts;
1791                         dev_priv->display.read_luts = chv_read_luts;
1792                 } else if (INTEL_GEN(dev_priv) >= 4) {
1793                         dev_priv->display.color_check = i9xx_color_check;
1794                         dev_priv->display.color_commit = i9xx_color_commit;
1795                         dev_priv->display.load_luts = i965_load_luts;
1796                         dev_priv->display.read_luts = i965_read_luts;
1797                 } else {
1798                         dev_priv->display.color_check = i9xx_color_check;
1799                         dev_priv->display.color_commit = i9xx_color_commit;
1800                         dev_priv->display.load_luts = i9xx_load_luts;
1801                         dev_priv->display.read_luts = i9xx_read_luts;
1802                 }
1803         } else {
1804                 if (INTEL_GEN(dev_priv) >= 11)
1805                         dev_priv->display.color_check = icl_color_check;
1806                 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1807                         dev_priv->display.color_check = glk_color_check;
1808                 else if (INTEL_GEN(dev_priv) >= 7)
1809                         dev_priv->display.color_check = ivb_color_check;
1810                 else
1811                         dev_priv->display.color_check = ilk_color_check;
1812
1813                 if (INTEL_GEN(dev_priv) >= 9)
1814                         dev_priv->display.color_commit = skl_color_commit;
1815                 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1816                         dev_priv->display.color_commit = hsw_color_commit;
1817                 else
1818                         dev_priv->display.color_commit = ilk_color_commit;
1819
1820                 if (INTEL_GEN(dev_priv) >= 11) {
1821                         dev_priv->display.load_luts = icl_load_luts;
1822                 } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1823                         dev_priv->display.load_luts = glk_load_luts;
1824                         dev_priv->display.read_luts = glk_read_luts;
1825                 } else if (INTEL_GEN(dev_priv) >= 8) {
1826                         dev_priv->display.load_luts = bdw_load_luts;
1827                 } else if (INTEL_GEN(dev_priv) >= 7) {
1828                         dev_priv->display.load_luts = ivb_load_luts;
1829                 } else {
1830                         dev_priv->display.load_luts = ilk_load_luts;
1831                         dev_priv->display.read_luts = ilk_read_luts;
1832                 }
1833         }
1834
1835         drm_crtc_enable_color_mgmt(&crtc->base,
1836                                    INTEL_INFO(dev_priv)->color.degamma_lut_size,
1837                                    has_ctm,
1838                                    INTEL_INFO(dev_priv)->color.gamma_lut_size);
1839 }