drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_link_training.h"
  38 #include "intel_dpio_phy.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_gmbus.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_hdmi.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_lspcon.h"
  46 #include "intel_panel.h"
  47 #include "intel_psr.h"
  48 #include "intel_sprite.h"
  49 #include "intel_tc.h"
  50 #include "intel_vdsc.h"
  51
  52 struct ddi_buf_trans {
  53         u32 trans1;     /* balance leg enable, de-emph level */
  54         u32 trans2;     /* vref sel, vswing */
  55         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  56 };
  57
  58 static const u8 index_to_dp_signal_levels[] = {
  59         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  60         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  61         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  62         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  63         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  64         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  65         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  66         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  67         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  68         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  69 };
  70
  71 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  72  * them for both DP and FDI transports, allowing those ports to
  73  * automatically adapt to HDMI connections as well
  74  */
  75 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  76         { 0x00FFFFFF, 0x0006000E, 0x0 },
  77         { 0x00D75FFF, 0x0005000A, 0x0 },
  78         { 0x00C30FFF, 0x00040006, 0x0 },
  79         { 0x80AAAFFF, 0x000B0000, 0x0 },
  80         { 0x00FFFFFF, 0x0005000A, 0x0 },
  81         { 0x00D75FFF, 0x000C0004, 0x0 },
  82         { 0x80C30FFF, 0x000B0000, 0x0 },
  83         { 0x00FFFFFF, 0x00040006, 0x0 },
  84         { 0x80D75FFF, 0x000B0000, 0x0 },
  85 };
  86
  87 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  88         { 0x00FFFFFF, 0x0007000E, 0x0 },
  89         { 0x00D75FFF, 0x000F000A, 0x0 },
  90         { 0x00C30FFF, 0x00060006, 0x0 },
  91         { 0x00AAAFFF, 0x001E0000, 0x0 },
  92         { 0x00FFFFFF, 0x000F000A, 0x0 },
  93         { 0x00D75FFF, 0x00160004, 0x0 },
  94         { 0x00C30FFF, 0x001E0000, 0x0 },
  95         { 0x00FFFFFF, 0x00060006, 0x0 },
  96         { 0x00D75FFF, 0x001E0000, 0x0 },
  97 };
  98
  99 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 100                                         /* Idx  NT mV d T mV d  db      */
 101         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 102         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 103         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 104         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 105         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 106         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 107         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 108         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 109         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 110         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 111         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 112         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 113 };
 114
 115 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 116         { 0x00FFFFFF, 0x00000012, 0x0 },
 117         { 0x00EBAFFF, 0x00020011, 0x0 },
 118         { 0x00C71FFF, 0x0006000F, 0x0 },
 119         { 0x00AAAFFF, 0x000E000A, 0x0 },
 120         { 0x00FFFFFF, 0x00020011, 0x0 },
 121         { 0x00DB6FFF, 0x0005000F, 0x0 },
 122         { 0x00BEEFFF, 0x000A000C, 0x0 },
 123         { 0x00FFFFFF, 0x0005000F, 0x0 },
 124         { 0x00DB6FFF, 0x000A000C, 0x0 },
 125 };
 126
 127 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 128         { 0x00FFFFFF, 0x0007000E, 0x0 },
 129         { 0x00D75FFF, 0x000E000A, 0x0 },
 130         { 0x00BEFFFF, 0x00140006, 0x0 },
 131         { 0x80B2CFFF, 0x001B0002, 0x0 },
 132         { 0x00FFFFFF, 0x000E000A, 0x0 },
 133         { 0x00DB6FFF, 0x00160005, 0x0 },
 134         { 0x80C71FFF, 0x001A0002, 0x0 },
 135         { 0x00F7DFFF, 0x00180004, 0x0 },
 136         { 0x80D75FFF, 0x001B0002, 0x0 },
 137 };
 138
 139 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 140         { 0x00FFFFFF, 0x0001000E, 0x0 },
 141         { 0x00D75FFF, 0x0004000A, 0x0 },
 142         { 0x00C30FFF, 0x00070006, 0x0 },
 143         { 0x00AAAFFF, 0x000C0000, 0x0 },
 144         { 0x00FFFFFF, 0x0004000A, 0x0 },
 145         { 0x00D75FFF, 0x00090004, 0x0 },
 146         { 0x00C30FFF, 0x000C0000, 0x0 },
 147         { 0x00FFFFFF, 0x00070006, 0x0 },
 148         { 0x00D75FFF, 0x000C0000, 0x0 },
 149 };
 150
 151 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 152                                         /* Idx  NT mV d T mV df db      */
 153         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 154         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 155         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 156         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 157         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 158         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 159         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 160         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 161         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 162         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 163 };
 164
 165 /* Skylake H and S */
 166 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 167         { 0x00002016, 0x000000A0, 0x0 },
 168         { 0x00005012, 0x0000009B, 0x0 },
 169         { 0x00007011, 0x00000088, 0x0 },
 170         { 0x80009010, 0x000000C0, 0x1 },
 171         { 0x00002016, 0x0000009B, 0x0 },
 172         { 0x00005012, 0x00000088, 0x0 },
 173         { 0x80007011, 0x000000C0, 0x1 },
 174         { 0x00002016, 0x000000DF, 0x0 },
 175         { 0x80005012, 0x000000C0, 0x1 },
 176 };
 177
 178 /* Skylake U */
 179 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 180         { 0x0000201B, 0x000000A2, 0x0 },
 181         { 0x00005012, 0x00000088, 0x0 },
 182         { 0x80007011, 0x000000CD, 0x1 },
 183         { 0x80009010, 0x000000C0, 0x1 },
 184         { 0x0000201B, 0x0000009D, 0x0 },
 185         { 0x80005012, 0x000000C0, 0x1 },
 186         { 0x80007011, 0x000000C0, 0x1 },
 187         { 0x00002016, 0x00000088, 0x0 },
 188         { 0x80005012, 0x000000C0, 0x1 },
 189 };
 190
 191 /* Skylake Y */
 192 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 193         { 0x00000018, 0x000000A2, 0x0 },
 194         { 0x00005012, 0x00000088, 0x0 },
 195         { 0x80007011, 0x000000CD, 0x3 },
 196         { 0x80009010, 0x000000C0, 0x3 },
 197         { 0x00000018, 0x0000009D, 0x0 },
 198         { 0x80005012, 0x000000C0, 0x3 },
 199         { 0x80007011, 0x000000C0, 0x3 },
 200         { 0x00000018, 0x00000088, 0x0 },
 201         { 0x80005012, 0x000000C0, 0x3 },
 202 };
 203
 204 /* Kabylake H and S */
 205 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 206         { 0x00002016, 0x000000A0, 0x0 },
 207         { 0x00005012, 0x0000009B, 0x0 },
 208         { 0x00007011, 0x00000088, 0x0 },
 209         { 0x80009010, 0x000000C0, 0x1 },
 210         { 0x00002016, 0x0000009B, 0x0 },
 211         { 0x00005012, 0x00000088, 0x0 },
 212         { 0x80007011, 0x000000C0, 0x1 },
 213         { 0x00002016, 0x00000097, 0x0 },
 214         { 0x80005012, 0x000000C0, 0x1 },
 215 };
 216
 217 /* Kabylake U */
 218 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 219         { 0x0000201B, 0x000000A1, 0x0 },
 220         { 0x00005012, 0x00000088, 0x0 },
 221         { 0x80007011, 0x000000CD, 0x3 },
 222         { 0x80009010, 0x000000C0, 0x3 },
 223         { 0x0000201B, 0x0000009D, 0x0 },
 224         { 0x80005012, 0x000000C0, 0x3 },
 225         { 0x80007011, 0x000000C0, 0x3 },
 226         { 0x00002016, 0x0000004F, 0x0 },
 227         { 0x80005012, 0x000000C0, 0x3 },
 228 };
 229
 230 /* Kabylake Y */
 231 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 232         { 0x00001017, 0x000000A1, 0x0 },
 233         { 0x00005012, 0x00000088, 0x0 },
 234         { 0x80007011, 0x000000CD, 0x3 },
 235         { 0x8000800F, 0x000000C0, 0x3 },
 236         { 0x00001017, 0x0000009D, 0x0 },
 237         { 0x80005012, 0x000000C0, 0x3 },
 238         { 0x80007011, 0x000000C0, 0x3 },
 239         { 0x00001017, 0x0000004C, 0x0 },
 240         { 0x80005012, 0x000000C0, 0x3 },
 241 };
 242
 243 /*
 244  * Skylake/Kabylake H and S
 245  * eDP 1.4 low vswing translation parameters
 246  */
 247 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 248         { 0x00000018, 0x000000A8, 0x0 },
 249         { 0x00004013, 0x000000A9, 0x0 },
 250         { 0x00007011, 0x000000A2, 0x0 },
 251         { 0x00009010, 0x0000009C, 0x0 },
 252         { 0x00000018, 0x000000A9, 0x0 },
 253         { 0x00006013, 0x000000A2, 0x0 },
 254         { 0x00007011, 0x000000A6, 0x0 },
 255         { 0x00000018, 0x000000AB, 0x0 },
 256         { 0x00007013, 0x0000009F, 0x0 },
 257         { 0x00000018, 0x000000DF, 0x0 },
 258 };
 259
 260 /*
 261  * Skylake/Kabylake U
 262  * eDP 1.4 low vswing translation parameters
 263  */
 264 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 265         { 0x00000018, 0x000000A8, 0x0 },
 266         { 0x00004013, 0x000000A9, 0x0 },
 267         { 0x00007011, 0x000000A2, 0x0 },
 268         { 0x00009010, 0x0000009C, 0x0 },
 269         { 0x00000018, 0x000000A9, 0x0 },
 270         { 0x00006013, 0x000000A2, 0x0 },
 271         { 0x00007011, 0x000000A6, 0x0 },
 272         { 0x00002016, 0x000000AB, 0x0 },
 273         { 0x00005013, 0x0000009F, 0x0 },
 274         { 0x00000018, 0x000000DF, 0x0 },
 275 };
 276
 277 /*
 278  * Skylake/Kabylake Y
 279  * eDP 1.4 low vswing translation parameters
 280  */
 281 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 282         { 0x00000018, 0x000000A8, 0x0 },
 283         { 0x00004013, 0x000000AB, 0x0 },
 284         { 0x00007011, 0x000000A4, 0x0 },
 285         { 0x00009010, 0x000000DF, 0x0 },
 286         { 0x00000018, 0x000000AA, 0x0 },
 287         { 0x00006013, 0x000000A4, 0x0 },
 288         { 0x00007011, 0x0000009D, 0x0 },
 289         { 0x00000018, 0x000000A0, 0x0 },
 290         { 0x00006012, 0x000000DF, 0x0 },
 291         { 0x00000018, 0x0000008A, 0x0 },
 292 };
 293
 294 /* Skylake/Kabylake U, H and S */
 295 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 296         { 0x00000018, 0x000000AC, 0x0 },
 297         { 0x00005012, 0x0000009D, 0x0 },
 298         { 0x00007011, 0x00000088, 0x0 },
 299         { 0x00000018, 0x000000A1, 0x0 },
 300         { 0x00000018, 0x00000098, 0x0 },
 301         { 0x00004013, 0x00000088, 0x0 },
 302         { 0x80006012, 0x000000CD, 0x1 },
 303         { 0x00000018, 0x000000DF, 0x0 },
 304         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 305         { 0x80003015, 0x000000C0, 0x1 },
 306         { 0x80000018, 0x000000C0, 0x1 },
 307 };
 308
 309 /* Skylake/Kabylake Y */
 310 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 311         { 0x00000018, 0x000000A1, 0x0 },
 312         { 0x00005012, 0x000000DF, 0x0 },
 313         { 0x80007011, 0x000000CB, 0x3 },
 314         { 0x00000018, 0x000000A4, 0x0 },
 315         { 0x00000018, 0x0000009D, 0x0 },
 316         { 0x00004013, 0x00000080, 0x0 },
 317         { 0x80006013, 0x000000C0, 0x3 },
 318         { 0x00000018, 0x0000008A, 0x0 },
 319         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 320         { 0x80003015, 0x000000C0, 0x3 },
 321         { 0x80000018, 0x000000C0, 0x3 },
 322 };
 323
 324 struct bxt_ddi_buf_trans {
 325         u8 margin;      /* swing value */
 326         u8 scale;       /* scale value */
 327         u8 enable;      /* scale enable */
 328         u8 deemphasis;
 329 };
 330
 331 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 332                                         /* Idx  NT mV diff      db  */
 333         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 334         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 335         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 336         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 337         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 338         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 339         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 340         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 341         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 342         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 343 };
 344
 345 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 346                                         /* Idx  NT mV diff      db  */
 347         { 26, 0, 0, 128, },     /* 0:   200             0   */
 348         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 349         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 350         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 351         { 32, 0, 0, 128, },     /* 4:   250             0   */
 352         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 353         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 354         { 43, 0, 0, 128, },     /* 7:   300             0   */
 355         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 356         { 48, 0, 0, 128, },     /* 9:   300             0   */
 357 };
 358
 359 /* BSpec has 2 recommended values - entries 0 and 8.
 360  * Using the entry with higher vswing.
 361  */
 362 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 363                                         /* Idx  NT mV diff      db  */
 364         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 365         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 366         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 367         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 368         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 369         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 370         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 371         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 372         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 373         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 374 };
 375
 376 struct cnl_ddi_buf_trans {
 377         u8 dw2_swing_sel;
 378         u8 dw7_n_scalar;
 379         u8 dw4_cursor_coeff;
 380         u8 dw4_post_cursor_2;
 381         u8 dw4_post_cursor_1;
 382 };
 383
 384 /* Voltage Swing Programming for VccIO 0.85V for DP */
 385 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 386                                                 /* NT mV Trans mV db    */
 387         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 388         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 389         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 390         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 391         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 392         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 393         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 394         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 395         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 396         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 397 };
 398
 399 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 400 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 401                                                 /* NT mV Trans mV db    */
 402         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 403         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 404         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 405         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 406         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 407         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 408         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 409 };
 410
 411 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 412 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 413                                                 /* NT mV Trans mV db    */
 414         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 415         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 416         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 417         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 418         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 419         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 420         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 421         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 422         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 423 };
 424
 425 /* Voltage Swing Programming for VccIO 0.95V for DP */
 426 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 427                                                 /* NT mV Trans mV db    */
 428         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 429         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 430         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 431         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 432         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 433         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 434         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 435         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 436         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 437         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 438 };
 439
 440 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 441 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 442                                                 /* NT mV Trans mV db    */
 443         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 444         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 445         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 446         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 447         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 448         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 449         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 450         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 451         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 452         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 453         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 454 };
 455
 456 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 457 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 458                                                 /* NT mV Trans mV db    */
 459         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 460         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 461         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 462         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 463         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 464         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 465         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 466         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 467         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 468         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 469 };
 470
 471 /* Voltage Swing Programming for VccIO 1.05V for DP */
 472 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 473                                                 /* NT mV Trans mV db    */
 474         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 475         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 476         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 477         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 478         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 479         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 480         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 481         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 482         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 483         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 484 };
 485
 486 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 487 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 488                                                 /* NT mV Trans mV db    */
 489         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 490         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 491         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 492         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 493         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 494         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 495         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 496         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 497         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 498         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 499         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 503 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 504                                                 /* NT mV Trans mV db    */
 505         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 506         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 507         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 508         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 509         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 510         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 511         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 512         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 513         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 514 };
 515
 516 /* icl_combo_phy_ddi_translations */
 517 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 518                                                 /* NT mV Trans mV db    */
 519         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 520         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 521         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 522         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 523         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 524         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 525         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 526         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 527         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 528         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 529 };
 530
 531 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 532                                                 /* NT mV Trans mV db    */
 533         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 534         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 535         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 536         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 537         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 538         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 539         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 540         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 541         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 542         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 543 };
 544
 545 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 546                                                 /* NT mV Trans mV db    */
 547         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 548         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 549         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 550         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 551         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 552         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 553         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 554         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 555         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 556         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 557 };
 558
 559 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 560                                                 /* NT mV Trans mV db    */
 561         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 562         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 563         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 564         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 565         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 566         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 567         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 568 };
 569
 570 struct icl_mg_phy_ddi_buf_trans {
 571         u32 cri_txdeemph_override_5_0;
 572         u32 cri_txdeemph_override_11_6;
 573         u32 cri_txdeemph_override_17_12;
 574 };
 575
 576 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 577                                 /* Voltage swing  pre-emphasis */
 578         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 579         { 0x0, 0x23, 0x08 },    /* 0              1   */
 580         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 581         { 0x0, 0x00, 0x00 },    /* 0              3   */
 582         { 0x0, 0x23, 0x00 },    /* 1              0   */
 583         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 584         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 585         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 586         { 0x0, 0x33, 0x0C },    /* 2              1   */
 587         { 0x0, 0x00, 0x00 },    /* 3              0   */
 588 };
 589
 590 struct tgl_dkl_phy_ddi_buf_trans {
 591         u32 dkl_vswing_control;
 592         u32 dkl_preshoot_control;
 593         u32 dkl_de_emphasis_control;
 594 };
 595
 596 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
 597                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 598         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 599         { 0x5, 0x0, 0x03 },     /* 0    1       400mV           3.5 dB */
 600         { 0x2, 0x0, 0x0b },     /* 0    2       400mV           6 dB */
 601         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 602         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 603         { 0x2, 0x0, 0x03 },     /* 1    1       600mV           3.5 dB */
 604         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 605         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 606         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 607         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 608 };
 609
 610 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
 611                                 /* HDMI Preset  VS      Pre-emph */
 612         { 0x7, 0x0, 0x0 },      /* 1            400mV   0dB */
 613         { 0x6, 0x0, 0x0 },      /* 2            500mV   0dB */
 614         { 0x4, 0x0, 0x0 },      /* 3            650mV   0dB */
 615         { 0x2, 0x0, 0x0 },      /* 4            800mV   0dB */
 616         { 0x0, 0x0, 0x0 },      /* 5            1000mV  0dB */
 617         { 0x0, 0x0, 0x5 },      /* 6            Full    -1.5 dB */
 618         { 0x0, 0x0, 0x6 },      /* 7            Full    -1.8 dB */
 619         { 0x0, 0x0, 0x7 },      /* 8            Full    -2 dB */
 620         { 0x0, 0x0, 0x8 },      /* 9            Full    -2.5 dB */
 621         { 0x0, 0x0, 0xA },      /* 10           Full    -3 dB */
 622 };
 623
 624 static const struct ddi_buf_trans *
 625 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 626 {
 627         if (dev_priv->vbt.edp.low_vswing) {
 628                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 629                 return bdw_ddi_translations_edp;
 630         } else {
 631                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 632                 return bdw_ddi_translations_dp;
 633         }
 634 }
 635
 636 static const struct ddi_buf_trans *
 637 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 638 {
 639         if (IS_SKL_ULX(dev_priv)) {
 640                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 641                 return skl_y_ddi_translations_dp;
 642         } else if (IS_SKL_ULT(dev_priv)) {
 643                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 644                 return skl_u_ddi_translations_dp;
 645         } else {
 646                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 647                 return skl_ddi_translations_dp;
 648         }
 649 }
 650
 651 static const struct ddi_buf_trans *
 652 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 653 {
 654         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 655                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 656                 return kbl_y_ddi_translations_dp;
 657         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 658                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 659                 return kbl_u_ddi_translations_dp;
 660         } else {
 661                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 662                 return kbl_ddi_translations_dp;
 663         }
 664 }
 665
 666 static const struct ddi_buf_trans *
 667 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 668 {
 669         if (dev_priv->vbt.edp.low_vswing) {
 670                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 671                     IS_CFL_ULX(dev_priv)) {
 672                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 673                         return skl_y_ddi_translations_edp;
 674                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 675                            IS_CFL_ULT(dev_priv)) {
 676                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 677                         return skl_u_ddi_translations_edp;
 678                 } else {
 679                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 680                         return skl_ddi_translations_edp;
 681                 }
 682         }
 683
 684         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 685                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 686         else
 687                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 688 }
 689
 690 static const struct ddi_buf_trans *
 691 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 692 {
 693         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 694             IS_CFL_ULX(dev_priv)) {
 695                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 696                 return skl_y_ddi_translations_hdmi;
 697         } else {
 698                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 699                 return skl_ddi_translations_hdmi;
 700         }
 701 }
 702
 703 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 704 {
 705         /* Only DDIA and DDIE can select the 10th register with DP */
 706         if (port == PORT_A || port == PORT_E)
 707                 return min(n_entries, 10);
 708         else
 709                 return min(n_entries, 9);
 710 }
 711
 712 static const struct ddi_buf_trans *
 713 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 714                            enum port port, int *n_entries)
 715 {
 716         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 717                 const struct ddi_buf_trans *ddi_translations =
 718                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 719                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 720                 return ddi_translations;
 721         } else if (IS_SKYLAKE(dev_priv)) {
 722                 const struct ddi_buf_trans *ddi_translations =
 723                         skl_get_buf_trans_dp(dev_priv, n_entries);
 724                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 725                 return ddi_translations;
 726         } else if (IS_BROADWELL(dev_priv)) {
 727                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 728                 return  bdw_ddi_translations_dp;
 729         } else if (IS_HASWELL(dev_priv)) {
 730                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 731                 return hsw_ddi_translations_dp;
 732         }
 733
 734         *n_entries = 0;
 735         return NULL;
 736 }
 737
 738 static const struct ddi_buf_trans *
 739 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 740                             enum port port, int *n_entries)
 741 {
 742         if (IS_GEN9_BC(dev_priv)) {
 743                 const struct ddi_buf_trans *ddi_translations =
 744                         skl_get_buf_trans_edp(dev_priv, n_entries);
 745                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 746                 return ddi_translations;
 747         } else if (IS_BROADWELL(dev_priv)) {
 748                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 749         } else if (IS_HASWELL(dev_priv)) {
 750                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 751                 return hsw_ddi_translations_dp;
 752         }
 753
 754         *n_entries = 0;
 755         return NULL;
 756 }
 757
 758 static const struct ddi_buf_trans *
 759 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 760                             int *n_entries)
 761 {
 762         if (IS_BROADWELL(dev_priv)) {
 763                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 764                 return bdw_ddi_translations_fdi;
 765         } else if (IS_HASWELL(dev_priv)) {
 766                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 767                 return hsw_ddi_translations_fdi;
 768         }
 769
 770         *n_entries = 0;
 771         return NULL;
 772 }
 773
 774 static const struct ddi_buf_trans *
 775 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 776                              int *n_entries)
 777 {
 778         if (IS_GEN9_BC(dev_priv)) {
 779                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 780         } else if (IS_BROADWELL(dev_priv)) {
 781                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 782                 return bdw_ddi_translations_hdmi;
 783         } else if (IS_HASWELL(dev_priv)) {
 784                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 785                 return hsw_ddi_translations_hdmi;
 786         }
 787
 788         *n_entries = 0;
 789         return NULL;
 790 }
 791
 792 static const struct bxt_ddi_buf_trans *
 793 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 794 {
 795         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 796         return bxt_ddi_translations_dp;
 797 }
 798
 799 static const struct bxt_ddi_buf_trans *
 800 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 801 {
 802         if (dev_priv->vbt.edp.low_vswing) {
 803                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 804                 return bxt_ddi_translations_edp;
 805         }
 806
 807         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 808 }
 809
 810 static const struct bxt_ddi_buf_trans *
 811 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 812 {
 813         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 814         return bxt_ddi_translations_hdmi;
 815 }
 816
 817 static const struct cnl_ddi_buf_trans *
 818 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 819 {
 820         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 821
 822         if (voltage == VOLTAGE_INFO_0_85V) {
 823                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 824                 return cnl_ddi_translations_hdmi_0_85V;
 825         } else if (voltage == VOLTAGE_INFO_0_95V) {
 826                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 827                 return cnl_ddi_translations_hdmi_0_95V;
 828         } else if (voltage == VOLTAGE_INFO_1_05V) {
 829                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 830                 return cnl_ddi_translations_hdmi_1_05V;
 831         } else {
 832                 *n_entries = 1; /* shut up gcc */
 833                 MISSING_CASE(voltage);
 834         }
 835         return NULL;
 836 }
 837
 838 static const struct cnl_ddi_buf_trans *
 839 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 840 {
 841         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 842
 843         if (voltage == VOLTAGE_INFO_0_85V) {
 844                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 845                 return cnl_ddi_translations_dp_0_85V;
 846         } else if (voltage == VOLTAGE_INFO_0_95V) {
 847                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 848                 return cnl_ddi_translations_dp_0_95V;
 849         } else if (voltage == VOLTAGE_INFO_1_05V) {
 850                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 851                 return cnl_ddi_translations_dp_1_05V;
 852         } else {
 853                 *n_entries = 1; /* shut up gcc */
 854                 MISSING_CASE(voltage);
 855         }
 856         return NULL;
 857 }
 858
 859 static const struct cnl_ddi_buf_trans *
 860 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 861 {
 862         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 863
 864         if (dev_priv->vbt.edp.low_vswing) {
 865                 if (voltage == VOLTAGE_INFO_0_85V) {
 866                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 867                         return cnl_ddi_translations_edp_0_85V;
 868                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 869                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 870                         return cnl_ddi_translations_edp_0_95V;
 871                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 872                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 873                         return cnl_ddi_translations_edp_1_05V;
 874                 } else {
 875                         *n_entries = 1; /* shut up gcc */
 876                         MISSING_CASE(voltage);
 877                 }
 878                 return NULL;
 879         } else {
 880                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 881         }
 882 }
 883
 884 static const struct cnl_ddi_buf_trans *
 885 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 886                         int *n_entries)
 887 {
 888         if (type == INTEL_OUTPUT_HDMI) {
 889                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 890                 return icl_combo_phy_ddi_translations_hdmi;
 891         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 892                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 893                 return icl_combo_phy_ddi_translations_edp_hbr3;
 894         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 895                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 896                 return icl_combo_phy_ddi_translations_edp_hbr2;
 897         }
 898
 899         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 900         return icl_combo_phy_ddi_translations_dp_hbr2;
 901 }
 902
 903 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 904 {
 905         struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port];
 906         int n_entries, level, default_entry;
 907         enum phy phy = intel_port_to_phy(dev_priv, port);
 908
 909         if (INTEL_GEN(dev_priv) >= 12) {
 910                 if (intel_phy_is_combo(dev_priv, phy))
 911                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 912                                                 0, &n_entries);
 913                 else
 914                         n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
 915                 default_entry = n_entries - 1;
 916         } else if (INTEL_GEN(dev_priv) == 11) {
 917                 if (intel_phy_is_combo(dev_priv, phy))
 918                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 919                                                 0, &n_entries);
 920                 else
 921                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 922                 default_entry = n_entries - 1;
 923         } else if (IS_CANNONLAKE(dev_priv)) {
 924                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 925                 default_entry = n_entries - 1;
 926         } else if (IS_GEN9_LP(dev_priv)) {
 927                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 928                 default_entry = n_entries - 1;
 929         } else if (IS_GEN9_BC(dev_priv)) {
 930                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 931                 default_entry = 8;
 932         } else if (IS_BROADWELL(dev_priv)) {
 933                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 934                 default_entry = 7;
 935         } else if (IS_HASWELL(dev_priv)) {
 936                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 937                 default_entry = 6;
 938         } else {
 939                 WARN(1, "ddi translation table missing\n");
 940                 return 0;
 941         }
 942
 943         if (WARN_ON_ONCE(n_entries == 0))
 944                 return 0;
 945
 946         if (port_info->hdmi_level_shift_set)
 947                 level = port_info->hdmi_level_shift;
 948         else
 949                 level = default_entry;
 950
 951         if (WARN_ON_ONCE(level >= n_entries))
 952                 level = n_entries - 1;
 953
 954         return level;
 955 }
 956
 957 /*
 958  * Starting with Haswell, DDI port buffers must be programmed with correct
 959  * values in advance. This function programs the correct values for
 960  * DP/eDP/FDI use cases.
 961  */
 962 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 963                                          const struct intel_crtc_state *crtc_state)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 966         u32 iboost_bit = 0;
 967         int i, n_entries;
 968         enum port port = encoder->port;
 969         const struct ddi_buf_trans *ddi_translations;
 970
 971         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 972                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 973                                                                &n_entries);
 974         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 975                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 976                                                                &n_entries);
 977         else
 978                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 979                                                               &n_entries);
 980
 981         /* If we're boosting the current, set bit 31 of trans1 */
 982         if (IS_GEN9_BC(dev_priv) &&
 983             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 984                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 985
 986         for (i = 0; i < n_entries; i++) {
 987                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 988                            ddi_translations[i].trans1 | iboost_bit);
 989                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 990                            ddi_translations[i].trans2);
 991         }
 992 }
 993
 994 /*
 995  * Starting with Haswell, DDI port buffers must be programmed with correct
 996  * values in advance. This function programs the correct values for
 997  * HDMI/DVI use cases.
 998  */
 999 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1000                                            int level)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1003         u32 iboost_bit = 0;
1004         int n_entries;
1005         enum port port = encoder->port;
1006         const struct ddi_buf_trans *ddi_translations;
1007
1008         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1009
1010         if (WARN_ON_ONCE(!ddi_translations))
1011                 return;
1012         if (WARN_ON_ONCE(level >= n_entries))
1013                 level = n_entries - 1;
1014
1015         /* If we're boosting the current, set bit 31 of trans1 */
1016         if (IS_GEN9_BC(dev_priv) &&
1017             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1018                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1019
1020         /* Entry 9 is for HDMI: */
1021         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1022                    ddi_translations[level].trans1 | iboost_bit);
1023         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1024                    ddi_translations[level].trans2);
1025 }
1026
1027 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1028                                     enum port port)
1029 {
1030         i915_reg_t reg = DDI_BUF_CTL(port);
1031         int i;
1032
1033         for (i = 0; i < 16; i++) {
1034                 udelay(1);
1035                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1036                         return;
1037         }
1038         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1039 }
1040
1041 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1042 {
1043         switch (pll->info->id) {
1044         case DPLL_ID_WRPLL1:
1045                 return PORT_CLK_SEL_WRPLL1;
1046         case DPLL_ID_WRPLL2:
1047                 return PORT_CLK_SEL_WRPLL2;
1048         case DPLL_ID_SPLL:
1049                 return PORT_CLK_SEL_SPLL;
1050         case DPLL_ID_LCPLL_810:
1051                 return PORT_CLK_SEL_LCPLL_810;
1052         case DPLL_ID_LCPLL_1350:
1053                 return PORT_CLK_SEL_LCPLL_1350;
1054         case DPLL_ID_LCPLL_2700:
1055                 return PORT_CLK_SEL_LCPLL_2700;
1056         default:
1057                 MISSING_CASE(pll->info->id);
1058                 return PORT_CLK_SEL_NONE;
1059         }
1060 }
1061
1062 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1063                                   const struct intel_crtc_state *crtc_state)
1064 {
1065         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1066         int clock = crtc_state->port_clock;
1067         const enum intel_dpll_id id = pll->info->id;
1068
1069         switch (id) {
1070         default:
1071                 /*
1072                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1073                  * here, so do warn if this get passed in
1074                  */
1075                 MISSING_CASE(id);
1076                 return DDI_CLK_SEL_NONE;
1077         case DPLL_ID_ICL_TBTPLL:
1078                 switch (clock) {
1079                 case 162000:
1080                         return DDI_CLK_SEL_TBT_162;
1081                 case 270000:
1082                         return DDI_CLK_SEL_TBT_270;
1083                 case 540000:
1084                         return DDI_CLK_SEL_TBT_540;
1085                 case 810000:
1086                         return DDI_CLK_SEL_TBT_810;
1087                 default:
1088                         MISSING_CASE(clock);
1089                         return DDI_CLK_SEL_NONE;
1090                 }
1091         case DPLL_ID_ICL_MGPLL1:
1092         case DPLL_ID_ICL_MGPLL2:
1093         case DPLL_ID_ICL_MGPLL3:
1094         case DPLL_ID_ICL_MGPLL4:
1095         case DPLL_ID_TGL_MGPLL5:
1096         case DPLL_ID_TGL_MGPLL6:
1097                 return DDI_CLK_SEL_MG;
1098         }
1099 }
1100
1101 /* Starting with Haswell, different DDI ports can work in FDI mode for
1102  * connection to the PCH-located connectors. For this, it is necessary to train
1103  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1104  *
1105  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1106  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1107  * DDI A (which is used for eDP)
1108  */
1109
1110 void hsw_fdi_link_train(struct intel_crtc *crtc,
1111                         const struct intel_crtc_state *crtc_state)
1112 {
1113         struct drm_device *dev = crtc->base.dev;
1114         struct drm_i915_private *dev_priv = to_i915(dev);
1115         struct intel_encoder *encoder;
1116         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1117
1118         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1119                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1120                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1121         }
1122
1123         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1124          * mode set "sequence for CRT port" document:
1125          * - TP1 to TP2 time with the default value
1126          * - FDI delay to 90h
1127          *
1128          * WaFDIAutoLinkSetTimingOverrride:hsw
1129          */
1130         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1131                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1132                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1133
1134         /* Enable the PCH Receiver FDI PLL */
1135         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1136                      FDI_RX_PLL_ENABLE |
1137                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1138         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1139         POSTING_READ(FDI_RX_CTL(PIPE_A));
1140         udelay(220);
1141
1142         /* Switch from Rawclk to PCDclk */
1143         rx_ctl_val |= FDI_PCDCLK;
1144         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1145
1146         /* Configure Port Clock Select */
1147         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1148         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1149         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1150
1151         /* Start the training iterating through available voltages and emphasis,
1152          * testing each value twice. */
1153         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1154                 /* Configure DP_TP_CTL with auto-training */
1155                 I915_WRITE(DP_TP_CTL(PORT_E),
1156                                         DP_TP_CTL_FDI_AUTOTRAIN |
1157                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1158                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1159                                         DP_TP_CTL_ENABLE);
1160
1161                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1162                  * DDI E does not support port reversal, the functionality is
1163                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1164                  * port reversal bit */
1165                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1166                            DDI_BUF_CTL_ENABLE |
1167                            ((crtc_state->fdi_lanes - 1) << 1) |
1168                            DDI_BUF_TRANS_SELECT(i / 2));
1169                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1170
1171                 udelay(600);
1172
1173                 /* Program PCH FDI Receiver TU */
1174                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1175
1176                 /* Enable PCH FDI Receiver with auto-training */
1177                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1178                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1179                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1180
1181                 /* Wait for FDI receiver lane calibration */
1182                 udelay(30);
1183
1184                 /* Unset FDI_RX_MISC pwrdn lanes */
1185                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1186                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1187                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1188                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1189
1190                 /* Wait for FDI auto training time */
1191                 udelay(5);
1192
1193                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1194                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1195                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1196                         break;
1197                 }
1198
1199                 /*
1200                  * Leave things enabled even if we failed to train FDI.
1201                  * Results in less fireworks from the state checker.
1202                  */
1203                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1204                         DRM_ERROR("FDI link training failed!\n");
1205                         break;
1206                 }
1207
1208                 rx_ctl_val &= ~FDI_RX_ENABLE;
1209                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1210                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1211
1212                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1213                 temp &= ~DDI_BUF_CTL_ENABLE;
1214                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1215                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1216
1217                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1218                 temp = I915_READ(DP_TP_CTL(PORT_E));
1219                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1220                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1221                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1222                 POSTING_READ(DP_TP_CTL(PORT_E));
1223
1224                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1225
1226                 /* Reset FDI_RX_MISC pwrdn lanes */
1227                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1228                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1229                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1230                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1231                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1232         }
1233
1234         /* Enable normal pixel sending for FDI */
1235         I915_WRITE(DP_TP_CTL(PORT_E),
1236                    DP_TP_CTL_FDI_AUTOTRAIN |
1237                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1238                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1239                    DP_TP_CTL_ENABLE);
1240 }
1241
1242 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1243 {
1244         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1245         struct intel_digital_port *intel_dig_port =
1246                 enc_to_dig_port(&encoder->base);
1247
1248         intel_dp->DP = intel_dig_port->saved_port_bits |
1249                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1250         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1251 }
1252
1253 static struct intel_encoder *
1254 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1255 {
1256         struct drm_device *dev = crtc->base.dev;
1257         struct intel_encoder *encoder, *ret = NULL;
1258         int num_encoders = 0;
1259
1260         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1261                 ret = encoder;
1262                 num_encoders++;
1263         }
1264
1265         if (num_encoders != 1)
1266                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1267                      pipe_name(crtc->pipe));
1268
1269         BUG_ON(ret == NULL);
1270         return ret;
1271 }
1272
1273 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1274                                    i915_reg_t reg)
1275 {
1276         int refclk;
1277         int n, p, r;
1278         u32 wrpll;
1279
1280         wrpll = I915_READ(reg);
1281         switch (wrpll & WRPLL_REF_MASK) {
1282         case WRPLL_REF_SPECIAL_HSW:
1283                 /*
1284                  * muxed-SSC for BDW.
1285                  * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1286                  * for the non-SSC reference frequency.
1287                  */
1288                 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1289                         if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1290                                 refclk = 24;
1291                         else
1292                                 refclk = 135;
1293                         break;
1294                 }
1295                 /* fall through */
1296         case WRPLL_REF_PCH_SSC:
1297                 /*
1298                  * We could calculate spread here, but our checking
1299                  * code only cares about 5% accuracy, and spread is a max of
1300                  * 0.5% downspread.
1301                  */
1302                 refclk = 135;
1303                 break;
1304         case WRPLL_REF_LCPLL:
1305                 refclk = 2700;
1306                 break;
1307         default:
1308                 MISSING_CASE(wrpll);
1309                 return 0;
1310         }
1311
1312         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1313         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1314         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1315
1316         /* Convert to KHz, p & r have a fixed point portion */
1317         return (refclk * n * 100) / (p * r);
1318 }
1319
1320 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1321 {
1322         u32 p0, p1, p2, dco_freq;
1323
1324         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1325         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1326
1327         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1328                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1329         else
1330                 p1 = 1;
1331
1332
1333         switch (p0) {
1334         case DPLL_CFGCR2_PDIV_1:
1335                 p0 = 1;
1336                 break;
1337         case DPLL_CFGCR2_PDIV_2:
1338                 p0 = 2;
1339                 break;
1340         case DPLL_CFGCR2_PDIV_3:
1341                 p0 = 3;
1342                 break;
1343         case DPLL_CFGCR2_PDIV_7:
1344                 p0 = 7;
1345                 break;
1346         }
1347
1348         switch (p2) {
1349         case DPLL_CFGCR2_KDIV_5:
1350                 p2 = 5;
1351                 break;
1352         case DPLL_CFGCR2_KDIV_2:
1353                 p2 = 2;
1354                 break;
1355         case DPLL_CFGCR2_KDIV_3:
1356                 p2 = 3;
1357                 break;
1358         case DPLL_CFGCR2_KDIV_1:
1359                 p2 = 1;
1360                 break;
1361         }
1362
1363         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1364                 * 24 * 1000;
1365
1366         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1367                      * 24 * 1000) / 0x8000;
1368
1369         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1370                 return 0;
1371
1372         return dco_freq / (p0 * p1 * p2 * 5);
1373 }
1374
1375 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1376                         struct intel_dpll_hw_state *pll_state)
1377 {
1378         u32 p0, p1, p2, dco_freq, ref_clock;
1379
1380         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1381         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1382
1383         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1384                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1385                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1386         else
1387                 p1 = 1;
1388
1389
1390         switch (p0) {
1391         case DPLL_CFGCR1_PDIV_2:
1392                 p0 = 2;
1393                 break;
1394         case DPLL_CFGCR1_PDIV_3:
1395                 p0 = 3;
1396                 break;
1397         case DPLL_CFGCR1_PDIV_5:
1398                 p0 = 5;
1399                 break;
1400         case DPLL_CFGCR1_PDIV_7:
1401                 p0 = 7;
1402                 break;
1403         }
1404
1405         switch (p2) {
1406         case DPLL_CFGCR1_KDIV_1:
1407                 p2 = 1;
1408                 break;
1409         case DPLL_CFGCR1_KDIV_2:
1410                 p2 = 2;
1411                 break;
1412         case DPLL_CFGCR1_KDIV_3:
1413                 p2 = 3;
1414                 break;
1415         }
1416
1417         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1418
1419         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1420                 * ref_clock;
1421
1422         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1423                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1424
1425         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1426                 return 0;
1427
1428         return dco_freq / (p0 * p1 * p2 * 5);
1429 }
1430
1431 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1432                                  enum port port)
1433 {
1434         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1435
1436         switch (val) {
1437         case DDI_CLK_SEL_NONE:
1438                 return 0;
1439         case DDI_CLK_SEL_TBT_162:
1440                 return 162000;
1441         case DDI_CLK_SEL_TBT_270:
1442                 return 270000;
1443         case DDI_CLK_SEL_TBT_540:
1444                 return 540000;
1445         case DDI_CLK_SEL_TBT_810:
1446                 return 810000;
1447         default:
1448                 MISSING_CASE(val);
1449                 return 0;
1450         }
1451 }
1452
1453 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1454                                 const struct intel_dpll_hw_state *pll_state)
1455 {
1456         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1457         u64 tmp;
1458
1459         ref_clock = dev_priv->cdclk.hw.ref;
1460
1461         if (INTEL_GEN(dev_priv) >= 12) {
1462                 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
1463                 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
1464                 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
1465
1466                 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
1467                         m2_frac = pll_state->mg_pll_bias &
1468                                   DKL_PLL_BIAS_FBDIV_FRAC_MASK;
1469                         m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
1470                 } else {
1471                         m2_frac = 0;
1472                 }
1473         } else {
1474                 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1475                 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1476
1477                 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
1478                         m2_frac = pll_state->mg_pll_div0 &
1479                                   MG_PLL_DIV0_FBDIV_FRAC_MASK;
1480                         m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
1481                 } else {
1482                         m2_frac = 0;
1483                 }
1484         }
1485
1486         switch (pll_state->mg_clktop2_hsclkctl &
1487                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1488         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1489                 div1 = 2;
1490                 break;
1491         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1492                 div1 = 3;
1493                 break;
1494         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1495                 div1 = 5;
1496                 break;
1497         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1498                 div1 = 7;
1499                 break;
1500         default:
1501                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1502                 return 0;
1503         }
1504
1505         div2 = (pll_state->mg_clktop2_hsclkctl &
1506                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1507                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1508
1509         /* div2 value of 0 is same as 1 means no div */
1510         if (div2 == 0)
1511                 div2 = 1;
1512
1513         /*
1514          * Adjust the original formula to delay the division by 2^22 in order to
1515          * minimize possible rounding errors.
1516          */
1517         tmp = (u64)m1 * m2_int * ref_clock +
1518               (((u64)m1 * m2_frac * ref_clock) >> 22);
1519         tmp = div_u64(tmp, 5 * div1 * div2);
1520
1521         return tmp;
1522 }
1523
1524 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1525 {
1526         int dotclock;
1527
1528         if (pipe_config->has_pch_encoder)
1529                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1530                                                     &pipe_config->fdi_m_n);
1531         else if (intel_crtc_has_dp_encoder(pipe_config))
1532                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1533                                                     &pipe_config->dp_m_n);
1534         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1535                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1536         else
1537                 dotclock = pipe_config->port_clock;
1538
1539         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1540             !intel_crtc_has_dp_encoder(pipe_config))
1541                 dotclock *= 2;
1542
1543         if (pipe_config->pixel_multiplier)
1544                 dotclock /= pipe_config->pixel_multiplier;
1545
1546         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1547 }
1548
1549 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1550                               struct intel_crtc_state *pipe_config)
1551 {
1552         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1553         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1554         enum port port = encoder->port;
1555         enum phy phy = intel_port_to_phy(dev_priv, port);
1556         int link_clock;
1557
1558         if (intel_phy_is_combo(dev_priv, phy)) {
1559                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1560         } else {
1561                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1562                                                 pipe_config->shared_dpll);
1563
1564                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1565                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1566                 else
1567                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1568         }
1569
1570         pipe_config->port_clock = link_clock;
1571
1572         ddi_dotclock_get(pipe_config);
1573 }
1574
1575 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1576                               struct intel_crtc_state *pipe_config)
1577 {
1578         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1579         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1580         int link_clock;
1581
1582         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1583                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1584         } else {
1585                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1586
1587                 switch (link_clock) {
1588                 case DPLL_CFGCR0_LINK_RATE_810:
1589                         link_clock = 81000;
1590                         break;
1591                 case DPLL_CFGCR0_LINK_RATE_1080:
1592                         link_clock = 108000;
1593                         break;
1594                 case DPLL_CFGCR0_LINK_RATE_1350:
1595                         link_clock = 135000;
1596                         break;
1597                 case DPLL_CFGCR0_LINK_RATE_1620:
1598                         link_clock = 162000;
1599                         break;
1600                 case DPLL_CFGCR0_LINK_RATE_2160:
1601                         link_clock = 216000;
1602                         break;
1603                 case DPLL_CFGCR0_LINK_RATE_2700:
1604                         link_clock = 270000;
1605                         break;
1606                 case DPLL_CFGCR0_LINK_RATE_3240:
1607                         link_clock = 324000;
1608                         break;
1609                 case DPLL_CFGCR0_LINK_RATE_4050:
1610                         link_clock = 405000;
1611                         break;
1612                 default:
1613                         WARN(1, "Unsupported link rate\n");
1614                         break;
1615                 }
1616                 link_clock *= 2;
1617         }
1618
1619         pipe_config->port_clock = link_clock;
1620
1621         ddi_dotclock_get(pipe_config);
1622 }
1623
1624 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1625                               struct intel_crtc_state *pipe_config)
1626 {
1627         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1628         int link_clock;
1629
1630         /*
1631          * ctrl1 register is already shifted for each pll, just use 0 to get
1632          * the internal shift for each field
1633          */
1634         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1635                 link_clock = skl_calc_wrpll_link(pll_state);
1636         } else {
1637                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1638                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1639
1640                 switch (link_clock) {
1641                 case DPLL_CTRL1_LINK_RATE_810:
1642                         link_clock = 81000;
1643                         break;
1644                 case DPLL_CTRL1_LINK_RATE_1080:
1645                         link_clock = 108000;
1646                         break;
1647                 case DPLL_CTRL1_LINK_RATE_1350:
1648                         link_clock = 135000;
1649                         break;
1650                 case DPLL_CTRL1_LINK_RATE_1620:
1651                         link_clock = 162000;
1652                         break;
1653                 case DPLL_CTRL1_LINK_RATE_2160:
1654                         link_clock = 216000;
1655                         break;
1656                 case DPLL_CTRL1_LINK_RATE_2700:
1657                         link_clock = 270000;
1658                         break;
1659                 default:
1660                         WARN(1, "Unsupported link rate\n");
1661                         break;
1662                 }
1663                 link_clock *= 2;
1664         }
1665
1666         pipe_config->port_clock = link_clock;
1667
1668         ddi_dotclock_get(pipe_config);
1669 }
1670
1671 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1672                               struct intel_crtc_state *pipe_config)
1673 {
1674         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1675         int link_clock = 0;
1676         u32 val, pll;
1677
1678         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1679         switch (val & PORT_CLK_SEL_MASK) {
1680         case PORT_CLK_SEL_LCPLL_810:
1681                 link_clock = 81000;
1682                 break;
1683         case PORT_CLK_SEL_LCPLL_1350:
1684                 link_clock = 135000;
1685                 break;
1686         case PORT_CLK_SEL_LCPLL_2700:
1687                 link_clock = 270000;
1688                 break;
1689         case PORT_CLK_SEL_WRPLL1:
1690                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1691                 break;
1692         case PORT_CLK_SEL_WRPLL2:
1693                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1694                 break;
1695         case PORT_CLK_SEL_SPLL:
1696                 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1697                 if (pll == SPLL_FREQ_810MHz)
1698                         link_clock = 81000;
1699                 else if (pll == SPLL_FREQ_1350MHz)
1700                         link_clock = 135000;
1701                 else if (pll == SPLL_FREQ_2700MHz)
1702                         link_clock = 270000;
1703                 else {
1704                         WARN(1, "bad spll freq\n");
1705                         return;
1706                 }
1707                 break;
1708         default:
1709                 WARN(1, "bad port clock sel\n");
1710                 return;
1711         }
1712
1713         pipe_config->port_clock = link_clock * 2;
1714
1715         ddi_dotclock_get(pipe_config);
1716 }
1717
1718 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1719 {
1720         struct dpll clock;
1721
1722         clock.m1 = 2;
1723         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1724         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1725                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1726         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1727         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1728         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1729
1730         return chv_calc_dpll_params(100000, &clock);
1731 }
1732
1733 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1734                               struct intel_crtc_state *pipe_config)
1735 {
1736         pipe_config->port_clock =
1737                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1738
1739         ddi_dotclock_get(pipe_config);
1740 }
1741
1742 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1743                                 struct intel_crtc_state *pipe_config)
1744 {
1745         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1746
1747         if (INTEL_GEN(dev_priv) >= 11)
1748                 icl_ddi_clock_get(encoder, pipe_config);
1749         else if (IS_CANNONLAKE(dev_priv))
1750                 cnl_ddi_clock_get(encoder, pipe_config);
1751         else if (IS_GEN9_LP(dev_priv))
1752                 bxt_ddi_clock_get(encoder, pipe_config);
1753         else if (IS_GEN9_BC(dev_priv))
1754                 skl_ddi_clock_get(encoder, pipe_config);
1755         else if (INTEL_GEN(dev_priv) <= 8)
1756                 hsw_ddi_clock_get(encoder, pipe_config);
1757 }
1758
1759 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1760                           const struct drm_connector_state *conn_state)
1761 {
1762         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1763         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1764         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1765         u32 temp;
1766
1767         if (!intel_crtc_has_dp_encoder(crtc_state))
1768                 return;
1769
1770         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1771
1772         temp = DP_MSA_MISC_SYNC_CLOCK;
1773
1774         switch (crtc_state->pipe_bpp) {
1775         case 18:
1776                 temp |= DP_MSA_MISC_6_BPC;
1777                 break;
1778         case 24:
1779                 temp |= DP_MSA_MISC_8_BPC;
1780                 break;
1781         case 30:
1782                 temp |= DP_MSA_MISC_10_BPC;
1783                 break;
1784         case 36:
1785                 temp |= DP_MSA_MISC_12_BPC;
1786                 break;
1787         default:
1788                 MISSING_CASE(crtc_state->pipe_bpp);
1789                 break;
1790         }
1791
1792         /* nonsense combination */
1793         WARN_ON(crtc_state->limited_color_range &&
1794                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1795
1796         if (crtc_state->limited_color_range)
1797                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1798
1799         /*
1800          * As per DP 1.2 spec section 2.3.4.3 while sending
1801          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1802          * colorspace information.
1803          */
1804         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1805                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1806
1807         /*
1808          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1809          * of Color Encoding Format and Content Color Gamut] while sending
1810          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1811          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1812          */
1813         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1814                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1815
1816         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1817 }
1818
1819 /*
1820  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1821  *
1822  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1823  * intel_ddi_config_transcoder_func().
1824  */
1825 static u32
1826 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
1827 {
1828         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1829         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1830         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1831         enum pipe pipe = crtc->pipe;
1832         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1833         enum port port = encoder->port;
1834         u32 temp;
1835
1836         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1837         temp = TRANS_DDI_FUNC_ENABLE;
1838         if (INTEL_GEN(dev_priv) >= 12)
1839                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1840         else
1841                 temp |= TRANS_DDI_SELECT_PORT(port);
1842
1843         switch (crtc_state->pipe_bpp) {
1844         case 18:
1845                 temp |= TRANS_DDI_BPC_6;
1846                 break;
1847         case 24:
1848                 temp |= TRANS_DDI_BPC_8;
1849                 break;
1850         case 30:
1851                 temp |= TRANS_DDI_BPC_10;
1852                 break;
1853         case 36:
1854                 temp |= TRANS_DDI_BPC_12;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1861                 temp |= TRANS_DDI_PVSYNC;
1862         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1863                 temp |= TRANS_DDI_PHSYNC;
1864
1865         if (cpu_transcoder == TRANSCODER_EDP) {
1866                 switch (pipe) {
1867                 case PIPE_A:
1868                         /* On Haswell, can only use the always-on power well for
1869                          * eDP when not using the panel fitter, and when not
1870                          * using motion blur mitigation (which we don't
1871                          * support). */
1872                         if (crtc_state->pch_pfit.force_thru)
1873                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1874                         else
1875                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1876                         break;
1877                 case PIPE_B:
1878                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1879                         break;
1880                 case PIPE_C:
1881                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1882                         break;
1883                 default:
1884                         BUG();
1885                         break;
1886                 }
1887         }
1888
1889         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1890                 if (crtc_state->has_hdmi_sink)
1891                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1892                 else
1893                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1894
1895                 if (crtc_state->hdmi_scrambling)
1896                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1897                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1898                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1899         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1900                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1901                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1902         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1903                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1904                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1905
1906                 if (INTEL_GEN(dev_priv) >= 12)
1907                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
1908         } else {
1909                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1910                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1911         }
1912
1913         return temp;
1914 }
1915
1916 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1917 {
1918         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1919         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1920         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1921         u32 temp;
1922
1923         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1924         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
1925                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1926         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1927 }
1928
1929 /*
1930  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1931  * bit.
1932  */
1933 static void
1934 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1935 {
1936         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1937         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1938         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1939         u32 temp;
1940
1941         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1942         temp &= ~TRANS_DDI_FUNC_ENABLE;
1943         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1944 }
1945
1946 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1947 {
1948         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1949         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1950         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1951         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1952         u32 val = I915_READ(reg);
1953
1954         if (INTEL_GEN(dev_priv) >= 12) {
1955                 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1956                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1957         } else {
1958                 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1959                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1960         }
1961         I915_WRITE(reg, val);
1962
1963         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1964             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1965                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1966                 /* Quirk time at 100ms for reliable operation */
1967                 msleep(100);
1968         }
1969 }
1970
1971 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1972                                      bool enable)
1973 {
1974         struct drm_device *dev = intel_encoder->base.dev;
1975         struct drm_i915_private *dev_priv = to_i915(dev);
1976         intel_wakeref_t wakeref;
1977         enum pipe pipe = 0;
1978         int ret = 0;
1979         u32 tmp;
1980
1981         wakeref = intel_display_power_get_if_enabled(dev_priv,
1982                                                      intel_encoder->power_domain);
1983         if (WARN_ON(!wakeref))
1984                 return -ENXIO;
1985
1986         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1987                 ret = -EIO;
1988                 goto out;
1989         }
1990
1991         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1992         if (enable)
1993                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1994         else
1995                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1996         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1997 out:
1998         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1999         return ret;
2000 }
2001
2002 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
2003 {
2004         struct drm_device *dev = intel_connector->base.dev;
2005         struct drm_i915_private *dev_priv = to_i915(dev);
2006         struct intel_encoder *encoder = intel_connector->encoder;
2007         int type = intel_connector->base.connector_type;
2008         enum port port = encoder->port;
2009         enum transcoder cpu_transcoder;
2010         intel_wakeref_t wakeref;
2011         enum pipe pipe = 0;
2012         u32 tmp;
2013         bool ret;
2014
2015         wakeref = intel_display_power_get_if_enabled(dev_priv,
2016                                                      encoder->power_domain);
2017         if (!wakeref)
2018                 return false;
2019
2020         if (!encoder->get_hw_state(encoder, &pipe)) {
2021                 ret = false;
2022                 goto out;
2023         }
2024
2025         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
2026                 cpu_transcoder = TRANSCODER_EDP;
2027         else
2028                 cpu_transcoder = (enum transcoder) pipe;
2029
2030         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2031
2032         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
2033         case TRANS_DDI_MODE_SELECT_HDMI:
2034         case TRANS_DDI_MODE_SELECT_DVI:
2035                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
2036                 break;
2037
2038         case TRANS_DDI_MODE_SELECT_DP_SST:
2039                 ret = type == DRM_MODE_CONNECTOR_eDP ||
2040                       type == DRM_MODE_CONNECTOR_DisplayPort;
2041                 break;
2042
2043         case TRANS_DDI_MODE_SELECT_DP_MST:
2044                 /* if the transcoder is in MST state then
2045                  * connector isn't connected */
2046                 ret = false;
2047                 break;
2048
2049         case TRANS_DDI_MODE_SELECT_FDI:
2050                 ret = type == DRM_MODE_CONNECTOR_VGA;
2051                 break;
2052
2053         default:
2054                 ret = false;
2055                 break;
2056         }
2057
2058 out:
2059         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2060
2061         return ret;
2062 }
2063
2064 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2065                                         u8 *pipe_mask, bool *is_dp_mst)
2066 {
2067         struct drm_device *dev = encoder->base.dev;
2068         struct drm_i915_private *dev_priv = to_i915(dev);
2069         enum port port = encoder->port;
2070         intel_wakeref_t wakeref;
2071         enum pipe p;
2072         u32 tmp;
2073         u8 mst_pipe_mask;
2074
2075         *pipe_mask = 0;
2076         *is_dp_mst = false;
2077
2078         wakeref = intel_display_power_get_if_enabled(dev_priv,
2079                                                      encoder->power_domain);
2080         if (!wakeref)
2081                 return;
2082
2083         tmp = I915_READ(DDI_BUF_CTL(port));
2084         if (!(tmp & DDI_BUF_CTL_ENABLE))
2085                 goto out;
2086
2087         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
2088                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2089
2090                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2091                 default:
2092                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2093                         /* fallthrough */
2094                 case TRANS_DDI_EDP_INPUT_A_ON:
2095                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2096                         *pipe_mask = BIT(PIPE_A);
2097                         break;
2098                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2099                         *pipe_mask = BIT(PIPE_B);
2100                         break;
2101                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2102                         *pipe_mask = BIT(PIPE_C);
2103                         break;
2104                 }
2105
2106                 goto out;
2107         }
2108
2109         mst_pipe_mask = 0;
2110         for_each_pipe(dev_priv, p) {
2111                 enum transcoder cpu_transcoder = (enum transcoder)p;
2112                 unsigned int port_mask, ddi_select;
2113                 intel_wakeref_t trans_wakeref;
2114
2115                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2116                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2117                 if (!trans_wakeref)
2118                         continue;
2119
2120                 if (INTEL_GEN(dev_priv) >= 12) {
2121                         port_mask = TGL_TRANS_DDI_PORT_MASK;
2122                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2123                 } else {
2124                         port_mask = TRANS_DDI_PORT_MASK;
2125                         ddi_select = TRANS_DDI_SELECT_PORT(port);
2126                 }
2127
2128                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2129                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2130                                         trans_wakeref);
2131
2132                 if ((tmp & port_mask) != ddi_select)
2133                         continue;
2134
2135                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2136                     TRANS_DDI_MODE_SELECT_DP_MST)
2137                         mst_pipe_mask |= BIT(p);
2138
2139                 *pipe_mask |= BIT(p);
2140         }
2141
2142         if (!*pipe_mask)
2143                 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
2144                               encoder->base.base.id, encoder->base.name);
2145
2146         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2147                 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2148                               encoder->base.base.id, encoder->base.name,
2149                               *pipe_mask);
2150                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2151         }
2152
2153         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2154                 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2155                               encoder->base.base.id, encoder->base.name,
2156                               *pipe_mask, mst_pipe_mask);
2157         else
2158                 *is_dp_mst = mst_pipe_mask;
2159
2160 out:
2161         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2162                 tmp = I915_READ(BXT_PHY_CTL(port));
2163                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2164                             BXT_PHY_LANE_POWERDOWN_ACK |
2165                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2166                         DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
2167                                   "(PHY_CTL %08x)\n", encoder->base.base.id,
2168                                   encoder->base.name, tmp);
2169         }
2170
2171         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2172 }
2173
2174 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2175                             enum pipe *pipe)
2176 {
2177         u8 pipe_mask;
2178         bool is_mst;
2179
2180         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2181
2182         if (is_mst || !pipe_mask)
2183                 return false;
2184
2185         *pipe = ffs(pipe_mask) - 1;
2186
2187         return true;
2188 }
2189
2190 static inline enum intel_display_power_domain
2191 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2192 {
2193         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2194          * DC states enabled at the same time, while for driver initiated AUX
2195          * transfers we need the same AUX IOs to be powered but with DC states
2196          * disabled. Accordingly use the AUX power domain here which leaves DC
2197          * states enabled.
2198          * However, for non-A AUX ports the corresponding non-EDP transcoders
2199          * would have already enabled power well 2 and DC_OFF. This means we can
2200          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2201          * specific AUX_IO reference without powering up any extra wells.
2202          * Note that PSR is enabled only on Port A even though this function
2203          * returns the correct domain for other ports too.
2204          */
2205         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2206                                               intel_aux_power_domain(dig_port);
2207 }
2208
2209 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2210                                         struct intel_crtc_state *crtc_state)
2211 {
2212         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2213         struct intel_digital_port *dig_port;
2214         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2215
2216         /*
2217          * TODO: Add support for MST encoders. Atm, the following should never
2218          * happen since fake-MST encoders don't set their get_power_domains()
2219          * hook.
2220          */
2221         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2222                 return;
2223
2224         dig_port = enc_to_dig_port(&encoder->base);
2225         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2226
2227         /*
2228          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2229          * ports.
2230          */
2231         if (intel_crtc_has_dp_encoder(crtc_state) ||
2232             intel_phy_is_tc(dev_priv, phy))
2233                 intel_display_power_get(dev_priv,
2234                                         intel_ddi_main_link_aux_domain(dig_port));
2235
2236         /*
2237          * VDSC power is needed when DSC is enabled
2238          */
2239         if (crtc_state->dsc.compression_enable)
2240                 intel_display_power_get(dev_priv,
2241                                         intel_dsc_power_domain(crtc_state));
2242 }
2243
2244 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2245 {
2246         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2247         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2248         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2249         enum port port = encoder->port;
2250         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2251
2252         if (cpu_transcoder != TRANSCODER_EDP) {
2253                 if (INTEL_GEN(dev_priv) >= 12)
2254                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2255                                    TGL_TRANS_CLK_SEL_PORT(port));
2256                 else
2257                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2258                                    TRANS_CLK_SEL_PORT(port));
2259         }
2260 }
2261
2262 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2263 {
2264         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2265         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2266
2267         if (cpu_transcoder != TRANSCODER_EDP) {
2268                 if (INTEL_GEN(dev_priv) >= 12)
2269                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2270                                    TGL_TRANS_CLK_SEL_DISABLED);
2271                 else
2272                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2273                                    TRANS_CLK_SEL_DISABLED);
2274         }
2275 }
2276
2277 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2278                                 enum port port, u8 iboost)
2279 {
2280         u32 tmp;
2281
2282         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2283         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2284         if (iboost)
2285                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2286         else
2287                 tmp |= BALANCE_LEG_DISABLE(port);
2288         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2289 }
2290
2291 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2292                                int level, enum intel_output_type type)
2293 {
2294         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2295         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2296         enum port port = encoder->port;
2297         u8 iboost;
2298
2299         if (type == INTEL_OUTPUT_HDMI)
2300                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2301         else
2302                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2303
2304         if (iboost == 0) {
2305                 const struct ddi_buf_trans *ddi_translations;
2306                 int n_entries;
2307
2308                 if (type == INTEL_OUTPUT_HDMI)
2309                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2310                 else if (type == INTEL_OUTPUT_EDP)
2311                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2312                 else
2313                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2314
2315                 if (WARN_ON_ONCE(!ddi_translations))
2316                         return;
2317                 if (WARN_ON_ONCE(level >= n_entries))
2318                         level = n_entries - 1;
2319
2320                 iboost = ddi_translations[level].i_boost;
2321         }
2322
2323         /* Make sure that the requested I_boost is valid */
2324         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2325                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2326                 return;
2327         }
2328
2329         _skl_ddi_set_iboost(dev_priv, port, iboost);
2330
2331         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2332                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2333 }
2334
2335 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2336                                     int level, enum intel_output_type type)
2337 {
2338         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2339         const struct bxt_ddi_buf_trans *ddi_translations;
2340         enum port port = encoder->port;
2341         int n_entries;
2342
2343         if (type == INTEL_OUTPUT_HDMI)
2344                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2345         else if (type == INTEL_OUTPUT_EDP)
2346                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2347         else
2348                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2349
2350         if (WARN_ON_ONCE(!ddi_translations))
2351                 return;
2352         if (WARN_ON_ONCE(level >= n_entries))
2353                 level = n_entries - 1;
2354
2355         bxt_ddi_phy_set_signal_level(dev_priv, port,
2356                                      ddi_translations[level].margin,
2357                                      ddi_translations[level].scale,
2358                                      ddi_translations[level].enable,
2359                                      ddi_translations[level].deemphasis);
2360 }
2361
2362 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2363 {
2364         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2365         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2366         enum port port = encoder->port;
2367         enum phy phy = intel_port_to_phy(dev_priv, port);
2368         int n_entries;
2369
2370         if (INTEL_GEN(dev_priv) >= 12) {
2371                 if (intel_phy_is_combo(dev_priv, phy))
2372                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2373                                                 intel_dp->link_rate, &n_entries);
2374                 else
2375                         n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2376         } else if (INTEL_GEN(dev_priv) == 11) {
2377                 if (intel_phy_is_combo(dev_priv, phy))
2378                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2379                                                 intel_dp->link_rate, &n_entries);
2380                 else
2381                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2382         } else if (IS_CANNONLAKE(dev_priv)) {
2383                 if (encoder->type == INTEL_OUTPUT_EDP)
2384                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2385                 else
2386                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2387         } else if (IS_GEN9_LP(dev_priv)) {
2388                 if (encoder->type == INTEL_OUTPUT_EDP)
2389                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2390                 else
2391                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2392         } else {
2393                 if (encoder->type == INTEL_OUTPUT_EDP)
2394                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2395                 else
2396                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2397         }
2398
2399         if (WARN_ON(n_entries < 1))
2400                 n_entries = 1;
2401         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2402                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2403
2404         return index_to_dp_signal_levels[n_entries - 1] &
2405                 DP_TRAIN_VOLTAGE_SWING_MASK;
2406 }
2407
2408 /*
2409  * We assume that the full set of pre-emphasis values can be
2410  * used on all DDI platforms. Should that change we need to
2411  * rethink this code.
2412  */
2413 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2414 {
2415         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2416         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2417                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2418         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2419                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2420         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2421                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2422         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2423         default:
2424                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2425         }
2426 }
2427
2428 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2429                                    int level, enum intel_output_type type)
2430 {
2431         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2432         const struct cnl_ddi_buf_trans *ddi_translations;
2433         enum port port = encoder->port;
2434         int n_entries, ln;
2435         u32 val;
2436
2437         if (type == INTEL_OUTPUT_HDMI)
2438                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2439         else if (type == INTEL_OUTPUT_EDP)
2440                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2441         else
2442                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2443
2444         if (WARN_ON_ONCE(!ddi_translations))
2445                 return;
2446         if (WARN_ON_ONCE(level >= n_entries))
2447                 level = n_entries - 1;
2448
2449         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2450         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2451         val &= ~SCALING_MODE_SEL_MASK;
2452         val |= SCALING_MODE_SEL(2);
2453         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2454
2455         /* Program PORT_TX_DW2 */
2456         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2457         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2458                  RCOMP_SCALAR_MASK);
2459         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2460         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2461         /* Rcomp scalar is fixed as 0x98 for every table entry */
2462         val |= RCOMP_SCALAR(0x98);
2463         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2464
2465         /* Program PORT_TX_DW4 */
2466         /* We cannot write to GRP. It would overrite individual loadgen */
2467         for (ln = 0; ln < 4; ln++) {
2468                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2469                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2470                          CURSOR_COEFF_MASK);
2471                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2472                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2473                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2474                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2475         }
2476
2477         /* Program PORT_TX_DW5 */
2478         /* All DW5 values are fixed for every table entry */
2479         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2480         val &= ~RTERM_SELECT_MASK;
2481         val |= RTERM_SELECT(6);
2482         val |= TAP3_DISABLE;
2483         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2484
2485         /* Program PORT_TX_DW7 */
2486         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2487         val &= ~N_SCALAR_MASK;
2488         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2489         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2490 }
2491
2492 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2493                                     int level, enum intel_output_type type)
2494 {
2495         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2496         enum port port = encoder->port;
2497         int width, rate, ln;
2498         u32 val;
2499
2500         if (type == INTEL_OUTPUT_HDMI) {
2501                 width = 4;
2502                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2503         } else {
2504                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2505
2506                 width = intel_dp->lane_count;
2507                 rate = intel_dp->link_rate;
2508         }
2509
2510         /*
2511          * 1. If port type is eDP or DP,
2512          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2513          * else clear to 0b.
2514          */
2515         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2516         if (type != INTEL_OUTPUT_HDMI)
2517                 val |= COMMON_KEEPER_EN;
2518         else
2519                 val &= ~COMMON_KEEPER_EN;
2520         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2521
2522         /* 2. Program loadgen select */
2523         /*
2524          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2525          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2526          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2527          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2528          */
2529         for (ln = 0; ln <= 3; ln++) {
2530                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2531                 val &= ~LOADGEN_SELECT;
2532
2533                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2534                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2535                         val |= LOADGEN_SELECT;
2536                 }
2537                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2538         }
2539
2540         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2541         val = I915_READ(CNL_PORT_CL1CM_DW5);
2542         val |= SUS_CLOCK_CONFIG;
2543         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2544
2545         /* 4. Clear training enable to change swing values */
2546         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2547         val &= ~TX_TRAINING_EN;
2548         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2549
2550         /* 5. Program swing and de-emphasis */
2551         cnl_ddi_vswing_program(encoder, level, type);
2552
2553         /* 6. Set training enable to trigger update */
2554         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2555         val |= TX_TRAINING_EN;
2556         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2557 }
2558
2559 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2560                                         u32 level, enum phy phy, int type,
2561                                         int rate)
2562 {
2563         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2564         u32 n_entries, val;
2565         int ln;
2566
2567         ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2568                                                    &n_entries);
2569         if (!ddi_translations)
2570                 return;
2571
2572         if (level >= n_entries) {
2573                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2574                 level = n_entries - 1;
2575         }
2576
2577         /* Set PORT_TX_DW5 */
2578         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2579         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2580                   TAP2_DISABLE | TAP3_DISABLE);
2581         val |= SCALING_MODE_SEL(0x2);
2582         val |= RTERM_SELECT(0x6);
2583         val |= TAP3_DISABLE;
2584         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2585
2586         /* Program PORT_TX_DW2 */
2587         val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2588         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2589                  RCOMP_SCALAR_MASK);
2590         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2591         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2592         /* Program Rcomp scalar for every table entry */
2593         val |= RCOMP_SCALAR(0x98);
2594         I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2595
2596         /* Program PORT_TX_DW4 */
2597         /* We cannot write to GRP. It would overwrite individual loadgen. */
2598         for (ln = 0; ln <= 3; ln++) {
2599                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2600                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2601                          CURSOR_COEFF_MASK);
2602                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2603                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2604                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2605                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2606         }
2607
2608         /* Program PORT_TX_DW7 */
2609         val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2610         val &= ~N_SCALAR_MASK;
2611         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2612         I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2613 }
2614
2615 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2616                                               u32 level,
2617                                               enum intel_output_type type)
2618 {
2619         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2620         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2621         int width = 0;
2622         int rate = 0;
2623         u32 val;
2624         int ln = 0;
2625
2626         if (type == INTEL_OUTPUT_HDMI) {
2627                 width = 4;
2628                 /* Rate is always < than 6GHz for HDMI */
2629         } else {
2630                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2631
2632                 width = intel_dp->lane_count;
2633                 rate = intel_dp->link_rate;
2634         }
2635
2636         /*
2637          * 1. If port type is eDP or DP,
2638          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2639          * else clear to 0b.
2640          */
2641         val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2642         if (type == INTEL_OUTPUT_HDMI)
2643                 val &= ~COMMON_KEEPER_EN;
2644         else
2645                 val |= COMMON_KEEPER_EN;
2646         I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2647
2648         /* 2. Program loadgen select */
2649         /*
2650          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2651          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2652          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2653          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2654          */
2655         for (ln = 0; ln <= 3; ln++) {
2656                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2657                 val &= ~LOADGEN_SELECT;
2658
2659                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2660                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2661                         val |= LOADGEN_SELECT;
2662                 }
2663                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2664         }
2665
2666         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2667         val = I915_READ(ICL_PORT_CL_DW5(phy));
2668         val |= SUS_CLOCK_CONFIG;
2669         I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2670
2671         /* 4. Clear training enable to change swing values */
2672         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2673         val &= ~TX_TRAINING_EN;
2674         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2675
2676         /* 5. Program swing and de-emphasis */
2677         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2678
2679         /* 6. Set training enable to trigger update */
2680         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2681         val |= TX_TRAINING_EN;
2682         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2683 }
2684
2685 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2686                                            int link_clock,
2687                                            u32 level)
2688 {
2689         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2690         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2691         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2692         u32 n_entries, val;
2693         int ln;
2694
2695         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2696         ddi_translations = icl_mg_phy_ddi_translations;
2697         /* The table does not have values for level 3 and level 9. */
2698         if (level >= n_entries || level == 3 || level == 9) {
2699                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2700                               level, n_entries - 2);
2701                 level = n_entries - 2;
2702         }
2703
2704         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2705         for (ln = 0; ln < 2; ln++) {
2706                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
2707                 val &= ~CRI_USE_FS32;
2708                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
2709
2710                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
2711                 val &= ~CRI_USE_FS32;
2712                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
2713         }
2714
2715         /* Program MG_TX_SWINGCTRL with values from vswing table */
2716         for (ln = 0; ln < 2; ln++) {
2717                 val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
2718                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2719                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2720                         ddi_translations[level].cri_txdeemph_override_17_12);
2721                 I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
2722
2723                 val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
2724                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2725                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2726                         ddi_translations[level].cri_txdeemph_override_17_12);
2727                 I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
2728         }
2729
2730         /* Program MG_TX_DRVCTRL with values from vswing table */
2731         for (ln = 0; ln < 2; ln++) {
2732                 val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
2733                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2734                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2735                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2736                         ddi_translations[level].cri_txdeemph_override_5_0) |
2737                         CRI_TXDEEMPH_OVERRIDE_11_6(
2738                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2739                         CRI_TXDEEMPH_OVERRIDE_EN;
2740                 I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
2741
2742                 val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
2743                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2744                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2745                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2746                         ddi_translations[level].cri_txdeemph_override_5_0) |
2747                         CRI_TXDEEMPH_OVERRIDE_11_6(
2748                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2749                         CRI_TXDEEMPH_OVERRIDE_EN;
2750                 I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
2751
2752                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2753         }
2754
2755         /*
2756          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2757          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2758          * values from table for which TX1 and TX2 enabled.
2759          */
2760         for (ln = 0; ln < 2; ln++) {
2761                 val = I915_READ(MG_CLKHUB(ln, tc_port));
2762                 if (link_clock < 300000)
2763                         val |= CFG_LOW_RATE_LKREN_EN;
2764                 else
2765                         val &= ~CFG_LOW_RATE_LKREN_EN;
2766                 I915_WRITE(MG_CLKHUB(ln, tc_port), val);
2767         }
2768
2769         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2770         for (ln = 0; ln < 2; ln++) {
2771                 val = I915_READ(MG_TX1_DCC(ln, tc_port));
2772                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2773                 if (link_clock <= 500000) {
2774                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2775                 } else {
2776                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2777                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2778                 }
2779                 I915_WRITE(MG_TX1_DCC(ln, tc_port), val);
2780
2781                 val = I915_READ(MG_TX2_DCC(ln, tc_port));
2782                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2783                 if (link_clock <= 500000) {
2784                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2785                 } else {
2786                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2787                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2788                 }
2789                 I915_WRITE(MG_TX2_DCC(ln, tc_port), val);
2790         }
2791
2792         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2793         for (ln = 0; ln < 2; ln++) {
2794                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port));
2795                 val |= CRI_CALCINIT;
2796                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val);
2797
2798                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port));
2799                 val |= CRI_CALCINIT;
2800                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val);
2801         }
2802 }
2803
2804 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2805                                     int link_clock,
2806                                     u32 level,
2807                                     enum intel_output_type type)
2808 {
2809         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2810         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2811
2812         if (intel_phy_is_combo(dev_priv, phy))
2813                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2814         else
2815                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2816 }
2817
2818 static void
2819 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2820                                 u32 level)
2821 {
2822         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2823         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2824         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2825         u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2826
2827         if (encoder->type == INTEL_OUTPUT_HDMI) {
2828                 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
2829                 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;
2830         } else {
2831                 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2832                 ddi_translations = tgl_dkl_phy_dp_ddi_trans;
2833         }
2834
2835         if (level >= n_entries)
2836                 level = n_entries - 1;
2837
2838         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2839                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2840                       DKL_TX_VSWING_CONTROL_MASK);
2841         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2842         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2843         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2844
2845         for (ln = 0; ln < 2; ln++) {
2846                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
2847
2848                 I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0);
2849
2850                 /* All the registers are RMW */
2851                 val = I915_READ(DKL_TX_DPCNTL0(tc_port));
2852                 val &= ~dpcnt_mask;
2853                 val |= dpcnt_val;
2854                 I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
2855
2856                 val = I915_READ(DKL_TX_DPCNTL1(tc_port));
2857                 val &= ~dpcnt_mask;
2858                 val |= dpcnt_val;
2859                 I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
2860
2861                 val = I915_READ(DKL_TX_DPCNTL2(tc_port));
2862                 val &= ~DKL_TX_DP20BITMODE;
2863                 I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
2864         }
2865 }
2866
2867 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2868                                     int link_clock,
2869                                     u32 level,
2870                                     enum intel_output_type type)
2871 {
2872         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2873         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2874
2875         if (intel_phy_is_combo(dev_priv, phy))
2876                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2877         else
2878                 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
2879 }
2880
2881 static u32 translate_signal_level(int signal_levels)
2882 {
2883         int i;
2884
2885         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2886                 if (index_to_dp_signal_levels[i] == signal_levels)
2887                         return i;
2888         }
2889
2890         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2891              signal_levels);
2892
2893         return 0;
2894 }
2895
2896 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2897 {
2898         u8 train_set = intel_dp->train_set[0];
2899         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2900                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2901
2902         return translate_signal_level(signal_levels);
2903 }
2904
2905 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2906 {
2907         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2908         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2909         struct intel_encoder *encoder = &dport->base;
2910         int level = intel_ddi_dp_level(intel_dp);
2911
2912         if (INTEL_GEN(dev_priv) >= 12)
2913                 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2914                                         level, encoder->type);
2915         else if (INTEL_GEN(dev_priv) >= 11)
2916                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2917                                         level, encoder->type);
2918         else if (IS_CANNONLAKE(dev_priv))
2919                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2920         else
2921                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2922
2923         return 0;
2924 }
2925
2926 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2927 {
2928         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2929         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2930         struct intel_encoder *encoder = &dport->base;
2931         int level = intel_ddi_dp_level(intel_dp);
2932
2933         if (IS_GEN9_BC(dev_priv))
2934                 skl_ddi_set_iboost(encoder, level, encoder->type);
2935
2936         return DDI_BUF_TRANS_SELECT(level);
2937 }
2938
2939 static inline
2940 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2941                               enum phy phy)
2942 {
2943         if (intel_phy_is_combo(dev_priv, phy)) {
2944                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2945         } else if (intel_phy_is_tc(dev_priv, phy)) {
2946                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2947                                                         (enum port)phy);
2948
2949                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2950         }
2951
2952         return 0;
2953 }
2954
2955 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2956                                   const struct intel_crtc_state *crtc_state)
2957 {
2958         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2959         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2960         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2961         u32 val;
2962
2963         mutex_lock(&dev_priv->dpll_lock);
2964
2965         val = I915_READ(ICL_DPCLKA_CFGCR0);
2966         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2967
2968         if (intel_phy_is_combo(dev_priv, phy)) {
2969                 /*
2970                  * Even though this register references DDIs, note that we
2971                  * want to pass the PHY rather than the port (DDI).  For
2972                  * ICL, port=phy in all cases so it doesn't matter, but for
2973                  * EHL the bspec notes the following:
2974                  *
2975                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2976                  *   Clock Select chooses the PLL for both DDIA and DDID and
2977                  *   drives port A in all cases."
2978                  */
2979                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2980                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2981                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2982                 POSTING_READ(ICL_DPCLKA_CFGCR0);
2983         }
2984
2985         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2986         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2987
2988         mutex_unlock(&dev_priv->dpll_lock);
2989 }
2990
2991 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2992 {
2993         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2994         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2995         u32 val;
2996
2997         mutex_lock(&dev_priv->dpll_lock);
2998
2999         val = I915_READ(ICL_DPCLKA_CFGCR0);
3000         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3001         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
3002
3003         mutex_unlock(&dev_priv->dpll_lock);
3004 }
3005
3006 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
3007 {
3008         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3009         u32 val;
3010         enum port port;
3011         u32 port_mask;
3012         bool ddi_clk_needed;
3013
3014         /*
3015          * In case of DP MST, we sanitize the primary encoder only, not the
3016          * virtual ones.
3017          */
3018         if (encoder->type == INTEL_OUTPUT_DP_MST)
3019                 return;
3020
3021         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3022                 u8 pipe_mask;
3023                 bool is_mst;
3024
3025                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3026                 /*
3027                  * In the unlikely case that BIOS enables DP in MST mode, just
3028                  * warn since our MST HW readout is incomplete.
3029                  */
3030                 if (WARN_ON(is_mst))
3031                         return;
3032         }
3033
3034         port_mask = BIT(encoder->port);
3035         ddi_clk_needed = encoder->base.crtc;
3036
3037         if (encoder->type == INTEL_OUTPUT_DSI) {
3038                 struct intel_encoder *other_encoder;
3039
3040                 port_mask = intel_dsi_encoder_ports(encoder);
3041                 /*
3042                  * Sanity check that we haven't incorrectly registered another
3043                  * encoder using any of the ports of this DSI encoder.
3044                  */
3045                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3046                         if (other_encoder == encoder)
3047                                 continue;
3048
3049                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
3050                                 return;
3051                 }
3052                 /*
3053                  * For DSI we keep the ddi clocks gated
3054                  * except during enable/disable sequence.
3055                  */
3056                 ddi_clk_needed = false;
3057         }
3058
3059         val = I915_READ(ICL_DPCLKA_CFGCR0);
3060         for_each_port_masked(port, port_mask) {
3061                 enum phy phy = intel_port_to_phy(dev_priv, port);
3062
3063                 bool ddi_clk_ungated = !(val &
3064                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
3065                                                                    phy));
3066
3067                 if (ddi_clk_needed == ddi_clk_ungated)
3068                         continue;
3069
3070                 /*
3071                  * Punt on the case now where clock is gated, but it would
3072                  * be needed by the port. Something else is really broken then.
3073                  */
3074                 if (WARN_ON(ddi_clk_needed))
3075                         continue;
3076
3077                 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
3078                          phy_name(port));
3079                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3080                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
3081         }
3082 }
3083
3084 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3085                                  const struct intel_crtc_state *crtc_state)
3086 {
3087         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3088         enum port port = encoder->port;
3089         enum phy phy = intel_port_to_phy(dev_priv, port);
3090         u32 val;
3091         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3092
3093         if (WARN_ON(!pll))
3094                 return;
3095
3096         mutex_lock(&dev_priv->dpll_lock);
3097
3098         if (INTEL_GEN(dev_priv) >= 11) {
3099                 if (!intel_phy_is_combo(dev_priv, phy))
3100                         I915_WRITE(DDI_CLK_SEL(port),
3101                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3102                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3103                         /*
3104                          * MG does not exist but the programming is required
3105                          * to ungate DDIC and DDID
3106                          */
3107                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
3108         } else if (IS_CANNONLAKE(dev_priv)) {
3109                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3110                 val = I915_READ(DPCLKA_CFGCR0);
3111                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3112                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3113                 I915_WRITE(DPCLKA_CFGCR0, val);
3114
3115                 /*
3116                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3117                  * This step and the step before must be done with separate
3118                  * register writes.
3119                  */
3120                 val = I915_READ(DPCLKA_CFGCR0);
3121                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3122                 I915_WRITE(DPCLKA_CFGCR0, val);
3123         } else if (IS_GEN9_BC(dev_priv)) {
3124                 /* DDI -> PLL mapping  */
3125                 val = I915_READ(DPLL_CTRL2);
3126
3127                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3128                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3129                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3130                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3131
3132                 I915_WRITE(DPLL_CTRL2, val);
3133
3134         } else if (INTEL_GEN(dev_priv) < 9) {
3135                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
3136         }
3137
3138         mutex_unlock(&dev_priv->dpll_lock);
3139 }
3140
3141 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3142 {
3143         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3144         enum port port = encoder->port;
3145         enum phy phy = intel_port_to_phy(dev_priv, port);
3146
3147         if (INTEL_GEN(dev_priv) >= 11) {
3148                 if (!intel_phy_is_combo(dev_priv, phy) ||
3149                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3150                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
3151         } else if (IS_CANNONLAKE(dev_priv)) {
3152                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
3153                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3154         } else if (IS_GEN9_BC(dev_priv)) {
3155                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
3156                            DPLL_CTRL2_DDI_CLK_OFF(port));
3157         } else if (INTEL_GEN(dev_priv) < 9) {
3158                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3159         }
3160 }
3161
3162 static void
3163 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
3164 {
3165         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3166         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3167         u32 val, bits;
3168         int ln;
3169
3170         if (tc_port == PORT_TC_NONE)
3171                 return;
3172
3173         bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
3174                MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
3175                MG_DP_MODE_CFG_GAONPWR_GATING;
3176
3177         for (ln = 0; ln < 2; ln++) {
3178                 if (INTEL_GEN(dev_priv) >= 12) {
3179                         I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
3180                         val = I915_READ(DKL_DP_MODE(tc_port));
3181                 } else {
3182                         val = I915_READ(MG_DP_MODE(ln, tc_port));
3183                 }
3184
3185                 if (enable)
3186                         val |= bits;
3187                 else
3188                         val &= ~bits;
3189
3190                 if (INTEL_GEN(dev_priv) >= 12)
3191                         I915_WRITE(DKL_DP_MODE(tc_port), val);
3192                 else
3193                         I915_WRITE(MG_DP_MODE(ln, tc_port), val);
3194         }
3195
3196         if (INTEL_GEN(dev_priv) == 11) {
3197                 bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
3198                        MG_MISC_SUS0_CFG_CL2PWR_GATING |
3199                        MG_MISC_SUS0_CFG_GAONPWR_GATING |
3200                        MG_MISC_SUS0_CFG_TRPWR_GATING |
3201                        MG_MISC_SUS0_CFG_CL1PWR_GATING |
3202                        MG_MISC_SUS0_CFG_DGPWR_GATING;
3203
3204                 val = I915_READ(MG_MISC_SUS0(tc_port));
3205                 if (enable)
3206                         val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
3207                 else
3208                         val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
3209                 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3210         }
3211 }
3212
3213 static void
3214 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
3215                        const struct intel_crtc_state *crtc_state)
3216 {
3217         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3218         enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
3219         u32 ln0, ln1, pin_assignment;
3220         u8 width;
3221
3222         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3223                 return;
3224
3225         if (INTEL_GEN(dev_priv) >= 12) {
3226                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3227                 ln0 = I915_READ(DKL_DP_MODE(tc_port));
3228                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3229                 ln1 = I915_READ(DKL_DP_MODE(tc_port));
3230         } else {
3231                 ln0 = I915_READ(MG_DP_MODE(0, tc_port));
3232                 ln1 = I915_READ(MG_DP_MODE(1, tc_port));
3233         }
3234
3235         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
3236         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3237
3238         /* DPPATC */
3239         pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
3240         width = crtc_state->lane_count;
3241
3242         switch (pin_assignment) {
3243         case 0x0:
3244                 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
3245                 if (width == 1) {
3246                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3247                 } else {
3248                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3249                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3250                 }
3251                 break;
3252         case 0x1:
3253                 if (width == 4) {
3254                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3255                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3256                 }
3257                 break;
3258         case 0x2:
3259                 if (width == 2) {
3260                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3261                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3262                 }
3263                 break;
3264         case 0x3:
3265         case 0x5:
3266                 if (width == 1) {
3267                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3268                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3269                 } else {
3270                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3271                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3272                 }
3273                 break;
3274         case 0x4:
3275         case 0x6:
3276                 if (width == 1) {
3277                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3278                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3279                 } else {
3280                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3281                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3282                 }
3283                 break;
3284         default:
3285                 MISSING_CASE(pin_assignment);
3286         }
3287
3288         if (INTEL_GEN(dev_priv) >= 12) {
3289                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3290                 I915_WRITE(DKL_DP_MODE(tc_port), ln0);
3291                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3292                 I915_WRITE(DKL_DP_MODE(tc_port), ln1);
3293         } else {
3294                 I915_WRITE(MG_DP_MODE(0, tc_port), ln0);
3295                 I915_WRITE(MG_DP_MODE(1, tc_port), ln1);
3296         }
3297 }
3298
3299 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3300                                         const struct intel_crtc_state *crtc_state)
3301 {
3302         if (!crtc_state->fec_enable)
3303                 return;
3304
3305         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3306                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3307 }
3308
3309 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3310                                  const struct intel_crtc_state *crtc_state)
3311 {
3312         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3313         struct intel_dp *intel_dp;
3314         u32 val;
3315
3316         if (!crtc_state->fec_enable)
3317                 return;
3318
3319         intel_dp = enc_to_intel_dp(&encoder->base);
3320         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3321         val |= DP_TP_CTL_FEC_ENABLE;
3322         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3323
3324         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3325                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3326                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3327 }
3328
3329 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3330                                         const struct intel_crtc_state *crtc_state)
3331 {
3332         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3333         struct intel_dp *intel_dp;
3334         u32 val;
3335
3336         if (!crtc_state->fec_enable)
3337                 return;
3338
3339         intel_dp = enc_to_intel_dp(&encoder->base);
3340         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3341         val &= ~DP_TP_CTL_FEC_ENABLE;
3342         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3343         POSTING_READ(intel_dp->regs.dp_tp_ctl);
3344 }
3345
3346 static void
3347 tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3348 {
3349         struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
3350         u32 val;
3351
3352         if (!cstate->dc3co_exitline)
3353                 return;
3354
3355         val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3356         val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3357         I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3358 }
3359
3360 static void
3361 tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3362 {
3363         u32 val, exit_scanlines;
3364         struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
3365
3366         if (!cstate->dc3co_exitline)
3367                 return;
3368
3369         exit_scanlines = cstate->dc3co_exitline;
3370         exit_scanlines <<= EXITLINE_SHIFT;
3371         val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3372         val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3373         val |= exit_scanlines;
3374         val |= EXITLINE_ENABLE;
3375         I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3376 }
3377
3378 static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
3379                                               struct intel_crtc_state *cstate)
3380 {
3381         u32 exit_scanlines;
3382         struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
3383         u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
3384
3385         cstate->dc3co_exitline = 0;
3386
3387         if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
3388                 return;
3389
3390         /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
3391         if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A ||
3392             encoder->port != PORT_A)
3393                 return;
3394
3395         if (!cstate->has_psr2 || !cstate->hw.active)
3396                 return;
3397
3398         /*
3399          * DC3CO Exit time 200us B.Spec 49196
3400          * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
3401          */
3402         exit_scanlines =
3403                 intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1;
3404
3405         if (WARN_ON(exit_scanlines > crtc_vdisplay))
3406                 return;
3407
3408         cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
3409         DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
3410 }
3411
3412 static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
3413 {
3414         u32 val;
3415         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3416
3417         if (INTEL_GEN(dev_priv) < 12)
3418                 return;
3419
3420         val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
3421
3422         if (val & EXITLINE_ENABLE)
3423                 crtc_state->dc3co_exitline = val & EXITLINE_MASK;
3424 }
3425
3426 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
3427                                   const struct intel_crtc_state *crtc_state,
3428                                   const struct drm_connector_state *conn_state)
3429 {
3430         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3431         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3432         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3433         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3434         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3435         int level = intel_ddi_dp_level(intel_dp);
3436         enum transcoder transcoder = crtc_state->cpu_transcoder;
3437
3438         tgl_set_psr2_transcoder_exitline(crtc_state);
3439         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3440                                  crtc_state->lane_count, is_mst);
3441
3442         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3443         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3444
3445         /*
3446          * 1. Enable Power Wells
3447          *
3448          * This was handled at the beginning of intel_atomic_commit_tail(),
3449          * before we called down into this function.
3450          */
3451
3452         /* 2. Enable Panel Power if PPS is required */
3453         intel_edp_panel_on(intel_dp);
3454
3455         /*
3456          * 3. For non-TBT Type-C ports, set FIA lane count
3457          * (DFLEXDPSP.DPX4TXLATC)
3458          *
3459          * This was done before tgl_ddi_pre_enable_dp by
3460          * haswell_crtc_enable()->intel_encoders_pre_pll_enable().
3461          */
3462
3463         /*
3464          * 4. Enable the port PLL.
3465          *
3466          * The PLL enabling itself was already done before this function by
3467          * haswell_crtc_enable()->intel_enable_shared_dpll().  We need only
3468          * configure the PLL to port mapping here.
3469          */
3470         intel_ddi_clk_select(encoder, crtc_state);
3471
3472         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3473         if (!intel_phy_is_tc(dev_priv, phy) ||
3474             dig_port->tc_mode != TC_PORT_TBT_ALT)
3475                 intel_display_power_get(dev_priv,
3476                                         dig_port->ddi_io_power_domain);
3477
3478         /* 6. Program DP_MODE */
3479         icl_program_mg_dp_mode(dig_port, crtc_state);
3480
3481         /*
3482          * 7. The rest of the below are substeps under the bspec's "Enable and
3483          * Train Display Port" step.  Note that steps that are specific to
3484          * MST will be handled by intel_mst_pre_enable_dp() before/after it
3485          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
3486          * us when active_mst_links==0, so any steps designated for "single
3487          * stream or multi-stream master transcoder" can just be performed
3488          * unconditionally here.
3489          */
3490
3491         /*
3492          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3493          * Transcoder.
3494          */
3495         intel_ddi_enable_pipe_clock(crtc_state);
3496
3497         /*
3498          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3499          * Transport Select
3500          */
3501         intel_ddi_config_transcoder_func(crtc_state);
3502
3503         /*
3504          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3505          * selected
3506          *
3507          * This will be handled by the intel_dp_start_link_train() farther
3508          * down this function.
3509          */
3510
3511         /*
3512          * 7.d Type C with DP alternate or fixed/legacy/static connection -
3513          * Disable PHY clock gating per Type-C DDI Buffer page
3514          */
3515         icl_phy_set_clock_gating(dig_port, false);
3516
3517         /* 7.e Configure voltage swing and related IO settings */
3518         tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3519                                 encoder->type);
3520
3521         /*
3522          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3523          * the used lanes of the DDI.
3524          */
3525         if (intel_phy_is_combo(dev_priv, phy)) {
3526                 bool lane_reversal =
3527                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3528
3529                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3530                                                crtc_state->lane_count,
3531                                                lane_reversal);
3532         }
3533
3534         /*
3535          * 7.g Configure and enable DDI_BUF_CTL
3536          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3537          *     after 500 us.
3538          *
3539          * We only configure what the register value will be here.  Actual
3540          * enabling happens during link training farther down.
3541          */
3542         intel_ddi_init_dp_buf_reg(encoder);
3543
3544         if (!is_mst)
3545                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3546
3547         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3548         /*
3549          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3550          * in the FEC_CONFIGURATION register to 1 before initiating link
3551          * training
3552          */
3553         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3554
3555         /*
3556          * 7.i Follow DisplayPort specification training sequence (see notes for
3557          *     failure handling)
3558          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3559          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3560          *     (timeout after 800 us)
3561          */
3562         intel_dp_start_link_train(intel_dp);
3563
3564         /* 7.k Set DP_TP_CTL link training to Normal */
3565         if (!is_trans_port_sync_mode(crtc_state))
3566                 intel_dp_stop_link_train(intel_dp);
3567
3568         /*
3569          * TODO: enable clock gating
3570          *
3571          * It is not written in DP enabling sequence but "PHY Clockgating
3572          * programming" states that clock gating should be enabled after the
3573          * link training but doing so causes all the following trainings to fail
3574          * so not enabling it for now.
3575          */
3576
3577         /* 7.l Configure and enable FEC if needed */
3578         intel_ddi_enable_fec(encoder, crtc_state);
3579         intel_dsc_enable(encoder, crtc_state);
3580 }
3581
3582 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3583                                   const struct intel_crtc_state *crtc_state,
3584                                   const struct drm_connector_state *conn_state)
3585 {
3586         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3587         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3588         enum port port = encoder->port;
3589         enum phy phy = intel_port_to_phy(dev_priv, port);
3590         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3591         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3592         int level = intel_ddi_dp_level(intel_dp);
3593
3594         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3595
3596         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3597                                  crtc_state->lane_count, is_mst);
3598
3599         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3600         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3601
3602         intel_edp_panel_on(intel_dp);
3603
3604         intel_ddi_clk_select(encoder, crtc_state);
3605
3606         if (!intel_phy_is_tc(dev_priv, phy) ||
3607             dig_port->tc_mode != TC_PORT_TBT_ALT)
3608                 intel_display_power_get(dev_priv,
3609                                         dig_port->ddi_io_power_domain);
3610
3611         icl_program_mg_dp_mode(dig_port, crtc_state);
3612         icl_phy_set_clock_gating(dig_port, false);
3613
3614         if (INTEL_GEN(dev_priv) >= 11)
3615                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3616                                         level, encoder->type);
3617         else if (IS_CANNONLAKE(dev_priv))
3618                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3619         else if (IS_GEN9_LP(dev_priv))
3620                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3621         else
3622                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3623
3624         if (intel_phy_is_combo(dev_priv, phy)) {
3625                 bool lane_reversal =
3626                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3627
3628                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3629                                                crtc_state->lane_count,
3630                                                lane_reversal);
3631         }
3632
3633         intel_ddi_init_dp_buf_reg(encoder);
3634         if (!is_mst)
3635                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3636         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3637                                               true);
3638         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3639         intel_dp_start_link_train(intel_dp);
3640         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3641             !is_trans_port_sync_mode(crtc_state))
3642                 intel_dp_stop_link_train(intel_dp);
3643
3644         intel_ddi_enable_fec(encoder, crtc_state);
3645
3646         icl_phy_set_clock_gating(dig_port, true);
3647
3648         if (!is_mst)
3649                 intel_ddi_enable_pipe_clock(crtc_state);
3650
3651         intel_dsc_enable(encoder, crtc_state);
3652 }
3653
3654 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3655                                     const struct intel_crtc_state *crtc_state,
3656                                     const struct drm_connector_state *conn_state)
3657 {
3658         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3659
3660         if (INTEL_GEN(dev_priv) >= 12)
3661                 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3662         else
3663                 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3664
3665         /* MST will call a setting of MSA after an allocating of Virtual Channel
3666          * from MST encoder pre_enable callback.
3667          */
3668         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
3669                 intel_ddi_set_dp_msa(crtc_state, conn_state);
3670 }
3671
3672 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3673                                       const struct intel_crtc_state *crtc_state,
3674                                       const struct drm_connector_state *conn_state)
3675 {
3676         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3677         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3678         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3679         enum port port = encoder->port;
3680         int level = intel_ddi_hdmi_level(dev_priv, port);
3681         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3682
3683         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3684         intel_ddi_clk_select(encoder, crtc_state);
3685
3686         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3687
3688         icl_program_mg_dp_mode(dig_port, crtc_state);
3689         icl_phy_set_clock_gating(dig_port, false);
3690
3691         if (INTEL_GEN(dev_priv) >= 12)
3692                 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3693                                         level, INTEL_OUTPUT_HDMI);
3694         else if (INTEL_GEN(dev_priv) == 11)
3695                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3696                                         level, INTEL_OUTPUT_HDMI);
3697         else if (IS_CANNONLAKE(dev_priv))
3698                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3699         else if (IS_GEN9_LP(dev_priv))
3700                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3701         else
3702                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3703
3704         icl_phy_set_clock_gating(dig_port, true);
3705
3706         if (IS_GEN9_BC(dev_priv))
3707                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3708
3709         intel_ddi_enable_pipe_clock(crtc_state);
3710
3711         intel_dig_port->set_infoframes(encoder,
3712                                        crtc_state->has_infoframe,
3713                                        crtc_state, conn_state);
3714 }
3715
3716 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3717                                  const struct intel_crtc_state *crtc_state,
3718                                  const struct drm_connector_state *conn_state)
3719 {
3720         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3721         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3722         enum pipe pipe = crtc->pipe;
3723
3724         /*
3725          * When called from DP MST code:
3726          * - conn_state will be NULL
3727          * - encoder will be the main encoder (ie. mst->primary)
3728          * - the main connector associated with this port
3729          *   won't be active or linked to a crtc
3730          * - crtc_state will be the state of the first stream to
3731          *   be activated on this port, and it may not be the same
3732          *   stream that will be deactivated last, but each stream
3733          *   should have a state that is identical when it comes to
3734          *   the DP link parameteres
3735          */
3736
3737         WARN_ON(crtc_state->has_pch_encoder);
3738
3739         if (INTEL_GEN(dev_priv) >= 11)
3740                 icl_map_plls_to_ports(encoder, crtc_state);
3741
3742         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3743
3744         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3745                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3746         } else {
3747                 struct intel_lspcon *lspcon =
3748                                 enc_to_intel_lspcon(&encoder->base);
3749
3750                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3751                 if (lspcon->active) {
3752                         struct intel_digital_port *dig_port =
3753                                         enc_to_dig_port(&encoder->base);
3754
3755                         dig_port->set_infoframes(encoder,
3756                                                  crtc_state->has_infoframe,
3757                                                  crtc_state, conn_state);
3758                 }
3759         }
3760 }
3761
3762 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3763                                   const struct intel_crtc_state *crtc_state)
3764 {
3765         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3766         enum port port = encoder->port;
3767         bool wait = false;
3768         u32 val;
3769
3770         val = I915_READ(DDI_BUF_CTL(port));
3771         if (val & DDI_BUF_CTL_ENABLE) {
3772                 val &= ~DDI_BUF_CTL_ENABLE;
3773                 I915_WRITE(DDI_BUF_CTL(port), val);
3774                 wait = true;
3775         }
3776
3777         if (intel_crtc_has_dp_encoder(crtc_state)) {
3778                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3779
3780                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3781                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3782                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3783                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3784         }
3785
3786         /* Disable FEC in DP Sink */
3787         intel_ddi_disable_fec_state(encoder, crtc_state);
3788
3789         if (wait)
3790                 intel_wait_ddi_buf_idle(dev_priv, port);
3791 }
3792
3793 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3794                                       const struct intel_crtc_state *old_crtc_state,
3795                                       const struct drm_connector_state *old_conn_state)
3796 {
3797         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3798         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3799         struct intel_dp *intel_dp = &dig_port->dp;
3800         bool is_mst = intel_crtc_has_type(old_crtc_state,
3801                                           INTEL_OUTPUT_DP_MST);
3802         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3803
3804         /*
3805          * Power down sink before disabling the port, otherwise we end
3806          * up getting interrupts from the sink on detecting link loss.
3807          */
3808         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3809
3810         if (INTEL_GEN(dev_priv) < 12 && !is_mst)
3811                 intel_ddi_disable_pipe_clock(old_crtc_state);
3812
3813         intel_disable_ddi_buf(encoder, old_crtc_state);
3814
3815         /*
3816          * From TGL spec: "If single stream or multi-stream master transcoder:
3817          * Configure Transcoder Clock select to direct no clock to the
3818          * transcoder"
3819          */
3820         if (INTEL_GEN(dev_priv) >= 12)
3821                 intel_ddi_disable_pipe_clock(old_crtc_state);
3822
3823         intel_edp_panel_vdd_on(intel_dp);
3824         intel_edp_panel_off(intel_dp);
3825
3826         if (!intel_phy_is_tc(dev_priv, phy) ||
3827             dig_port->tc_mode != TC_PORT_TBT_ALT)
3828                 intel_display_power_put_unchecked(dev_priv,
3829                                                   dig_port->ddi_io_power_domain);
3830
3831         intel_ddi_clk_disable(encoder);
3832         tgl_clear_psr2_transcoder_exitline(old_crtc_state);
3833 }
3834
3835 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3836                                         const struct intel_crtc_state *old_crtc_state,
3837                                         const struct drm_connector_state *old_conn_state)
3838 {
3839         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3840         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3841         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3842
3843         dig_port->set_infoframes(encoder, false,
3844                                  old_crtc_state, old_conn_state);
3845
3846         intel_ddi_disable_pipe_clock(old_crtc_state);
3847
3848         intel_disable_ddi_buf(encoder, old_crtc_state);
3849
3850         intel_display_power_put_unchecked(dev_priv,
3851                                           dig_port->ddi_io_power_domain);
3852
3853         intel_ddi_clk_disable(encoder);
3854
3855         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3856 }
3857
3858 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3859                                    const struct intel_crtc_state *old_crtc_state,
3860                                    const struct drm_connector_state *old_conn_state)
3861 {
3862         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3863
3864         /*
3865          * When called from DP MST code:
3866          * - old_conn_state will be NULL
3867          * - encoder will be the main encoder (ie. mst->primary)
3868          * - the main connector associated with this port
3869          *   won't be active or linked to a crtc
3870          * - old_crtc_state will be the state of the last stream to
3871          *   be deactivated on this port, and it may not be the same
3872          *   stream that was activated last, but each stream
3873          *   should have a state that is identical when it comes to
3874          *   the DP link parameteres
3875          */
3876
3877         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3878                 intel_ddi_post_disable_hdmi(encoder,
3879                                             old_crtc_state, old_conn_state);
3880         else
3881                 intel_ddi_post_disable_dp(encoder,
3882                                           old_crtc_state, old_conn_state);
3883
3884         if (INTEL_GEN(dev_priv) >= 11)
3885                 icl_unmap_plls_to_ports(encoder);
3886 }
3887
3888 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3889                                 const struct intel_crtc_state *old_crtc_state,
3890                                 const struct drm_connector_state *old_conn_state)
3891 {
3892         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3893         u32 val;
3894
3895         /*
3896          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3897          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3898          * step 13 is the correct place for it. Step 18 is where it was
3899          * originally before the BUN.
3900          */
3901         val = I915_READ(FDI_RX_CTL(PIPE_A));
3902         val &= ~FDI_RX_ENABLE;
3903         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3904
3905         intel_disable_ddi_buf(encoder, old_crtc_state);
3906         intel_ddi_clk_disable(encoder);
3907
3908         val = I915_READ(FDI_RX_MISC(PIPE_A));
3909         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3910         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3911         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3912
3913         val = I915_READ(FDI_RX_CTL(PIPE_A));
3914         val &= ~FDI_PCDCLK;
3915         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3916
3917         val = I915_READ(FDI_RX_CTL(PIPE_A));
3918         val &= ~FDI_RX_PLL_ENABLE;
3919         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3920 }
3921
3922 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3923                                 const struct intel_crtc_state *crtc_state,
3924                                 const struct drm_connector_state *conn_state)
3925 {
3926         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3927         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3928         enum port port = encoder->port;
3929
3930         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3931                 intel_dp_stop_link_train(intel_dp);
3932
3933         intel_edp_backlight_on(crtc_state, conn_state);
3934         intel_psr_enable(intel_dp, crtc_state);
3935         intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
3936         intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
3937         intel_edp_drrs_enable(intel_dp, crtc_state);
3938
3939         if (crtc_state->has_audio)
3940                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3941 }
3942
3943 static i915_reg_t
3944 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3945                                enum port port)
3946 {
3947         static const enum transcoder trans[] = {
3948                 [PORT_A] = TRANSCODER_EDP,
3949                 [PORT_B] = TRANSCODER_A,
3950                 [PORT_C] = TRANSCODER_B,
3951                 [PORT_D] = TRANSCODER_C,
3952                 [PORT_E] = TRANSCODER_A,
3953         };
3954
3955         WARN_ON(INTEL_GEN(dev_priv) < 9);
3956
3957         if (WARN_ON(port < PORT_A || port > PORT_E))
3958                 port = PORT_A;
3959
3960         return CHICKEN_TRANS(trans[port]);
3961 }
3962
3963 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3964                                   const struct intel_crtc_state *crtc_state,
3965                                   const struct drm_connector_state *conn_state)
3966 {
3967         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3968         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3969         struct drm_connector *connector = conn_state->connector;
3970         enum port port = encoder->port;
3971
3972         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3973                                                crtc_state->hdmi_high_tmds_clock_ratio,
3974                                                crtc_state->hdmi_scrambling))
3975                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3976                           connector->base.id, connector->name);
3977
3978         /* Display WA #1143: skl,kbl,cfl */
3979         if (IS_GEN9_BC(dev_priv)) {
3980                 /*
3981                  * For some reason these chicken bits have been
3982                  * stuffed into a transcoder register, event though
3983                  * the bits affect a specific DDI port rather than
3984                  * a specific transcoder.
3985                  */
3986                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3987                 u32 val;
3988
3989                 val = I915_READ(reg);
3990
3991                 if (port == PORT_E)
3992                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3993                                 DDIE_TRAINING_OVERRIDE_VALUE;
3994                 else
3995                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3996                                 DDI_TRAINING_OVERRIDE_VALUE;
3997
3998                 I915_WRITE(reg, val);
3999                 POSTING_READ(reg);
4000
4001                 udelay(1);
4002
4003                 if (port == PORT_E)
4004                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
4005                                  DDIE_TRAINING_OVERRIDE_VALUE);
4006                 else
4007                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
4008                                  DDI_TRAINING_OVERRIDE_VALUE);
4009
4010                 I915_WRITE(reg, val);
4011         }
4012
4013         /* In HDMI/DVI mode, the port width, and swing/emphasis values
4014          * are ignored so nothing special needs to be done besides
4015          * enabling the port.
4016          */
4017         I915_WRITE(DDI_BUF_CTL(port),
4018                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
4019
4020         if (crtc_state->has_audio)
4021                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
4022 }
4023
4024 static void intel_enable_ddi(struct intel_encoder *encoder,
4025                              const struct intel_crtc_state *crtc_state,
4026                              const struct drm_connector_state *conn_state)
4027 {
4028         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4029                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
4030         else
4031                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
4032
4033         /* Enable hdcp if it's desired */
4034         if (conn_state->content_protection ==
4035             DRM_MODE_CONTENT_PROTECTION_DESIRED)
4036                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
4037                                   crtc_state->cpu_transcoder,
4038                                   (u8)conn_state->hdcp_content_type);
4039 }
4040
4041 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
4042                                  const struct intel_crtc_state *old_crtc_state,
4043                                  const struct drm_connector_state *old_conn_state)
4044 {
4045         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4046
4047         intel_dp->link_trained = false;
4048
4049         if (old_crtc_state->has_audio)
4050                 intel_audio_codec_disable(encoder,
4051                                           old_crtc_state, old_conn_state);
4052
4053         intel_edp_drrs_disable(intel_dp, old_crtc_state);
4054         intel_psr_disable(intel_dp, old_crtc_state);
4055         intel_edp_backlight_off(old_conn_state);
4056         /* Disable the decompression in DP Sink */
4057         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
4058                                               false);
4059 }
4060
4061 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
4062                                    const struct intel_crtc_state *old_crtc_state,
4063                                    const struct drm_connector_state *old_conn_state)
4064 {
4065         struct drm_connector *connector = old_conn_state->connector;
4066
4067         if (old_crtc_state->has_audio)
4068                 intel_audio_codec_disable(encoder,
4069                                           old_crtc_state, old_conn_state);
4070
4071         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4072                                                false, false))
4073                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4074                               connector->base.id, connector->name);
4075 }
4076
4077 static void intel_disable_ddi(struct intel_encoder *encoder,
4078                               const struct intel_crtc_state *old_crtc_state,
4079                               const struct drm_connector_state *old_conn_state)
4080 {
4081         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4082
4083         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4084                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
4085         else
4086                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
4087 }
4088
4089 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
4090                                      const struct intel_crtc_state *crtc_state,
4091                                      const struct drm_connector_state *conn_state)
4092 {
4093         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4094
4095         intel_ddi_set_dp_msa(crtc_state, conn_state);
4096
4097         intel_psr_update(intel_dp, crtc_state);
4098         intel_edp_drrs_enable(intel_dp, crtc_state);
4099
4100         intel_panel_update_backlight(encoder, crtc_state, conn_state);
4101 }
4102
4103 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
4104                                   const struct intel_crtc_state *crtc_state,
4105                                   const struct drm_connector_state *conn_state)
4106 {
4107         struct intel_connector *connector =
4108                                 to_intel_connector(conn_state->connector);
4109         struct intel_hdcp *hdcp = &connector->hdcp;
4110         bool content_protection_type_changed =
4111                         (conn_state->hdcp_content_type != hdcp->content_type &&
4112                          conn_state->content_protection !=
4113                          DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
4114
4115         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4116                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
4117
4118         /*
4119          * During the HDCP encryption session if Type change is requested,
4120          * disable the HDCP and reenable it with new TYPE value.
4121          */
4122         if (conn_state->content_protection ==
4123             DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
4124             content_protection_type_changed)
4125                 intel_hdcp_disable(connector);
4126
4127         /*
4128          * Mark the hdcp state as DESIRED after the hdcp disable of type
4129          * change procedure.
4130          */
4131         if (content_protection_type_changed) {
4132                 mutex_lock(&hdcp->mutex);
4133                 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
4134                 schedule_work(&hdcp->prop_work);
4135                 mutex_unlock(&hdcp->mutex);
4136         }
4137
4138         if (conn_state->content_protection ==
4139             DRM_MODE_CONTENT_PROTECTION_DESIRED ||
4140             content_protection_type_changed)
4141                 intel_hdcp_enable(connector,
4142                                   crtc_state->cpu_transcoder,
4143                                   (u8)conn_state->hdcp_content_type);
4144 }
4145
4146 static void
4147 intel_ddi_update_prepare(struct intel_atomic_state *state,
4148                          struct intel_encoder *encoder,
4149                          struct intel_crtc *crtc)
4150 {
4151         struct intel_crtc_state *crtc_state =
4152                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4153         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4154
4155         WARN_ON(crtc && crtc->active);
4156
4157         intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
4158         if (crtc_state && crtc_state->hw.active)
4159                 intel_update_active_dpll(state, crtc, encoder);
4160 }
4161
4162 static void
4163 intel_ddi_update_complete(struct intel_atomic_state *state,
4164                           struct intel_encoder *encoder,
4165                           struct intel_crtc *crtc)
4166 {
4167         intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
4168 }
4169
4170 static void
4171 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
4172                          const struct intel_crtc_state *crtc_state,
4173                          const struct drm_connector_state *conn_state)
4174 {
4175         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4176         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4177         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4178         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4179
4180         if (is_tc_port)
4181                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4182
4183         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4184                 intel_display_power_get(dev_priv,
4185                                         intel_ddi_main_link_aux_domain(dig_port));
4186
4187         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4188                 /*
4189                  * Program the lane count for static/dynamic connections on
4190                  * Type-C ports.  Skip this step for TBT.
4191                  */
4192                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4193         else if (IS_GEN9_LP(dev_priv))
4194                 bxt_ddi_phy_set_lane_optim_mask(encoder,
4195                                                 crtc_state->lane_lat_optim_mask);
4196 }
4197
4198 static void
4199 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
4200                            const struct intel_crtc_state *crtc_state,
4201                            const struct drm_connector_state *conn_state)
4202 {
4203         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4204         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4205         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4206         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4207
4208         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4209                 intel_display_power_put_unchecked(dev_priv,
4210                                                   intel_ddi_main_link_aux_domain(dig_port));
4211
4212         if (is_tc_port)
4213                 intel_tc_port_put_link(dig_port);
4214 }
4215
4216 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4217 {
4218         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4219         struct drm_i915_private *dev_priv =
4220                 to_i915(intel_dig_port->base.base.dev);
4221         enum port port = intel_dig_port->base.port;
4222         u32 dp_tp_ctl, ddi_buf_ctl;
4223         bool wait = false;
4224
4225         dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
4226
4227         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4228                 ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port));
4229                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4230                         I915_WRITE(DDI_BUF_CTL(port),
4231                                    ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
4232                         wait = true;
4233                 }
4234
4235                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4236                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4237                 I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4238                 POSTING_READ(intel_dp->regs.dp_tp_ctl);
4239
4240                 if (wait)
4241                         intel_wait_ddi_buf_idle(dev_priv, port);
4242         }
4243
4244         dp_tp_ctl = DP_TP_CTL_ENABLE |
4245                     DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
4246         if (intel_dp->link_mst)
4247                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
4248         else {
4249                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
4250                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4251                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4252         }
4253         I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4254         POSTING_READ(intel_dp->regs.dp_tp_ctl);
4255
4256         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4257         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
4258         POSTING_READ(DDI_BUF_CTL(port));
4259
4260         udelay(600);
4261 }
4262
4263 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4264                                        enum transcoder cpu_transcoder)
4265 {
4266         if (cpu_transcoder == TRANSCODER_EDP)
4267                 return false;
4268
4269         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4270                 return false;
4271
4272         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
4273                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4274 }
4275
4276 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4277                                          struct intel_crtc_state *crtc_state)
4278 {
4279         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4280                 crtc_state->min_voltage_level = 1;
4281         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4282                 crtc_state->min_voltage_level = 2;
4283 }
4284
4285 void intel_ddi_get_config(struct intel_encoder *encoder,
4286                           struct intel_crtc_state *pipe_config)
4287 {
4288         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4289         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4290         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4291         u32 temp, flags = 0;
4292
4293         /* XXX: DSI transcoder paranoia */
4294         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
4295                 return;
4296
4297         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
4298         if (temp & TRANS_DDI_PHSYNC)
4299                 flags |= DRM_MODE_FLAG_PHSYNC;
4300         else
4301                 flags |= DRM_MODE_FLAG_NHSYNC;
4302         if (temp & TRANS_DDI_PVSYNC)
4303                 flags |= DRM_MODE_FLAG_PVSYNC;
4304         else
4305                 flags |= DRM_MODE_FLAG_NVSYNC;
4306
4307         pipe_config->hw.adjusted_mode.flags |= flags;
4308
4309         switch (temp & TRANS_DDI_BPC_MASK) {
4310         case TRANS_DDI_BPC_6:
4311                 pipe_config->pipe_bpp = 18;
4312                 break;
4313         case TRANS_DDI_BPC_8:
4314                 pipe_config->pipe_bpp = 24;
4315                 break;
4316         case TRANS_DDI_BPC_10:
4317                 pipe_config->pipe_bpp = 30;
4318                 break;
4319         case TRANS_DDI_BPC_12:
4320                 pipe_config->pipe_bpp = 36;
4321                 break;
4322         default:
4323                 break;
4324         }
4325
4326         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4327         case TRANS_DDI_MODE_SELECT_HDMI:
4328                 pipe_config->has_hdmi_sink = true;
4329
4330                 pipe_config->infoframes.enable |=
4331                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4332
4333                 if (pipe_config->infoframes.enable)
4334                         pipe_config->has_infoframe = true;
4335
4336                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4337                         pipe_config->hdmi_scrambling = true;
4338                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4339                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4340                 /* fall through */
4341         case TRANS_DDI_MODE_SELECT_DVI:
4342                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4343                 pipe_config->lane_count = 4;
4344                 break;
4345         case TRANS_DDI_MODE_SELECT_FDI:
4346                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4347                 break;
4348         case TRANS_DDI_MODE_SELECT_DP_SST:
4349                 if (encoder->type == INTEL_OUTPUT_EDP)
4350                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4351                 else
4352                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4353                 pipe_config->lane_count =
4354                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4355                 intel_dp_get_m_n(intel_crtc, pipe_config);
4356
4357                 if (INTEL_GEN(dev_priv) >= 11) {
4358                         i915_reg_t dp_tp_ctl;
4359
4360                         if (IS_GEN(dev_priv, 11))
4361                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4362                         else
4363                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4364
4365                         pipe_config->fec_enable =
4366                                 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4367
4368                         DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
4369                                       encoder->base.base.id, encoder->base.name,
4370                                       pipe_config->fec_enable);
4371                 }
4372
4373                 break;
4374         case TRANS_DDI_MODE_SELECT_DP_MST:
4375                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4376                 pipe_config->lane_count =
4377                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4378                 intel_dp_get_m_n(intel_crtc, pipe_config);
4379                 break;
4380         default:
4381                 break;
4382         }
4383
4384         if (encoder->type == INTEL_OUTPUT_EDP)
4385                 tgl_dc3co_exitline_get_config(pipe_config);
4386
4387         pipe_config->has_audio =
4388                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4389
4390         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4391             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4392                 /*
4393                  * This is a big fat ugly hack.
4394                  *
4395                  * Some machines in UEFI boot mode provide us a VBT that has 18
4396                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4397                  * unknown we fail to light up. Yet the same BIOS boots up with
4398                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4399                  * max, not what it tells us to use.
4400                  *
4401                  * Note: This will still be broken if the eDP panel is not lit
4402                  * up by the BIOS, and thus we can't get the mode at module
4403                  * load.
4404                  */
4405                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4406                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4407                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4408         }
4409
4410         intel_ddi_clock_get(encoder, pipe_config);
4411
4412         if (IS_GEN9_LP(dev_priv))
4413                 pipe_config->lane_lat_optim_mask =
4414                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4415
4416         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4417
4418         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4419
4420         intel_read_infoframe(encoder, pipe_config,
4421                              HDMI_INFOFRAME_TYPE_AVI,
4422                              &pipe_config->infoframes.avi);
4423         intel_read_infoframe(encoder, pipe_config,
4424                              HDMI_INFOFRAME_TYPE_SPD,
4425                              &pipe_config->infoframes.spd);
4426         intel_read_infoframe(encoder, pipe_config,
4427                              HDMI_INFOFRAME_TYPE_VENDOR,
4428                              &pipe_config->infoframes.hdmi);
4429         intel_read_infoframe(encoder, pipe_config,
4430                              HDMI_INFOFRAME_TYPE_DRM,
4431                              &pipe_config->infoframes.drm);
4432 }
4433
4434 static enum intel_output_type
4435 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4436                               struct intel_crtc_state *crtc_state,
4437                               struct drm_connector_state *conn_state)
4438 {
4439         switch (conn_state->connector->connector_type) {
4440         case DRM_MODE_CONNECTOR_HDMIA:
4441                 return INTEL_OUTPUT_HDMI;
4442         case DRM_MODE_CONNECTOR_eDP:
4443                 return INTEL_OUTPUT_EDP;
4444         case DRM_MODE_CONNECTOR_DisplayPort:
4445                 return INTEL_OUTPUT_DP;
4446         default:
4447                 MISSING_CASE(conn_state->connector->connector_type);
4448                 return INTEL_OUTPUT_UNUSED;
4449         }
4450 }
4451
4452 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4453                                     struct intel_crtc_state *pipe_config,
4454                                     struct drm_connector_state *conn_state)
4455 {
4456         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4457         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4458         enum port port = encoder->port;
4459         int ret;
4460
4461         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
4462                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4463
4464         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4465                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4466         } else {
4467                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4468                 tgl_dc3co_exitline_compute_config(encoder, pipe_config);
4469         }
4470
4471         if (ret)
4472                 return ret;
4473
4474         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4475             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4476                 pipe_config->pch_pfit.force_thru =
4477                         pipe_config->pch_pfit.enabled ||
4478                         pipe_config->crc_enabled;
4479
4480         if (IS_GEN9_LP(dev_priv))
4481                 pipe_config->lane_lat_optim_mask =
4482                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4483
4484         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4485
4486         return 0;
4487 }
4488
4489 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4490 {
4491         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4492
4493         intel_dp_encoder_flush_work(encoder);
4494
4495         drm_encoder_cleanup(encoder);
4496         kfree(dig_port);
4497 }
4498
4499 static const struct drm_encoder_funcs intel_ddi_funcs = {
4500         .reset = intel_dp_encoder_reset,
4501         .destroy = intel_ddi_encoder_destroy,
4502 };
4503
4504 static struct intel_connector *
4505 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4506 {
4507         struct intel_connector *connector;
4508         enum port port = intel_dig_port->base.port;
4509
4510         connector = intel_connector_alloc();
4511         if (!connector)
4512                 return NULL;
4513
4514         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4515         intel_dig_port->dp.prepare_link_retrain =
4516                 intel_ddi_prepare_link_retrain;
4517
4518         if (!intel_dp_init_connector(intel_dig_port, connector)) {
4519                 kfree(connector);
4520                 return NULL;
4521         }
4522
4523         return connector;
4524 }
4525
4526 static int modeset_pipe(struct drm_crtc *crtc,
4527                         struct drm_modeset_acquire_ctx *ctx)
4528 {
4529         struct drm_atomic_state *state;
4530         struct drm_crtc_state *crtc_state;
4531         int ret;
4532
4533         state = drm_atomic_state_alloc(crtc->dev);
4534         if (!state)
4535                 return -ENOMEM;
4536
4537         state->acquire_ctx = ctx;
4538
4539         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4540         if (IS_ERR(crtc_state)) {
4541                 ret = PTR_ERR(crtc_state);
4542                 goto out;
4543         }
4544
4545         crtc_state->connectors_changed = true;
4546
4547         ret = drm_atomic_commit(state);
4548 out:
4549         drm_atomic_state_put(state);
4550
4551         return ret;
4552 }
4553
4554 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4555                                  struct drm_modeset_acquire_ctx *ctx)
4556 {
4557         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4558         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4559         struct intel_connector *connector = hdmi->attached_connector;
4560         struct i2c_adapter *adapter =
4561                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4562         struct drm_connector_state *conn_state;
4563         struct intel_crtc_state *crtc_state;
4564         struct intel_crtc *crtc;
4565         u8 config;
4566         int ret;
4567
4568         if (!connector || connector->base.status != connector_status_connected)
4569                 return 0;
4570
4571         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4572                                ctx);
4573         if (ret)
4574                 return ret;
4575
4576         conn_state = connector->base.state;
4577
4578         crtc = to_intel_crtc(conn_state->crtc);
4579         if (!crtc)
4580                 return 0;
4581
4582         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4583         if (ret)
4584                 return ret;
4585
4586         crtc_state = to_intel_crtc_state(crtc->base.state);
4587
4588         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4589
4590         if (!crtc_state->hw.active)
4591                 return 0;
4592
4593         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4594             !crtc_state->hdmi_scrambling)
4595                 return 0;
4596
4597         if (conn_state->commit &&
4598             !try_wait_for_completion(&conn_state->commit->hw_done))
4599                 return 0;
4600
4601         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4602         if (ret < 0) {
4603                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4604                 return 0;
4605         }
4606
4607         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4608             crtc_state->hdmi_high_tmds_clock_ratio &&
4609             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4610             crtc_state->hdmi_scrambling)
4611                 return 0;
4612
4613         /*
4614          * HDMI 2.0 says that one should not send scrambled data
4615          * prior to configuring the sink scrambling, and that
4616          * TMDS clock/data transmission should be suspended when
4617          * changing the TMDS clock rate in the sink. So let's
4618          * just do a full modeset here, even though some sinks
4619          * would be perfectly happy if were to just reconfigure
4620          * the SCDC settings on the fly.
4621          */
4622         return modeset_pipe(&crtc->base, ctx);
4623 }
4624
4625 static enum intel_hotplug_state
4626 intel_ddi_hotplug(struct intel_encoder *encoder,
4627                   struct intel_connector *connector,
4628                   bool irq_received)
4629 {
4630         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4631         struct drm_modeset_acquire_ctx ctx;
4632         enum intel_hotplug_state state;
4633         int ret;
4634
4635         state = intel_encoder_hotplug(encoder, connector, irq_received);
4636
4637         drm_modeset_acquire_init(&ctx, 0);
4638
4639         for (;;) {
4640                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4641                         ret = intel_hdmi_reset_link(encoder, &ctx);
4642                 else
4643                         ret = intel_dp_retrain_link(encoder, &ctx);
4644
4645                 if (ret == -EDEADLK) {
4646                         drm_modeset_backoff(&ctx);
4647                         continue;
4648                 }
4649
4650                 break;
4651         }
4652
4653         drm_modeset_drop_locks(&ctx);
4654         drm_modeset_acquire_fini(&ctx);
4655         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4656
4657         /*
4658          * Unpowered type-c dongles can take some time to boot and be
4659          * responsible, so here giving some time to those dongles to power up
4660          * and then retrying the probe.
4661          *
4662          * On many platforms the HDMI live state signal is known to be
4663          * unreliable, so we can't use it to detect if a sink is connected or
4664          * not. Instead we detect if it's connected based on whether we can
4665          * read the EDID or not. That in turn has a problem during disconnect,
4666          * since the HPD interrupt may be raised before the DDC lines get
4667          * disconnected (due to how the required length of DDC vs. HPD
4668          * connector pins are specified) and so we'll still be able to get a
4669          * valid EDID. To solve this schedule another detection cycle if this
4670          * time around we didn't detect any change in the sink's connection
4671          * status.
4672          */
4673         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4674             !dig_port->dp.is_mst)
4675                 state = INTEL_HOTPLUG_RETRY;
4676
4677         return state;
4678 }
4679
4680 static struct intel_connector *
4681 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4682 {
4683         struct intel_connector *connector;
4684         enum port port = intel_dig_port->base.port;
4685
4686         connector = intel_connector_alloc();
4687         if (!connector)
4688                 return NULL;
4689
4690         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4691         intel_hdmi_init_connector(intel_dig_port, connector);
4692
4693         return connector;
4694 }
4695
4696 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4697 {
4698         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4699
4700         if (dport->base.port != PORT_A)
4701                 return false;
4702
4703         if (dport->saved_port_bits & DDI_A_4_LANES)
4704                 return false;
4705
4706         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4707          *                     supported configuration
4708          */
4709         if (IS_GEN9_LP(dev_priv))
4710                 return true;
4711
4712         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4713          *             one who does also have a full A/E split called
4714          *             DDI_F what makes DDI_E useless. However for this
4715          *             case let's trust VBT info.
4716          */
4717         if (IS_CANNONLAKE(dev_priv) &&
4718             !intel_bios_is_port_present(dev_priv, PORT_E))
4719                 return true;
4720
4721         return false;
4722 }
4723
4724 static int
4725 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4726 {
4727         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4728         enum port port = intel_dport->base.port;
4729         int max_lanes = 4;
4730
4731         if (INTEL_GEN(dev_priv) >= 11)
4732                 return max_lanes;
4733
4734         if (port == PORT_A || port == PORT_E) {
4735                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4736                         max_lanes = port == PORT_A ? 4 : 0;
4737                 else
4738                         /* Both A and E share 2 lanes */
4739                         max_lanes = 2;
4740         }
4741
4742         /*
4743          * Some BIOS might fail to set this bit on port A if eDP
4744          * wasn't lit up at boot.  Force this bit set when needed
4745          * so we use the proper lane count for our calculations.
4746          */
4747         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4748                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4749                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4750                 max_lanes = 4;
4751         }
4752
4753         return max_lanes;
4754 }
4755
4756 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4757 {
4758         struct ddi_vbt_port_info *port_info =
4759                 &dev_priv->vbt.ddi_port_info[port];
4760         struct intel_digital_port *intel_dig_port;
4761         struct intel_encoder *encoder;
4762         bool init_hdmi, init_dp, init_lspcon = false;
4763         enum phy phy = intel_port_to_phy(dev_priv, port);
4764
4765         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4766         init_dp = port_info->supports_dp;
4767
4768         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4769                 /*
4770                  * Lspcon device needs to be driven with DP connector
4771                  * with special detection sequence. So make sure DP
4772                  * is initialized before lspcon.
4773                  */
4774                 init_dp = true;
4775                 init_lspcon = true;
4776                 init_hdmi = false;
4777                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4778         }
4779
4780         if (!init_dp && !init_hdmi) {
4781                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4782                               port_name(port));
4783                 return;
4784         }
4785
4786         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4787         if (!intel_dig_port)
4788                 return;
4789
4790         encoder = &intel_dig_port->base;
4791
4792         drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4793                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4794
4795         encoder->hotplug = intel_ddi_hotplug;
4796         encoder->compute_output_type = intel_ddi_compute_output_type;
4797         encoder->compute_config = intel_ddi_compute_config;
4798         encoder->enable = intel_enable_ddi;
4799         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4800         encoder->post_pll_disable = intel_ddi_post_pll_disable;
4801         encoder->pre_enable = intel_ddi_pre_enable;
4802         encoder->disable = intel_disable_ddi;
4803         encoder->post_disable = intel_ddi_post_disable;
4804         encoder->update_pipe = intel_ddi_update_pipe;
4805         encoder->get_hw_state = intel_ddi_get_hw_state;
4806         encoder->get_config = intel_ddi_get_config;
4807         encoder->suspend = intel_dp_encoder_suspend;
4808         encoder->get_power_domains = intel_ddi_get_power_domains;
4809
4810         encoder->type = INTEL_OUTPUT_DDI;
4811         encoder->power_domain = intel_port_to_power_domain(port);
4812         encoder->port = port;
4813         encoder->cloneable = 0;
4814         encoder->pipe_mask = ~0;
4815
4816         if (INTEL_GEN(dev_priv) >= 11)
4817                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4818                         DDI_BUF_PORT_REVERSAL;
4819         else
4820                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4821                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4822
4823         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4824         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4825         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4826
4827         if (intel_phy_is_tc(dev_priv, phy)) {
4828                 bool is_legacy = !port_info->supports_typec_usb &&
4829                                  !port_info->supports_tbt;
4830
4831                 intel_tc_port_init(intel_dig_port, is_legacy);
4832
4833                 encoder->update_prepare = intel_ddi_update_prepare;
4834                 encoder->update_complete = intel_ddi_update_complete;
4835         }
4836
4837         WARN_ON(port > PORT_I);
4838         intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4839                                               port - PORT_A;
4840
4841         if (init_dp) {
4842                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4843                         goto err;
4844
4845                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4846         }
4847
4848         /* In theory we don't need the encoder->type check, but leave it just in
4849          * case we have some really bad VBTs... */
4850         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4851                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4852                         goto err;
4853         }
4854
4855         if (init_lspcon) {
4856                 if (lspcon_init(intel_dig_port))
4857                         /* TODO: handle hdmi info frame part */
4858                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4859                                 port_name(port));
4860                 else
4861                         /*
4862                          * LSPCON init faied, but DP init was success, so
4863                          * lets try to drive as DP++ port.
4864                          */
4865                         DRM_ERROR("LSPCON init failed on port %c\n",
4866                                 port_name(port));
4867         }
4868
4869         intel_infoframe_init(intel_dig_port);
4870
4871         return;
4872
4873 err:
4874         drm_encoder_cleanup(&encoder->base);
4875         kfree(intel_dig_port);
4876 }