drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_dp.h"
  36 #include "intel_dp_link_training.h"
  37 #include "intel_dpio_phy.h"
  38 #include "intel_drv.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_gmbus.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_hdmi.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_lspcon.h"
  46 #include "intel_panel.h"
  47 #include "intel_psr.h"
  48 #include "intel_tc.h"
  49 #include "intel_vdsc.h"
  50
  51 struct ddi_buf_trans {
  52         u32 trans1;     /* balance leg enable, de-emph level */
  53         u32 trans2;     /* vref sel, vswing */
  54         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  55 };
  56
  57 static const u8 index_to_dp_signal_levels[] = {
  58         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  59         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  60         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  61         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  62         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  63         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  64         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  65         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  66         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  67         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68 };
  69
  70 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  71  * them for both DP and FDI transports, allowing those ports to
  72  * automatically adapt to HDMI connections as well
  73  */
  74 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  75         { 0x00FFFFFF, 0x0006000E, 0x0 },
  76         { 0x00D75FFF, 0x0005000A, 0x0 },
  77         { 0x00C30FFF, 0x00040006, 0x0 },
  78         { 0x80AAAFFF, 0x000B0000, 0x0 },
  79         { 0x00FFFFFF, 0x0005000A, 0x0 },
  80         { 0x00D75FFF, 0x000C0004, 0x0 },
  81         { 0x80C30FFF, 0x000B0000, 0x0 },
  82         { 0x00FFFFFF, 0x00040006, 0x0 },
  83         { 0x80D75FFF, 0x000B0000, 0x0 },
  84 };
  85
  86 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  87         { 0x00FFFFFF, 0x0007000E, 0x0 },
  88         { 0x00D75FFF, 0x000F000A, 0x0 },
  89         { 0x00C30FFF, 0x00060006, 0x0 },
  90         { 0x00AAAFFF, 0x001E0000, 0x0 },
  91         { 0x00FFFFFF, 0x000F000A, 0x0 },
  92         { 0x00D75FFF, 0x00160004, 0x0 },
  93         { 0x00C30FFF, 0x001E0000, 0x0 },
  94         { 0x00FFFFFF, 0x00060006, 0x0 },
  95         { 0x00D75FFF, 0x001E0000, 0x0 },
  96 };
  97
  98 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  99                                         /* Idx  NT mV d T mV d  db      */
 100         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 101         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 102         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 103         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 104         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 105         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 106         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 107         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 108         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 109         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 110         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 111         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 112 };
 113
 114 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 115         { 0x00FFFFFF, 0x00000012, 0x0 },
 116         { 0x00EBAFFF, 0x00020011, 0x0 },
 117         { 0x00C71FFF, 0x0006000F, 0x0 },
 118         { 0x00AAAFFF, 0x000E000A, 0x0 },
 119         { 0x00FFFFFF, 0x00020011, 0x0 },
 120         { 0x00DB6FFF, 0x0005000F, 0x0 },
 121         { 0x00BEEFFF, 0x000A000C, 0x0 },
 122         { 0x00FFFFFF, 0x0005000F, 0x0 },
 123         { 0x00DB6FFF, 0x000A000C, 0x0 },
 124 };
 125
 126 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 127         { 0x00FFFFFF, 0x0007000E, 0x0 },
 128         { 0x00D75FFF, 0x000E000A, 0x0 },
 129         { 0x00BEFFFF, 0x00140006, 0x0 },
 130         { 0x80B2CFFF, 0x001B0002, 0x0 },
 131         { 0x00FFFFFF, 0x000E000A, 0x0 },
 132         { 0x00DB6FFF, 0x00160005, 0x0 },
 133         { 0x80C71FFF, 0x001A0002, 0x0 },
 134         { 0x00F7DFFF, 0x00180004, 0x0 },
 135         { 0x80D75FFF, 0x001B0002, 0x0 },
 136 };
 137
 138 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 139         { 0x00FFFFFF, 0x0001000E, 0x0 },
 140         { 0x00D75FFF, 0x0004000A, 0x0 },
 141         { 0x00C30FFF, 0x00070006, 0x0 },
 142         { 0x00AAAFFF, 0x000C0000, 0x0 },
 143         { 0x00FFFFFF, 0x0004000A, 0x0 },
 144         { 0x00D75FFF, 0x00090004, 0x0 },
 145         { 0x00C30FFF, 0x000C0000, 0x0 },
 146         { 0x00FFFFFF, 0x00070006, 0x0 },
 147         { 0x00D75FFF, 0x000C0000, 0x0 },
 148 };
 149
 150 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 151                                         /* Idx  NT mV d T mV df db      */
 152         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 153         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 154         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 155         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 156         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 157         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 158         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 159         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 160         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 161         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 162 };
 163
 164 /* Skylake H and S */
 165 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 166         { 0x00002016, 0x000000A0, 0x0 },
 167         { 0x00005012, 0x0000009B, 0x0 },
 168         { 0x00007011, 0x00000088, 0x0 },
 169         { 0x80009010, 0x000000C0, 0x1 },
 170         { 0x00002016, 0x0000009B, 0x0 },
 171         { 0x00005012, 0x00000088, 0x0 },
 172         { 0x80007011, 0x000000C0, 0x1 },
 173         { 0x00002016, 0x000000DF, 0x0 },
 174         { 0x80005012, 0x000000C0, 0x1 },
 175 };
 176
 177 /* Skylake U */
 178 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 179         { 0x0000201B, 0x000000A2, 0x0 },
 180         { 0x00005012, 0x00000088, 0x0 },
 181         { 0x80007011, 0x000000CD, 0x1 },
 182         { 0x80009010, 0x000000C0, 0x1 },
 183         { 0x0000201B, 0x0000009D, 0x0 },
 184         { 0x80005012, 0x000000C0, 0x1 },
 185         { 0x80007011, 0x000000C0, 0x1 },
 186         { 0x00002016, 0x00000088, 0x0 },
 187         { 0x80005012, 0x000000C0, 0x1 },
 188 };
 189
 190 /* Skylake Y */
 191 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 192         { 0x00000018, 0x000000A2, 0x0 },
 193         { 0x00005012, 0x00000088, 0x0 },
 194         { 0x80007011, 0x000000CD, 0x3 },
 195         { 0x80009010, 0x000000C0, 0x3 },
 196         { 0x00000018, 0x0000009D, 0x0 },
 197         { 0x80005012, 0x000000C0, 0x3 },
 198         { 0x80007011, 0x000000C0, 0x3 },
 199         { 0x00000018, 0x00000088, 0x0 },
 200         { 0x80005012, 0x000000C0, 0x3 },
 201 };
 202
 203 /* Kabylake H and S */
 204 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 205         { 0x00002016, 0x000000A0, 0x0 },
 206         { 0x00005012, 0x0000009B, 0x0 },
 207         { 0x00007011, 0x00000088, 0x0 },
 208         { 0x80009010, 0x000000C0, 0x1 },
 209         { 0x00002016, 0x0000009B, 0x0 },
 210         { 0x00005012, 0x00000088, 0x0 },
 211         { 0x80007011, 0x000000C0, 0x1 },
 212         { 0x00002016, 0x00000097, 0x0 },
 213         { 0x80005012, 0x000000C0, 0x1 },
 214 };
 215
 216 /* Kabylake U */
 217 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 218         { 0x0000201B, 0x000000A1, 0x0 },
 219         { 0x00005012, 0x00000088, 0x0 },
 220         { 0x80007011, 0x000000CD, 0x3 },
 221         { 0x80009010, 0x000000C0, 0x3 },
 222         { 0x0000201B, 0x0000009D, 0x0 },
 223         { 0x80005012, 0x000000C0, 0x3 },
 224         { 0x80007011, 0x000000C0, 0x3 },
 225         { 0x00002016, 0x0000004F, 0x0 },
 226         { 0x80005012, 0x000000C0, 0x3 },
 227 };
 228
 229 /* Kabylake Y */
 230 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 231         { 0x00001017, 0x000000A1, 0x0 },
 232         { 0x00005012, 0x00000088, 0x0 },
 233         { 0x80007011, 0x000000CD, 0x3 },
 234         { 0x8000800F, 0x000000C0, 0x3 },
 235         { 0x00001017, 0x0000009D, 0x0 },
 236         { 0x80005012, 0x000000C0, 0x3 },
 237         { 0x80007011, 0x000000C0, 0x3 },
 238         { 0x00001017, 0x0000004C, 0x0 },
 239         { 0x80005012, 0x000000C0, 0x3 },
 240 };
 241
 242 /*
 243  * Skylake/Kabylake H and S
 244  * eDP 1.4 low vswing translation parameters
 245  */
 246 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 247         { 0x00000018, 0x000000A8, 0x0 },
 248         { 0x00004013, 0x000000A9, 0x0 },
 249         { 0x00007011, 0x000000A2, 0x0 },
 250         { 0x00009010, 0x0000009C, 0x0 },
 251         { 0x00000018, 0x000000A9, 0x0 },
 252         { 0x00006013, 0x000000A2, 0x0 },
 253         { 0x00007011, 0x000000A6, 0x0 },
 254         { 0x00000018, 0x000000AB, 0x0 },
 255         { 0x00007013, 0x0000009F, 0x0 },
 256         { 0x00000018, 0x000000DF, 0x0 },
 257 };
 258
 259 /*
 260  * Skylake/Kabylake U
 261  * eDP 1.4 low vswing translation parameters
 262  */
 263 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 264         { 0x00000018, 0x000000A8, 0x0 },
 265         { 0x00004013, 0x000000A9, 0x0 },
 266         { 0x00007011, 0x000000A2, 0x0 },
 267         { 0x00009010, 0x0000009C, 0x0 },
 268         { 0x00000018, 0x000000A9, 0x0 },
 269         { 0x00006013, 0x000000A2, 0x0 },
 270         { 0x00007011, 0x000000A6, 0x0 },
 271         { 0x00002016, 0x000000AB, 0x0 },
 272         { 0x00005013, 0x0000009F, 0x0 },
 273         { 0x00000018, 0x000000DF, 0x0 },
 274 };
 275
 276 /*
 277  * Skylake/Kabylake Y
 278  * eDP 1.4 low vswing translation parameters
 279  */
 280 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 281         { 0x00000018, 0x000000A8, 0x0 },
 282         { 0x00004013, 0x000000AB, 0x0 },
 283         { 0x00007011, 0x000000A4, 0x0 },
 284         { 0x00009010, 0x000000DF, 0x0 },
 285         { 0x00000018, 0x000000AA, 0x0 },
 286         { 0x00006013, 0x000000A4, 0x0 },
 287         { 0x00007011, 0x0000009D, 0x0 },
 288         { 0x00000018, 0x000000A0, 0x0 },
 289         { 0x00006012, 0x000000DF, 0x0 },
 290         { 0x00000018, 0x0000008A, 0x0 },
 291 };
 292
 293 /* Skylake/Kabylake U, H and S */
 294 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 295         { 0x00000018, 0x000000AC, 0x0 },
 296         { 0x00005012, 0x0000009D, 0x0 },
 297         { 0x00007011, 0x00000088, 0x0 },
 298         { 0x00000018, 0x000000A1, 0x0 },
 299         { 0x00000018, 0x00000098, 0x0 },
 300         { 0x00004013, 0x00000088, 0x0 },
 301         { 0x80006012, 0x000000CD, 0x1 },
 302         { 0x00000018, 0x000000DF, 0x0 },
 303         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 304         { 0x80003015, 0x000000C0, 0x1 },
 305         { 0x80000018, 0x000000C0, 0x1 },
 306 };
 307
 308 /* Skylake/Kabylake Y */
 309 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 310         { 0x00000018, 0x000000A1, 0x0 },
 311         { 0x00005012, 0x000000DF, 0x0 },
 312         { 0x80007011, 0x000000CB, 0x3 },
 313         { 0x00000018, 0x000000A4, 0x0 },
 314         { 0x00000018, 0x0000009D, 0x0 },
 315         { 0x00004013, 0x00000080, 0x0 },
 316         { 0x80006013, 0x000000C0, 0x3 },
 317         { 0x00000018, 0x0000008A, 0x0 },
 318         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 319         { 0x80003015, 0x000000C0, 0x3 },
 320         { 0x80000018, 0x000000C0, 0x3 },
 321 };
 322
 323 struct bxt_ddi_buf_trans {
 324         u8 margin;      /* swing value */
 325         u8 scale;       /* scale value */
 326         u8 enable;      /* scale enable */
 327         u8 deemphasis;
 328 };
 329
 330 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 331                                         /* Idx  NT mV diff      db  */
 332         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 333         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 334         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 335         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 336         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 337         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 338         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 339         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 340         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 341         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 342 };
 343
 344 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 345                                         /* Idx  NT mV diff      db  */
 346         { 26, 0, 0, 128, },     /* 0:   200             0   */
 347         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 348         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 349         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 350         { 32, 0, 0, 128, },     /* 4:   250             0   */
 351         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 352         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 353         { 43, 0, 0, 128, },     /* 7:   300             0   */
 354         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 355         { 48, 0, 0, 128, },     /* 9:   300             0   */
 356 };
 357
 358 /* BSpec has 2 recommended values - entries 0 and 8.
 359  * Using the entry with higher vswing.
 360  */
 361 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 362                                         /* Idx  NT mV diff      db  */
 363         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 364         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 365         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 366         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 367         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 368         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 369         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 370         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 371         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 372         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 373 };
 374
 375 struct cnl_ddi_buf_trans {
 376         u8 dw2_swing_sel;
 377         u8 dw7_n_scalar;
 378         u8 dw4_cursor_coeff;
 379         u8 dw4_post_cursor_2;
 380         u8 dw4_post_cursor_1;
 381 };
 382
 383 /* Voltage Swing Programming for VccIO 0.85V for DP */
 384 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 385                                                 /* NT mV Trans mV db    */
 386         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 387         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 388         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 389         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 390         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 391         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 392         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 393         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 394         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 395         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 396 };
 397
 398 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 399 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 400                                                 /* NT mV Trans mV db    */
 401         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 402         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 403         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 404         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 405         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 406         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 407         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 408 };
 409
 410 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 411 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 412                                                 /* NT mV Trans mV db    */
 413         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 414         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 415         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 416         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 417         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 418         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 419         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 420         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 421         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 422 };
 423
 424 /* Voltage Swing Programming for VccIO 0.95V for DP */
 425 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 426                                                 /* NT mV Trans mV db    */
 427         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 428         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 429         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 430         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 431         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 432         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 433         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 434         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 435         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 436         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 437 };
 438
 439 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 440 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 441                                                 /* NT mV Trans mV db    */
 442         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 443         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 444         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 445         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 446         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 447         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 448         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 449         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 450         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 451         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 452         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 453 };
 454
 455 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 456 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 457                                                 /* NT mV Trans mV db    */
 458         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 459         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 460         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 461         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 462         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 463         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 464         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 465         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 466         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 467         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 468 };
 469
 470 /* Voltage Swing Programming for VccIO 1.05V for DP */
 471 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 472                                                 /* NT mV Trans mV db    */
 473         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 474         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 475         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 476         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 477         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 478         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 479         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 480         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 481         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 482         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 483 };
 484
 485 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 486 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 487                                                 /* NT mV Trans mV db    */
 488         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 489         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 490         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 491         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 492         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 493         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 494         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 495         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 496         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 497         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 498         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 499 };
 500
 501 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 502 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 503                                                 /* NT mV Trans mV db    */
 504         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 505         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 506         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 507         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 508         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 509         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 510         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 511         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 512         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 513 };
 514
 515 /* icl_combo_phy_ddi_translations */
 516 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 517                                                 /* NT mV Trans mV db    */
 518         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 519         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 520         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 521         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 522         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 523         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 524         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 525         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 526         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 527         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 528 };
 529
 530 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 531                                                 /* NT mV Trans mV db    */
 532         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 533         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 534         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 535         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 536         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 537         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 538         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 539         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 540         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 541         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 542 };
 543
 544 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 545                                                 /* NT mV Trans mV db    */
 546         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 547         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 548         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 549         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 550         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 551         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 552         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 553         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 554         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 555         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 556 };
 557
 558 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 559                                                 /* NT mV Trans mV db    */
 560         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 561         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 562         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 563         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 564         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 565         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 566         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 567 };
 568
 569 struct icl_mg_phy_ddi_buf_trans {
 570         u32 cri_txdeemph_override_5_0;
 571         u32 cri_txdeemph_override_11_6;
 572         u32 cri_txdeemph_override_17_12;
 573 };
 574
 575 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 576                                 /* Voltage swing  pre-emphasis */
 577         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 578         { 0x0, 0x23, 0x08 },    /* 0              1   */
 579         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 580         { 0x0, 0x00, 0x00 },    /* 0              3   */
 581         { 0x0, 0x23, 0x00 },    /* 1              0   */
 582         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 583         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 584         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 585         { 0x0, 0x33, 0x0C },    /* 2              1   */
 586         { 0x0, 0x00, 0x00 },    /* 3              0   */
 587 };
 588
 589 static const struct ddi_buf_trans *
 590 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 591 {
 592         if (dev_priv->vbt.edp.low_vswing) {
 593                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 594                 return bdw_ddi_translations_edp;
 595         } else {
 596                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 597                 return bdw_ddi_translations_dp;
 598         }
 599 }
 600
 601 static const struct ddi_buf_trans *
 602 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 603 {
 604         if (IS_SKL_ULX(dev_priv)) {
 605                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 606                 return skl_y_ddi_translations_dp;
 607         } else if (IS_SKL_ULT(dev_priv)) {
 608                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 609                 return skl_u_ddi_translations_dp;
 610         } else {
 611                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 612                 return skl_ddi_translations_dp;
 613         }
 614 }
 615
 616 static const struct ddi_buf_trans *
 617 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 618 {
 619         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 620                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 621                 return kbl_y_ddi_translations_dp;
 622         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 623                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 624                 return kbl_u_ddi_translations_dp;
 625         } else {
 626                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 627                 return kbl_ddi_translations_dp;
 628         }
 629 }
 630
 631 static const struct ddi_buf_trans *
 632 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 633 {
 634         if (dev_priv->vbt.edp.low_vswing) {
 635                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 636                     IS_CFL_ULX(dev_priv)) {
 637                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 638                         return skl_y_ddi_translations_edp;
 639                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 640                            IS_CFL_ULT(dev_priv)) {
 641                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 642                         return skl_u_ddi_translations_edp;
 643                 } else {
 644                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 645                         return skl_ddi_translations_edp;
 646                 }
 647         }
 648
 649         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 650                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 651         else
 652                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 653 }
 654
 655 static const struct ddi_buf_trans *
 656 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 657 {
 658         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 659             IS_CFL_ULX(dev_priv)) {
 660                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 661                 return skl_y_ddi_translations_hdmi;
 662         } else {
 663                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 664                 return skl_ddi_translations_hdmi;
 665         }
 666 }
 667
 668 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 669 {
 670         /* Only DDIA and DDIE can select the 10th register with DP */
 671         if (port == PORT_A || port == PORT_E)
 672                 return min(n_entries, 10);
 673         else
 674                 return min(n_entries, 9);
 675 }
 676
 677 static const struct ddi_buf_trans *
 678 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 679                            enum port port, int *n_entries)
 680 {
 681         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 682                 const struct ddi_buf_trans *ddi_translations =
 683                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 684                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 685                 return ddi_translations;
 686         } else if (IS_SKYLAKE(dev_priv)) {
 687                 const struct ddi_buf_trans *ddi_translations =
 688                         skl_get_buf_trans_dp(dev_priv, n_entries);
 689                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 690                 return ddi_translations;
 691         } else if (IS_BROADWELL(dev_priv)) {
 692                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 693                 return  bdw_ddi_translations_dp;
 694         } else if (IS_HASWELL(dev_priv)) {
 695                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 696                 return hsw_ddi_translations_dp;
 697         }
 698
 699         *n_entries = 0;
 700         return NULL;
 701 }
 702
 703 static const struct ddi_buf_trans *
 704 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 705                             enum port port, int *n_entries)
 706 {
 707         if (IS_GEN9_BC(dev_priv)) {
 708                 const struct ddi_buf_trans *ddi_translations =
 709                         skl_get_buf_trans_edp(dev_priv, n_entries);
 710                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 711                 return ddi_translations;
 712         } else if (IS_BROADWELL(dev_priv)) {
 713                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 714         } else if (IS_HASWELL(dev_priv)) {
 715                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 716                 return hsw_ddi_translations_dp;
 717         }
 718
 719         *n_entries = 0;
 720         return NULL;
 721 }
 722
 723 static const struct ddi_buf_trans *
 724 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 725                             int *n_entries)
 726 {
 727         if (IS_BROADWELL(dev_priv)) {
 728                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 729                 return bdw_ddi_translations_fdi;
 730         } else if (IS_HASWELL(dev_priv)) {
 731                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 732                 return hsw_ddi_translations_fdi;
 733         }
 734
 735         *n_entries = 0;
 736         return NULL;
 737 }
 738
 739 static const struct ddi_buf_trans *
 740 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 741                              int *n_entries)
 742 {
 743         if (IS_GEN9_BC(dev_priv)) {
 744                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 745         } else if (IS_BROADWELL(dev_priv)) {
 746                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 747                 return bdw_ddi_translations_hdmi;
 748         } else if (IS_HASWELL(dev_priv)) {
 749                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 750                 return hsw_ddi_translations_hdmi;
 751         }
 752
 753         *n_entries = 0;
 754         return NULL;
 755 }
 756
 757 static const struct bxt_ddi_buf_trans *
 758 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 759 {
 760         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 761         return bxt_ddi_translations_dp;
 762 }
 763
 764 static const struct bxt_ddi_buf_trans *
 765 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 766 {
 767         if (dev_priv->vbt.edp.low_vswing) {
 768                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 769                 return bxt_ddi_translations_edp;
 770         }
 771
 772         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 773 }
 774
 775 static const struct bxt_ddi_buf_trans *
 776 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 777 {
 778         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 779         return bxt_ddi_translations_hdmi;
 780 }
 781
 782 static const struct cnl_ddi_buf_trans *
 783 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 784 {
 785         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 786
 787         if (voltage == VOLTAGE_INFO_0_85V) {
 788                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 789                 return cnl_ddi_translations_hdmi_0_85V;
 790         } else if (voltage == VOLTAGE_INFO_0_95V) {
 791                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 792                 return cnl_ddi_translations_hdmi_0_95V;
 793         } else if (voltage == VOLTAGE_INFO_1_05V) {
 794                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 795                 return cnl_ddi_translations_hdmi_1_05V;
 796         } else {
 797                 *n_entries = 1; /* shut up gcc */
 798                 MISSING_CASE(voltage);
 799         }
 800         return NULL;
 801 }
 802
 803 static const struct cnl_ddi_buf_trans *
 804 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 805 {
 806         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 807
 808         if (voltage == VOLTAGE_INFO_0_85V) {
 809                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 810                 return cnl_ddi_translations_dp_0_85V;
 811         } else if (voltage == VOLTAGE_INFO_0_95V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 813                 return cnl_ddi_translations_dp_0_95V;
 814         } else if (voltage == VOLTAGE_INFO_1_05V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 816                 return cnl_ddi_translations_dp_1_05V;
 817         } else {
 818                 *n_entries = 1; /* shut up gcc */
 819                 MISSING_CASE(voltage);
 820         }
 821         return NULL;
 822 }
 823
 824 static const struct cnl_ddi_buf_trans *
 825 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 826 {
 827         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 828
 829         if (dev_priv->vbt.edp.low_vswing) {
 830                 if (voltage == VOLTAGE_INFO_0_85V) {
 831                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 832                         return cnl_ddi_translations_edp_0_85V;
 833                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 834                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 835                         return cnl_ddi_translations_edp_0_95V;
 836                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 837                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 838                         return cnl_ddi_translations_edp_1_05V;
 839                 } else {
 840                         *n_entries = 1; /* shut up gcc */
 841                         MISSING_CASE(voltage);
 842                 }
 843                 return NULL;
 844         } else {
 845                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 846         }
 847 }
 848
 849 static const struct cnl_ddi_buf_trans *
 850 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 851                         int *n_entries)
 852 {
 853         if (type == INTEL_OUTPUT_HDMI) {
 854                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 855                 return icl_combo_phy_ddi_translations_hdmi;
 856         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 857                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 858                 return icl_combo_phy_ddi_translations_edp_hbr3;
 859         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 860                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 861                 return icl_combo_phy_ddi_translations_edp_hbr2;
 862         }
 863
 864         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 865         return icl_combo_phy_ddi_translations_dp_hbr2;
 866 }
 867
 868 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 869 {
 870         int n_entries, level, default_entry;
 871
 872         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 873
 874         if (INTEL_GEN(dev_priv) >= 11) {
 875                 if (intel_port_is_combophy(dev_priv, port))
 876                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 877                                                 0, &n_entries);
 878                 else
 879                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 880                 default_entry = n_entries - 1;
 881         } else if (IS_CANNONLAKE(dev_priv)) {
 882                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 883                 default_entry = n_entries - 1;
 884         } else if (IS_GEN9_LP(dev_priv)) {
 885                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 886                 default_entry = n_entries - 1;
 887         } else if (IS_GEN9_BC(dev_priv)) {
 888                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 889                 default_entry = 8;
 890         } else if (IS_BROADWELL(dev_priv)) {
 891                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 892                 default_entry = 7;
 893         } else if (IS_HASWELL(dev_priv)) {
 894                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 895                 default_entry = 6;
 896         } else {
 897                 WARN(1, "ddi translation table missing\n");
 898                 return 0;
 899         }
 900
 901         /* Choose a good default if VBT is badly populated */
 902         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 903                 level = default_entry;
 904
 905         if (WARN_ON_ONCE(n_entries == 0))
 906                 return 0;
 907         if (WARN_ON_ONCE(level >= n_entries))
 908                 level = n_entries - 1;
 909
 910         return level;
 911 }
 912
 913 /*
 914  * Starting with Haswell, DDI port buffers must be programmed with correct
 915  * values in advance. This function programs the correct values for
 916  * DP/eDP/FDI use cases.
 917  */
 918 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 919                                          const struct intel_crtc_state *crtc_state)
 920 {
 921         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 922         u32 iboost_bit = 0;
 923         int i, n_entries;
 924         enum port port = encoder->port;
 925         const struct ddi_buf_trans *ddi_translations;
 926
 927         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 928                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 929                                                                &n_entries);
 930         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 931                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 932                                                                &n_entries);
 933         else
 934                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 935                                                               &n_entries);
 936
 937         /* If we're boosting the current, set bit 31 of trans1 */
 938         if (IS_GEN9_BC(dev_priv) &&
 939             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 940                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 941
 942         for (i = 0; i < n_entries; i++) {
 943                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 944                            ddi_translations[i].trans1 | iboost_bit);
 945                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 946                            ddi_translations[i].trans2);
 947         }
 948 }
 949
 950 /*
 951  * Starting with Haswell, DDI port buffers must be programmed with correct
 952  * values in advance. This function programs the correct values for
 953  * HDMI/DVI use cases.
 954  */
 955 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 956                                            int level)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 959         u32 iboost_bit = 0;
 960         int n_entries;
 961         enum port port = encoder->port;
 962         const struct ddi_buf_trans *ddi_translations;
 963
 964         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 965
 966         if (WARN_ON_ONCE(!ddi_translations))
 967                 return;
 968         if (WARN_ON_ONCE(level >= n_entries))
 969                 level = n_entries - 1;
 970
 971         /* If we're boosting the current, set bit 31 of trans1 */
 972         if (IS_GEN9_BC(dev_priv) &&
 973             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
 974                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 975
 976         /* Entry 9 is for HDMI: */
 977         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
 978                    ddi_translations[level].trans1 | iboost_bit);
 979         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
 980                    ddi_translations[level].trans2);
 981 }
 982
 983 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 984                                     enum port port)
 985 {
 986         i915_reg_t reg = DDI_BUF_CTL(port);
 987         int i;
 988
 989         for (i = 0; i < 16; i++) {
 990                 udelay(1);
 991                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 992                         return;
 993         }
 994         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 995 }
 996
 997 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 998 {
 999         switch (pll->info->id) {
1000         case DPLL_ID_WRPLL1:
1001                 return PORT_CLK_SEL_WRPLL1;
1002         case DPLL_ID_WRPLL2:
1003                 return PORT_CLK_SEL_WRPLL2;
1004         case DPLL_ID_SPLL:
1005                 return PORT_CLK_SEL_SPLL;
1006         case DPLL_ID_LCPLL_810:
1007                 return PORT_CLK_SEL_LCPLL_810;
1008         case DPLL_ID_LCPLL_1350:
1009                 return PORT_CLK_SEL_LCPLL_1350;
1010         case DPLL_ID_LCPLL_2700:
1011                 return PORT_CLK_SEL_LCPLL_2700;
1012         default:
1013                 MISSING_CASE(pll->info->id);
1014                 return PORT_CLK_SEL_NONE;
1015         }
1016 }
1017
1018 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1019                                   const struct intel_crtc_state *crtc_state)
1020 {
1021         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1022         int clock = crtc_state->port_clock;
1023         const enum intel_dpll_id id = pll->info->id;
1024
1025         switch (id) {
1026         default:
1027                 /*
1028                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1029                  * here, so do warn if this get passed in
1030                  */
1031                 MISSING_CASE(id);
1032                 return DDI_CLK_SEL_NONE;
1033         case DPLL_ID_ICL_TBTPLL:
1034                 switch (clock) {
1035                 case 162000:
1036                         return DDI_CLK_SEL_TBT_162;
1037                 case 270000:
1038                         return DDI_CLK_SEL_TBT_270;
1039                 case 540000:
1040                         return DDI_CLK_SEL_TBT_540;
1041                 case 810000:
1042                         return DDI_CLK_SEL_TBT_810;
1043                 default:
1044                         MISSING_CASE(clock);
1045                         return DDI_CLK_SEL_NONE;
1046                 }
1047         case DPLL_ID_ICL_MGPLL1:
1048         case DPLL_ID_ICL_MGPLL2:
1049         case DPLL_ID_ICL_MGPLL3:
1050         case DPLL_ID_ICL_MGPLL4:
1051                 return DDI_CLK_SEL_MG;
1052         }
1053 }
1054
1055 /* Starting with Haswell, different DDI ports can work in FDI mode for
1056  * connection to the PCH-located connectors. For this, it is necessary to train
1057  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1058  *
1059  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1060  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1061  * DDI A (which is used for eDP)
1062  */
1063
1064 void hsw_fdi_link_train(struct intel_crtc *crtc,
1065                         const struct intel_crtc_state *crtc_state)
1066 {
1067         struct drm_device *dev = crtc->base.dev;
1068         struct drm_i915_private *dev_priv = to_i915(dev);
1069         struct intel_encoder *encoder;
1070         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1071
1072         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1073                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1074                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1075         }
1076
1077         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1078          * mode set "sequence for CRT port" document:
1079          * - TP1 to TP2 time with the default value
1080          * - FDI delay to 90h
1081          *
1082          * WaFDIAutoLinkSetTimingOverrride:hsw
1083          */
1084         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1085                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1086                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1087
1088         /* Enable the PCH Receiver FDI PLL */
1089         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1090                      FDI_RX_PLL_ENABLE |
1091                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1092         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1093         POSTING_READ(FDI_RX_CTL(PIPE_A));
1094         udelay(220);
1095
1096         /* Switch from Rawclk to PCDclk */
1097         rx_ctl_val |= FDI_PCDCLK;
1098         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1099
1100         /* Configure Port Clock Select */
1101         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1102         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1103         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1104
1105         /* Start the training iterating through available voltages and emphasis,
1106          * testing each value twice. */
1107         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1108                 /* Configure DP_TP_CTL with auto-training */
1109                 I915_WRITE(DP_TP_CTL(PORT_E),
1110                                         DP_TP_CTL_FDI_AUTOTRAIN |
1111                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1112                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1113                                         DP_TP_CTL_ENABLE);
1114
1115                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1116                  * DDI E does not support port reversal, the functionality is
1117                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1118                  * port reversal bit */
1119                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1120                            DDI_BUF_CTL_ENABLE |
1121                            ((crtc_state->fdi_lanes - 1) << 1) |
1122                            DDI_BUF_TRANS_SELECT(i / 2));
1123                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1124
1125                 udelay(600);
1126
1127                 /* Program PCH FDI Receiver TU */
1128                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1129
1130                 /* Enable PCH FDI Receiver with auto-training */
1131                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1132                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1133                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1134
1135                 /* Wait for FDI receiver lane calibration */
1136                 udelay(30);
1137
1138                 /* Unset FDI_RX_MISC pwrdn lanes */
1139                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1140                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1141                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1142                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1143
1144                 /* Wait for FDI auto training time */
1145                 udelay(5);
1146
1147                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1148                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1149                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1150                         break;
1151                 }
1152
1153                 /*
1154                  * Leave things enabled even if we failed to train FDI.
1155                  * Results in less fireworks from the state checker.
1156                  */
1157                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1158                         DRM_ERROR("FDI link training failed!\n");
1159                         break;
1160                 }
1161
1162                 rx_ctl_val &= ~FDI_RX_ENABLE;
1163                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1164                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1165
1166                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1167                 temp &= ~DDI_BUF_CTL_ENABLE;
1168                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1169                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1170
1171                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1172                 temp = I915_READ(DP_TP_CTL(PORT_E));
1173                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1174                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1175                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1176                 POSTING_READ(DP_TP_CTL(PORT_E));
1177
1178                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1179
1180                 /* Reset FDI_RX_MISC pwrdn lanes */
1181                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1182                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1183                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1184                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1185                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1186         }
1187
1188         /* Enable normal pixel sending for FDI */
1189         I915_WRITE(DP_TP_CTL(PORT_E),
1190                    DP_TP_CTL_FDI_AUTOTRAIN |
1191                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1192                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1193                    DP_TP_CTL_ENABLE);
1194 }
1195
1196 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1197 {
1198         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1199         struct intel_digital_port *intel_dig_port =
1200                 enc_to_dig_port(&encoder->base);
1201
1202         intel_dp->DP = intel_dig_port->saved_port_bits |
1203                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1204         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1205 }
1206
1207 static struct intel_encoder *
1208 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1209 {
1210         struct drm_device *dev = crtc->base.dev;
1211         struct intel_encoder *encoder, *ret = NULL;
1212         int num_encoders = 0;
1213
1214         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1215                 ret = encoder;
1216                 num_encoders++;
1217         }
1218
1219         if (num_encoders != 1)
1220                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1221                      pipe_name(crtc->pipe));
1222
1223         BUG_ON(ret == NULL);
1224         return ret;
1225 }
1226
1227 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1228                                    i915_reg_t reg)
1229 {
1230         int refclk;
1231         int n, p, r;
1232         u32 wrpll;
1233
1234         wrpll = I915_READ(reg);
1235         switch (wrpll & WRPLL_REF_MASK) {
1236         case WRPLL_REF_SPECIAL_HSW:
1237                 /*
1238                  * muxed-SSC for BDW.
1239                  * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1240                  * for the non-SSC reference frequency.
1241                  */
1242                 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1243                         if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1244                                 refclk = 24;
1245                         else
1246                                 refclk = 135;
1247                         break;
1248                 }
1249                 /* fall through */
1250         case WRPLL_REF_PCH_SSC:
1251                 /*
1252                  * We could calculate spread here, but our checking
1253                  * code only cares about 5% accuracy, and spread is a max of
1254                  * 0.5% downspread.
1255                  */
1256                 refclk = 135;
1257                 break;
1258         case WRPLL_REF_LCPLL:
1259                 refclk = 2700;
1260                 break;
1261         default:
1262                 MISSING_CASE(wrpll);
1263                 return 0;
1264         }
1265
1266         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1267         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1268         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1269
1270         /* Convert to KHz, p & r have a fixed point portion */
1271         return (refclk * n * 100) / (p * r);
1272 }
1273
1274 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1275 {
1276         u32 p0, p1, p2, dco_freq;
1277
1278         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1279         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1280
1281         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1282                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1283         else
1284                 p1 = 1;
1285
1286
1287         switch (p0) {
1288         case DPLL_CFGCR2_PDIV_1:
1289                 p0 = 1;
1290                 break;
1291         case DPLL_CFGCR2_PDIV_2:
1292                 p0 = 2;
1293                 break;
1294         case DPLL_CFGCR2_PDIV_3:
1295                 p0 = 3;
1296                 break;
1297         case DPLL_CFGCR2_PDIV_7:
1298                 p0 = 7;
1299                 break;
1300         }
1301
1302         switch (p2) {
1303         case DPLL_CFGCR2_KDIV_5:
1304                 p2 = 5;
1305                 break;
1306         case DPLL_CFGCR2_KDIV_2:
1307                 p2 = 2;
1308                 break;
1309         case DPLL_CFGCR2_KDIV_3:
1310                 p2 = 3;
1311                 break;
1312         case DPLL_CFGCR2_KDIV_1:
1313                 p2 = 1;
1314                 break;
1315         }
1316
1317         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1318                 * 24 * 1000;
1319
1320         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1321                      * 24 * 1000) / 0x8000;
1322
1323         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1324                 return 0;
1325
1326         return dco_freq / (p0 * p1 * p2 * 5);
1327 }
1328
1329 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1330                         struct intel_dpll_hw_state *pll_state)
1331 {
1332         u32 p0, p1, p2, dco_freq, ref_clock;
1333
1334         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1335         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1336
1337         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1338                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1339                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1340         else
1341                 p1 = 1;
1342
1343
1344         switch (p0) {
1345         case DPLL_CFGCR1_PDIV_2:
1346                 p0 = 2;
1347                 break;
1348         case DPLL_CFGCR1_PDIV_3:
1349                 p0 = 3;
1350                 break;
1351         case DPLL_CFGCR1_PDIV_5:
1352                 p0 = 5;
1353                 break;
1354         case DPLL_CFGCR1_PDIV_7:
1355                 p0 = 7;
1356                 break;
1357         }
1358
1359         switch (p2) {
1360         case DPLL_CFGCR1_KDIV_1:
1361                 p2 = 1;
1362                 break;
1363         case DPLL_CFGCR1_KDIV_2:
1364                 p2 = 2;
1365                 break;
1366         case DPLL_CFGCR1_KDIV_3:
1367                 p2 = 3;
1368                 break;
1369         }
1370
1371         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1372
1373         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1374                 * ref_clock;
1375
1376         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1377                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1378
1379         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1380                 return 0;
1381
1382         return dco_freq / (p0 * p1 * p2 * 5);
1383 }
1384
1385 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1386                                  enum port port)
1387 {
1388         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1389
1390         switch (val) {
1391         case DDI_CLK_SEL_NONE:
1392                 return 0;
1393         case DDI_CLK_SEL_TBT_162:
1394                 return 162000;
1395         case DDI_CLK_SEL_TBT_270:
1396                 return 270000;
1397         case DDI_CLK_SEL_TBT_540:
1398                 return 540000;
1399         case DDI_CLK_SEL_TBT_810:
1400                 return 810000;
1401         default:
1402                 MISSING_CASE(val);
1403                 return 0;
1404         }
1405 }
1406
1407 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1408                                 const struct intel_dpll_hw_state *pll_state)
1409 {
1410         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1411         u64 tmp;
1412
1413         ref_clock = dev_priv->cdclk.hw.ref;
1414
1415         m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1416         m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1417         m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1418                 (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1419                 MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1420
1421         switch (pll_state->mg_clktop2_hsclkctl &
1422                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1423         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1424                 div1 = 2;
1425                 break;
1426         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1427                 div1 = 3;
1428                 break;
1429         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1430                 div1 = 5;
1431                 break;
1432         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1433                 div1 = 7;
1434                 break;
1435         default:
1436                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1437                 return 0;
1438         }
1439
1440         div2 = (pll_state->mg_clktop2_hsclkctl &
1441                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1442                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1443
1444         /* div2 value of 0 is same as 1 means no div */
1445         if (div2 == 0)
1446                 div2 = 1;
1447
1448         /*
1449          * Adjust the original formula to delay the division by 2^22 in order to
1450          * minimize possible rounding errors.
1451          */
1452         tmp = (u64)m1 * m2_int * ref_clock +
1453               (((u64)m1 * m2_frac * ref_clock) >> 22);
1454         tmp = div_u64(tmp, 5 * div1 * div2);
1455
1456         return tmp;
1457 }
1458
1459 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1460 {
1461         int dotclock;
1462
1463         if (pipe_config->has_pch_encoder)
1464                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1465                                                     &pipe_config->fdi_m_n);
1466         else if (intel_crtc_has_dp_encoder(pipe_config))
1467                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1468                                                     &pipe_config->dp_m_n);
1469         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1470                 dotclock = pipe_config->port_clock * 2 / 3;
1471         else
1472                 dotclock = pipe_config->port_clock;
1473
1474         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1475             !intel_crtc_has_dp_encoder(pipe_config))
1476                 dotclock *= 2;
1477
1478         if (pipe_config->pixel_multiplier)
1479                 dotclock /= pipe_config->pixel_multiplier;
1480
1481         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1482 }
1483
1484 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1485                               struct intel_crtc_state *pipe_config)
1486 {
1487         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1488         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1489         enum port port = encoder->port;
1490         int link_clock;
1491
1492         if (intel_port_is_combophy(dev_priv, port)) {
1493                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1494         } else {
1495                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1496                                                 pipe_config->shared_dpll);
1497
1498                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1499                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1500                 else
1501                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1502         }
1503
1504         pipe_config->port_clock = link_clock;
1505
1506         ddi_dotclock_get(pipe_config);
1507 }
1508
1509 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1510                               struct intel_crtc_state *pipe_config)
1511 {
1512         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1513         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1514         int link_clock;
1515
1516         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1517                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1518         } else {
1519                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1520
1521                 switch (link_clock) {
1522                 case DPLL_CFGCR0_LINK_RATE_810:
1523                         link_clock = 81000;
1524                         break;
1525                 case DPLL_CFGCR0_LINK_RATE_1080:
1526                         link_clock = 108000;
1527                         break;
1528                 case DPLL_CFGCR0_LINK_RATE_1350:
1529                         link_clock = 135000;
1530                         break;
1531                 case DPLL_CFGCR0_LINK_RATE_1620:
1532                         link_clock = 162000;
1533                         break;
1534                 case DPLL_CFGCR0_LINK_RATE_2160:
1535                         link_clock = 216000;
1536                         break;
1537                 case DPLL_CFGCR0_LINK_RATE_2700:
1538                         link_clock = 270000;
1539                         break;
1540                 case DPLL_CFGCR0_LINK_RATE_3240:
1541                         link_clock = 324000;
1542                         break;
1543                 case DPLL_CFGCR0_LINK_RATE_4050:
1544                         link_clock = 405000;
1545                         break;
1546                 default:
1547                         WARN(1, "Unsupported link rate\n");
1548                         break;
1549                 }
1550                 link_clock *= 2;
1551         }
1552
1553         pipe_config->port_clock = link_clock;
1554
1555         ddi_dotclock_get(pipe_config);
1556 }
1557
1558 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1559                               struct intel_crtc_state *pipe_config)
1560 {
1561         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1562         int link_clock;
1563
1564         /*
1565          * ctrl1 register is already shifted for each pll, just use 0 to get
1566          * the internal shift for each field
1567          */
1568         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1569                 link_clock = skl_calc_wrpll_link(pll_state);
1570         } else {
1571                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1572                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1573
1574                 switch (link_clock) {
1575                 case DPLL_CTRL1_LINK_RATE_810:
1576                         link_clock = 81000;
1577                         break;
1578                 case DPLL_CTRL1_LINK_RATE_1080:
1579                         link_clock = 108000;
1580                         break;
1581                 case DPLL_CTRL1_LINK_RATE_1350:
1582                         link_clock = 135000;
1583                         break;
1584                 case DPLL_CTRL1_LINK_RATE_1620:
1585                         link_clock = 162000;
1586                         break;
1587                 case DPLL_CTRL1_LINK_RATE_2160:
1588                         link_clock = 216000;
1589                         break;
1590                 case DPLL_CTRL1_LINK_RATE_2700:
1591                         link_clock = 270000;
1592                         break;
1593                 default:
1594                         WARN(1, "Unsupported link rate\n");
1595                         break;
1596                 }
1597                 link_clock *= 2;
1598         }
1599
1600         pipe_config->port_clock = link_clock;
1601
1602         ddi_dotclock_get(pipe_config);
1603 }
1604
1605 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1606                               struct intel_crtc_state *pipe_config)
1607 {
1608         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1609         int link_clock = 0;
1610         u32 val, pll;
1611
1612         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1613         switch (val & PORT_CLK_SEL_MASK) {
1614         case PORT_CLK_SEL_LCPLL_810:
1615                 link_clock = 81000;
1616                 break;
1617         case PORT_CLK_SEL_LCPLL_1350:
1618                 link_clock = 135000;
1619                 break;
1620         case PORT_CLK_SEL_LCPLL_2700:
1621                 link_clock = 270000;
1622                 break;
1623         case PORT_CLK_SEL_WRPLL1:
1624                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1625                 break;
1626         case PORT_CLK_SEL_WRPLL2:
1627                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1628                 break;
1629         case PORT_CLK_SEL_SPLL:
1630                 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1631                 if (pll == SPLL_FREQ_810MHz)
1632                         link_clock = 81000;
1633                 else if (pll == SPLL_FREQ_1350MHz)
1634                         link_clock = 135000;
1635                 else if (pll == SPLL_FREQ_2700MHz)
1636                         link_clock = 270000;
1637                 else {
1638                         WARN(1, "bad spll freq\n");
1639                         return;
1640                 }
1641                 break;
1642         default:
1643                 WARN(1, "bad port clock sel\n");
1644                 return;
1645         }
1646
1647         pipe_config->port_clock = link_clock * 2;
1648
1649         ddi_dotclock_get(pipe_config);
1650 }
1651
1652 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1653 {
1654         struct dpll clock;
1655
1656         clock.m1 = 2;
1657         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1658         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1659                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1660         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1661         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1662         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1663
1664         return chv_calc_dpll_params(100000, &clock);
1665 }
1666
1667 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1668                               struct intel_crtc_state *pipe_config)
1669 {
1670         pipe_config->port_clock =
1671                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1672
1673         ddi_dotclock_get(pipe_config);
1674 }
1675
1676 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1677                                 struct intel_crtc_state *pipe_config)
1678 {
1679         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1680
1681         if (INTEL_GEN(dev_priv) >= 11)
1682                 icl_ddi_clock_get(encoder, pipe_config);
1683         else if (IS_CANNONLAKE(dev_priv))
1684                 cnl_ddi_clock_get(encoder, pipe_config);
1685         else if (IS_GEN9_LP(dev_priv))
1686                 bxt_ddi_clock_get(encoder, pipe_config);
1687         else if (IS_GEN9_BC(dev_priv))
1688                 skl_ddi_clock_get(encoder, pipe_config);
1689         else if (INTEL_GEN(dev_priv) <= 8)
1690                 hsw_ddi_clock_get(encoder, pipe_config);
1691 }
1692
1693 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1694 {
1695         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1696         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1697         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1698         u32 temp;
1699
1700         if (!intel_crtc_has_dp_encoder(crtc_state))
1701                 return;
1702
1703         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1704
1705         temp = TRANS_MSA_SYNC_CLK;
1706
1707         if (crtc_state->limited_color_range)
1708                 temp |= TRANS_MSA_CEA_RANGE;
1709
1710         switch (crtc_state->pipe_bpp) {
1711         case 18:
1712                 temp |= TRANS_MSA_6_BPC;
1713                 break;
1714         case 24:
1715                 temp |= TRANS_MSA_8_BPC;
1716                 break;
1717         case 30:
1718                 temp |= TRANS_MSA_10_BPC;
1719                 break;
1720         case 36:
1721                 temp |= TRANS_MSA_12_BPC;
1722                 break;
1723         default:
1724                 MISSING_CASE(crtc_state->pipe_bpp);
1725                 break;
1726         }
1727
1728         /*
1729          * As per DP 1.2 spec section 2.3.4.3 while sending
1730          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1731          * colorspace information. The output colorspace encoding is BT601.
1732          */
1733         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1734                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1735         /*
1736          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1737          * of Color Encoding Format and Content Color Gamut] while sending
1738          * YCBCR 420 signals we should program MSA MISC1 fields which
1739          * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1740          */
1741         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1742                 temp |= TRANS_MSA_USE_VSC_SDP;
1743         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1744 }
1745
1746 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1747                                     bool state)
1748 {
1749         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1750         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1751         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1752         u32 temp;
1753
1754         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1755         if (state == true)
1756                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1757         else
1758                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1759         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1760 }
1761
1762 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1763 {
1764         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1765         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1766         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1767         enum pipe pipe = crtc->pipe;
1768         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1769         enum port port = encoder->port;
1770         u32 temp;
1771
1772         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1773         temp = TRANS_DDI_FUNC_ENABLE;
1774         temp |= TRANS_DDI_SELECT_PORT(port);
1775
1776         switch (crtc_state->pipe_bpp) {
1777         case 18:
1778                 temp |= TRANS_DDI_BPC_6;
1779                 break;
1780         case 24:
1781                 temp |= TRANS_DDI_BPC_8;
1782                 break;
1783         case 30:
1784                 temp |= TRANS_DDI_BPC_10;
1785                 break;
1786         case 36:
1787                 temp |= TRANS_DDI_BPC_12;
1788                 break;
1789         default:
1790                 BUG();
1791         }
1792
1793         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1794                 temp |= TRANS_DDI_PVSYNC;
1795         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1796                 temp |= TRANS_DDI_PHSYNC;
1797
1798         if (cpu_transcoder == TRANSCODER_EDP) {
1799                 switch (pipe) {
1800                 case PIPE_A:
1801                         /* On Haswell, can only use the always-on power well for
1802                          * eDP when not using the panel fitter, and when not
1803                          * using motion blur mitigation (which we don't
1804                          * support). */
1805                         if (crtc_state->pch_pfit.force_thru)
1806                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1807                         else
1808                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1809                         break;
1810                 case PIPE_B:
1811                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1812                         break;
1813                 case PIPE_C:
1814                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1815                         break;
1816                 default:
1817                         BUG();
1818                         break;
1819                 }
1820         }
1821
1822         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1823                 if (crtc_state->has_hdmi_sink)
1824                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1825                 else
1826                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1827
1828                 if (crtc_state->hdmi_scrambling)
1829                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1830                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1831                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1832         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1833                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1834                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1835         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1836                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1837                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1838         } else {
1839                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1840                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1841         }
1842
1843         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1844 }
1845
1846 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1847 {
1848         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1849         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1850         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1851         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1852         u32 val = I915_READ(reg);
1853
1854         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1855         val |= TRANS_DDI_PORT_NONE;
1856         I915_WRITE(reg, val);
1857
1858         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1859             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1860                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1861                 /* Quirk time at 100ms for reliable operation */
1862                 msleep(100);
1863         }
1864 }
1865
1866 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1867                                      bool enable)
1868 {
1869         struct drm_device *dev = intel_encoder->base.dev;
1870         struct drm_i915_private *dev_priv = to_i915(dev);
1871         intel_wakeref_t wakeref;
1872         enum pipe pipe = 0;
1873         int ret = 0;
1874         u32 tmp;
1875
1876         wakeref = intel_display_power_get_if_enabled(dev_priv,
1877                                                      intel_encoder->power_domain);
1878         if (WARN_ON(!wakeref))
1879                 return -ENXIO;
1880
1881         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1882                 ret = -EIO;
1883                 goto out;
1884         }
1885
1886         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1887         if (enable)
1888                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1889         else
1890                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1891         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1892 out:
1893         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1894         return ret;
1895 }
1896
1897 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1898 {
1899         struct drm_device *dev = intel_connector->base.dev;
1900         struct drm_i915_private *dev_priv = to_i915(dev);
1901         struct intel_encoder *encoder = intel_connector->encoder;
1902         int type = intel_connector->base.connector_type;
1903         enum port port = encoder->port;
1904         enum transcoder cpu_transcoder;
1905         intel_wakeref_t wakeref;
1906         enum pipe pipe = 0;
1907         u32 tmp;
1908         bool ret;
1909
1910         wakeref = intel_display_power_get_if_enabled(dev_priv,
1911                                                      encoder->power_domain);
1912         if (!wakeref)
1913                 return false;
1914
1915         if (!encoder->get_hw_state(encoder, &pipe)) {
1916                 ret = false;
1917                 goto out;
1918         }
1919
1920         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
1921                 cpu_transcoder = TRANSCODER_EDP;
1922         else
1923                 cpu_transcoder = (enum transcoder) pipe;
1924
1925         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1926
1927         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1928         case TRANS_DDI_MODE_SELECT_HDMI:
1929         case TRANS_DDI_MODE_SELECT_DVI:
1930                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1931                 break;
1932
1933         case TRANS_DDI_MODE_SELECT_DP_SST:
1934                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1935                       type == DRM_MODE_CONNECTOR_DisplayPort;
1936                 break;
1937
1938         case TRANS_DDI_MODE_SELECT_DP_MST:
1939                 /* if the transcoder is in MST state then
1940                  * connector isn't connected */
1941                 ret = false;
1942                 break;
1943
1944         case TRANS_DDI_MODE_SELECT_FDI:
1945                 ret = type == DRM_MODE_CONNECTOR_VGA;
1946                 break;
1947
1948         default:
1949                 ret = false;
1950                 break;
1951         }
1952
1953 out:
1954         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1955
1956         return ret;
1957 }
1958
1959 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1960                                         u8 *pipe_mask, bool *is_dp_mst)
1961 {
1962         struct drm_device *dev = encoder->base.dev;
1963         struct drm_i915_private *dev_priv = to_i915(dev);
1964         enum port port = encoder->port;
1965         intel_wakeref_t wakeref;
1966         enum pipe p;
1967         u32 tmp;
1968         u8 mst_pipe_mask;
1969
1970         *pipe_mask = 0;
1971         *is_dp_mst = false;
1972
1973         wakeref = intel_display_power_get_if_enabled(dev_priv,
1974                                                      encoder->power_domain);
1975         if (!wakeref)
1976                 return;
1977
1978         tmp = I915_READ(DDI_BUF_CTL(port));
1979         if (!(tmp & DDI_BUF_CTL_ENABLE))
1980                 goto out;
1981
1982         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
1983                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1984
1985                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1986                 default:
1987                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1988                         /* fallthrough */
1989                 case TRANS_DDI_EDP_INPUT_A_ON:
1990                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1991                         *pipe_mask = BIT(PIPE_A);
1992                         break;
1993                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1994                         *pipe_mask = BIT(PIPE_B);
1995                         break;
1996                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1997                         *pipe_mask = BIT(PIPE_C);
1998                         break;
1999                 }
2000
2001                 goto out;
2002         }
2003
2004         mst_pipe_mask = 0;
2005         for_each_pipe(dev_priv, p) {
2006                 enum transcoder cpu_transcoder = (enum transcoder)p;
2007
2008                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2009
2010                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2011                         continue;
2012
2013                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2014                     TRANS_DDI_MODE_SELECT_DP_MST)
2015                         mst_pipe_mask |= BIT(p);
2016
2017                 *pipe_mask |= BIT(p);
2018         }
2019
2020         if (!*pipe_mask)
2021                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2022                               port_name(port));
2023
2024         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2025                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2026                               port_name(port), *pipe_mask);
2027                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2028         }
2029
2030         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2031                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2032                               port_name(port), *pipe_mask, mst_pipe_mask);
2033         else
2034                 *is_dp_mst = mst_pipe_mask;
2035
2036 out:
2037         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2038                 tmp = I915_READ(BXT_PHY_CTL(port));
2039                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2040                             BXT_PHY_LANE_POWERDOWN_ACK |
2041                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2042                         DRM_ERROR("Port %c enabled but PHY powered down? "
2043                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2044         }
2045
2046         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2047 }
2048
2049 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2050                             enum pipe *pipe)
2051 {
2052         u8 pipe_mask;
2053         bool is_mst;
2054
2055         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2056
2057         if (is_mst || !pipe_mask)
2058                 return false;
2059
2060         *pipe = ffs(pipe_mask) - 1;
2061
2062         return true;
2063 }
2064
2065 static inline enum intel_display_power_domain
2066 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2067 {
2068         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2069          * DC states enabled at the same time, while for driver initiated AUX
2070          * transfers we need the same AUX IOs to be powered but with DC states
2071          * disabled. Accordingly use the AUX power domain here which leaves DC
2072          * states enabled.
2073          * However, for non-A AUX ports the corresponding non-EDP transcoders
2074          * would have already enabled power well 2 and DC_OFF. This means we can
2075          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2076          * specific AUX_IO reference without powering up any extra wells.
2077          * Note that PSR is enabled only on Port A even though this function
2078          * returns the correct domain for other ports too.
2079          */
2080         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2081                                               intel_aux_power_domain(dig_port);
2082 }
2083
2084 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2085                                         struct intel_crtc_state *crtc_state)
2086 {
2087         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2088         struct intel_digital_port *dig_port;
2089
2090         /*
2091          * TODO: Add support for MST encoders. Atm, the following should never
2092          * happen since fake-MST encoders don't set their get_power_domains()
2093          * hook.
2094          */
2095         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2096                 return;
2097
2098         dig_port = enc_to_dig_port(&encoder->base);
2099         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2100
2101         /*
2102          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2103          * ports.
2104          */
2105         if (intel_crtc_has_dp_encoder(crtc_state) ||
2106             intel_port_is_tc(dev_priv, encoder->port))
2107                 intel_display_power_get(dev_priv,
2108                                         intel_ddi_main_link_aux_domain(dig_port));
2109
2110         /*
2111          * VDSC power is needed when DSC is enabled
2112          */
2113         if (crtc_state->dsc_params.compression_enable)
2114                 intel_display_power_get(dev_priv,
2115                                         intel_dsc_power_domain(crtc_state));
2116 }
2117
2118 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2119 {
2120         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2121         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2122         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2123         enum port port = encoder->port;
2124         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2125
2126         if (cpu_transcoder != TRANSCODER_EDP)
2127                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2128                            TRANS_CLK_SEL_PORT(port));
2129 }
2130
2131 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2132 {
2133         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2134         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2135
2136         if (cpu_transcoder != TRANSCODER_EDP)
2137                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2138                            TRANS_CLK_SEL_DISABLED);
2139 }
2140
2141 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2142                                 enum port port, u8 iboost)
2143 {
2144         u32 tmp;
2145
2146         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2147         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2148         if (iboost)
2149                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2150         else
2151                 tmp |= BALANCE_LEG_DISABLE(port);
2152         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2153 }
2154
2155 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2156                                int level, enum intel_output_type type)
2157 {
2158         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2159         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2160         enum port port = encoder->port;
2161         u8 iboost;
2162
2163         if (type == INTEL_OUTPUT_HDMI)
2164                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2165         else
2166                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2167
2168         if (iboost == 0) {
2169                 const struct ddi_buf_trans *ddi_translations;
2170                 int n_entries;
2171
2172                 if (type == INTEL_OUTPUT_HDMI)
2173                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2174                 else if (type == INTEL_OUTPUT_EDP)
2175                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2176                 else
2177                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2178
2179                 if (WARN_ON_ONCE(!ddi_translations))
2180                         return;
2181                 if (WARN_ON_ONCE(level >= n_entries))
2182                         level = n_entries - 1;
2183
2184                 iboost = ddi_translations[level].i_boost;
2185         }
2186
2187         /* Make sure that the requested I_boost is valid */
2188         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2189                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2190                 return;
2191         }
2192
2193         _skl_ddi_set_iboost(dev_priv, port, iboost);
2194
2195         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2196                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2197 }
2198
2199 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2200                                     int level, enum intel_output_type type)
2201 {
2202         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2203         const struct bxt_ddi_buf_trans *ddi_translations;
2204         enum port port = encoder->port;
2205         int n_entries;
2206
2207         if (type == INTEL_OUTPUT_HDMI)
2208                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2209         else if (type == INTEL_OUTPUT_EDP)
2210                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2211         else
2212                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2213
2214         if (WARN_ON_ONCE(!ddi_translations))
2215                 return;
2216         if (WARN_ON_ONCE(level >= n_entries))
2217                 level = n_entries - 1;
2218
2219         bxt_ddi_phy_set_signal_level(dev_priv, port,
2220                                      ddi_translations[level].margin,
2221                                      ddi_translations[level].scale,
2222                                      ddi_translations[level].enable,
2223                                      ddi_translations[level].deemphasis);
2224 }
2225
2226 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2227 {
2228         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2229         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2230         enum port port = encoder->port;
2231         int n_entries;
2232
2233         if (INTEL_GEN(dev_priv) >= 11) {
2234                 if (intel_port_is_combophy(dev_priv, port))
2235                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2236                                                 intel_dp->link_rate, &n_entries);
2237                 else
2238                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2239         } else if (IS_CANNONLAKE(dev_priv)) {
2240                 if (encoder->type == INTEL_OUTPUT_EDP)
2241                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2242                 else
2243                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2244         } else if (IS_GEN9_LP(dev_priv)) {
2245                 if (encoder->type == INTEL_OUTPUT_EDP)
2246                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2247                 else
2248                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2249         } else {
2250                 if (encoder->type == INTEL_OUTPUT_EDP)
2251                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2252                 else
2253                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2254         }
2255
2256         if (WARN_ON(n_entries < 1))
2257                 n_entries = 1;
2258         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2259                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2260
2261         return index_to_dp_signal_levels[n_entries - 1] &
2262                 DP_TRAIN_VOLTAGE_SWING_MASK;
2263 }
2264
2265 /*
2266  * We assume that the full set of pre-emphasis values can be
2267  * used on all DDI platforms. Should that change we need to
2268  * rethink this code.
2269  */
2270 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2271 {
2272         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2273         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2274                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2275         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2276                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2277         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2278                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2279         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2280         default:
2281                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2282         }
2283 }
2284
2285 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2286                                    int level, enum intel_output_type type)
2287 {
2288         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2289         const struct cnl_ddi_buf_trans *ddi_translations;
2290         enum port port = encoder->port;
2291         int n_entries, ln;
2292         u32 val;
2293
2294         if (type == INTEL_OUTPUT_HDMI)
2295                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2296         else if (type == INTEL_OUTPUT_EDP)
2297                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2298         else
2299                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2300
2301         if (WARN_ON_ONCE(!ddi_translations))
2302                 return;
2303         if (WARN_ON_ONCE(level >= n_entries))
2304                 level = n_entries - 1;
2305
2306         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2307         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2308         val &= ~SCALING_MODE_SEL_MASK;
2309         val |= SCALING_MODE_SEL(2);
2310         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2311
2312         /* Program PORT_TX_DW2 */
2313         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2314         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2315                  RCOMP_SCALAR_MASK);
2316         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2317         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2318         /* Rcomp scalar is fixed as 0x98 for every table entry */
2319         val |= RCOMP_SCALAR(0x98);
2320         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2321
2322         /* Program PORT_TX_DW4 */
2323         /* We cannot write to GRP. It would overrite individual loadgen */
2324         for (ln = 0; ln < 4; ln++) {
2325                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2326                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2327                          CURSOR_COEFF_MASK);
2328                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2329                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2330                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2331                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2332         }
2333
2334         /* Program PORT_TX_DW5 */
2335         /* All DW5 values are fixed for every table entry */
2336         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2337         val &= ~RTERM_SELECT_MASK;
2338         val |= RTERM_SELECT(6);
2339         val |= TAP3_DISABLE;
2340         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2341
2342         /* Program PORT_TX_DW7 */
2343         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2344         val &= ~N_SCALAR_MASK;
2345         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2346         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2347 }
2348
2349 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2350                                     int level, enum intel_output_type type)
2351 {
2352         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2353         enum port port = encoder->port;
2354         int width, rate, ln;
2355         u32 val;
2356
2357         if (type == INTEL_OUTPUT_HDMI) {
2358                 width = 4;
2359                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2360         } else {
2361                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2362
2363                 width = intel_dp->lane_count;
2364                 rate = intel_dp->link_rate;
2365         }
2366
2367         /*
2368          * 1. If port type is eDP or DP,
2369          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2370          * else clear to 0b.
2371          */
2372         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2373         if (type != INTEL_OUTPUT_HDMI)
2374                 val |= COMMON_KEEPER_EN;
2375         else
2376                 val &= ~COMMON_KEEPER_EN;
2377         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2378
2379         /* 2. Program loadgen select */
2380         /*
2381          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2382          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2383          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2384          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2385          */
2386         for (ln = 0; ln <= 3; ln++) {
2387                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2388                 val &= ~LOADGEN_SELECT;
2389
2390                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2391                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2392                         val |= LOADGEN_SELECT;
2393                 }
2394                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2395         }
2396
2397         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2398         val = I915_READ(CNL_PORT_CL1CM_DW5);
2399         val |= SUS_CLOCK_CONFIG;
2400         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2401
2402         /* 4. Clear training enable to change swing values */
2403         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2404         val &= ~TX_TRAINING_EN;
2405         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2406
2407         /* 5. Program swing and de-emphasis */
2408         cnl_ddi_vswing_program(encoder, level, type);
2409
2410         /* 6. Set training enable to trigger update */
2411         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2412         val |= TX_TRAINING_EN;
2413         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2414 }
2415
2416 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2417                                         u32 level, enum phy phy, int type,
2418                                         int rate)
2419 {
2420         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2421         u32 n_entries, val;
2422         int ln;
2423
2424         ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2425                                                    &n_entries);
2426         if (!ddi_translations)
2427                 return;
2428
2429         if (level >= n_entries) {
2430                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2431                 level = n_entries - 1;
2432         }
2433
2434         /* Set PORT_TX_DW5 */
2435         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2436         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2437                   TAP2_DISABLE | TAP3_DISABLE);
2438         val |= SCALING_MODE_SEL(0x2);
2439         val |= RTERM_SELECT(0x6);
2440         val |= TAP3_DISABLE;
2441         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2442
2443         /* Program PORT_TX_DW2 */
2444         val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2445         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2446                  RCOMP_SCALAR_MASK);
2447         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2448         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2449         /* Program Rcomp scalar for every table entry */
2450         val |= RCOMP_SCALAR(0x98);
2451         I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2452
2453         /* Program PORT_TX_DW4 */
2454         /* We cannot write to GRP. It would overwrite individual loadgen. */
2455         for (ln = 0; ln <= 3; ln++) {
2456                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2457                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2458                          CURSOR_COEFF_MASK);
2459                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2460                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2461                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2462                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2463         }
2464
2465         /* Program PORT_TX_DW7 */
2466         val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2467         val &= ~N_SCALAR_MASK;
2468         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2469         I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2470 }
2471
2472 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2473                                               u32 level,
2474                                               enum intel_output_type type)
2475 {
2476         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2477         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2478         int width = 0;
2479         int rate = 0;
2480         u32 val;
2481         int ln = 0;
2482
2483         if (type == INTEL_OUTPUT_HDMI) {
2484                 width = 4;
2485                 /* Rate is always < than 6GHz for HDMI */
2486         } else {
2487                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2488
2489                 width = intel_dp->lane_count;
2490                 rate = intel_dp->link_rate;
2491         }
2492
2493         /*
2494          * 1. If port type is eDP or DP,
2495          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2496          * else clear to 0b.
2497          */
2498         val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2499         if (type == INTEL_OUTPUT_HDMI)
2500                 val &= ~COMMON_KEEPER_EN;
2501         else
2502                 val |= COMMON_KEEPER_EN;
2503         I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2504
2505         /* 2. Program loadgen select */
2506         /*
2507          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2508          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2509          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2510          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2511          */
2512         for (ln = 0; ln <= 3; ln++) {
2513                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2514                 val &= ~LOADGEN_SELECT;
2515
2516                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2517                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2518                         val |= LOADGEN_SELECT;
2519                 }
2520                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2521         }
2522
2523         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2524         val = I915_READ(ICL_PORT_CL_DW5(phy));
2525         val |= SUS_CLOCK_CONFIG;
2526         I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2527
2528         /* 4. Clear training enable to change swing values */
2529         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2530         val &= ~TX_TRAINING_EN;
2531         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2532
2533         /* 5. Program swing and de-emphasis */
2534         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2535
2536         /* 6. Set training enable to trigger update */
2537         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2538         val |= TX_TRAINING_EN;
2539         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2540 }
2541
2542 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2543                                            int link_clock,
2544                                            u32 level)
2545 {
2546         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2547         enum port port = encoder->port;
2548         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2549         u32 n_entries, val;
2550         int ln;
2551
2552         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2553         ddi_translations = icl_mg_phy_ddi_translations;
2554         /* The table does not have values for level 3 and level 9. */
2555         if (level >= n_entries || level == 3 || level == 9) {
2556                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2557                               level, n_entries - 2);
2558                 level = n_entries - 2;
2559         }
2560
2561         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2562         for (ln = 0; ln < 2; ln++) {
2563                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, port));
2564                 val &= ~CRI_USE_FS32;
2565                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val);
2566
2567                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, port));
2568                 val &= ~CRI_USE_FS32;
2569                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val);
2570         }
2571
2572         /* Program MG_TX_SWINGCTRL with values from vswing table */
2573         for (ln = 0; ln < 2; ln++) {
2574                 val = I915_READ(MG_TX1_SWINGCTRL(ln, port));
2575                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2576                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2577                         ddi_translations[level].cri_txdeemph_override_17_12);
2578                 I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val);
2579
2580                 val = I915_READ(MG_TX2_SWINGCTRL(ln, port));
2581                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2582                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2583                         ddi_translations[level].cri_txdeemph_override_17_12);
2584                 I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val);
2585         }
2586
2587         /* Program MG_TX_DRVCTRL with values from vswing table */
2588         for (ln = 0; ln < 2; ln++) {
2589                 val = I915_READ(MG_TX1_DRVCTRL(ln, port));
2590                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2591                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2592                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2593                         ddi_translations[level].cri_txdeemph_override_5_0) |
2594                         CRI_TXDEEMPH_OVERRIDE_11_6(
2595                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2596                         CRI_TXDEEMPH_OVERRIDE_EN;
2597                 I915_WRITE(MG_TX1_DRVCTRL(ln, port), val);
2598
2599                 val = I915_READ(MG_TX2_DRVCTRL(ln, port));
2600                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2601                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2602                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2603                         ddi_translations[level].cri_txdeemph_override_5_0) |
2604                         CRI_TXDEEMPH_OVERRIDE_11_6(
2605                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2606                         CRI_TXDEEMPH_OVERRIDE_EN;
2607                 I915_WRITE(MG_TX2_DRVCTRL(ln, port), val);
2608
2609                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2610         }
2611
2612         /*
2613          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2614          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2615          * values from table for which TX1 and TX2 enabled.
2616          */
2617         for (ln = 0; ln < 2; ln++) {
2618                 val = I915_READ(MG_CLKHUB(ln, port));
2619                 if (link_clock < 300000)
2620                         val |= CFG_LOW_RATE_LKREN_EN;
2621                 else
2622                         val &= ~CFG_LOW_RATE_LKREN_EN;
2623                 I915_WRITE(MG_CLKHUB(ln, port), val);
2624         }
2625
2626         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2627         for (ln = 0; ln < 2; ln++) {
2628                 val = I915_READ(MG_TX1_DCC(ln, port));
2629                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2630                 if (link_clock <= 500000) {
2631                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2632                 } else {
2633                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2634                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2635                 }
2636                 I915_WRITE(MG_TX1_DCC(ln, port), val);
2637
2638                 val = I915_READ(MG_TX2_DCC(ln, port));
2639                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2640                 if (link_clock <= 500000) {
2641                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2642                 } else {
2643                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2644                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2645                 }
2646                 I915_WRITE(MG_TX2_DCC(ln, port), val);
2647         }
2648
2649         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2650         for (ln = 0; ln < 2; ln++) {
2651                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, port));
2652                 val |= CRI_CALCINIT;
2653                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val);
2654
2655                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, port));
2656                 val |= CRI_CALCINIT;
2657                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val);
2658         }
2659 }
2660
2661 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2662                                     int link_clock,
2663                                     u32 level,
2664                                     enum intel_output_type type)
2665 {
2666         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2667         enum port port = encoder->port;
2668
2669         if (intel_port_is_combophy(dev_priv, port))
2670                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2671         else
2672                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2673 }
2674
2675 static u32 translate_signal_level(int signal_levels)
2676 {
2677         int i;
2678
2679         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2680                 if (index_to_dp_signal_levels[i] == signal_levels)
2681                         return i;
2682         }
2683
2684         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2685              signal_levels);
2686
2687         return 0;
2688 }
2689
2690 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2691 {
2692         u8 train_set = intel_dp->train_set[0];
2693         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2694                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2695
2696         return translate_signal_level(signal_levels);
2697 }
2698
2699 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2700 {
2701         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2702         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2703         struct intel_encoder *encoder = &dport->base;
2704         int level = intel_ddi_dp_level(intel_dp);
2705
2706         if (INTEL_GEN(dev_priv) >= 11)
2707                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2708                                         level, encoder->type);
2709         else if (IS_CANNONLAKE(dev_priv))
2710                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2711         else
2712                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2713
2714         return 0;
2715 }
2716
2717 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2718 {
2719         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2720         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2721         struct intel_encoder *encoder = &dport->base;
2722         int level = intel_ddi_dp_level(intel_dp);
2723
2724         if (IS_GEN9_BC(dev_priv))
2725                 skl_ddi_set_iboost(encoder, level, encoder->type);
2726
2727         return DDI_BUF_TRANS_SELECT(level);
2728 }
2729
2730 static inline
2731 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2732                               enum phy phy)
2733 {
2734         if (intel_phy_is_combo(dev_priv, phy)) {
2735                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2736         } else if (intel_phy_is_tc(dev_priv, phy)) {
2737                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2738                                                         (enum port)phy);
2739
2740                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2741         }
2742
2743         return 0;
2744 }
2745
2746 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2747                                   const struct intel_crtc_state *crtc_state)
2748 {
2749         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2750         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2751         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2752         u32 val;
2753
2754         mutex_lock(&dev_priv->dpll_lock);
2755
2756         val = I915_READ(ICL_DPCLKA_CFGCR0);
2757         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2758
2759         if (intel_phy_is_combo(dev_priv, phy)) {
2760                 /*
2761                  * Even though this register references DDIs, note that we
2762                  * want to pass the PHY rather than the port (DDI).  For
2763                  * ICL, port=phy in all cases so it doesn't matter, but for
2764                  * EHL the bspec notes the following:
2765                  *
2766                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2767                  *   Clock Select chooses the PLL for both DDIA and DDID and
2768                  *   drives port A in all cases."
2769                  */
2770                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2771                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2772                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2773                 POSTING_READ(ICL_DPCLKA_CFGCR0);
2774         }
2775
2776         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2777         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2778
2779         mutex_unlock(&dev_priv->dpll_lock);
2780 }
2781
2782 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2783 {
2784         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2785         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2786         u32 val;
2787
2788         mutex_lock(&dev_priv->dpll_lock);
2789
2790         val = I915_READ(ICL_DPCLKA_CFGCR0);
2791         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2792         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2793
2794         mutex_unlock(&dev_priv->dpll_lock);
2795 }
2796
2797 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2798 {
2799         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2800         u32 val;
2801         enum port port;
2802         u32 port_mask;
2803         bool ddi_clk_needed;
2804
2805         /*
2806          * In case of DP MST, we sanitize the primary encoder only, not the
2807          * virtual ones.
2808          */
2809         if (encoder->type == INTEL_OUTPUT_DP_MST)
2810                 return;
2811
2812         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2813                 u8 pipe_mask;
2814                 bool is_mst;
2815
2816                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2817                 /*
2818                  * In the unlikely case that BIOS enables DP in MST mode, just
2819                  * warn since our MST HW readout is incomplete.
2820                  */
2821                 if (WARN_ON(is_mst))
2822                         return;
2823         }
2824
2825         port_mask = BIT(encoder->port);
2826         ddi_clk_needed = encoder->base.crtc;
2827
2828         if (encoder->type == INTEL_OUTPUT_DSI) {
2829                 struct intel_encoder *other_encoder;
2830
2831                 port_mask = intel_dsi_encoder_ports(encoder);
2832                 /*
2833                  * Sanity check that we haven't incorrectly registered another
2834                  * encoder using any of the ports of this DSI encoder.
2835                  */
2836                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2837                         if (other_encoder == encoder)
2838                                 continue;
2839
2840                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2841                                 return;
2842                 }
2843                 /*
2844                  * For DSI we keep the ddi clocks gated
2845                  * except during enable/disable sequence.
2846                  */
2847                 ddi_clk_needed = false;
2848         }
2849
2850         val = I915_READ(ICL_DPCLKA_CFGCR0);
2851         for_each_port_masked(port, port_mask) {
2852                 enum phy phy = intel_port_to_phy(dev_priv, port);
2853
2854                 bool ddi_clk_ungated = !(val &
2855                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2856                                                                    phy));
2857
2858                 if (ddi_clk_needed == ddi_clk_ungated)
2859                         continue;
2860
2861                 /*
2862                  * Punt on the case now where clock is gated, but it would
2863                  * be needed by the port. Something else is really broken then.
2864                  */
2865                 if (WARN_ON(ddi_clk_needed))
2866                         continue;
2867
2868                 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2869                          phy_name(port));
2870                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2871                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2872         }
2873 }
2874
2875 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2876                                  const struct intel_crtc_state *crtc_state)
2877 {
2878         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2879         enum port port = encoder->port;
2880         u32 val;
2881         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2882
2883         if (WARN_ON(!pll))
2884                 return;
2885
2886         mutex_lock(&dev_priv->dpll_lock);
2887
2888         if (INTEL_GEN(dev_priv) >= 11) {
2889                 if (!intel_port_is_combophy(dev_priv, port))
2890                         I915_WRITE(DDI_CLK_SEL(port),
2891                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2892         } else if (IS_CANNONLAKE(dev_priv)) {
2893                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2894                 val = I915_READ(DPCLKA_CFGCR0);
2895                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2896                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2897                 I915_WRITE(DPCLKA_CFGCR0, val);
2898
2899                 /*
2900                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2901                  * This step and the step before must be done with separate
2902                  * register writes.
2903                  */
2904                 val = I915_READ(DPCLKA_CFGCR0);
2905                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2906                 I915_WRITE(DPCLKA_CFGCR0, val);
2907         } else if (IS_GEN9_BC(dev_priv)) {
2908                 /* DDI -> PLL mapping  */
2909                 val = I915_READ(DPLL_CTRL2);
2910
2911                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2912                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2913                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2914                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2915
2916                 I915_WRITE(DPLL_CTRL2, val);
2917
2918         } else if (INTEL_GEN(dev_priv) < 9) {
2919                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2920         }
2921
2922         mutex_unlock(&dev_priv->dpll_lock);
2923 }
2924
2925 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2926 {
2927         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2928         enum port port = encoder->port;
2929
2930         if (INTEL_GEN(dev_priv) >= 11) {
2931                 if (!intel_port_is_combophy(dev_priv, port))
2932                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2933         } else if (IS_CANNONLAKE(dev_priv)) {
2934                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2935                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2936         } else if (IS_GEN9_BC(dev_priv)) {
2937                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2938                            DPLL_CTRL2_DDI_CLK_OFF(port));
2939         } else if (INTEL_GEN(dev_priv) < 9) {
2940                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2941         }
2942 }
2943
2944 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2945 {
2946         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2947         enum port port = dig_port->base.port;
2948         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2949         u32 val;
2950         int ln;
2951
2952         if (tc_port == PORT_TC_NONE)
2953                 return;
2954
2955         for (ln = 0; ln < 2; ln++) {
2956                 val = I915_READ(MG_DP_MODE(ln, port));
2957                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2958                        MG_DP_MODE_CFG_TRPWR_GATING |
2959                        MG_DP_MODE_CFG_CLNPWR_GATING |
2960                        MG_DP_MODE_CFG_DIGPWR_GATING |
2961                        MG_DP_MODE_CFG_GAONPWR_GATING;
2962                 I915_WRITE(MG_DP_MODE(ln, port), val);
2963         }
2964
2965         val = I915_READ(MG_MISC_SUS0(tc_port));
2966         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
2967                MG_MISC_SUS0_CFG_TR2PWR_GATING |
2968                MG_MISC_SUS0_CFG_CL2PWR_GATING |
2969                MG_MISC_SUS0_CFG_GAONPWR_GATING |
2970                MG_MISC_SUS0_CFG_TRPWR_GATING |
2971                MG_MISC_SUS0_CFG_CL1PWR_GATING |
2972                MG_MISC_SUS0_CFG_DGPWR_GATING;
2973         I915_WRITE(MG_MISC_SUS0(tc_port), val);
2974 }
2975
2976 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
2977 {
2978         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2979         enum port port = dig_port->base.port;
2980         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2981         u32 val;
2982         int ln;
2983
2984         if (tc_port == PORT_TC_NONE)
2985                 return;
2986
2987         for (ln = 0; ln < 2; ln++) {
2988                 val = I915_READ(MG_DP_MODE(ln, port));
2989                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
2990                          MG_DP_MODE_CFG_TRPWR_GATING |
2991                          MG_DP_MODE_CFG_CLNPWR_GATING |
2992                          MG_DP_MODE_CFG_DIGPWR_GATING |
2993                          MG_DP_MODE_CFG_GAONPWR_GATING);
2994                 I915_WRITE(MG_DP_MODE(ln, port), val);
2995         }
2996
2997         val = I915_READ(MG_MISC_SUS0(tc_port));
2998         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
2999                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
3000                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
3001                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
3002                  MG_MISC_SUS0_CFG_TRPWR_GATING |
3003                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
3004                  MG_MISC_SUS0_CFG_DGPWR_GATING);
3005         I915_WRITE(MG_MISC_SUS0(tc_port), val);
3006 }
3007
3008 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
3009 {
3010         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3011         enum port port = intel_dig_port->base.port;
3012         u32 ln0, ln1, lane_mask;
3013
3014         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3015                 return;
3016
3017         ln0 = I915_READ(MG_DP_MODE(0, port));
3018         ln1 = I915_READ(MG_DP_MODE(1, port));
3019
3020         switch (intel_dig_port->tc_mode) {
3021         case TC_PORT_DP_ALT:
3022                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3023                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3024
3025                 lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
3026
3027                 switch (lane_mask) {
3028                 case 0x1:
3029                 case 0x4:
3030                         break;
3031                 case 0x2:
3032                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3033                         break;
3034                 case 0x3:
3035                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3036                                MG_DP_MODE_CFG_DP_X2_MODE;
3037                         break;
3038                 case 0x8:
3039                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3040                         break;
3041                 case 0xC:
3042                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3043                                MG_DP_MODE_CFG_DP_X2_MODE;
3044                         break;
3045                 case 0xF:
3046                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3047                                MG_DP_MODE_CFG_DP_X2_MODE;
3048                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3049                                MG_DP_MODE_CFG_DP_X2_MODE;
3050                         break;
3051                 default:
3052                         MISSING_CASE(lane_mask);
3053                 }
3054                 break;
3055
3056         case TC_PORT_LEGACY:
3057                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3058                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3059                 break;
3060
3061         default:
3062                 MISSING_CASE(intel_dig_port->tc_mode);
3063                 return;
3064         }
3065
3066         I915_WRITE(MG_DP_MODE(0, port), ln0);
3067         I915_WRITE(MG_DP_MODE(1, port), ln1);
3068 }
3069
3070 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3071                                         const struct intel_crtc_state *crtc_state)
3072 {
3073         if (!crtc_state->fec_enable)
3074                 return;
3075
3076         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3077                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3078 }
3079
3080 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3081                                  const struct intel_crtc_state *crtc_state)
3082 {
3083         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3084         enum port port = encoder->port;
3085         u32 val;
3086
3087         if (!crtc_state->fec_enable)
3088                 return;
3089
3090         val = I915_READ(DP_TP_CTL(port));
3091         val |= DP_TP_CTL_FEC_ENABLE;
3092         I915_WRITE(DP_TP_CTL(port), val);
3093
3094         if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
3095                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3096                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3097                                     1))
3098                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3099 }
3100
3101 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3102                                         const struct intel_crtc_state *crtc_state)
3103 {
3104         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3105         enum port port = encoder->port;
3106         u32 val;
3107
3108         if (!crtc_state->fec_enable)
3109                 return;
3110
3111         val = I915_READ(DP_TP_CTL(port));
3112         val &= ~DP_TP_CTL_FEC_ENABLE;
3113         I915_WRITE(DP_TP_CTL(port), val);
3114         POSTING_READ(DP_TP_CTL(port));
3115 }
3116
3117 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3118                                     const struct intel_crtc_state *crtc_state,
3119                                     const struct drm_connector_state *conn_state)
3120 {
3121         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3122         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3123         enum port port = encoder->port;
3124         enum phy phy = intel_port_to_phy(dev_priv, port);
3125         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3126         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3127         int level = intel_ddi_dp_level(intel_dp);
3128
3129         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3130
3131         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3132                                  crtc_state->lane_count, is_mst);
3133
3134         intel_edp_panel_on(intel_dp);
3135
3136         intel_ddi_clk_select(encoder, crtc_state);
3137
3138         if (!intel_port_is_tc(dev_priv, port) ||
3139             dig_port->tc_mode != TC_PORT_TBT_ALT)
3140                 intel_display_power_get(dev_priv,
3141                                         dig_port->ddi_io_power_domain);
3142
3143         icl_program_mg_dp_mode(dig_port);
3144         icl_disable_phy_clock_gating(dig_port);
3145
3146         if (INTEL_GEN(dev_priv) >= 11)
3147                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3148                                         level, encoder->type);
3149         else if (IS_CANNONLAKE(dev_priv))
3150                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3151         else if (IS_GEN9_LP(dev_priv))
3152                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3153         else
3154                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3155
3156         if (intel_port_is_combophy(dev_priv, port)) {
3157                 bool lane_reversal =
3158                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3159
3160                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3161                                                crtc_state->lane_count,
3162                                                lane_reversal);
3163         }
3164
3165         intel_ddi_init_dp_buf_reg(encoder);
3166         if (!is_mst)
3167                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3168         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3169                                               true);
3170         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3171         intel_dp_start_link_train(intel_dp);
3172         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3173                 intel_dp_stop_link_train(intel_dp);
3174
3175         intel_ddi_enable_fec(encoder, crtc_state);
3176
3177         icl_enable_phy_clock_gating(dig_port);
3178
3179         if (!is_mst)
3180                 intel_ddi_enable_pipe_clock(crtc_state);
3181
3182         intel_dsc_enable(encoder, crtc_state);
3183 }
3184
3185 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3186                                       const struct intel_crtc_state *crtc_state,
3187                                       const struct drm_connector_state *conn_state)
3188 {
3189         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3190         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3191         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3192         enum port port = encoder->port;
3193         int level = intel_ddi_hdmi_level(dev_priv, port);
3194         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3195
3196         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3197         intel_ddi_clk_select(encoder, crtc_state);
3198
3199         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3200
3201         icl_program_mg_dp_mode(dig_port);
3202         icl_disable_phy_clock_gating(dig_port);
3203
3204         if (INTEL_GEN(dev_priv) >= 11)
3205                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3206                                         level, INTEL_OUTPUT_HDMI);
3207         else if (IS_CANNONLAKE(dev_priv))
3208                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3209         else if (IS_GEN9_LP(dev_priv))
3210                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3211         else
3212                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3213
3214         icl_enable_phy_clock_gating(dig_port);
3215
3216         if (IS_GEN9_BC(dev_priv))
3217                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3218
3219         intel_ddi_enable_pipe_clock(crtc_state);
3220
3221         intel_dig_port->set_infoframes(encoder,
3222                                        crtc_state->has_infoframe,
3223                                        crtc_state, conn_state);
3224 }
3225
3226 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3227                                  const struct intel_crtc_state *crtc_state,
3228                                  const struct drm_connector_state *conn_state)
3229 {
3230         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3231         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3232         enum pipe pipe = crtc->pipe;
3233
3234         /*
3235          * When called from DP MST code:
3236          * - conn_state will be NULL
3237          * - encoder will be the main encoder (ie. mst->primary)
3238          * - the main connector associated with this port
3239          *   won't be active or linked to a crtc
3240          * - crtc_state will be the state of the first stream to
3241          *   be activated on this port, and it may not be the same
3242          *   stream that will be deactivated last, but each stream
3243          *   should have a state that is identical when it comes to
3244          *   the DP link parameteres
3245          */
3246
3247         WARN_ON(crtc_state->has_pch_encoder);
3248
3249         if (INTEL_GEN(dev_priv) >= 11)
3250                 icl_map_plls_to_ports(encoder, crtc_state);
3251
3252         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3253
3254         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3255                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3256         } else {
3257                 struct intel_lspcon *lspcon =
3258                                 enc_to_intel_lspcon(&encoder->base);
3259
3260                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3261                 if (lspcon->active) {
3262                         struct intel_digital_port *dig_port =
3263                                         enc_to_dig_port(&encoder->base);
3264
3265                         dig_port->set_infoframes(encoder,
3266                                                  crtc_state->has_infoframe,
3267                                                  crtc_state, conn_state);
3268                 }
3269         }
3270 }
3271
3272 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3273                                   const struct intel_crtc_state *crtc_state)
3274 {
3275         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3276         enum port port = encoder->port;
3277         bool wait = false;
3278         u32 val;
3279
3280         val = I915_READ(DDI_BUF_CTL(port));
3281         if (val & DDI_BUF_CTL_ENABLE) {
3282                 val &= ~DDI_BUF_CTL_ENABLE;
3283                 I915_WRITE(DDI_BUF_CTL(port), val);
3284                 wait = true;
3285         }
3286
3287         val = I915_READ(DP_TP_CTL(port));
3288         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3289         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3290         I915_WRITE(DP_TP_CTL(port), val);
3291
3292         /* Disable FEC in DP Sink */
3293         intel_ddi_disable_fec_state(encoder, crtc_state);
3294
3295         if (wait)
3296                 intel_wait_ddi_buf_idle(dev_priv, port);
3297 }
3298
3299 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3300                                       const struct intel_crtc_state *old_crtc_state,
3301                                       const struct drm_connector_state *old_conn_state)
3302 {
3303         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3304         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3305         struct intel_dp *intel_dp = &dig_port->dp;
3306         bool is_mst = intel_crtc_has_type(old_crtc_state,
3307                                           INTEL_OUTPUT_DP_MST);
3308
3309         if (!is_mst) {
3310                 intel_ddi_disable_pipe_clock(old_crtc_state);
3311                 /*
3312                  * Power down sink before disabling the port, otherwise we end
3313                  * up getting interrupts from the sink on detecting link loss.
3314                  */
3315                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3316         }
3317
3318         intel_disable_ddi_buf(encoder, old_crtc_state);
3319
3320         intel_edp_panel_vdd_on(intel_dp);
3321         intel_edp_panel_off(intel_dp);
3322
3323         if (!intel_port_is_tc(dev_priv, encoder->port) ||
3324             dig_port->tc_mode != TC_PORT_TBT_ALT)
3325                 intel_display_power_put_unchecked(dev_priv,
3326                                                   dig_port->ddi_io_power_domain);
3327
3328         intel_ddi_clk_disable(encoder);
3329 }
3330
3331 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3332                                         const struct intel_crtc_state *old_crtc_state,
3333                                         const struct drm_connector_state *old_conn_state)
3334 {
3335         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3336         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3337         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3338
3339         dig_port->set_infoframes(encoder, false,
3340                                  old_crtc_state, old_conn_state);
3341
3342         intel_ddi_disable_pipe_clock(old_crtc_state);
3343
3344         intel_disable_ddi_buf(encoder, old_crtc_state);
3345
3346         intel_display_power_put_unchecked(dev_priv,
3347                                           dig_port->ddi_io_power_domain);
3348
3349         intel_ddi_clk_disable(encoder);
3350
3351         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3352 }
3353
3354 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3355                                    const struct intel_crtc_state *old_crtc_state,
3356                                    const struct drm_connector_state *old_conn_state)
3357 {
3358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3359
3360         /*
3361          * When called from DP MST code:
3362          * - old_conn_state will be NULL
3363          * - encoder will be the main encoder (ie. mst->primary)
3364          * - the main connector associated with this port
3365          *   won't be active or linked to a crtc
3366          * - old_crtc_state will be the state of the last stream to
3367          *   be deactivated on this port, and it may not be the same
3368          *   stream that was activated last, but each stream
3369          *   should have a state that is identical when it comes to
3370          *   the DP link parameteres
3371          */
3372
3373         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3374                 intel_ddi_post_disable_hdmi(encoder,
3375                                             old_crtc_state, old_conn_state);
3376         else
3377                 intel_ddi_post_disable_dp(encoder,
3378                                           old_crtc_state, old_conn_state);
3379
3380         if (INTEL_GEN(dev_priv) >= 11)
3381                 icl_unmap_plls_to_ports(encoder);
3382 }
3383
3384 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3385                                 const struct intel_crtc_state *old_crtc_state,
3386                                 const struct drm_connector_state *old_conn_state)
3387 {
3388         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3389         u32 val;
3390
3391         /*
3392          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3393          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3394          * step 13 is the correct place for it. Step 18 is where it was
3395          * originally before the BUN.
3396          */
3397         val = I915_READ(FDI_RX_CTL(PIPE_A));
3398         val &= ~FDI_RX_ENABLE;
3399         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3400
3401         intel_disable_ddi_buf(encoder, old_crtc_state);
3402         intel_ddi_clk_disable(encoder);
3403
3404         val = I915_READ(FDI_RX_MISC(PIPE_A));
3405         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3406         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3407         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3408
3409         val = I915_READ(FDI_RX_CTL(PIPE_A));
3410         val &= ~FDI_PCDCLK;
3411         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3412
3413         val = I915_READ(FDI_RX_CTL(PIPE_A));
3414         val &= ~FDI_RX_PLL_ENABLE;
3415         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3416 }
3417
3418 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3419                                 const struct intel_crtc_state *crtc_state,
3420                                 const struct drm_connector_state *conn_state)
3421 {
3422         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3423         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3424         enum port port = encoder->port;
3425
3426         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3427                 intel_dp_stop_link_train(intel_dp);
3428
3429         intel_edp_backlight_on(crtc_state, conn_state);
3430         intel_psr_enable(intel_dp, crtc_state);
3431         intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
3432         intel_edp_drrs_enable(intel_dp, crtc_state);
3433
3434         if (crtc_state->has_audio)
3435                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3436 }
3437
3438 static i915_reg_t
3439 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3440                                enum port port)
3441 {
3442         static const i915_reg_t regs[] = {
3443                 [PORT_A] = CHICKEN_TRANS_EDP,
3444                 [PORT_B] = CHICKEN_TRANS_A,
3445                 [PORT_C] = CHICKEN_TRANS_B,
3446                 [PORT_D] = CHICKEN_TRANS_C,
3447                 [PORT_E] = CHICKEN_TRANS_A,
3448         };
3449
3450         WARN_ON(INTEL_GEN(dev_priv) < 9);
3451
3452         if (WARN_ON(port < PORT_A || port > PORT_E))
3453                 port = PORT_A;
3454
3455         return regs[port];
3456 }
3457
3458 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3459                                   const struct intel_crtc_state *crtc_state,
3460                                   const struct drm_connector_state *conn_state)
3461 {
3462         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3463         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3464         struct drm_connector *connector = conn_state->connector;
3465         enum port port = encoder->port;
3466
3467         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3468                                                crtc_state->hdmi_high_tmds_clock_ratio,
3469                                                crtc_state->hdmi_scrambling))
3470                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3471                           connector->base.id, connector->name);
3472
3473         /* Display WA #1143: skl,kbl,cfl */
3474         if (IS_GEN9_BC(dev_priv)) {
3475                 /*
3476                  * For some reason these chicken bits have been
3477                  * stuffed into a transcoder register, event though
3478                  * the bits affect a specific DDI port rather than
3479                  * a specific transcoder.
3480                  */
3481                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3482                 u32 val;
3483
3484                 val = I915_READ(reg);
3485
3486                 if (port == PORT_E)
3487                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3488                                 DDIE_TRAINING_OVERRIDE_VALUE;
3489                 else
3490                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3491                                 DDI_TRAINING_OVERRIDE_VALUE;
3492
3493                 I915_WRITE(reg, val);
3494                 POSTING_READ(reg);
3495
3496                 udelay(1);
3497
3498                 if (port == PORT_E)
3499                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3500                                  DDIE_TRAINING_OVERRIDE_VALUE);
3501                 else
3502                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3503                                  DDI_TRAINING_OVERRIDE_VALUE);
3504
3505                 I915_WRITE(reg, val);
3506         }
3507
3508         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3509          * are ignored so nothing special needs to be done besides
3510          * enabling the port.
3511          */
3512         I915_WRITE(DDI_BUF_CTL(port),
3513                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3514
3515         if (crtc_state->has_audio)
3516                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3517 }
3518
3519 static void intel_enable_ddi(struct intel_encoder *encoder,
3520                              const struct intel_crtc_state *crtc_state,
3521                              const struct drm_connector_state *conn_state)
3522 {
3523         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3524                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3525         else
3526                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3527
3528         /* Enable hdcp if it's desired */
3529         if (conn_state->content_protection ==
3530             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3531                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3532 }
3533
3534 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3535                                  const struct intel_crtc_state *old_crtc_state,
3536                                  const struct drm_connector_state *old_conn_state)
3537 {
3538         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3539
3540         intel_dp->link_trained = false;
3541
3542         if (old_crtc_state->has_audio)
3543                 intel_audio_codec_disable(encoder,
3544                                           old_crtc_state, old_conn_state);
3545
3546         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3547         intel_psr_disable(intel_dp, old_crtc_state);
3548         intel_edp_backlight_off(old_conn_state);
3549         /* Disable the decompression in DP Sink */
3550         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3551                                               false);
3552 }
3553
3554 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3555                                    const struct intel_crtc_state *old_crtc_state,
3556                                    const struct drm_connector_state *old_conn_state)
3557 {
3558         struct drm_connector *connector = old_conn_state->connector;
3559
3560         if (old_crtc_state->has_audio)
3561                 intel_audio_codec_disable(encoder,
3562                                           old_crtc_state, old_conn_state);
3563
3564         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3565                                                false, false))
3566                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3567                               connector->base.id, connector->name);
3568 }
3569
3570 static void intel_disable_ddi(struct intel_encoder *encoder,
3571                               const struct intel_crtc_state *old_crtc_state,
3572                               const struct drm_connector_state *old_conn_state)
3573 {
3574         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3575
3576         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3577                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3578         else
3579                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3580 }
3581
3582 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
3583                                      const struct intel_crtc_state *crtc_state,
3584                                      const struct drm_connector_state *conn_state)
3585 {
3586         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3587
3588         intel_ddi_set_pipe_settings(crtc_state);
3589
3590         intel_psr_update(intel_dp, crtc_state);
3591         intel_edp_drrs_enable(intel_dp, crtc_state);
3592
3593         intel_panel_update_backlight(encoder, crtc_state, conn_state);
3594 }
3595
3596 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
3597                                   const struct intel_crtc_state *crtc_state,
3598                                   const struct drm_connector_state *conn_state)
3599 {
3600         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3601                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
3602
3603         if (conn_state->content_protection ==
3604             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3605                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3606         else if (conn_state->content_protection ==
3607                  DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
3608                 intel_hdcp_disable(to_intel_connector(conn_state->connector));
3609 }
3610
3611 static void
3612 intel_ddi_update_prepare(struct intel_atomic_state *state,
3613                          struct intel_encoder *encoder,
3614                          struct intel_crtc *crtc)
3615 {
3616         struct intel_crtc_state *crtc_state =
3617                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3618         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3619
3620         WARN_ON(crtc && crtc->active);
3621
3622         intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
3623         if (crtc_state && crtc_state->base.active)
3624                 intel_update_active_dpll(state, crtc, encoder);
3625 }
3626
3627 static void
3628 intel_ddi_update_complete(struct intel_atomic_state *state,
3629                           struct intel_encoder *encoder,
3630                           struct intel_crtc *crtc)
3631 {
3632         intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
3633 }
3634
3635 static void
3636 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3637                          const struct intel_crtc_state *crtc_state,
3638                          const struct drm_connector_state *conn_state)
3639 {
3640         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3641         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3642         bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
3643
3644         if (is_tc_port)
3645                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3646
3647         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3648                 intel_display_power_get(dev_priv,
3649                                         intel_ddi_main_link_aux_domain(dig_port));
3650
3651         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3652                 /*
3653                  * Program the lane count for static/dynamic connections on
3654                  * Type-C ports.  Skip this step for TBT.
3655                  */
3656                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3657         else if (IS_GEN9_LP(dev_priv))
3658                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3659                                                 crtc_state->lane_lat_optim_mask);
3660 }
3661
3662 static void
3663 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3664                            const struct intel_crtc_state *crtc_state,
3665                            const struct drm_connector_state *conn_state)
3666 {
3667         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3668         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3669         bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
3670
3671         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
3672                 intel_display_power_put_unchecked(dev_priv,
3673                                                   intel_ddi_main_link_aux_domain(dig_port));
3674
3675         if (is_tc_port)
3676                 intel_tc_port_put_link(dig_port);
3677 }
3678
3679 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3680 {
3681         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3682         struct drm_i915_private *dev_priv =
3683                 to_i915(intel_dig_port->base.base.dev);
3684         enum port port = intel_dig_port->base.port;
3685         u32 val;
3686         bool wait = false;
3687
3688         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3689                 val = I915_READ(DDI_BUF_CTL(port));
3690                 if (val & DDI_BUF_CTL_ENABLE) {
3691                         val &= ~DDI_BUF_CTL_ENABLE;
3692                         I915_WRITE(DDI_BUF_CTL(port), val);
3693                         wait = true;
3694                 }
3695
3696                 val = I915_READ(DP_TP_CTL(port));
3697                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3698                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3699                 I915_WRITE(DP_TP_CTL(port), val);
3700                 POSTING_READ(DP_TP_CTL(port));
3701
3702                 if (wait)
3703                         intel_wait_ddi_buf_idle(dev_priv, port);
3704         }
3705
3706         val = DP_TP_CTL_ENABLE |
3707               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3708         if (intel_dp->link_mst)
3709                 val |= DP_TP_CTL_MODE_MST;
3710         else {
3711                 val |= DP_TP_CTL_MODE_SST;
3712                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3713                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3714         }
3715         I915_WRITE(DP_TP_CTL(port), val);
3716         POSTING_READ(DP_TP_CTL(port));
3717
3718         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3719         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3720         POSTING_READ(DDI_BUF_CTL(port));
3721
3722         udelay(600);
3723 }
3724
3725 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3726                                        enum transcoder cpu_transcoder)
3727 {
3728         if (cpu_transcoder == TRANSCODER_EDP)
3729                 return false;
3730
3731         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3732                 return false;
3733
3734         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3735                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3736 }
3737
3738 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3739                                          struct intel_crtc_state *crtc_state)
3740 {
3741         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3742                 crtc_state->min_voltage_level = 1;
3743         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3744                 crtc_state->min_voltage_level = 2;
3745 }
3746
3747 void intel_ddi_get_config(struct intel_encoder *encoder,
3748                           struct intel_crtc_state *pipe_config)
3749 {
3750         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3751         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3752         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3753         u32 temp, flags = 0;
3754
3755         /* XXX: DSI transcoder paranoia */
3756         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3757                 return;
3758
3759         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3760         if (temp & TRANS_DDI_PHSYNC)
3761                 flags |= DRM_MODE_FLAG_PHSYNC;
3762         else
3763                 flags |= DRM_MODE_FLAG_NHSYNC;
3764         if (temp & TRANS_DDI_PVSYNC)
3765                 flags |= DRM_MODE_FLAG_PVSYNC;
3766         else
3767                 flags |= DRM_MODE_FLAG_NVSYNC;
3768
3769         pipe_config->base.adjusted_mode.flags |= flags;
3770
3771         switch (temp & TRANS_DDI_BPC_MASK) {
3772         case TRANS_DDI_BPC_6:
3773                 pipe_config->pipe_bpp = 18;
3774                 break;
3775         case TRANS_DDI_BPC_8:
3776                 pipe_config->pipe_bpp = 24;
3777                 break;
3778         case TRANS_DDI_BPC_10:
3779                 pipe_config->pipe_bpp = 30;
3780                 break;
3781         case TRANS_DDI_BPC_12:
3782                 pipe_config->pipe_bpp = 36;
3783                 break;
3784         default:
3785                 break;
3786         }
3787
3788         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3789         case TRANS_DDI_MODE_SELECT_HDMI:
3790                 pipe_config->has_hdmi_sink = true;
3791
3792                 pipe_config->infoframes.enable |=
3793                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3794
3795                 if (pipe_config->infoframes.enable)
3796                         pipe_config->has_infoframe = true;
3797
3798                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3799                         pipe_config->hdmi_scrambling = true;
3800                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3801                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3802                 /* fall through */
3803         case TRANS_DDI_MODE_SELECT_DVI:
3804                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3805                 pipe_config->lane_count = 4;
3806                 break;
3807         case TRANS_DDI_MODE_SELECT_FDI:
3808                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3809                 break;
3810         case TRANS_DDI_MODE_SELECT_DP_SST:
3811                 if (encoder->type == INTEL_OUTPUT_EDP)
3812                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3813                 else
3814                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3815                 pipe_config->lane_count =
3816                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3817                 intel_dp_get_m_n(intel_crtc, pipe_config);
3818                 break;
3819         case TRANS_DDI_MODE_SELECT_DP_MST:
3820                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3821                 pipe_config->lane_count =
3822                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3823                 intel_dp_get_m_n(intel_crtc, pipe_config);
3824                 break;
3825         default:
3826                 break;
3827         }
3828
3829         pipe_config->has_audio =
3830                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3831
3832         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3833             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3834                 /*
3835                  * This is a big fat ugly hack.
3836                  *
3837                  * Some machines in UEFI boot mode provide us a VBT that has 18
3838                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3839                  * unknown we fail to light up. Yet the same BIOS boots up with
3840                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3841                  * max, not what it tells us to use.
3842                  *
3843                  * Note: This will still be broken if the eDP panel is not lit
3844                  * up by the BIOS, and thus we can't get the mode at module
3845                  * load.
3846                  */
3847                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3848                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3849                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3850         }
3851
3852         intel_ddi_clock_get(encoder, pipe_config);
3853
3854         if (IS_GEN9_LP(dev_priv))
3855                 pipe_config->lane_lat_optim_mask =
3856                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3857
3858         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3859
3860         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3861
3862         intel_read_infoframe(encoder, pipe_config,
3863                              HDMI_INFOFRAME_TYPE_AVI,
3864                              &pipe_config->infoframes.avi);
3865         intel_read_infoframe(encoder, pipe_config,
3866                              HDMI_INFOFRAME_TYPE_SPD,
3867                              &pipe_config->infoframes.spd);
3868         intel_read_infoframe(encoder, pipe_config,
3869                              HDMI_INFOFRAME_TYPE_VENDOR,
3870                              &pipe_config->infoframes.hdmi);
3871         intel_read_infoframe(encoder, pipe_config,
3872                              HDMI_INFOFRAME_TYPE_DRM,
3873                              &pipe_config->infoframes.drm);
3874 }
3875
3876 static enum intel_output_type
3877 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3878                               struct intel_crtc_state *crtc_state,
3879                               struct drm_connector_state *conn_state)
3880 {
3881         switch (conn_state->connector->connector_type) {
3882         case DRM_MODE_CONNECTOR_HDMIA:
3883                 return INTEL_OUTPUT_HDMI;
3884         case DRM_MODE_CONNECTOR_eDP:
3885                 return INTEL_OUTPUT_EDP;
3886         case DRM_MODE_CONNECTOR_DisplayPort:
3887                 return INTEL_OUTPUT_DP;
3888         default:
3889                 MISSING_CASE(conn_state->connector->connector_type);
3890                 return INTEL_OUTPUT_UNUSED;
3891         }
3892 }
3893
3894 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3895                                     struct intel_crtc_state *pipe_config,
3896                                     struct drm_connector_state *conn_state)
3897 {
3898         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3899         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3900         enum port port = encoder->port;
3901         int ret;
3902
3903         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
3904                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3905
3906         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3907                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3908         else
3909                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3910         if (ret)
3911                 return ret;
3912
3913         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3914             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3915                 pipe_config->pch_pfit.force_thru =
3916                         pipe_config->pch_pfit.enabled ||
3917                         pipe_config->crc_enabled;
3918
3919         if (IS_GEN9_LP(dev_priv))
3920                 pipe_config->lane_lat_optim_mask =
3921                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3922
3923         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3924
3925         return 0;
3926 }
3927
3928 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3929 {
3930         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3931
3932         intel_dp_encoder_flush_work(encoder);
3933
3934         drm_encoder_cleanup(encoder);
3935         kfree(dig_port);
3936 }
3937
3938 static const struct drm_encoder_funcs intel_ddi_funcs = {
3939         .reset = intel_dp_encoder_reset,
3940         .destroy = intel_ddi_encoder_destroy,
3941 };
3942
3943 static struct intel_connector *
3944 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3945 {
3946         struct intel_connector *connector;
3947         enum port port = intel_dig_port->base.port;
3948
3949         connector = intel_connector_alloc();
3950         if (!connector)
3951                 return NULL;
3952
3953         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3954         intel_dig_port->dp.prepare_link_retrain =
3955                 intel_ddi_prepare_link_retrain;
3956
3957         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3958                 kfree(connector);
3959                 return NULL;
3960         }
3961
3962         return connector;
3963 }
3964
3965 static int modeset_pipe(struct drm_crtc *crtc,
3966                         struct drm_modeset_acquire_ctx *ctx)
3967 {
3968         struct drm_atomic_state *state;
3969         struct drm_crtc_state *crtc_state;
3970         int ret;
3971
3972         state = drm_atomic_state_alloc(crtc->dev);
3973         if (!state)
3974                 return -ENOMEM;
3975
3976         state->acquire_ctx = ctx;
3977
3978         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3979         if (IS_ERR(crtc_state)) {
3980                 ret = PTR_ERR(crtc_state);
3981                 goto out;
3982         }
3983
3984         crtc_state->connectors_changed = true;
3985
3986         ret = drm_atomic_commit(state);
3987 out:
3988         drm_atomic_state_put(state);
3989
3990         return ret;
3991 }
3992
3993 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3994                                  struct drm_modeset_acquire_ctx *ctx)
3995 {
3996         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3997         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3998         struct intel_connector *connector = hdmi->attached_connector;
3999         struct i2c_adapter *adapter =
4000                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4001         struct drm_connector_state *conn_state;
4002         struct intel_crtc_state *crtc_state;
4003         struct intel_crtc *crtc;
4004         u8 config;
4005         int ret;
4006
4007         if (!connector || connector->base.status != connector_status_connected)
4008                 return 0;
4009
4010         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4011                                ctx);
4012         if (ret)
4013                 return ret;
4014
4015         conn_state = connector->base.state;
4016
4017         crtc = to_intel_crtc(conn_state->crtc);
4018         if (!crtc)
4019                 return 0;
4020
4021         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4022         if (ret)
4023                 return ret;
4024
4025         crtc_state = to_intel_crtc_state(crtc->base.state);
4026
4027         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4028
4029         if (!crtc_state->base.active)
4030                 return 0;
4031
4032         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4033             !crtc_state->hdmi_scrambling)
4034                 return 0;
4035
4036         if (conn_state->commit &&
4037             !try_wait_for_completion(&conn_state->commit->hw_done))
4038                 return 0;
4039
4040         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4041         if (ret < 0) {
4042                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4043                 return 0;
4044         }
4045
4046         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4047             crtc_state->hdmi_high_tmds_clock_ratio &&
4048             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4049             crtc_state->hdmi_scrambling)
4050                 return 0;
4051
4052         /*
4053          * HDMI 2.0 says that one should not send scrambled data
4054          * prior to configuring the sink scrambling, and that
4055          * TMDS clock/data transmission should be suspended when
4056          * changing the TMDS clock rate in the sink. So let's
4057          * just do a full modeset here, even though some sinks
4058          * would be perfectly happy if were to just reconfigure
4059          * the SCDC settings on the fly.
4060          */
4061         return modeset_pipe(&crtc->base, ctx);
4062 }
4063
4064 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4065                               struct intel_connector *connector)
4066 {
4067         struct drm_modeset_acquire_ctx ctx;
4068         bool changed;
4069         int ret;
4070
4071         changed = intel_encoder_hotplug(encoder, connector);
4072
4073         drm_modeset_acquire_init(&ctx, 0);
4074
4075         for (;;) {
4076                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4077                         ret = intel_hdmi_reset_link(encoder, &ctx);
4078                 else
4079                         ret = intel_dp_retrain_link(encoder, &ctx);
4080
4081                 if (ret == -EDEADLK) {
4082                         drm_modeset_backoff(&ctx);
4083                         continue;
4084                 }
4085
4086                 break;
4087         }
4088
4089         drm_modeset_drop_locks(&ctx);
4090         drm_modeset_acquire_fini(&ctx);
4091         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4092
4093         return changed;
4094 }
4095
4096 static struct intel_connector *
4097 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4098 {
4099         struct intel_connector *connector;
4100         enum port port = intel_dig_port->base.port;
4101
4102         connector = intel_connector_alloc();
4103         if (!connector)
4104                 return NULL;
4105
4106         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4107         intel_hdmi_init_connector(intel_dig_port, connector);
4108
4109         return connector;
4110 }
4111
4112 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4113 {
4114         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4115
4116         if (dport->base.port != PORT_A)
4117                 return false;
4118
4119         if (dport->saved_port_bits & DDI_A_4_LANES)
4120                 return false;
4121
4122         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4123          *                     supported configuration
4124          */
4125         if (IS_GEN9_LP(dev_priv))
4126                 return true;
4127
4128         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4129          *             one who does also have a full A/E split called
4130          *             DDI_F what makes DDI_E useless. However for this
4131          *             case let's trust VBT info.
4132          */
4133         if (IS_CANNONLAKE(dev_priv) &&
4134             !intel_bios_is_port_present(dev_priv, PORT_E))
4135                 return true;
4136
4137         return false;
4138 }
4139
4140 static int
4141 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4142 {
4143         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4144         enum port port = intel_dport->base.port;
4145         int max_lanes = 4;
4146
4147         if (INTEL_GEN(dev_priv) >= 11)
4148                 return max_lanes;
4149
4150         if (port == PORT_A || port == PORT_E) {
4151                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4152                         max_lanes = port == PORT_A ? 4 : 0;
4153                 else
4154                         /* Both A and E share 2 lanes */
4155                         max_lanes = 2;
4156         }
4157
4158         /*
4159          * Some BIOS might fail to set this bit on port A if eDP
4160          * wasn't lit up at boot.  Force this bit set when needed
4161          * so we use the proper lane count for our calculations.
4162          */
4163         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4164                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4165                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4166                 max_lanes = 4;
4167         }
4168
4169         return max_lanes;
4170 }
4171
4172 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4173 {
4174         struct ddi_vbt_port_info *port_info =
4175                 &dev_priv->vbt.ddi_port_info[port];
4176         struct intel_digital_port *intel_dig_port;
4177         struct intel_encoder *intel_encoder;
4178         struct drm_encoder *encoder;
4179         bool init_hdmi, init_dp, init_lspcon = false;
4180         enum pipe pipe;
4181
4182         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4183         init_dp = port_info->supports_dp;
4184
4185         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4186                 /*
4187                  * Lspcon device needs to be driven with DP connector
4188                  * with special detection sequence. So make sure DP
4189                  * is initialized before lspcon.
4190                  */
4191                 init_dp = true;
4192                 init_lspcon = true;
4193                 init_hdmi = false;
4194                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4195         }
4196
4197         if (!init_dp && !init_hdmi) {
4198                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4199                               port_name(port));
4200                 return;
4201         }
4202
4203         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4204         if (!intel_dig_port)
4205                 return;
4206
4207         intel_encoder = &intel_dig_port->base;
4208         encoder = &intel_encoder->base;
4209
4210         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4211                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4212
4213         intel_encoder->hotplug = intel_ddi_hotplug;
4214         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4215         intel_encoder->compute_config = intel_ddi_compute_config;
4216         intel_encoder->enable = intel_enable_ddi;
4217         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4218         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4219         intel_encoder->pre_enable = intel_ddi_pre_enable;
4220         intel_encoder->disable = intel_disable_ddi;
4221         intel_encoder->post_disable = intel_ddi_post_disable;
4222         intel_encoder->update_pipe = intel_ddi_update_pipe;
4223         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4224         intel_encoder->get_config = intel_ddi_get_config;
4225         intel_encoder->suspend = intel_dp_encoder_suspend;
4226         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4227         intel_encoder->type = INTEL_OUTPUT_DDI;
4228         intel_encoder->power_domain = intel_port_to_power_domain(port);
4229         intel_encoder->port = port;
4230         intel_encoder->cloneable = 0;
4231         for_each_pipe(dev_priv, pipe)
4232                 intel_encoder->crtc_mask |= BIT(pipe);
4233
4234         if (INTEL_GEN(dev_priv) >= 11)
4235                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4236                         DDI_BUF_PORT_REVERSAL;
4237         else
4238                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4239                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4240         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4241         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4242         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4243
4244         if (intel_port_is_tc(dev_priv, port)) {
4245                 bool is_legacy = !port_info->supports_typec_usb &&
4246                                  !port_info->supports_tbt;
4247
4248                 intel_tc_port_init(intel_dig_port, is_legacy);
4249
4250                 intel_encoder->update_prepare = intel_ddi_update_prepare;
4251                 intel_encoder->update_complete = intel_ddi_update_complete;
4252         }
4253
4254         switch (port) {
4255         case PORT_A:
4256                 intel_dig_port->ddi_io_power_domain =
4257                         POWER_DOMAIN_PORT_DDI_A_IO;
4258                 break;
4259         case PORT_B:
4260                 intel_dig_port->ddi_io_power_domain =
4261                         POWER_DOMAIN_PORT_DDI_B_IO;
4262                 break;
4263         case PORT_C:
4264                 intel_dig_port->ddi_io_power_domain =
4265                         POWER_DOMAIN_PORT_DDI_C_IO;
4266                 break;
4267         case PORT_D:
4268                 intel_dig_port->ddi_io_power_domain =
4269                         POWER_DOMAIN_PORT_DDI_D_IO;
4270                 break;
4271         case PORT_E:
4272                 intel_dig_port->ddi_io_power_domain =
4273                         POWER_DOMAIN_PORT_DDI_E_IO;
4274                 break;
4275         case PORT_F:
4276                 intel_dig_port->ddi_io_power_domain =
4277                         POWER_DOMAIN_PORT_DDI_F_IO;
4278                 break;
4279         default:
4280                 MISSING_CASE(port);
4281         }
4282
4283         if (init_dp) {
4284                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4285                         goto err;
4286
4287                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4288         }
4289
4290         /* In theory we don't need the encoder->type check, but leave it just in
4291          * case we have some really bad VBTs... */
4292         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4293                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4294                         goto err;
4295         }
4296
4297         if (init_lspcon) {
4298                 if (lspcon_init(intel_dig_port))
4299                         /* TODO: handle hdmi info frame part */
4300                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4301                                 port_name(port));
4302                 else
4303                         /*
4304                          * LSPCON init faied, but DP init was success, so
4305                          * lets try to drive as DP++ port.
4306                          */
4307                         DRM_ERROR("LSPCON init failed on port %c\n",
4308                                 port_name(port));
4309         }
4310
4311         intel_infoframe_init(intel_dig_port);
4312
4313         return;
4314
4315 err:
4316         drm_encoder_cleanup(encoder);
4317         kfree(intel_dig_port);
4318 }