2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
45 #include <drm/i915_drm.h>
47 #include "display/intel_crt.h"
48 #include "display/intel_ddi.h"
49 #include "display/intel_dp.h"
50 #include "display/intel_dsi.h"
51 #include "display/intel_dvo.h"
52 #include "display/intel_gmbus.h"
53 #include "display/intel_hdmi.h"
54 #include "display/intel_lvds.h"
55 #include "display/intel_sdvo.h"
56 #include "display/intel_tv.h"
57 #include "display/intel_vdsc.h"
60 #include "i915_trace.h"
61 #include "intel_acpi.h"
62 #include "intel_atomic.h"
63 #include "intel_atomic_plane.h"
65 #include "intel_cdclk.h"
66 #include "intel_color.h"
67 #include "intel_display_types.h"
68 #include "intel_fbc.h"
69 #include "intel_fbdev.h"
70 #include "intel_fifo_underrun.h"
71 #include "intel_frontbuffer.h"
72 #include "intel_hdcp.h"
73 #include "intel_hotplug.h"
74 #include "intel_overlay.h"
75 #include "intel_pipe_crc.h"
77 #include "intel_psr.h"
78 #include "intel_quirks.h"
79 #include "intel_sideband.h"
80 #include "intel_sprite.h"
83 /* Primary plane formats for gen <= 3 */
84 static const u32 i8xx_primary_formats[] = {
91 /* Primary plane formats for gen >= 4 */
92 static const u32 i965_primary_formats[] = {
97 DRM_FORMAT_XRGB2101010,
98 DRM_FORMAT_XBGR2101010,
101 static const u64 i9xx_format_modifiers[] = {
102 I915_FORMAT_MOD_X_TILED,
103 DRM_FORMAT_MOD_LINEAR,
104 DRM_FORMAT_MOD_INVALID
108 static const u32 intel_cursor_formats[] = {
112 static const u64 cursor_format_modifiers[] = {
113 DRM_FORMAT_MOD_LINEAR,
114 DRM_FORMAT_MOD_INVALID
117 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
118 struct intel_crtc_state *pipe_config);
119 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
120 struct intel_crtc_state *pipe_config);
122 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
123 struct drm_i915_gem_object *obj,
124 struct drm_mode_fb_cmd2 *mode_cmd);
125 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
126 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
127 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
128 const struct intel_link_m_n *m_n,
129 const struct intel_link_m_n *m2_n2);
130 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
131 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state);
132 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state);
133 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
134 static void vlv_prepare_pll(struct intel_crtc *crtc,
135 const struct intel_crtc_state *pipe_config);
136 static void chv_prepare_pll(struct intel_crtc *crtc,
137 const struct intel_crtc_state *pipe_config);
138 static void intel_begin_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
139 static void intel_finish_crtc_commit(struct intel_atomic_state *, struct intel_crtc *);
140 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
141 struct intel_crtc_state *crtc_state);
142 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
143 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
144 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
145 static void intel_modeset_setup_hw_state(struct drm_device *dev,
146 struct drm_modeset_acquire_ctx *ctx);
147 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
152 } dot, vco, n, m, m1, m2, p, p1;
156 int p2_slow, p2_fast;
160 /* returns HPLL frequency in kHz */
161 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
163 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
165 /* Obtain SKU information */
166 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
167 CCK_FUSE_HPLL_FREQ_MASK;
169 return vco_freq[hpll_freq] * 1000;
172 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
173 const char *name, u32 reg, int ref_freq)
178 val = vlv_cck_read(dev_priv, reg);
179 divider = val & CCK_FREQUENCY_VALUES;
181 WARN((val & CCK_FREQUENCY_STATUS) !=
182 (divider << CCK_FREQUENCY_STATUS_SHIFT),
183 "%s change in progress\n", name);
185 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
188 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
189 const char *name, u32 reg)
193 vlv_cck_get(dev_priv);
195 if (dev_priv->hpll_freq == 0)
196 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
198 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
200 vlv_cck_put(dev_priv);
205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
207 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
210 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
211 CCK_CZ_CLOCK_CONTROL);
213 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
216 static inline u32 /* units of 100MHz */
217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
218 const struct intel_crtc_state *pipe_config)
220 if (HAS_DDI(dev_priv))
221 return pipe_config->port_clock; /* SPLL */
223 return dev_priv->fdi_pll_freq;
226 static const struct intel_limit intel_limits_i8xx_dac = {
227 .dot = { .min = 25000, .max = 350000 },
228 .vco = { .min = 908000, .max = 1512000 },
229 .n = { .min = 2, .max = 16 },
230 .m = { .min = 96, .max = 140 },
231 .m1 = { .min = 18, .max = 26 },
232 .m2 = { .min = 6, .max = 16 },
233 .p = { .min = 4, .max = 128 },
234 .p1 = { .min = 2, .max = 33 },
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 4, .p2_fast = 2 },
239 static const struct intel_limit intel_limits_i8xx_dvo = {
240 .dot = { .min = 25000, .max = 350000 },
241 .vco = { .min = 908000, .max = 1512000 },
242 .n = { .min = 2, .max = 16 },
243 .m = { .min = 96, .max = 140 },
244 .m1 = { .min = 18, .max = 26 },
245 .m2 = { .min = 6, .max = 16 },
246 .p = { .min = 4, .max = 128 },
247 .p1 = { .min = 2, .max = 33 },
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 4, .p2_fast = 4 },
252 static const struct intel_limit intel_limits_i8xx_lvds = {
253 .dot = { .min = 25000, .max = 350000 },
254 .vco = { .min = 908000, .max = 1512000 },
255 .n = { .min = 2, .max = 16 },
256 .m = { .min = 96, .max = 140 },
257 .m1 = { .min = 18, .max = 26 },
258 .m2 = { .min = 6, .max = 16 },
259 .p = { .min = 4, .max = 128 },
260 .p1 = { .min = 1, .max = 6 },
261 .p2 = { .dot_limit = 165000,
262 .p2_slow = 14, .p2_fast = 7 },
265 static const struct intel_limit intel_limits_i9xx_sdvo = {
266 .dot = { .min = 20000, .max = 400000 },
267 .vco = { .min = 1400000, .max = 2800000 },
268 .n = { .min = 1, .max = 6 },
269 .m = { .min = 70, .max = 120 },
270 .m1 = { .min = 8, .max = 18 },
271 .m2 = { .min = 3, .max = 7 },
272 .p = { .min = 5, .max = 80 },
273 .p1 = { .min = 1, .max = 8 },
274 .p2 = { .dot_limit = 200000,
275 .p2_slow = 10, .p2_fast = 5 },
278 static const struct intel_limit intel_limits_i9xx_lvds = {
279 .dot = { .min = 20000, .max = 400000 },
280 .vco = { .min = 1400000, .max = 2800000 },
281 .n = { .min = 1, .max = 6 },
282 .m = { .min = 70, .max = 120 },
283 .m1 = { .min = 8, .max = 18 },
284 .m2 = { .min = 3, .max = 7 },
285 .p = { .min = 7, .max = 98 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 112000,
288 .p2_slow = 14, .p2_fast = 7 },
292 static const struct intel_limit intel_limits_g4x_sdvo = {
293 .dot = { .min = 25000, .max = 270000 },
294 .vco = { .min = 1750000, .max = 3500000},
295 .n = { .min = 1, .max = 4 },
296 .m = { .min = 104, .max = 138 },
297 .m1 = { .min = 17, .max = 23 },
298 .m2 = { .min = 5, .max = 11 },
299 .p = { .min = 10, .max = 30 },
300 .p1 = { .min = 1, .max = 3},
301 .p2 = { .dot_limit = 270000,
307 static const struct intel_limit intel_limits_g4x_hdmi = {
308 .dot = { .min = 22000, .max = 400000 },
309 .vco = { .min = 1750000, .max = 3500000},
310 .n = { .min = 1, .max = 4 },
311 .m = { .min = 104, .max = 138 },
312 .m1 = { .min = 16, .max = 23 },
313 .m2 = { .min = 5, .max = 11 },
314 .p = { .min = 5, .max = 80 },
315 .p1 = { .min = 1, .max = 8},
316 .p2 = { .dot_limit = 165000,
317 .p2_slow = 10, .p2_fast = 5 },
320 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
321 .dot = { .min = 20000, .max = 115000 },
322 .vco = { .min = 1750000, .max = 3500000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 0,
330 .p2_slow = 14, .p2_fast = 14
334 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
335 .dot = { .min = 80000, .max = 224000 },
336 .vco = { .min = 1750000, .max = 3500000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 104, .max = 138 },
339 .m1 = { .min = 17, .max = 23 },
340 .m2 = { .min = 5, .max = 11 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 0,
344 .p2_slow = 7, .p2_fast = 7
348 static const struct intel_limit intel_limits_pineview_sdvo = {
349 .dot = { .min = 20000, .max = 400000},
350 .vco = { .min = 1700000, .max = 3500000 },
351 /* Pineview's Ncounter is a ring counter */
352 .n = { .min = 3, .max = 6 },
353 .m = { .min = 2, .max = 256 },
354 /* Pineview only has one combined m divider, which we treat as m2. */
355 .m1 = { .min = 0, .max = 0 },
356 .m2 = { .min = 0, .max = 254 },
357 .p = { .min = 5, .max = 80 },
358 .p1 = { .min = 1, .max = 8 },
359 .p2 = { .dot_limit = 200000,
360 .p2_slow = 10, .p2_fast = 5 },
363 static const struct intel_limit intel_limits_pineview_lvds = {
364 .dot = { .min = 20000, .max = 400000 },
365 .vco = { .min = 1700000, .max = 3500000 },
366 .n = { .min = 3, .max = 6 },
367 .m = { .min = 2, .max = 256 },
368 .m1 = { .min = 0, .max = 0 },
369 .m2 = { .min = 0, .max = 254 },
370 .p = { .min = 7, .max = 112 },
371 .p1 = { .min = 1, .max = 8 },
372 .p2 = { .dot_limit = 112000,
373 .p2_slow = 14, .p2_fast = 14 },
376 /* Ironlake / Sandybridge
378 * We calculate clock using (register_value + 2) for N/M1/M2, so here
379 * the range value for them is (actual_value - 2).
381 static const struct intel_limit intel_limits_ironlake_dac = {
382 .dot = { .min = 25000, .max = 350000 },
383 .vco = { .min = 1760000, .max = 3510000 },
384 .n = { .min = 1, .max = 5 },
385 .m = { .min = 79, .max = 127 },
386 .m1 = { .min = 12, .max = 22 },
387 .m2 = { .min = 5, .max = 9 },
388 .p = { .min = 5, .max = 80 },
389 .p1 = { .min = 1, .max = 8 },
390 .p2 = { .dot_limit = 225000,
391 .p2_slow = 10, .p2_fast = 5 },
394 static const struct intel_limit intel_limits_ironlake_single_lvds = {
395 .dot = { .min = 25000, .max = 350000 },
396 .vco = { .min = 1760000, .max = 3510000 },
397 .n = { .min = 1, .max = 3 },
398 .m = { .min = 79, .max = 118 },
399 .m1 = { .min = 12, .max = 22 },
400 .m2 = { .min = 5, .max = 9 },
401 .p = { .min = 28, .max = 112 },
402 .p1 = { .min = 2, .max = 8 },
403 .p2 = { .dot_limit = 225000,
404 .p2_slow = 14, .p2_fast = 14 },
407 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
408 .dot = { .min = 25000, .max = 350000 },
409 .vco = { .min = 1760000, .max = 3510000 },
410 .n = { .min = 1, .max = 3 },
411 .m = { .min = 79, .max = 127 },
412 .m1 = { .min = 12, .max = 22 },
413 .m2 = { .min = 5, .max = 9 },
414 .p = { .min = 14, .max = 56 },
415 .p1 = { .min = 2, .max = 8 },
416 .p2 = { .dot_limit = 225000,
417 .p2_slow = 7, .p2_fast = 7 },
420 /* LVDS 100mhz refclk limits. */
421 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
422 .dot = { .min = 25000, .max = 350000 },
423 .vco = { .min = 1760000, .max = 3510000 },
424 .n = { .min = 1, .max = 2 },
425 .m = { .min = 79, .max = 126 },
426 .m1 = { .min = 12, .max = 22 },
427 .m2 = { .min = 5, .max = 9 },
428 .p = { .min = 28, .max = 112 },
429 .p1 = { .min = 2, .max = 8 },
430 .p2 = { .dot_limit = 225000,
431 .p2_slow = 14, .p2_fast = 14 },
434 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
435 .dot = { .min = 25000, .max = 350000 },
436 .vco = { .min = 1760000, .max = 3510000 },
437 .n = { .min = 1, .max = 3 },
438 .m = { .min = 79, .max = 126 },
439 .m1 = { .min = 12, .max = 22 },
440 .m2 = { .min = 5, .max = 9 },
441 .p = { .min = 14, .max = 42 },
442 .p1 = { .min = 2, .max = 6 },
443 .p2 = { .dot_limit = 225000,
444 .p2_slow = 7, .p2_fast = 7 },
447 static const struct intel_limit intel_limits_vlv = {
449 * These are the data rate limits (measured in fast clocks)
450 * since those are the strictest limits we have. The fast
451 * clock and actual rate limits are more relaxed, so checking
452 * them would make no difference.
454 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
455 .vco = { .min = 4000000, .max = 6000000 },
456 .n = { .min = 1, .max = 7 },
457 .m1 = { .min = 2, .max = 3 },
458 .m2 = { .min = 11, .max = 156 },
459 .p1 = { .min = 2, .max = 3 },
460 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
463 static const struct intel_limit intel_limits_chv = {
465 * These are the data rate limits (measured in fast clocks)
466 * since those are the strictest limits we have. The fast
467 * clock and actual rate limits are more relaxed, so checking
468 * them would make no difference.
470 .dot = { .min = 25000 * 5, .max = 540000 * 5},
471 .vco = { .min = 4800000, .max = 6480000 },
472 .n = { .min = 1, .max = 1 },
473 .m1 = { .min = 2, .max = 2 },
474 .m2 = { .min = 24 << 22, .max = 175 << 22 },
475 .p1 = { .min = 2, .max = 4 },
476 .p2 = { .p2_slow = 1, .p2_fast = 14 },
479 static const struct intel_limit intel_limits_bxt = {
480 /* FIXME: find real dot limits */
481 .dot = { .min = 0, .max = INT_MAX },
482 .vco = { .min = 4800000, .max = 6700000 },
483 .n = { .min = 1, .max = 1 },
484 .m1 = { .min = 2, .max = 2 },
485 /* FIXME: find real m2 limits */
486 .m2 = { .min = 2 << 22, .max = 255 << 22 },
487 .p1 = { .min = 2, .max = 4 },
488 .p2 = { .p2_slow = 1, .p2_fast = 20 },
491 /* WA Display #0827: Gen9:all */
493 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
496 I915_WRITE(CLKGATE_DIS_PSL(pipe),
497 I915_READ(CLKGATE_DIS_PSL(pipe)) |
498 DUPS1_GATING_DIS | DUPS2_GATING_DIS);
500 I915_WRITE(CLKGATE_DIS_PSL(pipe),
501 I915_READ(CLKGATE_DIS_PSL(pipe)) &
502 ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
505 /* Wa_2006604312:icl */
507 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
511 I915_WRITE(CLKGATE_DIS_PSL(pipe),
512 I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
514 I915_WRITE(CLKGATE_DIS_PSL(pipe),
515 I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
519 needs_modeset(const struct intel_crtc_state *state)
521 return drm_atomic_crtc_needs_modeset(&state->base);
525 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
526 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
527 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
528 * The helpers' return value is the rate of the clock that is fed to the
529 * display engine's pipe which can be the above fast dot clock rate or a
530 * divided-down version of it.
532 /* m1 is reserved as 0 in Pineview, n is a ring counter */
533 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
535 clock->m = clock->m2 + 2;
536 clock->p = clock->p1 * clock->p2;
537 if (WARN_ON(clock->n == 0 || clock->p == 0))
539 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
540 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
545 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
547 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
550 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
552 clock->m = i9xx_dpll_compute_m(clock);
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
556 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
562 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
564 clock->m = clock->m1 * clock->m2;
565 clock->p = clock->p1 * clock->p2;
566 if (WARN_ON(clock->n == 0 || clock->p == 0))
568 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
569 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
571 return clock->dot / 5;
574 int chv_calc_dpll_params(int refclk, struct dpll *clock)
576 clock->m = clock->m1 * clock->m2;
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n == 0 || clock->p == 0))
580 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
584 return clock->dot / 5;
587 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
590 * Returns whether the given set of divisors are valid for a given refclk with
591 * the given connectors.
593 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
594 const struct intel_limit *limit,
595 const struct dpll *clock)
597 if (clock->n < limit->n.min || limit->n.max < clock->n)
598 INTELPllInvalid("n out of range\n");
599 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
600 INTELPllInvalid("p1 out of range\n");
601 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
602 INTELPllInvalid("m2 out of range\n");
603 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
604 INTELPllInvalid("m1 out of range\n");
606 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
607 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
608 if (clock->m1 <= clock->m2)
609 INTELPllInvalid("m1 <= m2\n");
611 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
612 !IS_GEN9_LP(dev_priv)) {
613 if (clock->p < limit->p.min || limit->p.max < clock->p)
614 INTELPllInvalid("p out of range\n");
615 if (clock->m < limit->m.min || limit->m.max < clock->m)
616 INTELPllInvalid("m out of range\n");
619 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
620 INTELPllInvalid("vco out of range\n");
621 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
622 * connector, etc., rather than just a single range.
624 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
625 INTELPllInvalid("dot out of range\n");
631 i9xx_select_p2_div(const struct intel_limit *limit,
632 const struct intel_crtc_state *crtc_state,
635 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
637 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
639 * For LVDS just rely on its current settings for dual-channel.
640 * We haven't figured out how to reliably set up different
641 * single/dual channel state, if we even can.
643 if (intel_is_dual_link_lvds(dev_priv))
644 return limit->p2.p2_fast;
646 return limit->p2.p2_slow;
648 if (target < limit->p2.dot_limit)
649 return limit->p2.p2_slow;
651 return limit->p2.p2_fast;
656 * Returns a set of divisors for the desired target clock with the given
657 * refclk, or FALSE. The returned values represent the clock equation:
658 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
660 * Target and reference clocks are specified in kHz.
662 * If match_clock is provided, then best_clock P divider must match the P
663 * divider from @match_clock used for LVDS downclocking.
666 i9xx_find_best_dpll(const struct intel_limit *limit,
667 struct intel_crtc_state *crtc_state,
668 int target, int refclk, struct dpll *match_clock,
669 struct dpll *best_clock)
671 struct drm_device *dev = crtc_state->base.crtc->dev;
675 memset(best_clock, 0, sizeof(*best_clock));
677 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
679 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
681 for (clock.m2 = limit->m2.min;
682 clock.m2 <= limit->m2.max; clock.m2++) {
683 if (clock.m2 >= clock.m1)
685 for (clock.n = limit->n.min;
686 clock.n <= limit->n.max; clock.n++) {
687 for (clock.p1 = limit->p1.min;
688 clock.p1 <= limit->p1.max; clock.p1++) {
691 i9xx_calc_dpll_params(refclk, &clock);
692 if (!intel_PLL_is_valid(to_i915(dev),
697 clock.p != match_clock->p)
700 this_err = abs(clock.dot - target);
701 if (this_err < err) {
710 return (err != target);
714 * Returns a set of divisors for the desired target clock with the given
715 * refclk, or FALSE. The returned values represent the clock equation:
716 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
718 * Target and reference clocks are specified in kHz.
720 * If match_clock is provided, then best_clock P divider must match the P
721 * divider from @match_clock used for LVDS downclocking.
724 pnv_find_best_dpll(const struct intel_limit *limit,
725 struct intel_crtc_state *crtc_state,
726 int target, int refclk, struct dpll *match_clock,
727 struct dpll *best_clock)
729 struct drm_device *dev = crtc_state->base.crtc->dev;
733 memset(best_clock, 0, sizeof(*best_clock));
735 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 for (clock.m2 = limit->m2.min;
740 clock.m2 <= limit->m2.max; clock.m2++) {
741 for (clock.n = limit->n.min;
742 clock.n <= limit->n.max; clock.n++) {
743 for (clock.p1 = limit->p1.min;
744 clock.p1 <= limit->p1.max; clock.p1++) {
747 pnv_calc_dpll_params(refclk, &clock);
748 if (!intel_PLL_is_valid(to_i915(dev),
753 clock.p != match_clock->p)
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
766 return (err != target);
770 * Returns a set of divisors for the desired target clock with the given
771 * refclk, or FALSE. The returned values represent the clock equation:
772 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
774 * Target and reference clocks are specified in kHz.
776 * If match_clock is provided, then best_clock P divider must match the P
777 * divider from @match_clock used for LVDS downclocking.
780 g4x_find_best_dpll(const struct intel_limit *limit,
781 struct intel_crtc_state *crtc_state,
782 int target, int refclk, struct dpll *match_clock,
783 struct dpll *best_clock)
785 struct drm_device *dev = crtc_state->base.crtc->dev;
789 /* approximately equals target * 0.00585 */
790 int err_most = (target >> 8) + (target >> 9);
792 memset(best_clock, 0, sizeof(*best_clock));
794 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
796 max_n = limit->n.max;
797 /* based on hardware requirement, prefer smaller n to precision */
798 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
799 /* based on hardware requirement, prefere larger m1,m2 */
800 for (clock.m1 = limit->m1.max;
801 clock.m1 >= limit->m1.min; clock.m1--) {
802 for (clock.m2 = limit->m2.max;
803 clock.m2 >= limit->m2.min; clock.m2--) {
804 for (clock.p1 = limit->p1.max;
805 clock.p1 >= limit->p1.min; clock.p1--) {
808 i9xx_calc_dpll_params(refclk, &clock);
809 if (!intel_PLL_is_valid(to_i915(dev),
814 this_err = abs(clock.dot - target);
815 if (this_err < err_most) {
829 * Check if the calculated PLL configuration is more optimal compared to the
830 * best configuration and error found so far. Return the calculated error.
832 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
833 const struct dpll *calculated_clock,
834 const struct dpll *best_clock,
835 unsigned int best_error_ppm,
836 unsigned int *error_ppm)
839 * For CHV ignore the error and consider only the P value.
840 * Prefer a bigger P value based on HW requirements.
842 if (IS_CHERRYVIEW(to_i915(dev))) {
845 return calculated_clock->p > best_clock->p;
848 if (WARN_ON_ONCE(!target_freq))
851 *error_ppm = div_u64(1000000ULL *
852 abs(target_freq - calculated_clock->dot),
855 * Prefer a better P value over a better (smaller) error if the error
856 * is small. Ensure this preference for future configurations too by
857 * setting the error to 0.
859 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
865 return *error_ppm + 10 < best_error_ppm;
869 * Returns a set of divisors for the desired target clock with the given
870 * refclk, or FALSE. The returned values represent the clock equation:
871 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
874 vlv_find_best_dpll(const struct intel_limit *limit,
875 struct intel_crtc_state *crtc_state,
876 int target, int refclk, struct dpll *match_clock,
877 struct dpll *best_clock)
879 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
880 struct drm_device *dev = crtc->base.dev;
882 unsigned int bestppm = 1000000;
883 /* min update 19.2 MHz */
884 int max_n = min(limit->n.max, refclk / 19200);
887 target *= 5; /* fast clock */
889 memset(best_clock, 0, sizeof(*best_clock));
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
893 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
894 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
895 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
896 clock.p = clock.p1 * clock.p2;
897 /* based on hardware requirement, prefer bigger m1,m2 values */
898 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
901 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
904 vlv_calc_dpll_params(refclk, &clock);
906 if (!intel_PLL_is_valid(to_i915(dev),
911 if (!vlv_PLL_is_optimal(dev, target,
929 * Returns a set of divisors for the desired target clock with the given
930 * refclk, or FALSE. The returned values represent the clock equation:
931 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
934 chv_find_best_dpll(const struct intel_limit *limit,
935 struct intel_crtc_state *crtc_state,
936 int target, int refclk, struct dpll *match_clock,
937 struct dpll *best_clock)
939 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
940 struct drm_device *dev = crtc->base.dev;
941 unsigned int best_error_ppm;
946 memset(best_clock, 0, sizeof(*best_clock));
947 best_error_ppm = 1000000;
950 * Based on hardware doc, the n always set to 1, and m1 always
951 * set to 2. If requires to support 200Mhz refclk, we need to
952 * revisit this because n may not 1 anymore.
954 clock.n = 1, clock.m1 = 2;
955 target *= 5; /* fast clock */
957 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
958 for (clock.p2 = limit->p2.p2_fast;
959 clock.p2 >= limit->p2.p2_slow;
960 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
961 unsigned int error_ppm;
963 clock.p = clock.p1 * clock.p2;
965 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
968 if (m2 > INT_MAX/clock.m1)
973 chv_calc_dpll_params(refclk, &clock);
975 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
978 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
979 best_error_ppm, &error_ppm))
983 best_error_ppm = error_ppm;
991 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
992 struct dpll *best_clock)
995 const struct intel_limit *limit = &intel_limits_bxt;
997 return chv_find_best_dpll(limit, crtc_state,
998 crtc_state->port_clock, refclk,
1002 bool intel_crtc_active(struct intel_crtc *crtc)
1004 /* Be paranoid as we can arrive here with only partial
1005 * state retrieved from the hardware during setup.
1007 * We can ditch the adjusted_mode.crtc_clock check as soon
1008 * as Haswell has gained clock readout/fastboot support.
1010 * We can ditch the crtc->primary->state->fb check as soon as we can
1011 * properly reconstruct framebuffers.
1013 * FIXME: The intel_crtc->active here should be switched to
1014 * crtc->state->active once we have proper CRTC states wired up
1017 return crtc->active && crtc->base.primary->state->fb &&
1018 crtc->config->base.adjusted_mode.crtc_clock;
1021 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1024 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1026 return crtc->config->cpu_transcoder;
1029 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1032 i915_reg_t reg = PIPEDSL(pipe);
1036 if (IS_GEN(dev_priv, 2))
1037 line_mask = DSL_LINEMASK_GEN2;
1039 line_mask = DSL_LINEMASK_GEN3;
1041 line1 = I915_READ(reg) & line_mask;
1043 line2 = I915_READ(reg) & line_mask;
1045 return line1 != line2;
1048 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1050 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1051 enum pipe pipe = crtc->pipe;
1053 /* Wait for the display line to settle/start moving */
1054 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1055 DRM_ERROR("pipe %c scanline %s wait timed out\n",
1056 pipe_name(pipe), onoff(state));
1059 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1061 wait_for_pipe_scanline_moving(crtc, false);
1064 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1066 wait_for_pipe_scanline_moving(crtc, true);
1070 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1072 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1073 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1075 if (INTEL_GEN(dev_priv) >= 4) {
1076 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1077 i915_reg_t reg = PIPECONF(cpu_transcoder);
1079 /* Wait for the Pipe State to go off */
1080 if (intel_de_wait_for_clear(dev_priv, reg,
1081 I965_PIPECONF_ACTIVE, 100))
1082 WARN(1, "pipe_off wait timed out\n");
1084 intel_wait_for_pipe_scanline_stopped(crtc);
1088 /* Only for pre-ILK configs */
1089 void assert_pll(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1095 val = I915_READ(DPLL(pipe));
1096 cur_state = !!(val & DPLL_VCO_ENABLE);
1097 I915_STATE_WARN(cur_state != state,
1098 "PLL state assertion failure (expected %s, current %s)\n",
1099 onoff(state), onoff(cur_state));
1102 /* XXX: the dsi pll is shared between MIPI DSI ports */
1103 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1108 vlv_cck_get(dev_priv);
1109 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1110 vlv_cck_put(dev_priv);
1112 cur_state = val & DSI_PLL_VCO_EN;
1113 I915_STATE_WARN(cur_state != state,
1114 "DSI PLL state assertion failure (expected %s, current %s)\n",
1115 onoff(state), onoff(cur_state));
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 if (HAS_DDI(dev_priv)) {
1126 /* DDI does not have a specific FDI_TX register */
1127 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1130 u32 val = I915_READ(FDI_TX_CTL(pipe));
1131 cur_state = !!(val & FDI_TX_ENABLE);
1133 I915_STATE_WARN(cur_state != state,
1134 "FDI TX state assertion failure (expected %s, current %s)\n",
1135 onoff(state), onoff(cur_state));
1137 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1138 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1141 enum pipe pipe, bool state)
1146 val = I915_READ(FDI_RX_CTL(pipe));
1147 cur_state = !!(val & FDI_RX_ENABLE);
1148 I915_STATE_WARN(cur_state != state,
1149 "FDI RX state assertion failure (expected %s, current %s)\n",
1150 onoff(state), onoff(cur_state));
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160 /* ILK FDI PLL is always enabled */
1161 if (IS_GEN(dev_priv, 5))
1164 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1165 if (HAS_DDI(dev_priv))
1168 val = I915_READ(FDI_TX_CTL(pipe));
1169 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1172 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1173 enum pipe pipe, bool state)
1178 val = I915_READ(FDI_RX_CTL(pipe));
1179 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1180 I915_STATE_WARN(cur_state != state,
1181 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1182 onoff(state), onoff(cur_state));
1185 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1189 enum pipe panel_pipe = INVALID_PIPE;
1192 if (WARN_ON(HAS_DDI(dev_priv)))
1195 if (HAS_PCH_SPLIT(dev_priv)) {
1198 pp_reg = PP_CONTROL(0);
1199 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1202 case PANEL_PORT_SELECT_LVDS:
1203 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1205 case PANEL_PORT_SELECT_DPA:
1206 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1208 case PANEL_PORT_SELECT_DPC:
1209 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1211 case PANEL_PORT_SELECT_DPD:
1212 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1215 MISSING_CASE(port_sel);
1218 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1219 /* presumably write lock depends on pipe, not port select */
1220 pp_reg = PP_CONTROL(pipe);
1225 pp_reg = PP_CONTROL(0);
1226 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1228 WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS);
1229 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1232 val = I915_READ(pp_reg);
1233 if (!(val & PANEL_POWER_ON) ||
1234 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1237 I915_STATE_WARN(panel_pipe == pipe && locked,
1238 "panel assertion failure, pipe %c regs locked\n",
1242 void assert_pipe(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1248 enum intel_display_power_domain power_domain;
1249 intel_wakeref_t wakeref;
1251 /* we keep both pipes enabled on 830 */
1252 if (IS_I830(dev_priv))
1255 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1256 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1258 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1259 cur_state = !!(val & PIPECONF_ENABLE);
1261 intel_display_power_put(dev_priv, power_domain, wakeref);
1266 I915_STATE_WARN(cur_state != state,
1267 "pipe %c assertion failure (expected %s, current %s)\n",
1268 pipe_name(pipe), onoff(state), onoff(cur_state));
1271 static void assert_plane(struct intel_plane *plane, bool state)
1276 cur_state = plane->get_hw_state(plane, &pipe);
1278 I915_STATE_WARN(cur_state != state,
1279 "%s assertion failure (expected %s, current %s)\n",
1280 plane->base.name, onoff(state), onoff(cur_state));
1283 #define assert_plane_enabled(p) assert_plane(p, true)
1284 #define assert_plane_disabled(p) assert_plane(p, false)
1286 static void assert_planes_disabled(struct intel_crtc *crtc)
1288 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1289 struct intel_plane *plane;
1291 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1292 assert_plane_disabled(plane);
1295 static void assert_vblank_disabled(struct drm_crtc *crtc)
1297 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1298 drm_crtc_vblank_put(crtc);
1301 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1307 val = I915_READ(PCH_TRANSCONF(pipe));
1308 enabled = !!(val & TRANS_ENABLE);
1309 I915_STATE_WARN(enabled,
1310 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1314 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, enum port port,
1318 enum pipe port_pipe;
1321 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1323 I915_STATE_WARN(state && port_pipe == pipe,
1324 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1325 port_name(port), pipe_name(pipe));
1327 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1328 "IBX PCH DP %c still using transcoder B\n",
1332 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1333 enum pipe pipe, enum port port,
1334 i915_reg_t hdmi_reg)
1336 enum pipe port_pipe;
1339 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1341 I915_STATE_WARN(state && port_pipe == pipe,
1342 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1343 port_name(port), pipe_name(pipe));
1345 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1346 "IBX PCH HDMI %c still using transcoder B\n",
1350 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1353 enum pipe port_pipe;
1355 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1356 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1357 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1359 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1361 "PCH VGA enabled on transcoder %c, should be disabled\n",
1364 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1366 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1369 /* PCH SDVOB multiplex with HDMIB */
1370 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1371 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1372 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1375 static void _vlv_enable_pll(struct intel_crtc *crtc,
1376 const struct intel_crtc_state *pipe_config)
1378 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1379 enum pipe pipe = crtc->pipe;
1381 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1382 POSTING_READ(DPLL(pipe));
1385 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1386 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1389 static void vlv_enable_pll(struct intel_crtc *crtc,
1390 const struct intel_crtc_state *pipe_config)
1392 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1393 enum pipe pipe = crtc->pipe;
1395 assert_pipe_disabled(dev_priv, pipe);
1397 /* PLL is protected by panel, make sure we can write it */
1398 assert_panel_unlocked(dev_priv, pipe);
1400 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1401 _vlv_enable_pll(crtc, pipe_config);
1403 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1404 POSTING_READ(DPLL_MD(pipe));
1408 static void _chv_enable_pll(struct intel_crtc *crtc,
1409 const struct intel_crtc_state *pipe_config)
1411 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1412 enum pipe pipe = crtc->pipe;
1413 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1416 vlv_dpio_get(dev_priv);
1418 /* Enable back the 10bit clock to display controller */
1419 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1420 tmp |= DPIO_DCLKP_EN;
1421 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1423 vlv_dpio_put(dev_priv);
1426 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1431 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1433 /* Check PLL is locked */
1434 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1435 DRM_ERROR("PLL %d failed to lock\n", pipe);
1438 static void chv_enable_pll(struct intel_crtc *crtc,
1439 const struct intel_crtc_state *pipe_config)
1441 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1442 enum pipe pipe = crtc->pipe;
1444 assert_pipe_disabled(dev_priv, pipe);
1446 /* PLL is protected by panel, make sure we can write it */
1447 assert_panel_unlocked(dev_priv, pipe);
1449 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1450 _chv_enable_pll(crtc, pipe_config);
1452 if (pipe != PIPE_A) {
1454 * WaPixelRepeatModeFixForC0:chv
1456 * DPLLCMD is AWOL. Use chicken bits to propagate
1457 * the value from DPLLBMD to either pipe B or C.
1459 I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1460 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1461 I915_WRITE(CBR4_VLV, 0);
1462 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1465 * DPLLB VGA mode also seems to cause problems.
1466 * We should always have it disabled.
1468 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1470 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1471 POSTING_READ(DPLL_MD(pipe));
1475 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1477 if (IS_I830(dev_priv))
1480 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1483 static void i9xx_enable_pll(struct intel_crtc *crtc,
1484 const struct intel_crtc_state *crtc_state)
1486 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1487 i915_reg_t reg = DPLL(crtc->pipe);
1488 u32 dpll = crtc_state->dpll_hw_state.dpll;
1491 assert_pipe_disabled(dev_priv, crtc->pipe);
1493 /* PLL is protected by panel, make sure we can write it */
1494 if (i9xx_has_pps(dev_priv))
1495 assert_panel_unlocked(dev_priv, crtc->pipe);
1498 * Apparently we need to have VGA mode enabled prior to changing
1499 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1500 * dividers, even though the register value does change.
1502 I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
1503 I915_WRITE(reg, dpll);
1505 /* Wait for the clocks to stabilize. */
1509 if (INTEL_GEN(dev_priv) >= 4) {
1510 I915_WRITE(DPLL_MD(crtc->pipe),
1511 crtc_state->dpll_hw_state.dpll_md);
1513 /* The pixel multiplier can only be updated once the
1514 * DPLL is enabled and the clocks are stable.
1516 * So write it again.
1518 I915_WRITE(reg, dpll);
1521 /* We do this three times for luck */
1522 for (i = 0; i < 3; i++) {
1523 I915_WRITE(reg, dpll);
1525 udelay(150); /* wait for warmup */
1529 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1531 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1532 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1533 enum pipe pipe = crtc->pipe;
1535 /* Don't disable pipe or pipe PLLs if needed */
1536 if (IS_I830(dev_priv))
1539 /* Make sure the pipe isn't still relying on us */
1540 assert_pipe_disabled(dev_priv, pipe);
1542 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1543 POSTING_READ(DPLL(pipe));
1546 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1550 /* Make sure the pipe isn't still relying on us */
1551 assert_pipe_disabled(dev_priv, pipe);
1553 val = DPLL_INTEGRATED_REF_CLK_VLV |
1554 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1556 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1558 I915_WRITE(DPLL(pipe), val);
1559 POSTING_READ(DPLL(pipe));
1562 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1564 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1567 /* Make sure the pipe isn't still relying on us */
1568 assert_pipe_disabled(dev_priv, pipe);
1570 val = DPLL_SSC_REF_CLK_CHV |
1571 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1573 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1575 I915_WRITE(DPLL(pipe), val);
1576 POSTING_READ(DPLL(pipe));
1578 vlv_dpio_get(dev_priv);
1580 /* Disable 10bit clock to display controller */
1581 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1582 val &= ~DPIO_DCLKP_EN;
1583 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1585 vlv_dpio_put(dev_priv);
1588 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1589 struct intel_digital_port *dport,
1590 unsigned int expected_mask)
1593 i915_reg_t dpll_reg;
1595 switch (dport->base.port) {
1597 port_mask = DPLL_PORTB_READY_MASK;
1601 port_mask = DPLL_PORTC_READY_MASK;
1603 expected_mask <<= 4;
1606 port_mask = DPLL_PORTD_READY_MASK;
1607 dpll_reg = DPIO_PHY_STATUS;
1613 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1614 port_mask, expected_mask, 1000))
1615 WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1616 dport->base.base.base.id, dport->base.base.name,
1617 I915_READ(dpll_reg) & port_mask, expected_mask);
1620 static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1622 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1623 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1624 enum pipe pipe = crtc->pipe;
1626 u32 val, pipeconf_val;
1628 /* Make sure PCH DPLL is enabled */
1629 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1631 /* FDI must be feeding us bits for PCH ports */
1632 assert_fdi_tx_enabled(dev_priv, pipe);
1633 assert_fdi_rx_enabled(dev_priv, pipe);
1635 if (HAS_PCH_CPT(dev_priv)) {
1636 /* Workaround: Set the timing override bit before enabling the
1637 * pch transcoder. */
1638 reg = TRANS_CHICKEN2(pipe);
1639 val = I915_READ(reg);
1640 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641 I915_WRITE(reg, val);
1644 reg = PCH_TRANSCONF(pipe);
1645 val = I915_READ(reg);
1646 pipeconf_val = I915_READ(PIPECONF(pipe));
1648 if (HAS_PCH_IBX(dev_priv)) {
1650 * Make the BPC in transcoder be consistent with
1651 * that in pipeconf reg. For HDMI we must use 8bpc
1652 * here for both 8bpc and 12bpc.
1654 val &= ~PIPECONF_BPC_MASK;
1655 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1656 val |= PIPECONF_8BPC;
1658 val |= pipeconf_val & PIPECONF_BPC_MASK;
1661 val &= ~TRANS_INTERLACE_MASK;
1662 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1663 if (HAS_PCH_IBX(dev_priv) &&
1664 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1665 val |= TRANS_LEGACY_INTERLACED_ILK;
1667 val |= TRANS_INTERLACED;
1669 val |= TRANS_PROGRESSIVE;
1672 I915_WRITE(reg, val | TRANS_ENABLE);
1673 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1674 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1677 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1678 enum transcoder cpu_transcoder)
1680 u32 val, pipeconf_val;
1682 /* FDI must be feeding us bits for PCH ports */
1683 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1684 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1686 /* Workaround: set timing override bit. */
1687 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1688 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1689 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1692 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1694 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1695 PIPECONF_INTERLACED_ILK)
1696 val |= TRANS_INTERLACED;
1698 val |= TRANS_PROGRESSIVE;
1700 I915_WRITE(LPT_TRANSCONF, val);
1701 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1702 TRANS_STATE_ENABLE, 100))
1703 DRM_ERROR("Failed to enable PCH transcoder\n");
1706 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1712 /* FDI relies on the transcoder */
1713 assert_fdi_tx_disabled(dev_priv, pipe);
1714 assert_fdi_rx_disabled(dev_priv, pipe);
1716 /* Ports must be off as well */
1717 assert_pch_ports_disabled(dev_priv, pipe);
1719 reg = PCH_TRANSCONF(pipe);
1720 val = I915_READ(reg);
1721 val &= ~TRANS_ENABLE;
1722 I915_WRITE(reg, val);
1723 /* wait for PCH transcoder off, transcoder state */
1724 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1725 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1727 if (HAS_PCH_CPT(dev_priv)) {
1728 /* Workaround: Clear the timing override chicken bit again. */
1729 reg = TRANS_CHICKEN2(pipe);
1730 val = I915_READ(reg);
1731 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1732 I915_WRITE(reg, val);
1736 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1740 val = I915_READ(LPT_TRANSCONF);
1741 val &= ~TRANS_ENABLE;
1742 I915_WRITE(LPT_TRANSCONF, val);
1743 /* wait for PCH transcoder off, transcoder state */
1744 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1745 TRANS_STATE_ENABLE, 50))
1746 DRM_ERROR("Failed to disable PCH transcoder\n");
1748 /* Workaround: clear timing override bit. */
1749 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1750 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1751 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1754 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1756 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1758 if (HAS_PCH_LPT(dev_priv))
1764 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1766 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1769 * On i965gm the hardware frame counter reads
1770 * zero when the TV encoder is enabled :(
1772 if (IS_I965GM(dev_priv) &&
1773 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1776 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1777 return 0xffffffff; /* full 32 bit counter */
1778 else if (INTEL_GEN(dev_priv) >= 3)
1779 return 0xffffff; /* only 24 bits of frame count */
1781 return 0; /* Gen2 doesn't have a hardware frame counter */
1784 static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1786 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1788 drm_crtc_set_max_vblank_count(&crtc->base,
1789 intel_crtc_max_vblank_count(crtc_state));
1790 drm_crtc_vblank_on(&crtc->base);
1793 static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1795 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1796 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1797 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1798 enum pipe pipe = crtc->pipe;
1802 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1804 assert_planes_disabled(crtc);
1807 * A pipe without a PLL won't actually be able to drive bits from
1808 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1811 if (HAS_GMCH(dev_priv)) {
1812 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1813 assert_dsi_pll_enabled(dev_priv);
1815 assert_pll_enabled(dev_priv, pipe);
1817 if (new_crtc_state->has_pch_encoder) {
1818 /* if driving the PCH, we need FDI enabled */
1819 assert_fdi_rx_pll_enabled(dev_priv,
1820 intel_crtc_pch_transcoder(crtc));
1821 assert_fdi_tx_pll_enabled(dev_priv,
1822 (enum pipe) cpu_transcoder);
1824 /* FIXME: assert CPU port conditions for SNB+ */
1827 trace_intel_pipe_enable(crtc);
1829 reg = PIPECONF(cpu_transcoder);
1830 val = I915_READ(reg);
1831 if (val & PIPECONF_ENABLE) {
1832 /* we keep both pipes enabled on 830 */
1833 WARN_ON(!IS_I830(dev_priv));
1837 I915_WRITE(reg, val | PIPECONF_ENABLE);
1841 * Until the pipe starts PIPEDSL reads will return a stale value,
1842 * which causes an apparent vblank timestamp jump when PIPEDSL
1843 * resets to its proper value. That also messes up the frame count
1844 * when it's derived from the timestamps. So let's wait for the
1845 * pipe to start properly before we call drm_crtc_vblank_on()
1847 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1848 intel_wait_for_pipe_scanline_moving(crtc);
1851 static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1853 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1855 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1856 enum pipe pipe = crtc->pipe;
1860 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1863 * Make sure planes won't keep trying to pump pixels to us,
1864 * or we might hang the display.
1866 assert_planes_disabled(crtc);
1868 trace_intel_pipe_disable(crtc);
1870 reg = PIPECONF(cpu_transcoder);
1871 val = I915_READ(reg);
1872 if ((val & PIPECONF_ENABLE) == 0)
1876 * Double wide has implications for planes
1877 * so best keep it disabled when not needed.
1879 if (old_crtc_state->double_wide)
1880 val &= ~PIPECONF_DOUBLE_WIDE;
1882 /* Don't disable pipe or pipe PLLs if needed */
1883 if (!IS_I830(dev_priv))
1884 val &= ~PIPECONF_ENABLE;
1886 I915_WRITE(reg, val);
1887 if ((val & PIPECONF_ENABLE) == 0)
1888 intel_wait_for_pipe_off(old_crtc_state);
1891 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1893 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1897 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
1899 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1900 unsigned int cpp = fb->format->cpp[color_plane];
1902 switch (fb->modifier) {
1903 case DRM_FORMAT_MOD_LINEAR:
1904 return intel_tile_size(dev_priv);
1905 case I915_FORMAT_MOD_X_TILED:
1906 if (IS_GEN(dev_priv, 2))
1910 case I915_FORMAT_MOD_Y_TILED_CCS:
1911 if (color_plane == 1)
1914 case I915_FORMAT_MOD_Y_TILED:
1915 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
1919 case I915_FORMAT_MOD_Yf_TILED_CCS:
1920 if (color_plane == 1)
1923 case I915_FORMAT_MOD_Yf_TILED:
1939 MISSING_CASE(fb->modifier);
1945 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
1947 return intel_tile_size(to_i915(fb->dev)) /
1948 intel_tile_width_bytes(fb, color_plane);
1951 /* Return the tile dimensions in pixel units */
1952 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
1953 unsigned int *tile_width,
1954 unsigned int *tile_height)
1956 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
1957 unsigned int cpp = fb->format->cpp[color_plane];
1959 *tile_width = tile_width_bytes / cpp;
1960 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
1964 intel_fb_align_height(const struct drm_framebuffer *fb,
1965 int color_plane, unsigned int height)
1967 unsigned int tile_height = intel_tile_height(fb, color_plane);
1969 return ALIGN(height, tile_height);
1972 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
1974 unsigned int size = 0;
1977 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
1978 size += rot_info->plane[i].width * rot_info->plane[i].height;
1983 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
1985 unsigned int size = 0;
1988 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
1989 size += rem_info->plane[i].width * rem_info->plane[i].height;
1995 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
1996 const struct drm_framebuffer *fb,
1997 unsigned int rotation)
1999 view->type = I915_GGTT_VIEW_NORMAL;
2000 if (drm_rotation_90_or_270(rotation)) {
2001 view->type = I915_GGTT_VIEW_ROTATED;
2002 view->rotated = to_intel_framebuffer(fb)->rot_info;
2006 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2008 if (IS_I830(dev_priv))
2010 else if (IS_I85X(dev_priv))
2012 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2018 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2020 if (INTEL_GEN(dev_priv) >= 9)
2022 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2023 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2025 else if (INTEL_GEN(dev_priv) >= 4)
2031 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2034 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2036 /* AUX_DIST needs only 4K alignment */
2037 if (color_plane == 1)
2040 switch (fb->modifier) {
2041 case DRM_FORMAT_MOD_LINEAR:
2042 return intel_linear_alignment(dev_priv);
2043 case I915_FORMAT_MOD_X_TILED:
2044 if (INTEL_GEN(dev_priv) >= 9)
2047 case I915_FORMAT_MOD_Y_TILED_CCS:
2048 case I915_FORMAT_MOD_Yf_TILED_CCS:
2049 case I915_FORMAT_MOD_Y_TILED:
2050 case I915_FORMAT_MOD_Yf_TILED:
2051 return 1 * 1024 * 1024;
2053 MISSING_CASE(fb->modifier);
2058 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2060 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2061 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2063 return INTEL_GEN(dev_priv) < 4 ||
2065 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2069 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2070 const struct i915_ggtt_view *view,
2072 unsigned long *out_flags)
2074 struct drm_device *dev = fb->dev;
2075 struct drm_i915_private *dev_priv = to_i915(dev);
2076 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2077 intel_wakeref_t wakeref;
2078 struct i915_vma *vma;
2079 unsigned int pinctl;
2082 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2083 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
2084 return ERR_PTR(-EINVAL);
2086 alignment = intel_surf_alignment(fb, 0);
2088 /* Note that the w/a also requires 64 PTE of padding following the
2089 * bo. We currently fill all unused PTE with the shadow page and so
2090 * we should always have valid PTE following the scanout preventing
2093 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2094 alignment = 256 * 1024;
2097 * Global gtt pte registers are special registers which actually forward
2098 * writes to a chunk of system memory. Which means that there is no risk
2099 * that the register values disappear as soon as we call
2100 * intel_runtime_pm_put(), so it is correct to wrap only the
2101 * pin/unpin/fence and not more.
2103 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2104 i915_gem_object_lock(obj);
2106 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2110 /* Valleyview is definitely limited to scanning out the first
2111 * 512MiB. Lets presume this behaviour was inherited from the
2112 * g4x display engine and that all earlier gen are similarly
2113 * limited. Testing suggests that it is a little more
2114 * complicated than this. For example, Cherryview appears quite
2115 * happy to scanout from anywhere within its global aperture.
2117 if (HAS_GMCH(dev_priv))
2118 pinctl |= PIN_MAPPABLE;
2120 vma = i915_gem_object_pin_to_display_plane(obj,
2121 alignment, view, pinctl);
2125 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2128 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2129 * fence, whereas 965+ only requires a fence if using
2130 * framebuffer compression. For simplicity, we always, when
2131 * possible, install a fence as the cost is not that onerous.
2133 * If we fail to fence the tiled scanout, then either the
2134 * modeset will reject the change (which is highly unlikely as
2135 * the affected systems, all but one, do not have unmappable
2136 * space) or we will not be able to enable full powersaving
2137 * techniques (also likely not to apply due to various limits
2138 * FBC and the like impose on the size of the buffer, which
2139 * presumably we violated anyway with this unmappable buffer).
2140 * Anyway, it is presumably better to stumble onwards with
2141 * something and try to run the system in a "less than optimal"
2142 * mode that matches the user configuration.
2144 ret = i915_vma_pin_fence(vma);
2145 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2146 i915_gem_object_unpin_from_display_plane(vma);
2151 if (ret == 0 && vma->fence)
2152 *out_flags |= PLANE_HAS_FENCE;
2157 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2159 i915_gem_object_unlock(obj);
2160 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2164 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2166 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2168 i915_gem_object_lock(vma->obj);
2169 if (flags & PLANE_HAS_FENCE)
2170 i915_vma_unpin_fence(vma);
2171 i915_gem_object_unpin_from_display_plane(vma);
2172 i915_gem_object_unlock(vma->obj);
2177 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2178 unsigned int rotation)
2180 if (drm_rotation_90_or_270(rotation))
2181 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2183 return fb->pitches[color_plane];
2187 * Convert the x/y offsets into a linear offset.
2188 * Only valid with 0/180 degree rotation, which is fine since linear
2189 * offset is only used with linear buffers on pre-hsw and tiled buffers
2190 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2192 u32 intel_fb_xy_to_linear(int x, int y,
2193 const struct intel_plane_state *state,
2196 const struct drm_framebuffer *fb = state->base.fb;
2197 unsigned int cpp = fb->format->cpp[color_plane];
2198 unsigned int pitch = state->color_plane[color_plane].stride;
2200 return y * pitch + x * cpp;
2204 * Add the x/y offsets derived from fb->offsets[] to the user
2205 * specified plane src x/y offsets. The resulting x/y offsets
2206 * specify the start of scanout from the beginning of the gtt mapping.
2208 void intel_add_fb_offsets(int *x, int *y,
2209 const struct intel_plane_state *state,
2213 *x += state->color_plane[color_plane].x;
2214 *y += state->color_plane[color_plane].y;
2217 static u32 intel_adjust_tile_offset(int *x, int *y,
2218 unsigned int tile_width,
2219 unsigned int tile_height,
2220 unsigned int tile_size,
2221 unsigned int pitch_tiles,
2225 unsigned int pitch_pixels = pitch_tiles * tile_width;
2228 WARN_ON(old_offset & (tile_size - 1));
2229 WARN_ON(new_offset & (tile_size - 1));
2230 WARN_ON(new_offset > old_offset);
2232 tiles = (old_offset - new_offset) / tile_size;
2234 *y += tiles / pitch_tiles * tile_height;
2235 *x += tiles % pitch_tiles * tile_width;
2237 /* minimize x in case it got needlessly big */
2238 *y += *x / pitch_pixels * tile_height;
2244 static bool is_surface_linear(u64 modifier, int color_plane)
2246 return modifier == DRM_FORMAT_MOD_LINEAR;
2249 static u32 intel_adjust_aligned_offset(int *x, int *y,
2250 const struct drm_framebuffer *fb,
2252 unsigned int rotation,
2254 u32 old_offset, u32 new_offset)
2256 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2257 unsigned int cpp = fb->format->cpp[color_plane];
2259 WARN_ON(new_offset > old_offset);
2261 if (!is_surface_linear(fb->modifier, color_plane)) {
2262 unsigned int tile_size, tile_width, tile_height;
2263 unsigned int pitch_tiles;
2265 tile_size = intel_tile_size(dev_priv);
2266 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2268 if (drm_rotation_90_or_270(rotation)) {
2269 pitch_tiles = pitch / tile_height;
2270 swap(tile_width, tile_height);
2272 pitch_tiles = pitch / (tile_width * cpp);
2275 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2276 tile_size, pitch_tiles,
2277 old_offset, new_offset);
2279 old_offset += *y * pitch + *x * cpp;
2281 *y = (old_offset - new_offset) / pitch;
2282 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2289 * Adjust the tile offset by moving the difference into
2292 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2293 const struct intel_plane_state *state,
2295 u32 old_offset, u32 new_offset)
2297 return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
2298 state->base.rotation,
2299 state->color_plane[color_plane].stride,
2300 old_offset, new_offset);
2304 * Computes the aligned offset to the base tile and adjusts
2305 * x, y. bytes per pixel is assumed to be a power-of-two.
2307 * In the 90/270 rotated case, x and y are assumed
2308 * to be already rotated to match the rotated GTT view, and
2309 * pitch is the tile_height aligned framebuffer height.
2311 * This function is used when computing the derived information
2312 * under intel_framebuffer, so using any of that information
2313 * here is not allowed. Anything under drm_framebuffer can be
2314 * used. This is why the user has to pass in the pitch since it
2315 * is specified in the rotated orientation.
2317 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2319 const struct drm_framebuffer *fb,
2322 unsigned int rotation,
2325 unsigned int cpp = fb->format->cpp[color_plane];
2326 u32 offset, offset_aligned;
2331 if (!is_surface_linear(fb->modifier, color_plane)) {
2332 unsigned int tile_size, tile_width, tile_height;
2333 unsigned int tile_rows, tiles, pitch_tiles;
2335 tile_size = intel_tile_size(dev_priv);
2336 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2338 if (drm_rotation_90_or_270(rotation)) {
2339 pitch_tiles = pitch / tile_height;
2340 swap(tile_width, tile_height);
2342 pitch_tiles = pitch / (tile_width * cpp);
2345 tile_rows = *y / tile_height;
2348 tiles = *x / tile_width;
2351 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2352 offset_aligned = offset & ~alignment;
2354 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2355 tile_size, pitch_tiles,
2356 offset, offset_aligned);
2358 offset = *y * pitch + *x * cpp;
2359 offset_aligned = offset & ~alignment;
2361 *y = (offset & alignment) / pitch;
2362 *x = ((offset & alignment) - *y * pitch) / cpp;
2365 return offset_aligned;
2368 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2369 const struct intel_plane_state *state,
2372 struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2373 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2374 const struct drm_framebuffer *fb = state->base.fb;
2375 unsigned int rotation = state->base.rotation;
2376 int pitch = state->color_plane[color_plane].stride;
2379 if (intel_plane->id == PLANE_CURSOR)
2380 alignment = intel_cursor_alignment(dev_priv);
2382 alignment = intel_surf_alignment(fb, color_plane);
2384 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2385 pitch, rotation, alignment);
2388 /* Convert the fb->offset[] into x/y offsets */
2389 static int intel_fb_offset_to_xy(int *x, int *y,
2390 const struct drm_framebuffer *fb,
2393 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2394 unsigned int height;
2396 if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2397 fb->offsets[color_plane] % intel_tile_size(dev_priv)) {
2398 DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n",
2399 fb->offsets[color_plane], color_plane);
2403 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2404 height = ALIGN(height, intel_tile_height(fb, color_plane));
2406 /* Catch potential overflows early */
2407 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2408 fb->offsets[color_plane])) {
2409 DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n",
2410 fb->offsets[color_plane], fb->pitches[color_plane],
2418 intel_adjust_aligned_offset(x, y,
2419 fb, color_plane, DRM_MODE_ROTATE_0,
2420 fb->pitches[color_plane],
2421 fb->offsets[color_plane], 0);
2426 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2428 switch (fb_modifier) {
2429 case I915_FORMAT_MOD_X_TILED:
2430 return I915_TILING_X;
2431 case I915_FORMAT_MOD_Y_TILED:
2432 case I915_FORMAT_MOD_Y_TILED_CCS:
2433 return I915_TILING_Y;
2435 return I915_TILING_NONE;
2440 * From the Sky Lake PRM:
2441 * "The Color Control Surface (CCS) contains the compression status of
2442 * the cache-line pairs. The compression state of the cache-line pair
2443 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2444 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2445 * cache-line-pairs. CCS is always Y tiled."
2447 * Since cache line pairs refers to horizontally adjacent cache lines,
2448 * each cache line in the CCS corresponds to an area of 32x16 cache
2449 * lines on the main surface. Since each pixel is 4 bytes, this gives
2450 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2453 static const struct drm_format_info ccs_formats[] = {
2454 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2455 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2456 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2457 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2458 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2459 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2460 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2461 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2464 static const struct drm_format_info *
2465 lookup_format_info(const struct drm_format_info formats[],
2466 int num_formats, u32 format)
2470 for (i = 0; i < num_formats; i++) {
2471 if (formats[i].format == format)
2478 static const struct drm_format_info *
2479 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2481 switch (cmd->modifier[0]) {
2482 case I915_FORMAT_MOD_Y_TILED_CCS:
2483 case I915_FORMAT_MOD_Yf_TILED_CCS:
2484 return lookup_format_info(ccs_formats,
2485 ARRAY_SIZE(ccs_formats),
2492 bool is_ccs_modifier(u64 modifier)
2494 return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2495 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2498 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2499 u32 pixel_format, u64 modifier)
2501 struct intel_crtc *crtc;
2502 struct intel_plane *plane;
2505 * We assume the primary plane for pipe A has
2506 * the highest stride limits of them all.
2508 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2509 plane = to_intel_plane(crtc->base.primary);
2511 return plane->max_stride(plane, pixel_format, modifier,
2516 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2517 u32 pixel_format, u64 modifier)
2520 * Arbitrary limit for gen4+ chosen to match the
2521 * render engine max stride.
2523 * The new CCS hash mode makes remapping impossible
2525 if (!is_ccs_modifier(modifier)) {
2526 if (INTEL_GEN(dev_priv) >= 7)
2528 else if (INTEL_GEN(dev_priv) >= 4)
2532 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2536 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2538 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2540 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2541 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2546 * To make remapping with linear generally feasible
2547 * we need the stride to be page aligned.
2549 if (fb->pitches[color_plane] > max_stride)
2550 return intel_tile_size(dev_priv);
2554 return intel_tile_width_bytes(fb, color_plane);
2558 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2560 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2561 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2562 const struct drm_framebuffer *fb = plane_state->base.fb;
2565 /* We don't want to deal with remapping with cursors */
2566 if (plane->id == PLANE_CURSOR)
2570 * The display engine limits already match/exceed the
2571 * render engine limits, so not much point in remapping.
2572 * Would also need to deal with the fence POT alignment
2573 * and gen2 2KiB GTT tile size.
2575 if (INTEL_GEN(dev_priv) < 4)
2579 * The new CCS hash mode isn't compatible with remapping as
2580 * the virtual address of the pages affects the compressed data.
2582 if (is_ccs_modifier(fb->modifier))
2585 /* Linear needs a page aligned stride for remapping */
2586 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2587 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2589 for (i = 0; i < fb->format->num_planes; i++) {
2590 if (fb->pitches[i] & alignment)
2598 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2600 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2601 const struct drm_framebuffer *fb = plane_state->base.fb;
2602 unsigned int rotation = plane_state->base.rotation;
2603 u32 stride, max_stride;
2606 * No remapping for invisible planes since we don't have
2607 * an actual source viewport to remap.
2609 if (!plane_state->base.visible)
2612 if (!intel_plane_can_remap(plane_state))
2616 * FIXME: aux plane limits on gen9+ are
2617 * unclear in Bspec, for now no checking.
2619 stride = intel_fb_pitch(fb, 0, rotation);
2620 max_stride = plane->max_stride(plane, fb->format->format,
2621 fb->modifier, rotation);
2623 return stride > max_stride;
2627 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2628 struct drm_framebuffer *fb)
2630 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2631 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2632 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2633 u32 gtt_offset_rotated = 0;
2634 unsigned int max_size = 0;
2635 int i, num_planes = fb->format->num_planes;
2636 unsigned int tile_size = intel_tile_size(dev_priv);
2638 for (i = 0; i < num_planes; i++) {
2639 unsigned int width, height;
2640 unsigned int cpp, size;
2645 cpp = fb->format->cpp[i];
2646 width = drm_framebuffer_plane_width(fb->width, fb, i);
2647 height = drm_framebuffer_plane_height(fb->height, fb, i);
2649 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2651 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2656 if (is_ccs_modifier(fb->modifier) && i == 1) {
2657 int hsub = fb->format->hsub;
2658 int vsub = fb->format->vsub;
2659 int tile_width, tile_height;
2663 intel_tile_dims(fb, i, &tile_width, &tile_height);
2665 tile_height *= vsub;
2667 ccs_x = (x * hsub) % tile_width;
2668 ccs_y = (y * vsub) % tile_height;
2669 main_x = intel_fb->normal[0].x % tile_width;
2670 main_y = intel_fb->normal[0].y % tile_height;
2673 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2674 * x/y offsets must match between CCS and the main surface.
2676 if (main_x != ccs_x || main_y != ccs_y) {
2677 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2680 intel_fb->normal[0].x,
2681 intel_fb->normal[0].y,
2688 * The fence (if used) is aligned to the start of the object
2689 * so having the framebuffer wrap around across the edge of the
2690 * fenced region doesn't really work. We have no API to configure
2691 * the fence start offset within the object (nor could we probably
2692 * on gen2/3). So it's just easier if we just require that the
2693 * fb layout agrees with the fence layout. We already check that the
2694 * fb stride matches the fence stride elsewhere.
2696 if (i == 0 && i915_gem_object_is_tiled(obj) &&
2697 (x + width) * cpp > fb->pitches[i]) {
2698 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2704 * First pixel of the framebuffer from
2705 * the start of the normal gtt mapping.
2707 intel_fb->normal[i].x = x;
2708 intel_fb->normal[i].y = y;
2710 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
2714 offset /= tile_size;
2716 if (!is_surface_linear(fb->modifier, i)) {
2717 unsigned int tile_width, tile_height;
2718 unsigned int pitch_tiles;
2721 intel_tile_dims(fb, i, &tile_width, &tile_height);
2723 rot_info->plane[i].offset = offset;
2724 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2725 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2726 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2728 intel_fb->rotated[i].pitch =
2729 rot_info->plane[i].height * tile_height;
2731 /* how many tiles does this plane need */
2732 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2734 * If the plane isn't horizontally tile aligned,
2735 * we need one more tile.
2740 /* rotate the x/y offsets to match the GTT view */
2746 rot_info->plane[i].width * tile_width,
2747 rot_info->plane[i].height * tile_height,
2748 DRM_MODE_ROTATE_270);
2752 /* rotate the tile dimensions to match the GTT view */
2753 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2754 swap(tile_width, tile_height);
2757 * We only keep the x/y offsets, so push all of the
2758 * gtt offset into the x/y offsets.
2760 intel_adjust_tile_offset(&x, &y,
2761 tile_width, tile_height,
2762 tile_size, pitch_tiles,
2763 gtt_offset_rotated * tile_size, 0);
2765 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2768 * First pixel of the framebuffer from
2769 * the start of the rotated gtt mapping.
2771 intel_fb->rotated[i].x = x;
2772 intel_fb->rotated[i].y = y;
2774 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2775 x * cpp, tile_size);
2778 /* how many tiles in total needed in the bo */
2779 max_size = max(max_size, offset + size);
2782 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
2783 DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n",
2784 mul_u32_u32(max_size, tile_size), obj->base.size);
2792 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
2794 struct drm_i915_private *dev_priv =
2795 to_i915(plane_state->base.plane->dev);
2796 struct drm_framebuffer *fb = plane_state->base.fb;
2797 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2798 struct intel_rotation_info *info = &plane_state->view.rotated;
2799 unsigned int rotation = plane_state->base.rotation;
2800 int i, num_planes = fb->format->num_planes;
2801 unsigned int tile_size = intel_tile_size(dev_priv);
2802 unsigned int src_x, src_y;
2803 unsigned int src_w, src_h;
2806 memset(&plane_state->view, 0, sizeof(plane_state->view));
2807 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
2808 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
2810 src_x = plane_state->base.src.x1 >> 16;
2811 src_y = plane_state->base.src.y1 >> 16;
2812 src_w = drm_rect_width(&plane_state->base.src) >> 16;
2813 src_h = drm_rect_height(&plane_state->base.src) >> 16;
2815 WARN_ON(is_ccs_modifier(fb->modifier));
2817 /* Make src coordinates relative to the viewport */
2818 drm_rect_translate(&plane_state->base.src,
2819 -(src_x << 16), -(src_y << 16));
2821 /* Rotate src coordinates to match rotated GTT view */
2822 if (drm_rotation_90_or_270(rotation))
2823 drm_rect_rotate(&plane_state->base.src,
2824 src_w << 16, src_h << 16,
2825 DRM_MODE_ROTATE_270);
2827 for (i = 0; i < num_planes; i++) {
2828 unsigned int hsub = i ? fb->format->hsub : 1;
2829 unsigned int vsub = i ? fb->format->vsub : 1;
2830 unsigned int cpp = fb->format->cpp[i];
2831 unsigned int tile_width, tile_height;
2832 unsigned int width, height;
2833 unsigned int pitch_tiles;
2837 intel_tile_dims(fb, i, &tile_width, &tile_height);
2841 width = src_w / hsub;
2842 height = src_h / vsub;
2845 * First pixel of the src viewport from the
2846 * start of the normal gtt mapping.
2848 x += intel_fb->normal[i].x;
2849 y += intel_fb->normal[i].y;
2851 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
2852 fb, i, fb->pitches[i],
2853 DRM_MODE_ROTATE_0, tile_size);
2854 offset /= tile_size;
2856 info->plane[i].offset = offset;
2857 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
2859 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2860 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2862 if (drm_rotation_90_or_270(rotation)) {
2865 /* rotate the x/y offsets to match the GTT view */
2871 info->plane[i].width * tile_width,
2872 info->plane[i].height * tile_height,
2873 DRM_MODE_ROTATE_270);
2877 pitch_tiles = info->plane[i].height;
2878 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
2880 /* rotate the tile dimensions to match the GTT view */
2881 swap(tile_width, tile_height);
2883 pitch_tiles = info->plane[i].width;
2884 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
2888 * We only keep the x/y offsets, so push all of the
2889 * gtt offset into the x/y offsets.
2891 intel_adjust_tile_offset(&x, &y,
2892 tile_width, tile_height,
2893 tile_size, pitch_tiles,
2894 gtt_offset * tile_size, 0);
2896 gtt_offset += info->plane[i].width * info->plane[i].height;
2898 plane_state->color_plane[i].offset = 0;
2899 plane_state->color_plane[i].x = x;
2900 plane_state->color_plane[i].y = y;
2905 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
2907 const struct intel_framebuffer *fb =
2908 to_intel_framebuffer(plane_state->base.fb);
2909 unsigned int rotation = plane_state->base.rotation;
2915 num_planes = fb->base.format->num_planes;
2917 if (intel_plane_needs_remap(plane_state)) {
2918 intel_plane_remap_gtt(plane_state);
2921 * Sometimes even remapping can't overcome
2922 * the stride limitations :( Can happen with
2923 * big plane sizes and suitably misaligned
2926 return intel_plane_check_stride(plane_state);
2929 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
2931 for (i = 0; i < num_planes; i++) {
2932 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
2933 plane_state->color_plane[i].offset = 0;
2935 if (drm_rotation_90_or_270(rotation)) {
2936 plane_state->color_plane[i].x = fb->rotated[i].x;
2937 plane_state->color_plane[i].y = fb->rotated[i].y;
2939 plane_state->color_plane[i].x = fb->normal[i].x;
2940 plane_state->color_plane[i].y = fb->normal[i].y;
2944 /* Rotate src coordinates to match rotated GTT view */
2945 if (drm_rotation_90_or_270(rotation))
2946 drm_rect_rotate(&plane_state->base.src,
2947 fb->base.width << 16, fb->base.height << 16,
2948 DRM_MODE_ROTATE_270);
2950 return intel_plane_check_stride(plane_state);
2953 static int i9xx_format_to_fourcc(int format)
2956 case DISPPLANE_8BPP:
2957 return DRM_FORMAT_C8;
2958 case DISPPLANE_BGRX555:
2959 return DRM_FORMAT_XRGB1555;
2960 case DISPPLANE_BGRX565:
2961 return DRM_FORMAT_RGB565;
2963 case DISPPLANE_BGRX888:
2964 return DRM_FORMAT_XRGB8888;
2965 case DISPPLANE_RGBX888:
2966 return DRM_FORMAT_XBGR8888;
2967 case DISPPLANE_BGRX101010:
2968 return DRM_FORMAT_XRGB2101010;
2969 case DISPPLANE_RGBX101010:
2970 return DRM_FORMAT_XBGR2101010;
2974 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2977 case PLANE_CTL_FORMAT_RGB_565:
2978 return DRM_FORMAT_RGB565;
2979 case PLANE_CTL_FORMAT_NV12:
2980 return DRM_FORMAT_NV12;
2981 case PLANE_CTL_FORMAT_P010:
2982 return DRM_FORMAT_P010;
2983 case PLANE_CTL_FORMAT_P012:
2984 return DRM_FORMAT_P012;
2985 case PLANE_CTL_FORMAT_P016:
2986 return DRM_FORMAT_P016;
2987 case PLANE_CTL_FORMAT_Y210:
2988 return DRM_FORMAT_Y210;
2989 case PLANE_CTL_FORMAT_Y212:
2990 return DRM_FORMAT_Y212;
2991 case PLANE_CTL_FORMAT_Y216:
2992 return DRM_FORMAT_Y216;
2993 case PLANE_CTL_FORMAT_Y410:
2994 return DRM_FORMAT_XVYU2101010;
2995 case PLANE_CTL_FORMAT_Y412:
2996 return DRM_FORMAT_XVYU12_16161616;
2997 case PLANE_CTL_FORMAT_Y416:
2998 return DRM_FORMAT_XVYU16161616;
3000 case PLANE_CTL_FORMAT_XRGB_8888:
3003 return DRM_FORMAT_ABGR8888;
3005 return DRM_FORMAT_XBGR8888;
3008 return DRM_FORMAT_ARGB8888;
3010 return DRM_FORMAT_XRGB8888;
3012 case PLANE_CTL_FORMAT_XRGB_2101010:
3014 return DRM_FORMAT_XBGR2101010;
3016 return DRM_FORMAT_XRGB2101010;
3017 case PLANE_CTL_FORMAT_XRGB_16161616F:
3020 return DRM_FORMAT_ABGR16161616F;
3022 return DRM_FORMAT_XBGR16161616F;
3025 return DRM_FORMAT_ARGB16161616F;
3027 return DRM_FORMAT_XRGB16161616F;
3033 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3034 struct intel_initial_plane_config *plane_config)
3036 struct drm_device *dev = crtc->base.dev;
3037 struct drm_i915_private *dev_priv = to_i915(dev);
3038 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3039 struct drm_framebuffer *fb = &plane_config->fb->base;
3040 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
3041 u32 size_aligned = round_up(plane_config->base + plane_config->size,
3043 struct drm_i915_gem_object *obj;
3046 size_aligned -= base_aligned;
3048 if (plane_config->size == 0)
3051 /* If the FB is too big, just don't use it since fbdev is not very
3052 * important and we should probably use that space with FBC or other
3054 if (size_aligned * 2 > dev_priv->stolen_usable_size)
3057 switch (fb->modifier) {
3058 case DRM_FORMAT_MOD_LINEAR:
3059 case I915_FORMAT_MOD_X_TILED:
3060 case I915_FORMAT_MOD_Y_TILED:
3063 DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n",
3068 mutex_lock(&dev->struct_mutex);
3069 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
3073 mutex_unlock(&dev->struct_mutex);
3077 switch (plane_config->tiling) {
3078 case I915_TILING_NONE:
3082 obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling;
3085 MISSING_CASE(plane_config->tiling);
3089 mode_cmd.pixel_format = fb->format->format;
3090 mode_cmd.width = fb->width;
3091 mode_cmd.height = fb->height;
3092 mode_cmd.pitches[0] = fb->pitches[0];
3093 mode_cmd.modifier[0] = fb->modifier;
3094 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3096 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
3097 DRM_DEBUG_KMS("intel fb init failed\n");
3102 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
3105 i915_gem_object_put(obj);
3110 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3111 struct intel_plane_state *plane_state,
3114 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3116 plane_state->base.visible = visible;
3119 crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
3121 crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
3124 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3126 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3127 struct drm_plane *plane;
3130 * Active_planes aliases if multiple "primary" or cursor planes
3131 * have been used on the same (or wrong) pipe. plane_mask uses
3132 * unique ids, hence we can use that to reconstruct active_planes.
3134 crtc_state->active_planes = 0;
3136 drm_for_each_plane_mask(plane, &dev_priv->drm,
3137 crtc_state->base.plane_mask)
3138 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3141 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3142 struct intel_plane *plane)
3144 struct intel_crtc_state *crtc_state =
3145 to_intel_crtc_state(crtc->base.state);
3146 struct intel_plane_state *plane_state =
3147 to_intel_plane_state(plane->base.state);
3149 DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3150 plane->base.base.id, plane->base.name,
3151 crtc->base.base.id, crtc->base.name);
3153 intel_set_plane_visible(crtc_state, plane_state, false);
3154 fixup_active_planes(crtc_state);
3155 crtc_state->data_rate[plane->id] = 0;
3157 if (plane->id == PLANE_PRIMARY)
3158 intel_pre_disable_primary_noatomic(&crtc->base);
3160 intel_disable_plane(plane, crtc_state);
3163 static struct intel_frontbuffer *
3164 to_intel_frontbuffer(struct drm_framebuffer *fb)
3166 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3170 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3171 struct intel_initial_plane_config *plane_config)
3173 struct drm_device *dev = intel_crtc->base.dev;
3174 struct drm_i915_private *dev_priv = to_i915(dev);
3176 struct drm_plane *primary = intel_crtc->base.primary;
3177 struct drm_plane_state *plane_state = primary->state;
3178 struct intel_plane *intel_plane = to_intel_plane(primary);
3179 struct intel_plane_state *intel_state =
3180 to_intel_plane_state(plane_state);
3181 struct drm_framebuffer *fb;
3183 if (!plane_config->fb)
3186 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3187 fb = &plane_config->fb->base;
3191 kfree(plane_config->fb);
3194 * Failed to alloc the obj, check to see if we should share
3195 * an fb with another CRTC instead
3197 for_each_crtc(dev, c) {
3198 struct intel_plane_state *state;
3200 if (c == &intel_crtc->base)
3203 if (!to_intel_crtc(c)->active)
3206 state = to_intel_plane_state(c->primary->state);
3210 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3211 fb = state->base.fb;
3212 drm_framebuffer_get(fb);
3218 * We've failed to reconstruct the BIOS FB. Current display state
3219 * indicates that the primary plane is visible, but has a NULL FB,
3220 * which will lead to problems later if we don't fix it up. The
3221 * simplest solution is to just disable the primary plane now and
3222 * pretend the BIOS never had it enabled.
3224 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3229 intel_state->base.rotation = plane_config->rotation;
3230 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3231 intel_state->base.rotation);
3232 intel_state->color_plane[0].stride =
3233 intel_fb_pitch(fb, 0, intel_state->base.rotation);
3235 mutex_lock(&dev->struct_mutex);
3237 intel_pin_and_fence_fb_obj(fb,
3239 intel_plane_uses_fence(intel_state),
3240 &intel_state->flags);
3241 mutex_unlock(&dev->struct_mutex);
3242 if (IS_ERR(intel_state->vma)) {
3243 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
3244 intel_crtc->pipe, PTR_ERR(intel_state->vma));
3246 intel_state->vma = NULL;
3247 drm_framebuffer_put(fb);
3251 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3253 plane_state->src_x = 0;
3254 plane_state->src_y = 0;
3255 plane_state->src_w = fb->width << 16;
3256 plane_state->src_h = fb->height << 16;
3258 plane_state->crtc_x = 0;
3259 plane_state->crtc_y = 0;
3260 plane_state->crtc_w = fb->width;
3261 plane_state->crtc_h = fb->height;
3263 intel_state->base.src = drm_plane_state_src(plane_state);
3264 intel_state->base.dst = drm_plane_state_dest(plane_state);
3266 if (plane_config->tiling)
3267 dev_priv->preserve_bios_swizzle = true;
3269 plane_state->fb = fb;
3270 plane_state->crtc = &intel_crtc->base;
3272 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3273 &to_intel_frontbuffer(fb)->bits);
3276 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3278 unsigned int rotation)
3280 int cpp = fb->format->cpp[color_plane];
3282 switch (fb->modifier) {
3283 case DRM_FORMAT_MOD_LINEAR:
3284 case I915_FORMAT_MOD_X_TILED:
3286 case I915_FORMAT_MOD_Y_TILED_CCS:
3287 case I915_FORMAT_MOD_Yf_TILED_CCS:
3288 /* FIXME AUX plane? */
3289 case I915_FORMAT_MOD_Y_TILED:
3290 case I915_FORMAT_MOD_Yf_TILED:
3296 MISSING_CASE(fb->modifier);
3301 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3303 unsigned int rotation)
3305 int cpp = fb->format->cpp[color_plane];
3307 switch (fb->modifier) {
3308 case DRM_FORMAT_MOD_LINEAR:
3309 case I915_FORMAT_MOD_X_TILED:
3314 case I915_FORMAT_MOD_Y_TILED_CCS:
3315 case I915_FORMAT_MOD_Yf_TILED_CCS:
3316 /* FIXME AUX plane? */
3317 case I915_FORMAT_MOD_Y_TILED:
3318 case I915_FORMAT_MOD_Yf_TILED:
3324 MISSING_CASE(fb->modifier);
3329 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3331 unsigned int rotation)
3336 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3337 int main_x, int main_y, u32 main_offset)
3339 const struct drm_framebuffer *fb = plane_state->base.fb;
3340 int hsub = fb->format->hsub;
3341 int vsub = fb->format->vsub;
3342 int aux_x = plane_state->color_plane[1].x;
3343 int aux_y = plane_state->color_plane[1].y;
3344 u32 aux_offset = plane_state->color_plane[1].offset;
3345 u32 alignment = intel_surf_alignment(fb, 1);
3347 while (aux_offset >= main_offset && aux_y <= main_y) {
3350 if (aux_x == main_x && aux_y == main_y)
3353 if (aux_offset == 0)
3358 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
3359 aux_offset, aux_offset - alignment);
3360 aux_x = x * hsub + aux_x % hsub;
3361 aux_y = y * vsub + aux_y % vsub;
3364 if (aux_x != main_x || aux_y != main_y)
3367 plane_state->color_plane[1].offset = aux_offset;
3368 plane_state->color_plane[1].x = aux_x;
3369 plane_state->color_plane[1].y = aux_y;
3374 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3376 struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
3377 const struct drm_framebuffer *fb = plane_state->base.fb;
3378 unsigned int rotation = plane_state->base.rotation;
3379 int x = plane_state->base.src.x1 >> 16;
3380 int y = plane_state->base.src.y1 >> 16;
3381 int w = drm_rect_width(&plane_state->base.src) >> 16;
3382 int h = drm_rect_height(&plane_state->base.src) >> 16;
3384 int max_height = 4096;
3385 u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
3387 if (INTEL_GEN(dev_priv) >= 11)
3388 max_width = icl_max_plane_width(fb, 0, rotation);
3389 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3390 max_width = glk_max_plane_width(fb, 0, rotation);
3392 max_width = skl_max_plane_width(fb, 0, rotation);
3394 if (w > max_width || h > max_height) {
3395 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3396 w, h, max_width, max_height);
3400 intel_add_fb_offsets(&x, &y, plane_state, 0);
3401 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3402 alignment = intel_surf_alignment(fb, 0);
3405 * AUX surface offset is specified as the distance from the
3406 * main surface offset, and it must be non-negative. Make
3407 * sure that is what we will get.
3409 if (offset > aux_offset)
3410 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3411 offset, aux_offset & ~(alignment - 1));
3414 * When using an X-tiled surface, the plane blows up
3415 * if the x offset + width exceed the stride.
3417 * TODO: linear and Y-tiled seem fine, Yf untested,
3419 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3420 int cpp = fb->format->cpp[0];
3422 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3424 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3428 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3429 offset, offset - alignment);
3434 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3435 * they match with the main surface x/y offsets.
3437 if (is_ccs_modifier(fb->modifier)) {
3438 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3442 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3443 offset, offset - alignment);
3446 if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
3447 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3452 plane_state->color_plane[0].offset = offset;
3453 plane_state->color_plane[0].x = x;
3454 plane_state->color_plane[0].y = y;
3457 * Put the final coordinates back so that the src
3458 * coordinate checks will see the right values.
3460 drm_rect_translate(&plane_state->base.src,
3461 (x << 16) - plane_state->base.src.x1,
3462 (y << 16) - plane_state->base.src.y1);
3467 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3469 const struct drm_framebuffer *fb = plane_state->base.fb;
3470 unsigned int rotation = plane_state->base.rotation;
3471 int max_width = skl_max_plane_width(fb, 1, rotation);
3472 int max_height = 4096;
3473 int x = plane_state->base.src.x1 >> 17;
3474 int y = plane_state->base.src.y1 >> 17;
3475 int w = drm_rect_width(&plane_state->base.src) >> 17;
3476 int h = drm_rect_height(&plane_state->base.src) >> 17;
3479 intel_add_fb_offsets(&x, &y, plane_state, 1);
3480 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3482 /* FIXME not quite sure how/if these apply to the chroma plane */
3483 if (w > max_width || h > max_height) {
3484 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3485 w, h, max_width, max_height);
3489 plane_state->color_plane[1].offset = offset;
3490 plane_state->color_plane[1].x = x;
3491 plane_state->color_plane[1].y = y;
3496 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3498 const struct drm_framebuffer *fb = plane_state->base.fb;
3499 int src_x = plane_state->base.src.x1 >> 16;
3500 int src_y = plane_state->base.src.y1 >> 16;
3501 int hsub = fb->format->hsub;
3502 int vsub = fb->format->vsub;
3503 int x = src_x / hsub;
3504 int y = src_y / vsub;
3507 intel_add_fb_offsets(&x, &y, plane_state, 1);
3508 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
3510 plane_state->color_plane[1].offset = offset;
3511 plane_state->color_plane[1].x = x * hsub + src_x % hsub;
3512 plane_state->color_plane[1].y = y * vsub + src_y % vsub;
3517 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3519 const struct drm_framebuffer *fb = plane_state->base.fb;
3522 ret = intel_plane_compute_gtt(plane_state);
3526 if (!plane_state->base.visible)
3530 * Handle the AUX surface first since
3531 * the main surface setup depends on it.
3533 if (is_planar_yuv_format(fb->format->format)) {
3534 ret = skl_check_nv12_aux_surface(plane_state);
3537 } else if (is_ccs_modifier(fb->modifier)) {
3538 ret = skl_check_ccs_aux_surface(plane_state);
3542 plane_state->color_plane[1].offset = ~0xfff;
3543 plane_state->color_plane[1].x = 0;
3544 plane_state->color_plane[1].y = 0;
3547 ret = skl_check_main_surface(plane_state);
3555 i9xx_plane_max_stride(struct intel_plane *plane,
3556 u32 pixel_format, u64 modifier,
3557 unsigned int rotation)
3559 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3561 if (!HAS_GMCH(dev_priv)) {
3563 } else if (INTEL_GEN(dev_priv) >= 4) {
3564 if (modifier == I915_FORMAT_MOD_X_TILED)
3568 } else if (INTEL_GEN(dev_priv) >= 3) {
3569 if (modifier == I915_FORMAT_MOD_X_TILED)
3574 if (plane->i9xx_plane == PLANE_C)
3581 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
3583 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3587 if (crtc_state->gamma_enable)
3588 dspcntr |= DISPPLANE_GAMMA_ENABLE;
3590 if (crtc_state->csc_enable)
3591 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3593 if (INTEL_GEN(dev_priv) < 5)
3594 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3599 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3600 const struct intel_plane_state *plane_state)
3602 struct drm_i915_private *dev_priv =
3603 to_i915(plane_state->base.plane->dev);
3604 const struct drm_framebuffer *fb = plane_state->base.fb;
3605 unsigned int rotation = plane_state->base.rotation;
3608 dspcntr = DISPLAY_PLANE_ENABLE;
3610 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
3611 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
3612 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3614 switch (fb->format->format) {
3616 dspcntr |= DISPPLANE_8BPP;
3618 case DRM_FORMAT_XRGB1555:
3619 dspcntr |= DISPPLANE_BGRX555;
3621 case DRM_FORMAT_RGB565:
3622 dspcntr |= DISPPLANE_BGRX565;
3624 case DRM_FORMAT_XRGB8888:
3625 dspcntr |= DISPPLANE_BGRX888;
3627 case DRM_FORMAT_XBGR8888:
3628 dspcntr |= DISPPLANE_RGBX888;
3630 case DRM_FORMAT_XRGB2101010:
3631 dspcntr |= DISPPLANE_BGRX101010;
3633 case DRM_FORMAT_XBGR2101010:
3634 dspcntr |= DISPPLANE_RGBX101010;
3637 MISSING_CASE(fb->format->format);
3641 if (INTEL_GEN(dev_priv) >= 4 &&
3642 fb->modifier == I915_FORMAT_MOD_X_TILED)
3643 dspcntr |= DISPPLANE_TILED;
3645 if (rotation & DRM_MODE_ROTATE_180)
3646 dspcntr |= DISPPLANE_ROTATE_180;
3648 if (rotation & DRM_MODE_REFLECT_X)
3649 dspcntr |= DISPPLANE_MIRROR;
3654 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3656 struct drm_i915_private *dev_priv =
3657 to_i915(plane_state->base.plane->dev);
3662 ret = intel_plane_compute_gtt(plane_state);
3666 if (!plane_state->base.visible)
3669 src_x = plane_state->base.src.x1 >> 16;
3670 src_y = plane_state->base.src.y1 >> 16;
3672 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3674 if (INTEL_GEN(dev_priv) >= 4)
3675 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
3681 * Put the final coordinates back so that the src
3682 * coordinate checks will see the right values.
3684 drm_rect_translate(&plane_state->base.src,
3685 (src_x << 16) - plane_state->base.src.x1,
3686 (src_y << 16) - plane_state->base.src.y1);
3688 /* HSW/BDW do this automagically in hardware */
3689 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3690 unsigned int rotation = plane_state->base.rotation;
3691 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3692 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3694 if (rotation & DRM_MODE_ROTATE_180) {
3697 } else if (rotation & DRM_MODE_REFLECT_X) {
3702 plane_state->color_plane[0].offset = offset;
3703 plane_state->color_plane[0].x = src_x;
3704 plane_state->color_plane[0].y = src_y;
3709 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
3711 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3712 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3714 if (IS_CHERRYVIEW(dev_priv))
3715 return i9xx_plane == PLANE_B;
3716 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3718 else if (IS_GEN(dev_priv, 4))
3719 return i9xx_plane == PLANE_C;
3721 return i9xx_plane == PLANE_B ||
3722 i9xx_plane == PLANE_C;
3726 i9xx_plane_check(struct intel_crtc_state *crtc_state,
3727 struct intel_plane_state *plane_state)
3729 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3732 ret = chv_plane_check_rotation(plane_state);
3736 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
3738 DRM_PLANE_HELPER_NO_SCALING,
3739 DRM_PLANE_HELPER_NO_SCALING,
3740 i9xx_plane_has_windowing(plane),
3745 ret = i9xx_check_plane_surface(plane_state);
3749 if (!plane_state->base.visible)
3752 ret = intel_plane_check_src_coordinates(plane_state);
3756 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
3761 static void i9xx_update_plane(struct intel_plane *plane,
3762 const struct intel_crtc_state *crtc_state,
3763 const struct intel_plane_state *plane_state)
3765 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3766 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3768 int x = plane_state->color_plane[0].x;
3769 int y = plane_state->color_plane[0].y;
3770 int crtc_x = plane_state->base.dst.x1;
3771 int crtc_y = plane_state->base.dst.y1;
3772 int crtc_w = drm_rect_width(&plane_state->base.dst);
3773 int crtc_h = drm_rect_height(&plane_state->base.dst);
3774 unsigned long irqflags;
3778 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
3780 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3782 if (INTEL_GEN(dev_priv) >= 4)
3783 dspaddr_offset = plane_state->color_plane[0].offset;
3785 dspaddr_offset = linear_offset;
3787 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3789 I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3791 if (INTEL_GEN(dev_priv) < 4) {
3793 * PLANE_A doesn't actually have a full window
3794 * generator but let's assume we still need to
3795 * program whatever is there.
3797 I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3798 I915_WRITE_FW(DSPSIZE(i9xx_plane),
3799 ((crtc_h - 1) << 16) | (crtc_w - 1));
3800 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3801 I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
3802 I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3803 ((crtc_h - 1) << 16) | (crtc_w - 1));
3804 I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3807 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3808 I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
3809 } else if (INTEL_GEN(dev_priv) >= 4) {
3810 I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset);
3811 I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x);
3815 * The control register self-arms if the plane was previously
3816 * disabled. Try to make the plane enable atomic by writing
3817 * the control register just before the surface register.
3819 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3820 if (INTEL_GEN(dev_priv) >= 4)
3821 I915_WRITE_FW(DSPSURF(i9xx_plane),
3822 intel_plane_ggtt_offset(plane_state) +
3825 I915_WRITE_FW(DSPADDR(i9xx_plane),
3826 intel_plane_ggtt_offset(plane_state) +
3829 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3832 static void i9xx_disable_plane(struct intel_plane *plane,
3833 const struct intel_crtc_state *crtc_state)
3835 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3836 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3837 unsigned long irqflags;
3841 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
3842 * enable on ilk+ affect the pipe bottom color as
3843 * well, so we must configure them even if the plane
3846 * On pre-g4x there is no way to gamma correct the
3847 * pipe bottom color but we'll keep on doing this
3848 * anyway so that the crtc state readout works correctly.
3850 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
3852 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3854 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr);
3855 if (INTEL_GEN(dev_priv) >= 4)
3856 I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
3858 I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
3860 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3863 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
3866 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3867 enum intel_display_power_domain power_domain;
3868 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3869 intel_wakeref_t wakeref;
3874 * Not 100% correct for planes that can move between pipes,
3875 * but that's only the case for gen2-4 which don't have any
3876 * display power wells.
3878 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
3879 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3883 val = I915_READ(DSPCNTR(i9xx_plane));
3885 ret = val & DISPLAY_PLANE_ENABLE;
3887 if (INTEL_GEN(dev_priv) >= 5)
3888 *pipe = plane->pipe;
3890 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
3891 DISPPLANE_SEL_PIPE_SHIFT;
3893 intel_display_power_put(dev_priv, power_domain, wakeref);
3898 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3900 struct drm_device *dev = intel_crtc->base.dev;
3901 struct drm_i915_private *dev_priv = to_i915(dev);
3903 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3904 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3905 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3909 * This function detaches (aka. unbinds) unused scalers in hardware
3911 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
3913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3914 const struct intel_crtc_scaler_state *scaler_state =
3915 &crtc_state->scaler_state;
3918 /* loop through and disable scalers that aren't in use */
3919 for (i = 0; i < intel_crtc->num_scalers; i++) {
3920 if (!scaler_state->scalers[i].in_use)
3921 skl_detach_scaler(intel_crtc, i);
3925 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
3926 int color_plane, unsigned int rotation)
3929 * The stride is either expressed as a multiple of 64 bytes chunks for
3930 * linear buffers or in number of tiles for tiled buffers.
3932 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3934 else if (drm_rotation_90_or_270(rotation))
3935 return intel_tile_height(fb, color_plane);
3937 return intel_tile_width_bytes(fb, color_plane);
3940 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
3943 const struct drm_framebuffer *fb = plane_state->base.fb;
3944 unsigned int rotation = plane_state->base.rotation;
3945 u32 stride = plane_state->color_plane[color_plane].stride;
3947 if (color_plane >= fb->format->num_planes)
3950 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
3953 static u32 skl_plane_ctl_format(u32 pixel_format)
3955 switch (pixel_format) {
3957 return PLANE_CTL_FORMAT_INDEXED;
3958 case DRM_FORMAT_RGB565:
3959 return PLANE_CTL_FORMAT_RGB_565;
3960 case DRM_FORMAT_XBGR8888:
3961 case DRM_FORMAT_ABGR8888:
3962 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3963 case DRM_FORMAT_XRGB8888:
3964 case DRM_FORMAT_ARGB8888:
3965 return PLANE_CTL_FORMAT_XRGB_8888;
3966 case DRM_FORMAT_XBGR2101010:
3967 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
3968 case DRM_FORMAT_XRGB2101010:
3969 return PLANE_CTL_FORMAT_XRGB_2101010;
3970 case DRM_FORMAT_XBGR16161616F:
3971 case DRM_FORMAT_ABGR16161616F:
3972 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
3973 case DRM_FORMAT_XRGB16161616F:
3974 case DRM_FORMAT_ARGB16161616F:
3975 return PLANE_CTL_FORMAT_XRGB_16161616F;
3976 case DRM_FORMAT_YUYV:
3977 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3978 case DRM_FORMAT_YVYU:
3979 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3980 case DRM_FORMAT_UYVY:
3981 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3982 case DRM_FORMAT_VYUY:
3983 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3984 case DRM_FORMAT_NV12:
3985 return PLANE_CTL_FORMAT_NV12;
3986 case DRM_FORMAT_P010:
3987 return PLANE_CTL_FORMAT_P010;
3988 case DRM_FORMAT_P012:
3989 return PLANE_CTL_FORMAT_P012;
3990 case DRM_FORMAT_P016:
3991 return PLANE_CTL_FORMAT_P016;
3992 case DRM_FORMAT_Y210:
3993 return PLANE_CTL_FORMAT_Y210;
3994 case DRM_FORMAT_Y212:
3995 return PLANE_CTL_FORMAT_Y212;
3996 case DRM_FORMAT_Y216:
3997 return PLANE_CTL_FORMAT_Y216;
3998 case DRM_FORMAT_XVYU2101010:
3999 return PLANE_CTL_FORMAT_Y410;
4000 case DRM_FORMAT_XVYU12_16161616:
4001 return PLANE_CTL_FORMAT_Y412;
4002 case DRM_FORMAT_XVYU16161616:
4003 return PLANE_CTL_FORMAT_Y416;
4005 MISSING_CASE(pixel_format);
4011 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4013 if (!plane_state->base.fb->format->has_alpha)
4014 return PLANE_CTL_ALPHA_DISABLE;
4016 switch (plane_state->base.pixel_blend_mode) {
4017 case DRM_MODE_BLEND_PIXEL_NONE:
4018 return PLANE_CTL_ALPHA_DISABLE;
4019 case DRM_MODE_BLEND_PREMULTI:
4020 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4021 case DRM_MODE_BLEND_COVERAGE:
4022 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4024 MISSING_CASE(plane_state->base.pixel_blend_mode);
4025 return PLANE_CTL_ALPHA_DISABLE;
4029 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4031 if (!plane_state->base.fb->format->has_alpha)
4032 return PLANE_COLOR_ALPHA_DISABLE;
4034 switch (plane_state->base.pixel_blend_mode) {
4035 case DRM_MODE_BLEND_PIXEL_NONE:
4036 return PLANE_COLOR_ALPHA_DISABLE;
4037 case DRM_MODE_BLEND_PREMULTI:
4038 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4039 case DRM_MODE_BLEND_COVERAGE:
4040 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4042 MISSING_CASE(plane_state->base.pixel_blend_mode);
4043 return PLANE_COLOR_ALPHA_DISABLE;
4047 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4049 switch (fb_modifier) {
4050 case DRM_FORMAT_MOD_LINEAR:
4052 case I915_FORMAT_MOD_X_TILED:
4053 return PLANE_CTL_TILED_X;
4054 case I915_FORMAT_MOD_Y_TILED:
4055 return PLANE_CTL_TILED_Y;
4056 case I915_FORMAT_MOD_Y_TILED_CCS:
4057 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4058 case I915_FORMAT_MOD_Yf_TILED:
4059 return PLANE_CTL_TILED_YF;
4060 case I915_FORMAT_MOD_Yf_TILED_CCS:
4061 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4063 MISSING_CASE(fb_modifier);
4069 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4072 case DRM_MODE_ROTATE_0:
4075 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4076 * while i915 HW rotation is clockwise, thats why this swapping.
4078 case DRM_MODE_ROTATE_90:
4079 return PLANE_CTL_ROTATE_270;
4080 case DRM_MODE_ROTATE_180:
4081 return PLANE_CTL_ROTATE_180;
4082 case DRM_MODE_ROTATE_270:
4083 return PLANE_CTL_ROTATE_90;
4085 MISSING_CASE(rotate);
4091 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4096 case DRM_MODE_REFLECT_X:
4097 return PLANE_CTL_FLIP_HORIZONTAL;
4098 case DRM_MODE_REFLECT_Y:
4100 MISSING_CASE(reflect);
4106 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4108 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
4111 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4114 if (crtc_state->gamma_enable)
4115 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4117 if (crtc_state->csc_enable)
4118 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4123 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4124 const struct intel_plane_state *plane_state)
4126 struct drm_i915_private *dev_priv =
4127 to_i915(plane_state->base.plane->dev);
4128 const struct drm_framebuffer *fb = plane_state->base.fb;
4129 unsigned int rotation = plane_state->base.rotation;
4130 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4133 plane_ctl = PLANE_CTL_ENABLE;
4135 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4136 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4137 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4139 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
4140 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4142 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4143 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4146 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4147 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4148 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4150 if (INTEL_GEN(dev_priv) >= 10)
4151 plane_ctl |= cnl_plane_ctl_flip(rotation &
4152 DRM_MODE_REFLECT_MASK);
4154 if (key->flags & I915_SET_COLORKEY_DESTINATION)
4155 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4156 else if (key->flags & I915_SET_COLORKEY_SOURCE)
4157 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4162 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4164 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
4165 u32 plane_color_ctl = 0;
4167 if (INTEL_GEN(dev_priv) >= 11)
4168 return plane_color_ctl;
4170 if (crtc_state->gamma_enable)
4171 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4173 if (crtc_state->csc_enable)
4174 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4176 return plane_color_ctl;
4179 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4180 const struct intel_plane_state *plane_state)
4182 struct drm_i915_private *dev_priv =
4183 to_i915(plane_state->base.plane->dev);
4184 const struct drm_framebuffer *fb = plane_state->base.fb;
4185 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
4186 u32 plane_color_ctl = 0;
4188 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4189 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4191 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4192 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
4193 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4195 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4197 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4198 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4199 } else if (fb->format->is_yuv) {
4200 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4203 return plane_color_ctl;
4207 __intel_display_resume(struct drm_device *dev,
4208 struct drm_atomic_state *state,
4209 struct drm_modeset_acquire_ctx *ctx)
4211 struct drm_crtc_state *crtc_state;
4212 struct drm_crtc *crtc;
4215 intel_modeset_setup_hw_state(dev, ctx);
4216 i915_redisable_vga(to_i915(dev));
4222 * We've duplicated the state, pointers to the old state are invalid.
4224 * Don't attempt to use the old state until we commit the duplicated state.
4226 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4228 * Force recalculation even if we restore
4229 * current state. With fast modeset this may not result
4230 * in a modeset when the state is compatible.
4232 crtc_state->mode_changed = true;
4235 /* ignore any reset values/BIOS leftovers in the WM registers */
4236 if (!HAS_GMCH(to_i915(dev)))
4237 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4239 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4241 WARN_ON(ret == -EDEADLK);
4245 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4247 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4248 intel_has_gpu_reset(dev_priv));
4251 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4253 struct drm_device *dev = &dev_priv->drm;
4254 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4255 struct drm_atomic_state *state;
4258 /* reset doesn't touch the display */
4259 if (!i915_modparams.force_reset_modeset_test &&
4260 !gpu_reset_clobbers_display(dev_priv))
4263 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4264 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4265 smp_mb__after_atomic();
4266 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4268 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4269 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4270 intel_gt_set_wedged(&dev_priv->gt);
4274 * Need mode_config.mutex so that we don't
4275 * trample ongoing ->detect() and whatnot.
4277 mutex_lock(&dev->mode_config.mutex);
4278 drm_modeset_acquire_init(ctx, 0);
4280 ret = drm_modeset_lock_all_ctx(dev, ctx);
4281 if (ret != -EDEADLK)
4284 drm_modeset_backoff(ctx);
4287 * Disabling the crtcs gracefully seems nicer. Also the
4288 * g33 docs say we should at least disable all the planes.
4290 state = drm_atomic_helper_duplicate_state(dev, ctx);
4291 if (IS_ERR(state)) {
4292 ret = PTR_ERR(state);
4293 DRM_ERROR("Duplicating state failed with %i\n", ret);
4297 ret = drm_atomic_helper_disable_all(dev, ctx);
4299 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
4300 drm_atomic_state_put(state);
4304 dev_priv->modeset_restore_state = state;
4305 state->acquire_ctx = ctx;
4308 void intel_finish_reset(struct drm_i915_private *dev_priv)
4310 struct drm_device *dev = &dev_priv->drm;
4311 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4312 struct drm_atomic_state *state;
4315 /* reset doesn't touch the display */
4316 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4319 state = fetch_and_zero(&dev_priv->modeset_restore_state);
4323 /* reset doesn't touch the display */
4324 if (!gpu_reset_clobbers_display(dev_priv)) {
4325 /* for testing only restore the display */
4326 ret = __intel_display_resume(dev, state, ctx);
4328 DRM_ERROR("Restoring old state failed with %i\n", ret);
4331 * The display has been reset as well,
4332 * so need a full re-initialization.
4334 intel_pps_unlock_regs_wa(dev_priv);
4335 intel_modeset_init_hw(dev);
4336 intel_init_clock_gating(dev_priv);
4338 spin_lock_irq(&dev_priv->irq_lock);
4339 if (dev_priv->display.hpd_irq_setup)
4340 dev_priv->display.hpd_irq_setup(dev_priv);
4341 spin_unlock_irq(&dev_priv->irq_lock);
4343 ret = __intel_display_resume(dev, state, ctx);
4345 DRM_ERROR("Restoring old state failed with %i\n", ret);
4347 intel_hpd_init(dev_priv);
4350 drm_atomic_state_put(state);
4352 drm_modeset_drop_locks(ctx);
4353 drm_modeset_acquire_fini(ctx);
4354 mutex_unlock(&dev->mode_config.mutex);
4356 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4359 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4361 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4362 enum pipe pipe = crtc->pipe;
4365 tmp = I915_READ(PIPE_CHICKEN(pipe));
4368 * Display WA #1153: icl
4369 * enable hardware to bypass the alpha math
4370 * and rounding for per-pixel values 00 and 0xff
4372 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4374 * Display WA # 1605353570: icl
4375 * Set the pixel rounding bit to 1 for allowing
4376 * passthrough of Frame buffer pixels unmodified
4379 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4380 I915_WRITE(PIPE_CHICKEN(pipe), tmp);
4383 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
4384 const struct intel_crtc_state *new_crtc_state)
4386 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
4387 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4389 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
4390 crtc->base.mode = new_crtc_state->base.mode;
4393 * Update pipe size and adjust fitter if needed: the reason for this is
4394 * that in compute_mode_changes we check the native mode (not the pfit
4395 * mode) to see if we can flip rather than do a full mode set. In the
4396 * fastboot case, we'll flip, but if we don't update the pipesrc and
4397 * pfit state, we'll end up with a big fb scanned out into the wrong
4401 I915_WRITE(PIPESRC(crtc->pipe),
4402 ((new_crtc_state->pipe_src_w - 1) << 16) |
4403 (new_crtc_state->pipe_src_h - 1));
4405 /* on skylake this is done by detaching scalers */
4406 if (INTEL_GEN(dev_priv) >= 9) {
4407 skl_detach_scalers(new_crtc_state);
4409 if (new_crtc_state->pch_pfit.enabled)
4410 skylake_pfit_enable(new_crtc_state);
4411 } else if (HAS_PCH_SPLIT(dev_priv)) {
4412 if (new_crtc_state->pch_pfit.enabled)
4413 ironlake_pfit_enable(new_crtc_state);
4414 else if (old_crtc_state->pch_pfit.enabled)
4415 ironlake_pfit_disable(old_crtc_state);
4418 if (INTEL_GEN(dev_priv) >= 11)
4419 icl_set_pipe_chicken(crtc);
4422 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4424 struct drm_device *dev = crtc->base.dev;
4425 struct drm_i915_private *dev_priv = to_i915(dev);
4426 enum pipe pipe = crtc->pipe;
4430 /* enable normal train */
4431 reg = FDI_TX_CTL(pipe);
4432 temp = I915_READ(reg);
4433 if (IS_IVYBRIDGE(dev_priv)) {
4434 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4435 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
4437 temp &= ~FDI_LINK_TRAIN_NONE;
4438 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
4440 I915_WRITE(reg, temp);
4442 reg = FDI_RX_CTL(pipe);
4443 temp = I915_READ(reg);
4444 if (HAS_PCH_CPT(dev_priv)) {
4445 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4446 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
4448 temp &= ~FDI_LINK_TRAIN_NONE;
4449 temp |= FDI_LINK_TRAIN_NONE;
4451 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
4453 /* wait one idle pattern time */
4457 /* IVB wants error correction enabled */
4458 if (IS_IVYBRIDGE(dev_priv))
4459 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
4460 FDI_FE_ERRC_ENABLE);
4463 /* The FDI link training functions for ILK/Ibexpeak. */
4464 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
4465 const struct intel_crtc_state *crtc_state)
4467 struct drm_device *dev = crtc->base.dev;
4468 struct drm_i915_private *dev_priv = to_i915(dev);
4469 enum pipe pipe = crtc->pipe;
4473 /* FDI needs bits from pipe first */
4474 assert_pipe_enabled(dev_priv, pipe);
4476 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4478 reg = FDI_RX_IMR(pipe);
4479 temp = I915_READ(reg);
4480 temp &= ~FDI_RX_SYMBOL_LOCK;
4481 temp &= ~FDI_RX_BIT_LOCK;
4482 I915_WRITE(reg, temp);
4486 /* enable CPU FDI TX and PCH FDI RX */
4487 reg = FDI_TX_CTL(pipe);
4488 temp = I915_READ(reg);
4489 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4490 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4491 temp &= ~FDI_LINK_TRAIN_NONE;
4492 temp |= FDI_LINK_TRAIN_PATTERN_1;
4493 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4495 reg = FDI_RX_CTL(pipe);
4496 temp = I915_READ(reg);
4497 temp &= ~FDI_LINK_TRAIN_NONE;
4498 temp |= FDI_LINK_TRAIN_PATTERN_1;
4499 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4504 /* Ironlake workaround, enable clock pointer after FDI enable*/
4505 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4506 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
4507 FDI_RX_PHASE_SYNC_POINTER_EN);
4509 reg = FDI_RX_IIR(pipe);
4510 for (tries = 0; tries < 5; tries++) {
4511 temp = I915_READ(reg);
4512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4514 if ((temp & FDI_RX_BIT_LOCK)) {
4515 DRM_DEBUG_KMS("FDI train 1 done.\n");
4516 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4521 DRM_ERROR("FDI train 1 fail!\n");
4524 reg = FDI_TX_CTL(pipe);
4525 temp = I915_READ(reg);
4526 temp &= ~FDI_LINK_TRAIN_NONE;
4527 temp |= FDI_LINK_TRAIN_PATTERN_2;
4528 I915_WRITE(reg, temp);
4530 reg = FDI_RX_CTL(pipe);
4531 temp = I915_READ(reg);
4532 temp &= ~FDI_LINK_TRAIN_NONE;
4533 temp |= FDI_LINK_TRAIN_PATTERN_2;
4534 I915_WRITE(reg, temp);
4539 reg = FDI_RX_IIR(pipe);
4540 for (tries = 0; tries < 5; tries++) {
4541 temp = I915_READ(reg);
4542 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4544 if (temp & FDI_RX_SYMBOL_LOCK) {
4545 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4546 DRM_DEBUG_KMS("FDI train 2 done.\n");
4551 DRM_ERROR("FDI train 2 fail!\n");
4553 DRM_DEBUG_KMS("FDI train done\n");
4557 static const int snb_b_fdi_train_param[] = {
4558 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
4559 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
4560 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
4561 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
4564 /* The FDI link training functions for SNB/Cougarpoint. */
4565 static void gen6_fdi_link_train(struct intel_crtc *crtc,
4566 const struct intel_crtc_state *crtc_state)
4568 struct drm_device *dev = crtc->base.dev;
4569 struct drm_i915_private *dev_priv = to_i915(dev);
4570 enum pipe pipe = crtc->pipe;
4574 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4576 reg = FDI_RX_IMR(pipe);
4577 temp = I915_READ(reg);
4578 temp &= ~FDI_RX_SYMBOL_LOCK;
4579 temp &= ~FDI_RX_BIT_LOCK;
4580 I915_WRITE(reg, temp);
4585 /* enable CPU FDI TX and PCH FDI RX */
4586 reg = FDI_TX_CTL(pipe);
4587 temp = I915_READ(reg);
4588 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4589 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4590 temp &= ~FDI_LINK_TRAIN_NONE;
4591 temp |= FDI_LINK_TRAIN_PATTERN_1;
4592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4594 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4595 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4597 I915_WRITE(FDI_RX_MISC(pipe),
4598 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4600 reg = FDI_RX_CTL(pipe);
4601 temp = I915_READ(reg);
4602 if (HAS_PCH_CPT(dev_priv)) {
4603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4604 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4606 temp &= ~FDI_LINK_TRAIN_NONE;
4607 temp |= FDI_LINK_TRAIN_PATTERN_1;
4609 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4614 for (i = 0; i < 4; i++) {
4615 reg = FDI_TX_CTL(pipe);
4616 temp = I915_READ(reg);
4617 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4618 temp |= snb_b_fdi_train_param[i];
4619 I915_WRITE(reg, temp);
4624 for (retry = 0; retry < 5; retry++) {
4625 reg = FDI_RX_IIR(pipe);
4626 temp = I915_READ(reg);
4627 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4628 if (temp & FDI_RX_BIT_LOCK) {
4629 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4630 DRM_DEBUG_KMS("FDI train 1 done.\n");
4639 DRM_ERROR("FDI train 1 fail!\n");
4642 reg = FDI_TX_CTL(pipe);
4643 temp = I915_READ(reg);
4644 temp &= ~FDI_LINK_TRAIN_NONE;
4645 temp |= FDI_LINK_TRAIN_PATTERN_2;
4646 if (IS_GEN(dev_priv, 6)) {
4647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4649 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4651 I915_WRITE(reg, temp);
4653 reg = FDI_RX_CTL(pipe);
4654 temp = I915_READ(reg);
4655 if (HAS_PCH_CPT(dev_priv)) {
4656 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4657 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4659 temp &= ~FDI_LINK_TRAIN_NONE;
4660 temp |= FDI_LINK_TRAIN_PATTERN_2;
4662 I915_WRITE(reg, temp);
4667 for (i = 0; i < 4; i++) {
4668 reg = FDI_TX_CTL(pipe);
4669 temp = I915_READ(reg);
4670 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4671 temp |= snb_b_fdi_train_param[i];
4672 I915_WRITE(reg, temp);
4677 for (retry = 0; retry < 5; retry++) {
4678 reg = FDI_RX_IIR(pipe);
4679 temp = I915_READ(reg);
4680 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4681 if (temp & FDI_RX_SYMBOL_LOCK) {
4682 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4683 DRM_DEBUG_KMS("FDI train 2 done.\n");
4692 DRM_ERROR("FDI train 2 fail!\n");
4694 DRM_DEBUG_KMS("FDI train done.\n");
4697 /* Manual link training for Ivy Bridge A0 parts */
4698 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4699 const struct intel_crtc_state *crtc_state)
4701 struct drm_device *dev = crtc->base.dev;
4702 struct drm_i915_private *dev_priv = to_i915(dev);
4703 enum pipe pipe = crtc->pipe;
4707 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4709 reg = FDI_RX_IMR(pipe);
4710 temp = I915_READ(reg);
4711 temp &= ~FDI_RX_SYMBOL_LOCK;
4712 temp &= ~FDI_RX_BIT_LOCK;
4713 I915_WRITE(reg, temp);
4718 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4719 I915_READ(FDI_RX_IIR(pipe)));
4721 /* Try each vswing and preemphasis setting twice before moving on */
4722 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4723 /* disable first in case we need to retry */
4724 reg = FDI_TX_CTL(pipe);
4725 temp = I915_READ(reg);
4726 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4727 temp &= ~FDI_TX_ENABLE;
4728 I915_WRITE(reg, temp);
4730 reg = FDI_RX_CTL(pipe);
4731 temp = I915_READ(reg);
4732 temp &= ~FDI_LINK_TRAIN_AUTO;
4733 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4734 temp &= ~FDI_RX_ENABLE;
4735 I915_WRITE(reg, temp);
4737 /* enable CPU FDI TX and PCH FDI RX */
4738 reg = FDI_TX_CTL(pipe);
4739 temp = I915_READ(reg);
4740 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4741 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4742 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4743 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4744 temp |= snb_b_fdi_train_param[j/2];
4745 temp |= FDI_COMPOSITE_SYNC;
4746 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4748 I915_WRITE(FDI_RX_MISC(pipe),
4749 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4751 reg = FDI_RX_CTL(pipe);
4752 temp = I915_READ(reg);
4753 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4754 temp |= FDI_COMPOSITE_SYNC;
4755 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4758 udelay(1); /* should be 0.5us */
4760 for (i = 0; i < 4; i++) {
4761 reg = FDI_RX_IIR(pipe);
4762 temp = I915_READ(reg);
4763 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4765 if (temp & FDI_RX_BIT_LOCK ||
4766 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4767 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4768 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4772 udelay(1); /* should be 0.5us */
4775 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4780 reg = FDI_TX_CTL(pipe);
4781 temp = I915_READ(reg);
4782 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4783 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4784 I915_WRITE(reg, temp);
4786 reg = FDI_RX_CTL(pipe);
4787 temp = I915_READ(reg);
4788 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4789 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4790 I915_WRITE(reg, temp);
4793 udelay(2); /* should be 1.5us */
4795 for (i = 0; i < 4; i++) {
4796 reg = FDI_RX_IIR(pipe);
4797 temp = I915_READ(reg);
4798 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4800 if (temp & FDI_RX_SYMBOL_LOCK ||
4801 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4802 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4803 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4807 udelay(2); /* should be 1.5us */
4810 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4814 DRM_DEBUG_KMS("FDI train done.\n");
4817 static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
4819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4820 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4821 enum pipe pipe = intel_crtc->pipe;
4825 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4826 reg = FDI_RX_CTL(pipe);
4827 temp = I915_READ(reg);
4828 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4829 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4830 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4831 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4836 /* Switch from Rawclk to PCDclk */
4837 temp = I915_READ(reg);
4838 I915_WRITE(reg, temp | FDI_PCDCLK);
4843 /* Enable CPU FDI TX PLL, always on for Ironlake */
4844 reg = FDI_TX_CTL(pipe);
4845 temp = I915_READ(reg);
4846 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4847 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4854 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4856 struct drm_device *dev = intel_crtc->base.dev;
4857 struct drm_i915_private *dev_priv = to_i915(dev);
4858 enum pipe pipe = intel_crtc->pipe;
4862 /* Switch from PCDclk to Rawclk */
4863 reg = FDI_RX_CTL(pipe);
4864 temp = I915_READ(reg);
4865 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4867 /* Disable CPU FDI TX PLL */
4868 reg = FDI_TX_CTL(pipe);
4869 temp = I915_READ(reg);
4870 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4875 reg = FDI_RX_CTL(pipe);
4876 temp = I915_READ(reg);
4877 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4879 /* Wait for the clocks to turn off. */
4884 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4886 struct drm_device *dev = crtc->dev;
4887 struct drm_i915_private *dev_priv = to_i915(dev);
4888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4889 enum pipe pipe = intel_crtc->pipe;
4893 /* disable CPU FDI tx and PCH FDI rx */
4894 reg = FDI_TX_CTL(pipe);
4895 temp = I915_READ(reg);
4896 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4899 reg = FDI_RX_CTL(pipe);
4900 temp = I915_READ(reg);
4901 temp &= ~(0x7 << 16);
4902 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4903 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4908 /* Ironlake workaround, disable clock pointer after downing FDI */
4909 if (HAS_PCH_IBX(dev_priv))
4910 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4912 /* still set train pattern 1 */
4913 reg = FDI_TX_CTL(pipe);
4914 temp = I915_READ(reg);
4915 temp &= ~FDI_LINK_TRAIN_NONE;
4916 temp |= FDI_LINK_TRAIN_PATTERN_1;
4917 I915_WRITE(reg, temp);
4919 reg = FDI_RX_CTL(pipe);
4920 temp = I915_READ(reg);
4921 if (HAS_PCH_CPT(dev_priv)) {
4922 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4923 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4925 temp &= ~FDI_LINK_TRAIN_NONE;
4926 temp |= FDI_LINK_TRAIN_PATTERN_1;
4928 /* BPC in FDI rx is consistent with that in PIPECONF */
4929 temp &= ~(0x07 << 16);
4930 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4931 I915_WRITE(reg, temp);
4937 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4939 struct drm_crtc *crtc;
4942 drm_for_each_crtc(crtc, &dev_priv->drm) {
4943 struct drm_crtc_commit *commit;
4944 spin_lock(&crtc->commit_lock);
4945 commit = list_first_entry_or_null(&crtc->commit_list,
4946 struct drm_crtc_commit, commit_entry);
4947 cleanup_done = commit ?
4948 try_wait_for_completion(&commit->cleanup_done) : true;
4949 spin_unlock(&crtc->commit_lock);
4954 drm_crtc_wait_one_vblank(crtc);
4962 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4966 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4968 mutex_lock(&dev_priv->sb_lock);
4970 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4971 temp |= SBI_SSCCTL_DISABLE;
4972 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4974 mutex_unlock(&dev_priv->sb_lock);
4977 /* Program iCLKIP clock to the desired frequency */
4978 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
4980 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4981 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4982 int clock = crtc_state->base.adjusted_mode.crtc_clock;
4983 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4986 lpt_disable_iclkip(dev_priv);
4988 /* The iCLK virtual clock root frequency is in MHz,
4989 * but the adjusted_mode->crtc_clock in in KHz. To get the
4990 * divisors, it is necessary to divide one by another, so we
4991 * convert the virtual clock precision to KHz here for higher
4994 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4995 u32 iclk_virtual_root_freq = 172800 * 1000;
4996 u32 iclk_pi_range = 64;
4997 u32 desired_divisor;
4999 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5001 divsel = (desired_divisor / iclk_pi_range) - 2;
5002 phaseinc = desired_divisor % iclk_pi_range;
5005 * Near 20MHz is a corner case which is
5006 * out of range for the 7-bit divisor
5012 /* This should not happen with any sane values */
5013 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5014 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5015 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
5016 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5018 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5025 mutex_lock(&dev_priv->sb_lock);
5027 /* Program SSCDIVINTPHASE6 */
5028 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5029 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5030 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5031 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5032 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5033 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5034 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5035 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5037 /* Program SSCAUXDIV */
5038 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5039 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5040 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5041 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5043 /* Enable modulator and associated divider */
5044 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5045 temp &= ~SBI_SSCCTL_DISABLE;
5046 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5048 mutex_unlock(&dev_priv->sb_lock);
5050 /* Wait for initialization time */
5053 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5056 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5058 u32 divsel, phaseinc, auxdiv;
5059 u32 iclk_virtual_root_freq = 172800 * 1000;
5060 u32 iclk_pi_range = 64;
5061 u32 desired_divisor;
5064 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5067 mutex_lock(&dev_priv->sb_lock);
5069 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5070 if (temp & SBI_SSCCTL_DISABLE) {
5071 mutex_unlock(&dev_priv->sb_lock);
5075 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5076 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5077 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5078 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5079 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5081 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5082 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5083 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5085 mutex_unlock(&dev_priv->sb_lock);
5087 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5089 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5090 desired_divisor << auxdiv);
5093 static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5094 enum pipe pch_transcoder)
5096 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5097 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5098 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5100 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
5101 I915_READ(HTOTAL(cpu_transcoder)));
5102 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
5103 I915_READ(HBLANK(cpu_transcoder)));
5104 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
5105 I915_READ(HSYNC(cpu_transcoder)));
5107 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
5108 I915_READ(VTOTAL(cpu_transcoder)));
5109 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
5110 I915_READ(VBLANK(cpu_transcoder)));
5111 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
5112 I915_READ(VSYNC(cpu_transcoder)));
5113 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5114 I915_READ(VSYNCSHIFT(cpu_transcoder)));
5117 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5121 temp = I915_READ(SOUTH_CHICKEN1);
5122 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5125 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5126 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5128 temp &= ~FDI_BC_BIFURCATION_SELECT;
5130 temp |= FDI_BC_BIFURCATION_SELECT;
5132 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
5133 I915_WRITE(SOUTH_CHICKEN1, temp);
5134 POSTING_READ(SOUTH_CHICKEN1);
5137 static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5139 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5140 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5142 switch (crtc->pipe) {
5146 if (crtc_state->fdi_lanes > 2)
5147 cpt_set_fdi_bc_bifurcation(dev_priv, false);
5149 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5153 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5162 * Finds the encoder associated with the given CRTC. This can only be
5163 * used when we know that the CRTC isn't feeding multiple encoders!
5165 static struct intel_encoder *
5166 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5167 const struct intel_crtc_state *crtc_state)
5169 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5170 const struct drm_connector_state *connector_state;
5171 const struct drm_connector *connector;
5172 struct intel_encoder *encoder = NULL;
5173 int num_encoders = 0;
5176 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5177 if (connector_state->crtc != &crtc->base)
5180 encoder = to_intel_encoder(connector_state->best_encoder);
5184 WARN(num_encoders != 1, "%d encoders for pipe %c\n",
5185 num_encoders, pipe_name(crtc->pipe));
5191 * Enable PCH resources required for PCH ports:
5193 * - FDI training & RX/TX
5194 * - update transcoder timings
5195 * - DP transcoding bits
5198 static void ironlake_pch_enable(const struct intel_atomic_state *state,
5199 const struct intel_crtc_state *crtc_state)
5201 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5202 struct drm_device *dev = crtc->base.dev;
5203 struct drm_i915_private *dev_priv = to_i915(dev);
5204 enum pipe pipe = crtc->pipe;
5207 assert_pch_transcoder_disabled(dev_priv, pipe);
5209 if (IS_IVYBRIDGE(dev_priv))
5210 ivybridge_update_fdi_bc_bifurcation(crtc_state);
5212 /* Write the TU size bits before fdi link training, so that error
5213 * detection works. */
5214 I915_WRITE(FDI_RX_TUSIZE1(pipe),
5215 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5217 /* For PCH output, training FDI link */
5218 dev_priv->display.fdi_link_train(crtc, crtc_state);
5220 /* We need to program the right clock selection before writing the pixel
5221 * mutliplier into the DPLL. */
5222 if (HAS_PCH_CPT(dev_priv)) {
5225 temp = I915_READ(PCH_DPLL_SEL);
5226 temp |= TRANS_DPLL_ENABLE(pipe);
5227 sel = TRANS_DPLLB_SEL(pipe);
5228 if (crtc_state->shared_dpll ==
5229 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5233 I915_WRITE(PCH_DPLL_SEL, temp);
5236 /* XXX: pch pll's can be enabled any time before we enable the PCH
5237 * transcoder, and we actually should do this to not upset any PCH
5238 * transcoder that already use the clock when we share it.
5240 * Note that enable_shared_dpll tries to do the right thing, but
5241 * get_shared_dpll unconditionally resets the pll - we need that to have
5242 * the right LVDS enable sequence. */
5243 intel_enable_shared_dpll(crtc_state);
5245 /* set transcoder timing, panel must allow it */
5246 assert_panel_unlocked(dev_priv, pipe);
5247 ironlake_pch_transcoder_set_timings(crtc_state, pipe);
5249 intel_fdi_normal_train(crtc);
5251 /* For PCH DP, enable TRANS_DP_CTL */
5252 if (HAS_PCH_CPT(dev_priv) &&
5253 intel_crtc_has_dp_encoder(crtc_state)) {
5254 const struct drm_display_mode *adjusted_mode =
5255 &crtc_state->base.adjusted_mode;
5256 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5257 i915_reg_t reg = TRANS_DP_CTL(pipe);
5260 temp = I915_READ(reg);
5261 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5262 TRANS_DP_SYNC_MASK |
5264 temp |= TRANS_DP_OUTPUT_ENABLE;
5265 temp |= bpc << 9; /* same format but at 11:9 */
5267 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5268 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5269 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5270 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5272 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5273 WARN_ON(port < PORT_B || port > PORT_D);
5274 temp |= TRANS_DP_PORT_SEL(port);
5276 I915_WRITE(reg, temp);
5279 ironlake_enable_pch_transcoder(crtc_state);
5282 static void lpt_pch_enable(const struct intel_atomic_state *state,
5283 const struct intel_crtc_state *crtc_state)
5285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5287 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5289 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5291 lpt_program_iclkip(crtc_state);
5293 /* Set transcoder timing. */
5294 ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A);
5296 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5299 static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
5301 struct drm_i915_private *dev_priv = to_i915(dev);
5302 i915_reg_t dslreg = PIPEDSL(pipe);
5305 temp = I915_READ(dslreg);
5307 if (wait_for(I915_READ(dslreg) != temp, 5)) {
5308 if (wait_for(I915_READ(dslreg) != temp, 5))
5309 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
5314 * The hardware phase 0.0 refers to the center of the pixel.
5315 * We want to start from the top/left edge which is phase
5316 * -0.5. That matches how the hardware calculates the scaling
5317 * factors (from top-left of the first pixel to bottom-right
5318 * of the last pixel, as opposed to the pixel centers).
5320 * For 4:2:0 subsampled chroma planes we obviously have to
5321 * adjust that so that the chroma sample position lands in
5324 * Note that for packed YCbCr 4:2:2 formats there is no way to
5325 * control chroma siting. The hardware simply replicates the
5326 * chroma samples for both of the luma samples, and thus we don't
5327 * actually get the expected MPEG2 chroma siting convention :(
5328 * The same behaviour is observed on pre-SKL platforms as well.
5330 * Theory behind the formula (note that we ignore sub-pixel
5331 * source coordinates):
5332 * s = source sample position
5333 * d = destination sample position
5338 * | | 1.5 (initial phase)
5346 * | -0.375 (initial phase)
5353 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5355 int phase = -0x8000;
5359 phase += (sub - 1) * 0x8000 / sub;
5361 phase += scale / (2 * sub);
5364 * Hardware initial phase limited to [-0.5:1.5].
5365 * Since the max hardware scale factor is 3.0, we
5366 * should never actually excdeed 1.0 here.
5368 WARN_ON(phase < -0x8000 || phase > 0x18000);
5371 phase = 0x10000 + phase;
5373 trip = PS_PHASE_TRIP;
5375 return ((phase >> 2) & PS_PHASE_MASK) | trip;
5378 #define SKL_MIN_SRC_W 8
5379 #define SKL_MAX_SRC_W 4096
5380 #define SKL_MIN_SRC_H 8
5381 #define SKL_MAX_SRC_H 4096
5382 #define SKL_MIN_DST_W 8
5383 #define SKL_MAX_DST_W 4096
5384 #define SKL_MIN_DST_H 8
5385 #define SKL_MAX_DST_H 4096
5386 #define ICL_MAX_SRC_W 5120
5387 #define ICL_MAX_SRC_H 4096
5388 #define ICL_MAX_DST_W 5120
5389 #define ICL_MAX_DST_H 4096
5390 #define SKL_MIN_YUV_420_SRC_W 16
5391 #define SKL_MIN_YUV_420_SRC_H 16
5394 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5395 unsigned int scaler_user, int *scaler_id,
5396 int src_w, int src_h, int dst_w, int dst_h,
5397 const struct drm_format_info *format, bool need_scaler)
5399 struct intel_crtc_scaler_state *scaler_state =
5400 &crtc_state->scaler_state;
5401 struct intel_crtc *intel_crtc =
5402 to_intel_crtc(crtc_state->base.crtc);
5403 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5404 const struct drm_display_mode *adjusted_mode =
5405 &crtc_state->base.adjusted_mode;
5408 * Src coordinates are already rotated by 270 degrees for
5409 * the 90/270 degree plane rotation cases (to match the
5410 * GTT mapping), hence no need to account for rotation here.
5412 if (src_w != dst_w || src_h != dst_h)
5416 * Scaling/fitting not supported in IF-ID mode in GEN9+
5417 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
5418 * Once NV12 is enabled, handle it here while allocating scaler
5421 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
5422 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5423 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
5428 * if plane is being disabled or scaler is no more required or force detach
5429 * - free scaler binded to this plane/crtc
5430 * - in order to do this, update crtc->scaler_usage
5432 * Here scaler state in crtc_state is set free so that
5433 * scaler can be assigned to other user. Actual register
5434 * update to free the scaler is done in plane/panel-fit programming.
5435 * For this purpose crtc/plane_state->scaler_id isn't reset here.
5437 if (force_detach || !need_scaler) {
5438 if (*scaler_id >= 0) {
5439 scaler_state->scaler_users &= ~(1 << scaler_user);
5440 scaler_state->scalers[*scaler_id].in_use = 0;
5442 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5443 "Staged freeing scaler id %d scaler_users = 0x%x\n",
5444 intel_crtc->pipe, scaler_user, *scaler_id,
5445 scaler_state->scaler_users);
5451 if (format && is_planar_yuv_format(format->format) &&
5452 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
5453 DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
5458 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
5459 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
5460 (INTEL_GEN(dev_priv) >= 11 &&
5461 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
5462 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
5463 (INTEL_GEN(dev_priv) < 11 &&
5464 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
5465 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
5466 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
5467 "size is out of scaler range\n",
5468 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
5472 /* mark this plane as a scaler user in crtc_state */
5473 scaler_state->scaler_users |= (1 << scaler_user);
5474 DRM_DEBUG_KMS("scaler_user index %u.%u: "
5475 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
5476 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
5477 scaler_state->scaler_users);
5483 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
5485 * @state: crtc's scaler state
5488 * 0 - scaler_usage updated successfully
5489 * error - requested scaling cannot be supported or other error condition
5491 int skl_update_scaler_crtc(struct intel_crtc_state *state)
5493 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
5494 bool need_scaler = false;
5496 if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5499 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
5500 &state->scaler_state.scaler_id,
5501 state->pipe_src_w, state->pipe_src_h,
5502 adjusted_mode->crtc_hdisplay,
5503 adjusted_mode->crtc_vdisplay, NULL, need_scaler);
5507 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
5508 * @crtc_state: crtc's scaler state
5509 * @plane_state: atomic plane state to update
5512 * 0 - scaler_usage updated successfully
5513 * error - requested scaling cannot be supported or other error condition
5515 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
5516 struct intel_plane_state *plane_state)
5518 struct intel_plane *intel_plane =
5519 to_intel_plane(plane_state->base.plane);
5520 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
5521 struct drm_framebuffer *fb = plane_state->base.fb;
5523 bool force_detach = !fb || !plane_state->base.visible;
5524 bool need_scaler = false;
5526 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
5527 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
5528 fb && is_planar_yuv_format(fb->format->format))
5531 ret = skl_update_scaler(crtc_state, force_detach,
5532 drm_plane_index(&intel_plane->base),
5533 &plane_state->scaler_id,
5534 drm_rect_width(&plane_state->base.src) >> 16,
5535 drm_rect_height(&plane_state->base.src) >> 16,
5536 drm_rect_width(&plane_state->base.dst),
5537 drm_rect_height(&plane_state->base.dst),
5538 fb ? fb->format : NULL, need_scaler);
5540 if (ret || plane_state->scaler_id < 0)
5543 /* check colorkey */
5544 if (plane_state->ckey.flags) {
5545 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
5546 intel_plane->base.base.id,
5547 intel_plane->base.name);
5551 /* Check src format */
5552 switch (fb->format->format) {
5553 case DRM_FORMAT_RGB565:
5554 case DRM_FORMAT_XBGR8888:
5555 case DRM_FORMAT_XRGB8888:
5556 case DRM_FORMAT_ABGR8888:
5557 case DRM_FORMAT_ARGB8888:
5558 case DRM_FORMAT_XRGB2101010:
5559 case DRM_FORMAT_XBGR2101010:
5560 case DRM_FORMAT_XBGR16161616F:
5561 case DRM_FORMAT_ABGR16161616F:
5562 case DRM_FORMAT_XRGB16161616F:
5563 case DRM_FORMAT_ARGB16161616F:
5564 case DRM_FORMAT_YUYV:
5565 case DRM_FORMAT_YVYU:
5566 case DRM_FORMAT_UYVY:
5567 case DRM_FORMAT_VYUY:
5568 case DRM_FORMAT_NV12:
5569 case DRM_FORMAT_P010:
5570 case DRM_FORMAT_P012:
5571 case DRM_FORMAT_P016:
5572 case DRM_FORMAT_Y210:
5573 case DRM_FORMAT_Y212:
5574 case DRM_FORMAT_Y216:
5575 case DRM_FORMAT_XVYU2101010:
5576 case DRM_FORMAT_XVYU12_16161616:
5577 case DRM_FORMAT_XVYU16161616:
5580 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
5581 intel_plane->base.base.id, intel_plane->base.name,
5582 fb->base.id, fb->format->format);
5589 static void skylake_scaler_disable(struct intel_crtc *crtc)
5593 for (i = 0; i < crtc->num_scalers; i++)
5594 skl_detach_scaler(crtc, i);
5597 static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
5599 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5600 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5601 enum pipe pipe = crtc->pipe;
5602 const struct intel_crtc_scaler_state *scaler_state =
5603 &crtc_state->scaler_state;
5605 if (crtc_state->pch_pfit.enabled) {
5606 u16 uv_rgb_hphase, uv_rgb_vphase;
5607 int pfit_w, pfit_h, hscale, vscale;
5610 if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
5613 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
5614 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
5616 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
5617 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
5619 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
5620 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
5622 id = scaler_state->scaler_id;
5623 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
5624 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
5625 I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
5626 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
5627 I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
5628 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
5629 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
5630 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
5634 static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
5636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5638 enum pipe pipe = crtc->pipe;
5640 if (crtc_state->pch_pfit.enabled) {
5641 /* Force use of hard-coded filter coefficients
5642 * as some pre-programmed values are broken,
5645 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
5646 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
5647 PF_PIPE_SEL_IVB(pipe));
5649 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
5650 I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
5651 I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
5655 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
5657 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5658 struct drm_device *dev = crtc->base.dev;
5659 struct drm_i915_private *dev_priv = to_i915(dev);
5661 if (!crtc_state->ips_enabled)
5665 * We can only enable IPS after we enable a plane and wait for a vblank
5666 * This function is called from post_plane_update, which is run after
5669 WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
5671 if (IS_BROADWELL(dev_priv)) {
5672 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
5673 IPS_ENABLE | IPS_PCODE_CONTROL));
5674 /* Quoting Art Runyan: "its not safe to expect any particular
5675 * value in IPS_CTL bit 31 after enabling IPS through the
5676 * mailbox." Moreover, the mailbox may return a bogus state,
5677 * so we need to just enable it and continue on.
5680 I915_WRITE(IPS_CTL, IPS_ENABLE);
5681 /* The bit only becomes 1 in the next vblank, so this wait here
5682 * is essentially intel_wait_for_vblank. If we don't have this
5683 * and don't wait for vblanks until the end of crtc_enable, then
5684 * the HW state readout code will complain that the expected
5685 * IPS_CTL value is not the one we read. */
5686 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
5687 DRM_ERROR("Timed out waiting for IPS enable\n");
5691 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
5693 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5694 struct drm_device *dev = crtc->base.dev;
5695 struct drm_i915_private *dev_priv = to_i915(dev);
5697 if (!crtc_state->ips_enabled)
5700 if (IS_BROADWELL(dev_priv)) {
5701 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
5703 * Wait for PCODE to finish disabling IPS. The BSpec specified
5704 * 42ms timeout value leads to occasional timeouts so use 100ms
5707 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
5708 DRM_ERROR("Timed out waiting for IPS disable\n");
5710 I915_WRITE(IPS_CTL, 0);
5711 POSTING_READ(IPS_CTL);
5714 /* We need to wait for a vblank before we can disable the plane. */
5715 intel_wait_for_vblank(dev_priv, crtc->pipe);
5718 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5720 if (intel_crtc->overlay) {
5721 struct drm_device *dev = intel_crtc->base.dev;
5723 mutex_lock(&dev->struct_mutex);
5724 (void) intel_overlay_switch_off(intel_crtc->overlay);
5725 mutex_unlock(&dev->struct_mutex);
5728 /* Let userspace switch the overlay on again. In most cases userspace
5729 * has to recompute where to put it anyway.
5734 * intel_post_enable_primary - Perform operations after enabling primary plane
5735 * @crtc: the CRTC whose primary plane was just enabled
5736 * @new_crtc_state: the enabling state
5738 * Performs potentially sleeping operations that must be done after the primary
5739 * plane is enabled, such as updating FBC and IPS. Note that this may be
5740 * called due to an explicit primary plane update, or due to an implicit
5741 * re-enable that is caused when a sprite plane is updated to no longer
5742 * completely hide the primary plane.
5745 intel_post_enable_primary(struct drm_crtc *crtc,
5746 const struct intel_crtc_state *new_crtc_state)
5748 struct drm_device *dev = crtc->dev;
5749 struct drm_i915_private *dev_priv = to_i915(dev);
5750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5751 enum pipe pipe = intel_crtc->pipe;
5754 * Gen2 reports pipe underruns whenever all planes are disabled.
5755 * So don't enable underrun reporting before at least some planes
5757 * FIXME: Need to fix the logic to work when we turn off all planes
5758 * but leave the pipe running.
5760 if (IS_GEN(dev_priv, 2))
5761 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5763 /* Underruns don't always raise interrupts, so check manually. */
5764 intel_check_cpu_fifo_underruns(dev_priv);
5765 intel_check_pch_fifo_underruns(dev_priv);
5768 /* FIXME get rid of this and use pre_plane_update */
5770 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5772 struct drm_device *dev = crtc->dev;
5773 struct drm_i915_private *dev_priv = to_i915(dev);
5774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5775 enum pipe pipe = intel_crtc->pipe;
5778 * Gen2 reports pipe underruns whenever all planes are disabled.
5779 * So disable underrun reporting before all the planes get disabled.
5781 if (IS_GEN(dev_priv, 2))
5782 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5784 hsw_disable_ips(to_intel_crtc_state(crtc->state));
5787 * Vblank time updates from the shadow to live plane control register
5788 * are blocked if the memory self-refresh mode is active at that
5789 * moment. So to make sure the plane gets truly disabled, disable
5790 * first the self-refresh mode. The self-refresh enable bit in turn
5791 * will be checked/applied by the HW only at the next frame start
5792 * event which is after the vblank start event, so we need to have a
5793 * wait-for-vblank between disabling the plane and the pipe.
5795 if (HAS_GMCH(dev_priv) &&
5796 intel_set_memory_cxsr(dev_priv, false))
5797 intel_wait_for_vblank(dev_priv, pipe);
5800 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
5801 const struct intel_crtc_state *new_crtc_state)
5803 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5804 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5806 if (!old_crtc_state->ips_enabled)
5809 if (needs_modeset(new_crtc_state))
5813 * Workaround : Do not read or write the pipe palette/gamma data while
5814 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5816 * Disable IPS before we program the LUT.
5818 if (IS_HASWELL(dev_priv) &&
5819 (new_crtc_state->base.color_mgmt_changed ||
5820 new_crtc_state->update_pipe) &&
5821 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5824 return !new_crtc_state->ips_enabled;
5827 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
5828 const struct intel_crtc_state *new_crtc_state)
5830 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5833 if (!new_crtc_state->ips_enabled)
5836 if (needs_modeset(new_crtc_state))
5840 * Workaround : Do not read or write the pipe palette/gamma data while
5841 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
5843 * Re-enable IPS after the LUT has been programmed.
5845 if (IS_HASWELL(dev_priv) &&
5846 (new_crtc_state->base.color_mgmt_changed ||
5847 new_crtc_state->update_pipe) &&
5848 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
5852 * We can't read out IPS on broadwell, assume the worst and
5853 * forcibly enable IPS on the first fastset.
5855 if (new_crtc_state->update_pipe &&
5856 old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
5859 return !old_crtc_state->ips_enabled;
5862 static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
5863 const struct intel_crtc_state *crtc_state)
5865 if (!crtc_state->nv12_planes)
5868 /* WA Display #0827: Gen9:all */
5869 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
5875 static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
5876 const struct intel_crtc_state *crtc_state)
5878 /* Wa_2006604312:icl */
5879 if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
5885 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5887 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5888 struct drm_device *dev = crtc->base.dev;
5889 struct drm_i915_private *dev_priv = to_i915(dev);
5890 struct drm_atomic_state *state = old_crtc_state->base.state;
5891 struct intel_crtc_state *pipe_config =
5892 intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
5894 struct drm_plane *primary = crtc->base.primary;
5895 struct drm_plane_state *old_primary_state =
5896 drm_atomic_get_old_plane_state(state, primary);
5898 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5900 if (pipe_config->update_wm_post && pipe_config->base.active)
5901 intel_update_watermarks(crtc);
5903 if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
5904 hsw_enable_ips(pipe_config);
5906 if (old_primary_state) {
5907 struct drm_plane_state *new_primary_state =
5908 drm_atomic_get_new_plane_state(state, primary);
5910 intel_fbc_post_update(crtc);
5912 if (new_primary_state->visible &&
5913 (needs_modeset(pipe_config) ||
5914 !old_primary_state->visible))
5915 intel_post_enable_primary(&crtc->base, pipe_config);
5918 if (needs_nv12_wa(dev_priv, old_crtc_state) &&
5919 !needs_nv12_wa(dev_priv, pipe_config))
5920 skl_wa_827(dev_priv, crtc->pipe, false);
5922 if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
5923 !needs_scalerclk_wa(dev_priv, pipe_config))
5924 icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
5927 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5928 struct intel_crtc_state *pipe_config)
5930 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5931 struct drm_device *dev = crtc->base.dev;
5932 struct drm_i915_private *dev_priv = to_i915(dev);
5933 struct drm_atomic_state *state = old_crtc_state->base.state;
5934 struct drm_plane *primary = crtc->base.primary;
5935 struct drm_plane_state *old_primary_state =
5936 drm_atomic_get_old_plane_state(state, primary);
5937 bool modeset = needs_modeset(pipe_config);
5938 struct intel_atomic_state *intel_state =
5939 to_intel_atomic_state(state);
5941 if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5942 hsw_disable_ips(old_crtc_state);
5944 if (old_primary_state) {
5945 struct intel_plane_state *new_primary_state =
5946 intel_atomic_get_new_plane_state(intel_state,
5947 to_intel_plane(primary));
5949 intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
5951 * Gen2 reports pipe underruns whenever all planes are disabled.
5952 * So disable underrun reporting before all the planes get disabled.
5954 if (IS_GEN(dev_priv, 2) && old_primary_state->visible &&
5955 (modeset || !new_primary_state->base.visible))
5956 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5959 /* Display WA 827 */
5960 if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
5961 needs_nv12_wa(dev_priv, pipe_config))
5962 skl_wa_827(dev_priv, crtc->pipe, true);
5964 /* Wa_2006604312:icl */
5965 if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
5966 needs_scalerclk_wa(dev_priv, pipe_config))
5967 icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
5970 * Vblank time updates from the shadow to live plane control register
5971 * are blocked if the memory self-refresh mode is active at that
5972 * moment. So to make sure the plane gets truly disabled, disable
5973 * first the self-refresh mode. The self-refresh enable bit in turn
5974 * will be checked/applied by the HW only at the next frame start
5975 * event which is after the vblank start event, so we need to have a
5976 * wait-for-vblank between disabling the plane and the pipe.
5978 if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
5979 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5980 intel_wait_for_vblank(dev_priv, crtc->pipe);
5983 * IVB workaround: must disable low power watermarks for at least
5984 * one frame before enabling scaling. LP watermarks can be re-enabled
5985 * when scaling is disabled.
5987 * WaCxSRDisabledForSpriteScaling:ivb
5989 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
5990 old_crtc_state->base.active)
5991 intel_wait_for_vblank(dev_priv, crtc->pipe);
5994 * If we're doing a modeset, we're done. No need to do any pre-vblank
5995 * watermark programming here.
5997 if (needs_modeset(pipe_config))
6001 * For platforms that support atomic watermarks, program the
6002 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
6003 * will be the intermediate values that are safe for both pre- and
6004 * post- vblank; when vblank happens, the 'active' values will be set
6005 * to the final 'target' values and we'll do this again to get the
6006 * optimal watermarks. For gen9+ platforms, the values we program here
6007 * will be the final target values which will get automatically latched
6008 * at vblank time; no further programming will be necessary.
6010 * If a platform hasn't been transitioned to atomic watermarks yet,
6011 * we'll continue to update watermarks the old way, if flags tell
6014 if (dev_priv->display.initial_watermarks != NULL)
6015 dev_priv->display.initial_watermarks(intel_state,
6017 else if (pipe_config->update_wm_pre)
6018 intel_update_watermarks(crtc);
6021 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6022 struct intel_crtc *crtc)
6024 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6025 const struct intel_crtc_state *new_crtc_state =
6026 intel_atomic_get_new_crtc_state(state, crtc);
6027 unsigned int update_mask = new_crtc_state->update_planes;
6028 const struct intel_plane_state *old_plane_state;
6029 struct intel_plane *plane;
6030 unsigned fb_bits = 0;
6033 intel_crtc_dpms_overlay_disable(crtc);
6035 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6036 if (crtc->pipe != plane->pipe ||
6037 !(update_mask & BIT(plane->id)))
6040 intel_disable_plane(plane, new_crtc_state);
6042 if (old_plane_state->base.visible)
6043 fb_bits |= plane->frontbuffer_bit;
6046 intel_frontbuffer_flip(dev_priv, fb_bits);
6050 * intel_connector_primary_encoder - get the primary encoder for a connector
6051 * @connector: connector for which to return the encoder
6053 * Returns the primary encoder for a connector. There is a 1:1 mapping from
6054 * all connectors to their encoder, except for DP-MST connectors which have
6055 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6056 * pointed to by as many DP-MST connectors as there are pipes.
6058 static struct intel_encoder *
6059 intel_connector_primary_encoder(struct intel_connector *connector)
6061 struct intel_encoder *encoder;
6063 if (connector->mst_port)
6064 return &dp_to_dig_port(connector->mst_port)->base;
6066 encoder = intel_attached_encoder(&connector->base);
6073 intel_connector_needs_modeset(struct intel_atomic_state *state,
6074 const struct drm_connector_state *old_conn_state,
6075 const struct drm_connector_state *new_conn_state)
6077 struct intel_crtc *old_crtc = old_conn_state->crtc ?
6078 to_intel_crtc(old_conn_state->crtc) : NULL;
6079 struct intel_crtc *new_crtc = new_conn_state->crtc ?
6080 to_intel_crtc(new_conn_state->crtc) : NULL;
6082 return new_crtc != old_crtc ||
6084 needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
6087 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6089 struct drm_connector_state *old_conn_state;
6090 struct drm_connector_state *new_conn_state;
6091 struct drm_connector *conn;
6094 for_each_oldnew_connector_in_state(&state->base, conn,
6095 old_conn_state, new_conn_state, i) {
6096 struct intel_encoder *encoder;
6097 struct intel_crtc *crtc;
6099 if (!intel_connector_needs_modeset(state,
6104 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6105 if (!encoder->update_prepare)
6108 crtc = new_conn_state->crtc ?
6109 to_intel_crtc(new_conn_state->crtc) : NULL;
6110 encoder->update_prepare(state, encoder, crtc);
6114 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6116 struct drm_connector_state *old_conn_state;
6117 struct drm_connector_state *new_conn_state;
6118 struct drm_connector *conn;
6121 for_each_oldnew_connector_in_state(&state->base, conn,
6122 old_conn_state, new_conn_state, i) {
6123 struct intel_encoder *encoder;
6124 struct intel_crtc *crtc;
6126 if (!intel_connector_needs_modeset(state,
6131 encoder = intel_connector_primary_encoder(to_intel_connector(conn));
6132 if (!encoder->update_complete)
6135 crtc = new_conn_state->crtc ?
6136 to_intel_crtc(new_conn_state->crtc) : NULL;
6137 encoder->update_complete(state, encoder, crtc);
6141 static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
6142 struct intel_crtc_state *crtc_state,
6143 struct intel_atomic_state *state)
6145 struct drm_connector_state *conn_state;
6146 struct drm_connector *conn;
6149 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6150 struct intel_encoder *encoder =
6151 to_intel_encoder(conn_state->best_encoder);
6153 if (conn_state->crtc != &crtc->base)
6156 if (encoder->pre_pll_enable)
6157 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6161 static void intel_encoders_pre_enable(struct intel_crtc *crtc,
6162 struct intel_crtc_state *crtc_state,
6163 struct intel_atomic_state *state)
6165 struct drm_connector_state *conn_state;
6166 struct drm_connector *conn;
6169 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6170 struct intel_encoder *encoder =
6171 to_intel_encoder(conn_state->best_encoder);
6173 if (conn_state->crtc != &crtc->base)
6176 if (encoder->pre_enable)
6177 encoder->pre_enable(encoder, crtc_state, conn_state);
6181 static void intel_encoders_enable(struct intel_crtc *crtc,
6182 struct intel_crtc_state *crtc_state,
6183 struct intel_atomic_state *state)
6185 struct drm_connector_state *conn_state;
6186 struct drm_connector *conn;
6189 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6190 struct intel_encoder *encoder =
6191 to_intel_encoder(conn_state->best_encoder);
6193 if (conn_state->crtc != &crtc->base)
6196 if (encoder->enable)
6197 encoder->enable(encoder, crtc_state, conn_state);
6198 intel_opregion_notify_encoder(encoder, true);
6202 static void intel_encoders_disable(struct intel_crtc *crtc,
6203 struct intel_crtc_state *old_crtc_state,
6204 struct intel_atomic_state *state)
6206 struct drm_connector_state *old_conn_state;
6207 struct drm_connector *conn;
6210 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6211 struct intel_encoder *encoder =
6212 to_intel_encoder(old_conn_state->best_encoder);
6214 if (old_conn_state->crtc != &crtc->base)
6217 intel_opregion_notify_encoder(encoder, false);
6218 if (encoder->disable)
6219 encoder->disable(encoder, old_crtc_state, old_conn_state);
6223 static void intel_encoders_post_disable(struct intel_crtc *crtc,
6224 struct intel_crtc_state *old_crtc_state,
6225 struct intel_atomic_state *state)
6227 struct drm_connector_state *old_conn_state;
6228 struct drm_connector *conn;
6231 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6232 struct intel_encoder *encoder =
6233 to_intel_encoder(old_conn_state->best_encoder);
6235 if (old_conn_state->crtc != &crtc->base)
6238 if (encoder->post_disable)
6239 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6243 static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
6244 struct intel_crtc_state *old_crtc_state,
6245 struct intel_atomic_state *state)
6247 struct drm_connector_state *old_conn_state;
6248 struct drm_connector *conn;
6251 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6252 struct intel_encoder *encoder =
6253 to_intel_encoder(old_conn_state->best_encoder);
6255 if (old_conn_state->crtc != &crtc->base)
6258 if (encoder->post_pll_disable)
6259 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6263 static void intel_encoders_update_pipe(struct intel_crtc *crtc,
6264 struct intel_crtc_state *crtc_state,
6265 struct intel_atomic_state *state)
6267 struct drm_connector_state *conn_state;
6268 struct drm_connector *conn;
6271 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6272 struct intel_encoder *encoder =
6273 to_intel_encoder(conn_state->best_encoder);
6275 if (conn_state->crtc != &crtc->base)
6278 if (encoder->update_pipe)
6279 encoder->update_pipe(encoder, crtc_state, conn_state);
6283 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6286 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6288 plane->disable_plane(plane, crtc_state);
6291 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
6292 struct intel_atomic_state *state)
6294 struct drm_crtc *crtc = pipe_config->base.crtc;
6295 struct drm_device *dev = crtc->dev;
6296 struct drm_i915_private *dev_priv = to_i915(dev);
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298 enum pipe pipe = intel_crtc->pipe;
6300 if (WARN_ON(intel_crtc->active))
6304 * Sometimes spurious CPU pipe underruns happen during FDI
6305 * training, at least with VGA+HDMI cloning. Suppress them.
6307 * On ILK we get an occasional spurious CPU pipe underruns
6308 * between eDP port A enable and vdd enable. Also PCH port
6309 * enable seems to result in the occasional CPU pipe underrun.
6311 * Spurious PCH underruns also occur during PCH enabling.
6313 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6314 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6316 if (pipe_config->has_pch_encoder)
6317 intel_prepare_shared_dpll(pipe_config);
6319 if (intel_crtc_has_dp_encoder(pipe_config))
6320 intel_dp_set_m_n(pipe_config, M1_N1);
6322 intel_set_pipe_timings(pipe_config);
6323 intel_set_pipe_src_size(pipe_config);
6325 if (pipe_config->has_pch_encoder) {
6326 intel_cpu_transcoder_set_m_n(pipe_config,
6327 &pipe_config->fdi_m_n, NULL);
6330 ironlake_set_pipeconf(pipe_config);
6332 intel_crtc->active = true;
6334 intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6336 if (pipe_config->has_pch_encoder) {
6337 /* Note: FDI PLL enabling _must_ be done before we enable the
6338 * cpu pipes, hence this is separate from all the other fdi/pch
6340 ironlake_fdi_pll_enable(pipe_config);
6342 assert_fdi_tx_disabled(dev_priv, pipe);
6343 assert_fdi_rx_disabled(dev_priv, pipe);
6346 ironlake_pfit_enable(pipe_config);
6349 * On ILK+ LUT must be loaded before the pipe is running but with
6352 intel_color_load_luts(pipe_config);
6353 intel_color_commit(pipe_config);
6354 /* update DSPCNTR to configure gamma for pipe bottom color */
6355 intel_disable_primary_plane(pipe_config);
6357 if (dev_priv->display.initial_watermarks != NULL)
6358 dev_priv->display.initial_watermarks(state, pipe_config);
6359 intel_enable_pipe(pipe_config);
6361 if (pipe_config->has_pch_encoder)
6362 ironlake_pch_enable(state, pipe_config);
6364 assert_vblank_disabled(crtc);
6365 intel_crtc_vblank_on(pipe_config);
6367 intel_encoders_enable(intel_crtc, pipe_config, state);
6369 if (HAS_PCH_CPT(dev_priv))
6370 cpt_verify_modeset(dev, intel_crtc->pipe);
6373 * Must wait for vblank to avoid spurious PCH FIFO underruns.
6374 * And a second vblank wait is needed at least on ILK with
6375 * some interlaced HDMI modes. Let's do the double wait always
6376 * in case there are more corner cases we don't know about.
6378 if (pipe_config->has_pch_encoder) {
6379 intel_wait_for_vblank(dev_priv, pipe);
6380 intel_wait_for_vblank(dev_priv, pipe);
6382 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6383 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6386 /* IPS only exists on ULT machines and is tied to pipe A. */
6387 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6389 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6392 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6393 enum pipe pipe, bool apply)
6395 u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));
6396 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6403 I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
6406 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6408 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6409 enum pipe pipe = crtc->pipe;
6412 val = MBUS_DBOX_A_CREDIT(2);
6414 if (INTEL_GEN(dev_priv) >= 12) {
6415 val |= MBUS_DBOX_BW_CREDIT(2);
6416 val |= MBUS_DBOX_B_CREDIT(12);
6418 val |= MBUS_DBOX_BW_CREDIT(1);
6419 val |= MBUS_DBOX_B_CREDIT(8);
6422 I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6425 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
6426 struct intel_atomic_state *state)
6428 struct drm_crtc *crtc = pipe_config->base.crtc;
6429 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6431 enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
6432 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6433 bool psl_clkgate_wa;
6435 if (WARN_ON(intel_crtc->active))
6438 intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
6440 if (pipe_config->shared_dpll)
6441 intel_enable_shared_dpll(pipe_config);
6443 intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6445 if (intel_crtc_has_dp_encoder(pipe_config))
6446 intel_dp_set_m_n(pipe_config, M1_N1);
6448 if (!transcoder_is_dsi(cpu_transcoder))
6449 intel_set_pipe_timings(pipe_config);
6451 intel_set_pipe_src_size(pipe_config);
6453 if (cpu_transcoder != TRANSCODER_EDP &&
6454 !transcoder_is_dsi(cpu_transcoder)) {
6455 I915_WRITE(PIPE_MULT(cpu_transcoder),
6456 pipe_config->pixel_multiplier - 1);
6459 if (pipe_config->has_pch_encoder) {
6460 intel_cpu_transcoder_set_m_n(pipe_config,
6461 &pipe_config->fdi_m_n, NULL);
6464 if (!transcoder_is_dsi(cpu_transcoder))
6465 haswell_set_pipeconf(pipe_config);
6467 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6468 bdw_set_pipemisc(pipe_config);
6470 intel_crtc->active = true;
6472 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
6473 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
6474 pipe_config->pch_pfit.enabled;
6476 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
6478 if (INTEL_GEN(dev_priv) >= 9)
6479 skylake_pfit_enable(pipe_config);
6481 ironlake_pfit_enable(pipe_config);
6484 * On ILK+ LUT must be loaded before the pipe is running but with
6487 intel_color_load_luts(pipe_config);
6488 intel_color_commit(pipe_config);
6489 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
6490 if (INTEL_GEN(dev_priv) < 9)
6491 intel_disable_primary_plane(pipe_config);
6493 if (INTEL_GEN(dev_priv) >= 11)
6494 icl_set_pipe_chicken(intel_crtc);
6496 intel_ddi_set_pipe_settings(pipe_config);
6497 if (!transcoder_is_dsi(cpu_transcoder))
6498 intel_ddi_enable_transcoder_func(pipe_config);
6500 if (dev_priv->display.initial_watermarks != NULL)
6501 dev_priv->display.initial_watermarks(state, pipe_config);
6503 if (INTEL_GEN(dev_priv) >= 11)
6504 icl_pipe_mbus_enable(intel_crtc);
6506 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6507 if (!transcoder_is_dsi(cpu_transcoder))
6508 intel_enable_pipe(pipe_config);
6510 if (pipe_config->has_pch_encoder)
6511 lpt_pch_enable(state, pipe_config);
6513 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
6514 intel_ddi_set_vc_payload_alloc(pipe_config, true);
6516 assert_vblank_disabled(crtc);
6517 intel_crtc_vblank_on(pipe_config);
6519 intel_encoders_enable(intel_crtc, pipe_config, state);
6521 if (psl_clkgate_wa) {
6522 intel_wait_for_vblank(dev_priv, pipe);
6523 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
6526 /* If we change the relative order between pipe/planes enabling, we need
6527 * to change the workaround. */
6528 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
6529 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
6530 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6531 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
6535 static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6537 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6538 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6539 enum pipe pipe = crtc->pipe;
6541 /* To avoid upsetting the power well on haswell only disable the pfit if
6542 * it's in use. The hw state code will make sure we get this right. */
6543 if (old_crtc_state->pch_pfit.enabled) {
6544 I915_WRITE(PF_CTL(pipe), 0);
6545 I915_WRITE(PF_WIN_POS(pipe), 0);
6546 I915_WRITE(PF_WIN_SZ(pipe), 0);
6550 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6551 struct intel_atomic_state *state)
6553 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6554 struct drm_device *dev = crtc->dev;
6555 struct drm_i915_private *dev_priv = to_i915(dev);
6556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6557 enum pipe pipe = intel_crtc->pipe;
6560 * Sometimes spurious CPU pipe underruns happen when the
6561 * pipe is already disabled, but FDI RX/TX is still enabled.
6562 * Happens at least with VGA+HDMI cloning. Suppress them.
6564 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6565 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6567 intel_encoders_disable(intel_crtc, old_crtc_state, state);
6569 drm_crtc_vblank_off(crtc);
6570 assert_vblank_disabled(crtc);
6572 intel_disable_pipe(old_crtc_state);
6574 ironlake_pfit_disable(old_crtc_state);
6576 if (old_crtc_state->has_pch_encoder)
6577 ironlake_fdi_disable(crtc);
6579 intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6581 if (old_crtc_state->has_pch_encoder) {
6582 ironlake_disable_pch_transcoder(dev_priv, pipe);
6584 if (HAS_PCH_CPT(dev_priv)) {
6588 /* disable TRANS_DP_CTL */
6589 reg = TRANS_DP_CTL(pipe);
6590 temp = I915_READ(reg);
6591 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
6592 TRANS_DP_PORT_SEL_MASK);
6593 temp |= TRANS_DP_PORT_SEL_NONE;
6594 I915_WRITE(reg, temp);
6596 /* disable DPLL_SEL */
6597 temp = I915_READ(PCH_DPLL_SEL);
6598 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
6599 I915_WRITE(PCH_DPLL_SEL, temp);
6602 ironlake_fdi_pll_disable(intel_crtc);
6605 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6606 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6609 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6610 struct intel_atomic_state *state)
6612 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6613 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6617 intel_encoders_disable(intel_crtc, old_crtc_state, state);
6619 drm_crtc_vblank_off(crtc);
6620 assert_vblank_disabled(crtc);
6622 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
6623 if (!transcoder_is_dsi(cpu_transcoder))
6624 intel_disable_pipe(old_crtc_state);
6626 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
6627 intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
6629 if (!transcoder_is_dsi(cpu_transcoder))
6630 intel_ddi_disable_transcoder_func(old_crtc_state);
6632 intel_dsc_disable(old_crtc_state);
6634 if (INTEL_GEN(dev_priv) >= 9)
6635 skylake_scaler_disable(intel_crtc);
6637 ironlake_pfit_disable(old_crtc_state);
6639 intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6641 intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
6644 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
6646 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6647 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6649 if (!crtc_state->gmch_pfit.control)
6653 * The panel fitter should only be adjusted whilst the pipe is disabled,
6654 * according to register description and PRM.
6656 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
6657 assert_pipe_disabled(dev_priv, crtc->pipe);
6659 I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios);
6660 I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control);
6662 /* Border color in case we don't scale up to the full screen. Black by
6663 * default, change to something else for debugging. */
6664 I915_WRITE(BCLRPAT(crtc->pipe), 0);
6667 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6669 if (phy == PHY_NONE)
6672 if (IS_ELKHARTLAKE(dev_priv))
6673 return phy <= PHY_C;
6675 if (INTEL_GEN(dev_priv) >= 11)
6676 return phy <= PHY_B;
6681 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6683 if (INTEL_GEN(dev_priv) >= 12)
6684 return phy >= PHY_D && phy <= PHY_I;
6686 if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6687 return phy >= PHY_C && phy <= PHY_F;
6692 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
6694 if (IS_ELKHARTLAKE(i915) && port == PORT_D)
6697 return (enum phy)port;
6700 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6702 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6703 return PORT_TC_NONE;
6705 if (INTEL_GEN(dev_priv) >= 12)
6706 return port - PORT_D;
6708 return port - PORT_C;
6711 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
6715 return POWER_DOMAIN_PORT_DDI_A_LANES;
6717 return POWER_DOMAIN_PORT_DDI_B_LANES;
6719 return POWER_DOMAIN_PORT_DDI_C_LANES;
6721 return POWER_DOMAIN_PORT_DDI_D_LANES;
6723 return POWER_DOMAIN_PORT_DDI_E_LANES;
6725 return POWER_DOMAIN_PORT_DDI_F_LANES;
6728 return POWER_DOMAIN_PORT_OTHER;
6732 enum intel_display_power_domain
6733 intel_aux_power_domain(struct intel_digital_port *dig_port)
6735 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
6736 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
6738 if (intel_phy_is_tc(dev_priv, phy) &&
6739 dig_port->tc_mode == TC_PORT_TBT_ALT) {
6740 switch (dig_port->aux_ch) {
6742 return POWER_DOMAIN_AUX_C_TBT;
6744 return POWER_DOMAIN_AUX_D_TBT;
6746 return POWER_DOMAIN_AUX_E_TBT;
6748 return POWER_DOMAIN_AUX_F_TBT;
6750 MISSING_CASE(dig_port->aux_ch);
6751 return POWER_DOMAIN_AUX_C_TBT;
6755 switch (dig_port->aux_ch) {
6757 return POWER_DOMAIN_AUX_A;
6759 return POWER_DOMAIN_AUX_B;
6761 return POWER_DOMAIN_AUX_C;
6763 return POWER_DOMAIN_AUX_D;
6765 return POWER_DOMAIN_AUX_E;
6767 return POWER_DOMAIN_AUX_F;
6769 MISSING_CASE(dig_port->aux_ch);
6770 return POWER_DOMAIN_AUX_A;
6774 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6777 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6778 struct drm_encoder *encoder;
6779 enum pipe pipe = crtc->pipe;
6781 enum transcoder transcoder = crtc_state->cpu_transcoder;
6783 if (!crtc_state->base.active)
6786 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
6787 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
6788 if (crtc_state->pch_pfit.enabled ||
6789 crtc_state->pch_pfit.force_thru)
6790 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6792 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
6793 crtc_state->base.encoder_mask) {
6794 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6796 mask |= BIT_ULL(intel_encoder->power_domain);
6799 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
6800 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
6802 if (crtc_state->shared_dpll)
6803 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
6809 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6812 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6813 enum intel_display_power_domain domain;
6814 u64 domains, new_domains, old_domains;
6816 old_domains = crtc->enabled_power_domains;
6817 crtc->enabled_power_domains = new_domains =
6818 get_crtc_power_domains(crtc_state);
6820 domains = new_domains & ~old_domains;
6822 for_each_power_domain(domain, domains)
6823 intel_display_power_get(dev_priv, domain);
6825 return old_domains & ~new_domains;
6828 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
6831 enum intel_display_power_domain domain;
6833 for_each_power_domain(domain, domains)
6834 intel_display_power_put_unchecked(dev_priv, domain);
6837 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6838 struct intel_atomic_state *state)
6840 struct drm_crtc *crtc = pipe_config->base.crtc;
6841 struct drm_device *dev = crtc->dev;
6842 struct drm_i915_private *dev_priv = to_i915(dev);
6843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6844 enum pipe pipe = intel_crtc->pipe;
6846 if (WARN_ON(intel_crtc->active))
6849 if (intel_crtc_has_dp_encoder(pipe_config))
6850 intel_dp_set_m_n(pipe_config, M1_N1);
6852 intel_set_pipe_timings(pipe_config);
6853 intel_set_pipe_src_size(pipe_config);
6855 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
6856 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6857 I915_WRITE(CHV_CANVAS(pipe), 0);
6860 i9xx_set_pipeconf(pipe_config);
6862 intel_crtc->active = true;
6864 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6866 intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
6868 if (IS_CHERRYVIEW(dev_priv)) {
6869 chv_prepare_pll(intel_crtc, pipe_config);
6870 chv_enable_pll(intel_crtc, pipe_config);
6872 vlv_prepare_pll(intel_crtc, pipe_config);
6873 vlv_enable_pll(intel_crtc, pipe_config);
6876 intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6878 i9xx_pfit_enable(pipe_config);
6880 intel_color_load_luts(pipe_config);
6881 intel_color_commit(pipe_config);
6882 /* update DSPCNTR to configure gamma for pipe bottom color */
6883 intel_disable_primary_plane(pipe_config);
6885 dev_priv->display.initial_watermarks(state, pipe_config);
6886 intel_enable_pipe(pipe_config);
6888 assert_vblank_disabled(crtc);
6889 intel_crtc_vblank_on(pipe_config);
6891 intel_encoders_enable(intel_crtc, pipe_config, state);
6894 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
6896 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6899 I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
6900 I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
6903 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6904 struct intel_atomic_state *state)
6906 struct drm_crtc *crtc = pipe_config->base.crtc;
6907 struct drm_device *dev = crtc->dev;
6908 struct drm_i915_private *dev_priv = to_i915(dev);
6909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6910 enum pipe pipe = intel_crtc->pipe;
6912 if (WARN_ON(intel_crtc->active))
6915 i9xx_set_pll_dividers(pipe_config);
6917 if (intel_crtc_has_dp_encoder(pipe_config))
6918 intel_dp_set_m_n(pipe_config, M1_N1);
6920 intel_set_pipe_timings(pipe_config);
6921 intel_set_pipe_src_size(pipe_config);
6923 i9xx_set_pipeconf(pipe_config);
6925 intel_crtc->active = true;
6927 if (!IS_GEN(dev_priv, 2))
6928 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6930 intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6932 i9xx_enable_pll(intel_crtc, pipe_config);
6934 i9xx_pfit_enable(pipe_config);
6936 intel_color_load_luts(pipe_config);
6937 intel_color_commit(pipe_config);
6938 /* update DSPCNTR to configure gamma for pipe bottom color */
6939 intel_disable_primary_plane(pipe_config);
6941 if (dev_priv->display.initial_watermarks != NULL)
6942 dev_priv->display.initial_watermarks(state,
6945 intel_update_watermarks(intel_crtc);
6946 intel_enable_pipe(pipe_config);
6948 assert_vblank_disabled(crtc);
6949 intel_crtc_vblank_on(pipe_config);
6951 intel_encoders_enable(intel_crtc, pipe_config, state);
6954 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
6956 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
6957 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6959 if (!old_crtc_state->gmch_pfit.control)
6962 assert_pipe_disabled(dev_priv, crtc->pipe);
6964 DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n",
6965 I915_READ(PFIT_CONTROL));
6966 I915_WRITE(PFIT_CONTROL, 0);
6969 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6970 struct intel_atomic_state *state)
6972 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6973 struct drm_device *dev = crtc->dev;
6974 struct drm_i915_private *dev_priv = to_i915(dev);
6975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6976 enum pipe pipe = intel_crtc->pipe;
6979 * On gen2 planes are double buffered but the pipe isn't, so we must
6980 * wait for planes to fully turn off before disabling the pipe.
6982 if (IS_GEN(dev_priv, 2))
6983 intel_wait_for_vblank(dev_priv, pipe);
6985 intel_encoders_disable(intel_crtc, old_crtc_state, state);
6987 drm_crtc_vblank_off(crtc);
6988 assert_vblank_disabled(crtc);
6990 intel_disable_pipe(old_crtc_state);
6992 i9xx_pfit_disable(old_crtc_state);
6994 intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6996 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
6997 if (IS_CHERRYVIEW(dev_priv))
6998 chv_disable_pll(dev_priv, pipe);
6999 else if (IS_VALLEYVIEW(dev_priv))
7000 vlv_disable_pll(dev_priv, pipe);
7002 i9xx_disable_pll(old_crtc_state);
7005 intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
7007 if (!IS_GEN(dev_priv, 2))
7008 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7010 if (!dev_priv->display.initial_watermarks)
7011 intel_update_watermarks(intel_crtc);
7013 /* clock the pipe down to 640x480@60 to potentially save power */
7014 if (IS_I830(dev_priv))
7015 i830_enable_pipe(dev_priv, pipe);
7018 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
7019 struct drm_modeset_acquire_ctx *ctx)
7021 struct intel_encoder *encoder;
7022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
7024 struct intel_bw_state *bw_state =
7025 to_intel_bw_state(dev_priv->bw_obj.state);
7026 enum intel_display_power_domain domain;
7027 struct intel_plane *plane;
7029 struct drm_atomic_state *state;
7030 struct intel_crtc_state *crtc_state;
7033 if (!intel_crtc->active)
7036 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
7037 const struct intel_plane_state *plane_state =
7038 to_intel_plane_state(plane->base.state);
7040 if (plane_state->base.visible)
7041 intel_plane_disable_noatomic(intel_crtc, plane);
7044 state = drm_atomic_state_alloc(crtc->dev);
7046 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
7047 crtc->base.id, crtc->name);
7051 state->acquire_ctx = ctx;
7053 /* Everything's already locked, -EDEADLK can't happen. */
7054 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
7055 ret = drm_atomic_add_affected_connectors(state, crtc);
7057 WARN_ON(IS_ERR(crtc_state) || ret);
7059 dev_priv->display.crtc_disable(crtc_state, to_intel_atomic_state(state));
7061 drm_atomic_state_put(state);
7063 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7064 crtc->base.id, crtc->name);
7066 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
7067 crtc->state->active = false;
7068 intel_crtc->active = false;
7069 crtc->enabled = false;
7070 crtc->state->connector_mask = 0;
7071 crtc->state->encoder_mask = 0;
7073 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
7074 encoder->base.crtc = NULL;
7076 intel_fbc_disable(intel_crtc);
7077 intel_update_watermarks(intel_crtc);
7078 intel_disable_shared_dpll(to_intel_crtc_state(crtc->state));
7080 domains = intel_crtc->enabled_power_domains;
7081 for_each_power_domain(domain, domains)
7082 intel_display_power_put_unchecked(dev_priv, domain);
7083 intel_crtc->enabled_power_domains = 0;
7085 dev_priv->active_pipes &= ~BIT(intel_crtc->pipe);
7086 dev_priv->min_cdclk[intel_crtc->pipe] = 0;
7087 dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
7089 bw_state->data_rate[intel_crtc->pipe] = 0;
7090 bw_state->num_active_planes[intel_crtc->pipe] = 0;
7094 * turn all crtc's off, but do not adjust state
7095 * This has to be paired with a call to intel_modeset_setup_hw_state.
7097 int intel_display_suspend(struct drm_device *dev)
7099 struct drm_i915_private *dev_priv = to_i915(dev);
7100 struct drm_atomic_state *state;
7103 state = drm_atomic_helper_suspend(dev);
7104 ret = PTR_ERR_OR_ZERO(state);
7106 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
7108 dev_priv->modeset_restore_state = state;
7112 void intel_encoder_destroy(struct drm_encoder *encoder)
7114 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7116 drm_encoder_cleanup(encoder);
7117 kfree(intel_encoder);
7120 /* Cross check the actual hw state with our own modeset state tracking (and it's
7121 * internal consistency). */
7122 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7123 struct drm_connector_state *conn_state)
7125 struct intel_connector *connector = to_intel_connector(conn_state->connector);
7127 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
7128 connector->base.base.id,
7129 connector->base.name);
7131 if (connector->get_hw_state(connector)) {
7132 struct intel_encoder *encoder = connector->encoder;
7134 I915_STATE_WARN(!crtc_state,
7135 "connector enabled without attached crtc\n");
7140 I915_STATE_WARN(!crtc_state->base.active,
7141 "connector is active, but attached crtc isn't\n");
7143 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7146 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7147 "atomic encoder doesn't match attached encoder\n");
7149 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7150 "attached encoder crtc differs from connector crtc\n");
7152 I915_STATE_WARN(crtc_state && crtc_state->base.active,
7153 "attached crtc is active, but connector isn't\n");
7154 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7155 "best encoder set without crtc!\n");
7159 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7161 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7162 return crtc_state->fdi_lanes;
7167 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7168 struct intel_crtc_state *pipe_config)
7170 struct drm_i915_private *dev_priv = to_i915(dev);
7171 struct drm_atomic_state *state = pipe_config->base.state;
7172 struct intel_crtc *other_crtc;
7173 struct intel_crtc_state *other_crtc_state;
7175 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7176 pipe_name(pipe), pipe_config->fdi_lanes);
7177 if (pipe_config->fdi_lanes > 4) {
7178 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7179 pipe_name(pipe), pipe_config->fdi_lanes);
7183 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7184 if (pipe_config->fdi_lanes > 2) {
7185 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7186 pipe_config->fdi_lanes);
7193 if (INTEL_INFO(dev_priv)->num_pipes == 2)
7196 /* Ivybridge 3 pipe is really complicated */
7201 if (pipe_config->fdi_lanes <= 2)
7204 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7206 intel_atomic_get_crtc_state(state, other_crtc);
7207 if (IS_ERR(other_crtc_state))
7208 return PTR_ERR(other_crtc_state);
7210 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7211 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7212 pipe_name(pipe), pipe_config->fdi_lanes);
7217 if (pipe_config->fdi_lanes > 2) {
7218 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7219 pipe_name(pipe), pipe_config->fdi_lanes);
7223 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7225 intel_atomic_get_crtc_state(state, other_crtc);
7226 if (IS_ERR(other_crtc_state))
7227 return PTR_ERR(other_crtc_state);
7229 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7230 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7240 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7241 struct intel_crtc_state *pipe_config)
7243 struct drm_device *dev = intel_crtc->base.dev;
7244 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7245 int lane, link_bw, fdi_dotclock, ret;
7246 bool needs_recompute = false;
7249 /* FDI is a binary signal running at ~2.7GHz, encoding
7250 * each output octet as 10 bits. The actual frequency
7251 * is stored as a divider into a 100MHz clock, and the
7252 * mode pixel clock is stored in units of 1KHz.
7253 * Hence the bw of each lane in terms of the mode signal
7256 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7258 fdi_dotclock = adjusted_mode->crtc_clock;
7260 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7261 pipe_config->pipe_bpp);
7263 pipe_config->fdi_lanes = lane;
7265 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7266 link_bw, &pipe_config->fdi_m_n, false);
7268 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7269 if (ret == -EDEADLK)
7272 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7273 pipe_config->pipe_bpp -= 2*3;
7274 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7275 pipe_config->pipe_bpp);
7276 needs_recompute = true;
7277 pipe_config->bw_constrained = true;
7282 if (needs_recompute)
7288 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7290 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7291 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7293 /* IPS only exists on ULT machines and is tied to pipe A. */
7294 if (!hsw_crtc_supports_ips(crtc))
7297 if (!i915_modparams.enable_ips)
7300 if (crtc_state->pipe_bpp > 24)
7304 * We compare against max which means we must take
7305 * the increased cdclk requirement into account when
7306 * calculating the new cdclk.
7308 * Should measure whether using a lower cdclk w/o IPS
7310 if (IS_BROADWELL(dev_priv) &&
7311 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7317 static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7319 struct drm_i915_private *dev_priv =
7320 to_i915(crtc_state->base.crtc->dev);
7321 struct intel_atomic_state *intel_state =
7322 to_intel_atomic_state(crtc_state->base.state);
7324 if (!hsw_crtc_state_ips_capable(crtc_state))
7328 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7329 * enabled and disabled dynamically based on package C states,
7330 * user space can't make reliable use of the CRCs, so let's just
7331 * completely disable it.
7333 if (crtc_state->crc_enabled)
7336 /* IPS should be fine as long as at least one plane is enabled. */
7337 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7340 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7341 if (IS_BROADWELL(dev_priv) &&
7342 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
7348 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7350 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7352 /* GDG double wide on either pipe, otherwise pipe A only */
7353 return INTEL_GEN(dev_priv) < 4 &&
7354 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7357 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7361 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
7364 * We only use IF-ID interlacing. If we ever use
7365 * PF-ID we'll need to adjust the pixel_rate here.
7368 if (pipe_config->pch_pfit.enabled) {
7369 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7370 u32 pfit_size = pipe_config->pch_pfit.size;
7372 pipe_w = pipe_config->pipe_src_w;
7373 pipe_h = pipe_config->pipe_src_h;
7375 pfit_w = (pfit_size >> 16) & 0xFFFF;
7376 pfit_h = pfit_size & 0xFFFF;
7377 if (pipe_w < pfit_w)
7379 if (pipe_h < pfit_h)
7382 if (WARN_ON(!pfit_w || !pfit_h))
7385 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7392 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7394 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
7396 if (HAS_GMCH(dev_priv))
7397 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7398 crtc_state->pixel_rate =
7399 crtc_state->base.adjusted_mode.crtc_clock;
7401 crtc_state->pixel_rate =
7402 ilk_pipe_pixel_rate(crtc_state);
7405 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7406 struct intel_crtc_state *pipe_config)
7408 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7409 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7410 int clock_limit = dev_priv->max_dotclk_freq;
7412 if (INTEL_GEN(dev_priv) < 4) {
7413 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7416 * Enable double wide mode when the dot clock
7417 * is > 90% of the (display) core speed.
7419 if (intel_crtc_supports_double_wide(crtc) &&
7420 adjusted_mode->crtc_clock > clock_limit) {
7421 clock_limit = dev_priv->max_dotclk_freq;
7422 pipe_config->double_wide = true;
7426 if (adjusted_mode->crtc_clock > clock_limit) {
7427 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7428 adjusted_mode->crtc_clock, clock_limit,
7429 yesno(pipe_config->double_wide));
7433 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
7434 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
7435 pipe_config->base.ctm) {
7437 * There is only one pipe CSC unit per pipe, and we need that
7438 * for output conversion from RGB->YCBCR. So if CTM is already
7439 * applied we can't support YCBCR420 output.
7441 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
7446 * Pipe horizontal size must be even in:
7448 * - LVDS dual channel mode
7449 * - Double wide pipe
7451 if (pipe_config->pipe_src_w & 1) {
7452 if (pipe_config->double_wide) {
7453 DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n");
7457 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7458 intel_is_dual_link_lvds(dev_priv)) {
7459 DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n");
7464 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7465 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7467 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7468 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7471 intel_crtc_compute_pixel_rate(pipe_config);
7473 if (pipe_config->has_pch_encoder)
7474 return ironlake_fdi_compute_config(crtc, pipe_config);
7480 intel_reduce_m_n_ratio(u32 *num, u32 *den)
7482 while (*num > DATA_LINK_M_N_MASK ||
7483 *den > DATA_LINK_M_N_MASK) {
7489 static void compute_m_n(unsigned int m, unsigned int n,
7490 u32 *ret_m, u32 *ret_n,
7494 * Several DP dongles in particular seem to be fussy about
7495 * too large link M/N values. Give N value as 0x8000 that
7496 * should be acceptable by specific devices. 0x8000 is the
7497 * specified fixed N value for asynchronous clock mode,
7498 * which the devices expect also in synchronous clock mode.
7503 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7505 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
7506 intel_reduce_m_n_ratio(ret_m, ret_n);
7510 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
7511 int pixel_clock, int link_clock,
7512 struct intel_link_m_n *m_n,
7517 compute_m_n(bits_per_pixel * pixel_clock,
7518 link_clock * nlanes * 8,
7519 &m_n->gmch_m, &m_n->gmch_n,
7522 compute_m_n(pixel_clock, link_clock,
7523 &m_n->link_m, &m_n->link_n,
7527 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7529 if (i915_modparams.panel_use_ssc >= 0)
7530 return i915_modparams.panel_use_ssc != 0;
7531 return dev_priv->vbt.lvds_use_ssc
7532 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7535 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
7537 return (1 << dpll->n) << 16 | dpll->m2;
7540 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
7542 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7545 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7546 struct intel_crtc_state *crtc_state,
7547 struct dpll *reduced_clock)
7549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7552 if (IS_PINEVIEW(dev_priv)) {
7553 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7555 fp2 = pnv_dpll_compute_fp(reduced_clock);
7557 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7559 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7562 crtc_state->dpll_hw_state.fp0 = fp;
7564 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7566 crtc_state->dpll_hw_state.fp1 = fp2;
7568 crtc_state->dpll_hw_state.fp1 = fp;
7572 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7578 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7579 * and set it to a reasonable value instead.
7581 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7582 reg_val &= 0xffffff00;
7583 reg_val |= 0x00000030;
7584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7586 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7587 reg_val &= 0x00ffffff;
7588 reg_val |= 0x8c000000;
7589 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7591 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7592 reg_val &= 0xffffff00;
7593 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7595 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7596 reg_val &= 0x00ffffff;
7597 reg_val |= 0xb0000000;
7598 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7601 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7602 const struct intel_link_m_n *m_n)
7604 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7605 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7606 enum pipe pipe = crtc->pipe;
7608 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7609 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7610 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7611 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7614 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
7615 enum transcoder transcoder)
7617 if (IS_HASWELL(dev_priv))
7618 return transcoder == TRANSCODER_EDP;
7621 * Strictly speaking some registers are available before
7622 * gen7, but we only support DRRS on gen7+
7624 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
7627 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
7628 const struct intel_link_m_n *m_n,
7629 const struct intel_link_m_n *m2_n2)
7631 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
7632 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7633 enum pipe pipe = crtc->pipe;
7634 enum transcoder transcoder = crtc_state->cpu_transcoder;
7636 if (INTEL_GEN(dev_priv) >= 5) {
7637 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7638 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7639 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7640 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7642 * M2_N2 registers are set only if DRRS is supported
7643 * (to make sure the registers are not unnecessarily accessed).
7645 if (m2_n2 && crtc_state->has_drrs &&
7646 transcoder_has_m2_n2(dev_priv, transcoder)) {
7647 I915_WRITE(PIPE_DATA_M2(transcoder),
7648 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7649 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7650 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7651 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7654 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7655 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7656 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7657 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7661 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
7663 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7666 dp_m_n = &crtc_state->dp_m_n;
7667 dp_m2_n2 = &crtc_state->dp_m2_n2;
7668 } else if (m_n == M2_N2) {
7671 * M2_N2 registers are not supported. Hence m2_n2 divider value
7672 * needs to be programmed into M1_N1.
7674 dp_m_n = &crtc_state->dp_m2_n2;
7676 DRM_ERROR("Unsupported divider value\n");
7680 if (crtc_state->has_pch_encoder)
7681 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
7683 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
7686 static void vlv_compute_dpll(struct intel_crtc *crtc,
7687 struct intel_crtc_state *pipe_config)
7689 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7690 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7691 if (crtc->pipe != PIPE_A)
7692 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7694 /* DPLL not used with DSI, but still need the rest set up */
7695 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7696 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7697 DPLL_EXT_BUFFER_ENABLE_VLV;
7699 pipe_config->dpll_hw_state.dpll_md =
7700 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7703 static void chv_compute_dpll(struct intel_crtc *crtc,
7704 struct intel_crtc_state *pipe_config)
7706 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7707 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7708 if (crtc->pipe != PIPE_A)
7709 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7711 /* DPLL not used with DSI, but still need the rest set up */
7712 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7713 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7715 pipe_config->dpll_hw_state.dpll_md =
7716 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7719 static void vlv_prepare_pll(struct intel_crtc *crtc,
7720 const struct intel_crtc_state *pipe_config)
7722 struct drm_device *dev = crtc->base.dev;
7723 struct drm_i915_private *dev_priv = to_i915(dev);
7724 enum pipe pipe = crtc->pipe;
7726 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7727 u32 coreclk, reg_val;
7730 I915_WRITE(DPLL(pipe),
7731 pipe_config->dpll_hw_state.dpll &
7732 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7734 /* No need to actually set up the DPLL with DSI */
7735 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7738 vlv_dpio_get(dev_priv);
7740 bestn = pipe_config->dpll.n;
7741 bestm1 = pipe_config->dpll.m1;
7742 bestm2 = pipe_config->dpll.m2;
7743 bestp1 = pipe_config->dpll.p1;
7744 bestp2 = pipe_config->dpll.p2;
7746 /* See eDP HDMI DPIO driver vbios notes doc */
7748 /* PLL B needs special handling */
7750 vlv_pllb_recal_opamp(dev_priv, pipe);
7752 /* Set up Tx target for periodic Rcomp update */
7753 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7755 /* Disable target IRef on PLL */
7756 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7757 reg_val &= 0x00ffffff;
7758 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7760 /* Disable fast lock */
7761 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7763 /* Set idtafcrecal before PLL is enabled */
7764 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7765 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7766 mdiv |= ((bestn << DPIO_N_SHIFT));
7767 mdiv |= (1 << DPIO_K_SHIFT);
7770 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7771 * but we don't support that).
7772 * Note: don't use the DAC post divider as it seems unstable.
7774 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7775 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7777 mdiv |= DPIO_ENABLE_CALIBRATION;
7778 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7780 /* Set HBR and RBR LPF coefficients */
7781 if (pipe_config->port_clock == 162000 ||
7782 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
7783 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
7784 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7787 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7790 if (intel_crtc_has_dp_encoder(pipe_config)) {
7791 /* Use SSC source */
7793 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7796 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7798 } else { /* HDMI or VGA */
7799 /* Use bend source */
7801 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7804 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7808 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7809 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7810 if (intel_crtc_has_dp_encoder(pipe_config))
7811 coreclk |= 0x01000000;
7812 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7814 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7816 vlv_dpio_put(dev_priv);
7819 static void chv_prepare_pll(struct intel_crtc *crtc,
7820 const struct intel_crtc_state *pipe_config)
7822 struct drm_device *dev = crtc->base.dev;
7823 struct drm_i915_private *dev_priv = to_i915(dev);
7824 enum pipe pipe = crtc->pipe;
7825 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7826 u32 loopfilter, tribuf_calcntr;
7827 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7831 /* Enable Refclk and SSC */
7832 I915_WRITE(DPLL(pipe),
7833 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7835 /* No need to actually set up the DPLL with DSI */
7836 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7839 bestn = pipe_config->dpll.n;
7840 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7841 bestm1 = pipe_config->dpll.m1;
7842 bestm2 = pipe_config->dpll.m2 >> 22;
7843 bestp1 = pipe_config->dpll.p1;
7844 bestp2 = pipe_config->dpll.p2;
7845 vco = pipe_config->dpll.vco;
7849 vlv_dpio_get(dev_priv);
7851 /* p1 and p2 divider */
7852 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7853 5 << DPIO_CHV_S1_DIV_SHIFT |
7854 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7855 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7856 1 << DPIO_CHV_K_DIV_SHIFT);
7858 /* Feedback post-divider - m2 */
7859 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7861 /* Feedback refclk divider - n and m1 */
7862 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7863 DPIO_CHV_M1_DIV_BY_2 |
7864 1 << DPIO_CHV_N_DIV_SHIFT);
7866 /* M2 fraction division */
7867 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7869 /* M2 fraction division enable */
7870 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7871 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7872 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7874 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7875 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7877 /* Program digital lock detect threshold */
7878 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7879 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7880 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7881 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7883 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7884 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7887 if (vco == 5400000) {
7888 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7889 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7890 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7891 tribuf_calcntr = 0x9;
7892 } else if (vco <= 6200000) {
7893 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7894 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7895 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7896 tribuf_calcntr = 0x9;
7897 } else if (vco <= 6480000) {
7898 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7899 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7900 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7901 tribuf_calcntr = 0x8;
7903 /* Not supported. Apply the same limits as in the max case */
7904 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7905 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7906 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7909 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7911 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7912 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7913 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7914 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7917 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7918 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7921 vlv_dpio_put(dev_priv);
7925 * vlv_force_pll_on - forcibly enable just the PLL
7926 * @dev_priv: i915 private structure
7927 * @pipe: pipe PLL to enable
7928 * @dpll: PLL configuration
7930 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7931 * in cases where we need the PLL enabled even when @pipe is not going to
7934 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
7935 const struct dpll *dpll)
7937 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
7938 struct intel_crtc_state *pipe_config;
7940 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7944 pipe_config->base.crtc = &crtc->base;
7945 pipe_config->pixel_multiplier = 1;
7946 pipe_config->dpll = *dpll;
7948 if (IS_CHERRYVIEW(dev_priv)) {
7949 chv_compute_dpll(crtc, pipe_config);
7950 chv_prepare_pll(crtc, pipe_config);
7951 chv_enable_pll(crtc, pipe_config);
7953 vlv_compute_dpll(crtc, pipe_config);
7954 vlv_prepare_pll(crtc, pipe_config);
7955 vlv_enable_pll(crtc, pipe_config);
7964 * vlv_force_pll_off - forcibly disable just the PLL
7965 * @dev_priv: i915 private structure
7966 * @pipe: pipe PLL to disable
7968 * Disable the PLL for @pipe. To be used in cases where we need
7969 * the PLL enabled even when @pipe is not going to be enabled.
7971 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
7973 if (IS_CHERRYVIEW(dev_priv))
7974 chv_disable_pll(dev_priv, pipe);
7976 vlv_disable_pll(dev_priv, pipe);
7979 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7980 struct intel_crtc_state *crtc_state,
7981 struct dpll *reduced_clock)
7983 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7985 struct dpll *clock = &crtc_state->dpll;
7987 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7989 dpll = DPLL_VGA_MODE_DIS;
7991 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
7992 dpll |= DPLLB_MODE_LVDS;
7994 dpll |= DPLLB_MODE_DAC_SERIAL;
7996 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7997 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7998 dpll |= (crtc_state->pixel_multiplier - 1)
7999 << SDVO_MULTIPLIER_SHIFT_HIRES;
8002 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8003 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8004 dpll |= DPLL_SDVO_HIGH_SPEED;
8006 if (intel_crtc_has_dp_encoder(crtc_state))
8007 dpll |= DPLL_SDVO_HIGH_SPEED;
8009 /* compute bitmask from p1 value */
8010 if (IS_PINEVIEW(dev_priv))
8011 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8013 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8014 if (IS_G4X(dev_priv) && reduced_clock)
8015 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8017 switch (clock->p2) {
8019 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8022 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8025 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8028 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8031 if (INTEL_GEN(dev_priv) >= 4)
8032 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8034 if (crtc_state->sdvo_tv_clock)
8035 dpll |= PLL_REF_INPUT_TVCLKINBC;
8036 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8037 intel_panel_use_ssc(dev_priv))
8038 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8040 dpll |= PLL_REF_INPUT_DREFCLK;
8042 dpll |= DPLL_VCO_ENABLE;
8043 crtc_state->dpll_hw_state.dpll = dpll;
8045 if (INTEL_GEN(dev_priv) >= 4) {
8046 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8047 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8048 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8052 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8053 struct intel_crtc_state *crtc_state,
8054 struct dpll *reduced_clock)
8056 struct drm_device *dev = crtc->base.dev;
8057 struct drm_i915_private *dev_priv = to_i915(dev);
8059 struct dpll *clock = &crtc_state->dpll;
8061 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8063 dpll = DPLL_VGA_MODE_DIS;
8065 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8066 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8069 dpll |= PLL_P1_DIVIDE_BY_TWO;
8071 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8073 dpll |= PLL_P2_DIVIDE_BY_4;
8078 * "[Almador Errata}: For the correct operation of the muxed DVO pins
8079 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8080 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8081 * Enable) must be set to “1” in both the DPLL A Control Register
8082 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8084 * For simplicity We simply keep both bits always enabled in
8085 * both DPLLS. The spec says we should disable the DVO 2X clock
8086 * when not needed, but this seems to work fine in practice.
8088 if (IS_I830(dev_priv) ||
8089 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8090 dpll |= DPLL_DVO_2X_MODE;
8092 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8093 intel_panel_use_ssc(dev_priv))
8094 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8096 dpll |= PLL_REF_INPUT_DREFCLK;
8098 dpll |= DPLL_VCO_ENABLE;
8099 crtc_state->dpll_hw_state.dpll = dpll;
8102 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8104 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8105 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8106 enum pipe pipe = crtc->pipe;
8107 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8108 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
8109 u32 crtc_vtotal, crtc_vblank_end;
8112 /* We need to be careful not to changed the adjusted mode, for otherwise
8113 * the hw state checker will get angry at the mismatch. */
8114 crtc_vtotal = adjusted_mode->crtc_vtotal;
8115 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8117 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8118 /* the chip adds 2 halflines automatically */
8120 crtc_vblank_end -= 1;
8122 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8123 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8125 vsyncshift = adjusted_mode->crtc_hsync_start -
8126 adjusted_mode->crtc_htotal / 2;
8128 vsyncshift += adjusted_mode->crtc_htotal;
8131 if (INTEL_GEN(dev_priv) > 3)
8132 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8134 I915_WRITE(HTOTAL(cpu_transcoder),
8135 (adjusted_mode->crtc_hdisplay - 1) |
8136 ((adjusted_mode->crtc_htotal - 1) << 16));
8137 I915_WRITE(HBLANK(cpu_transcoder),
8138 (adjusted_mode->crtc_hblank_start - 1) |
8139 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8140 I915_WRITE(HSYNC(cpu_transcoder),
8141 (adjusted_mode->crtc_hsync_start - 1) |
8142 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8144 I915_WRITE(VTOTAL(cpu_transcoder),
8145 (adjusted_mode->crtc_vdisplay - 1) |
8146 ((crtc_vtotal - 1) << 16));
8147 I915_WRITE(VBLANK(cpu_transcoder),
8148 (adjusted_mode->crtc_vblank_start - 1) |
8149 ((crtc_vblank_end - 1) << 16));
8150 I915_WRITE(VSYNC(cpu_transcoder),
8151 (adjusted_mode->crtc_vsync_start - 1) |
8152 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8154 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8155 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8156 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8158 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8159 (pipe == PIPE_B || pipe == PIPE_C))
8160 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8164 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8166 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8167 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8168 enum pipe pipe = crtc->pipe;
8170 /* pipesrc controls the size that is scaled from, which should
8171 * always be the user's requested size.
8173 I915_WRITE(PIPESRC(pipe),
8174 ((crtc_state->pipe_src_w - 1) << 16) |
8175 (crtc_state->pipe_src_h - 1));
8178 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8179 struct intel_crtc_state *pipe_config)
8181 struct drm_device *dev = crtc->base.dev;
8182 struct drm_i915_private *dev_priv = to_i915(dev);
8183 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8186 tmp = I915_READ(HTOTAL(cpu_transcoder));
8187 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8188 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8190 if (!transcoder_is_dsi(cpu_transcoder)) {
8191 tmp = I915_READ(HBLANK(cpu_transcoder));
8192 pipe_config->base.adjusted_mode.crtc_hblank_start =
8194 pipe_config->base.adjusted_mode.crtc_hblank_end =
8195 ((tmp >> 16) & 0xffff) + 1;
8197 tmp = I915_READ(HSYNC(cpu_transcoder));
8198 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8199 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8201 tmp = I915_READ(VTOTAL(cpu_transcoder));
8202 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8203 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8205 if (!transcoder_is_dsi(cpu_transcoder)) {
8206 tmp = I915_READ(VBLANK(cpu_transcoder));
8207 pipe_config->base.adjusted_mode.crtc_vblank_start =
8209 pipe_config->base.adjusted_mode.crtc_vblank_end =
8210 ((tmp >> 16) & 0xffff) + 1;
8212 tmp = I915_READ(VSYNC(cpu_transcoder));
8213 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8214 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8216 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8217 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8218 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8219 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8223 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8224 struct intel_crtc_state *pipe_config)
8226 struct drm_device *dev = crtc->base.dev;
8227 struct drm_i915_private *dev_priv = to_i915(dev);
8230 tmp = I915_READ(PIPESRC(crtc->pipe));
8231 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8232 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8234 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8235 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8238 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8239 struct intel_crtc_state *pipe_config)
8241 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8242 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8243 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8244 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8246 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8247 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8248 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8249 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8251 mode->flags = pipe_config->base.adjusted_mode.flags;
8252 mode->type = DRM_MODE_TYPE_DRIVER;
8254 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8256 mode->hsync = drm_mode_hsync(mode);
8257 mode->vrefresh = drm_mode_vrefresh(mode);
8258 drm_mode_set_name(mode);
8261 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8263 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8269 /* we keep both pipes enabled on 830 */
8270 if (IS_I830(dev_priv))
8271 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8273 if (crtc_state->double_wide)
8274 pipeconf |= PIPECONF_DOUBLE_WIDE;
8276 /* only g4x and later have fancy bpc/dither controls */
8277 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8278 IS_CHERRYVIEW(dev_priv)) {
8279 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8280 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8281 pipeconf |= PIPECONF_DITHER_EN |
8282 PIPECONF_DITHER_TYPE_SP;
8284 switch (crtc_state->pipe_bpp) {
8286 pipeconf |= PIPECONF_6BPC;
8289 pipeconf |= PIPECONF_8BPC;
8292 pipeconf |= PIPECONF_10BPC;
8295 /* Case prevented by intel_choose_pipe_bpp_dither. */
8300 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8301 if (INTEL_GEN(dev_priv) < 4 ||
8302 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8303 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8305 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8307 pipeconf |= PIPECONF_PROGRESSIVE;
8310 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8311 crtc_state->limited_color_range)
8312 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8314 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8316 I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
8317 POSTING_READ(PIPECONF(crtc->pipe));
8320 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8321 struct intel_crtc_state *crtc_state)
8323 struct drm_device *dev = crtc->base.dev;
8324 struct drm_i915_private *dev_priv = to_i915(dev);
8325 const struct intel_limit *limit;
8328 memset(&crtc_state->dpll_hw_state, 0,
8329 sizeof(crtc_state->dpll_hw_state));
8331 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8332 if (intel_panel_use_ssc(dev_priv)) {
8333 refclk = dev_priv->vbt.lvds_ssc_freq;
8334 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8337 limit = &intel_limits_i8xx_lvds;
8338 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8339 limit = &intel_limits_i8xx_dvo;
8341 limit = &intel_limits_i8xx_dac;
8344 if (!crtc_state->clock_set &&
8345 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8346 refclk, NULL, &crtc_state->dpll)) {
8347 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8351 i8xx_compute_dpll(crtc, crtc_state, NULL);
8356 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8357 struct intel_crtc_state *crtc_state)
8359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8360 const struct intel_limit *limit;
8363 memset(&crtc_state->dpll_hw_state, 0,
8364 sizeof(crtc_state->dpll_hw_state));
8366 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8367 if (intel_panel_use_ssc(dev_priv)) {
8368 refclk = dev_priv->vbt.lvds_ssc_freq;
8369 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8372 if (intel_is_dual_link_lvds(dev_priv))
8373 limit = &intel_limits_g4x_dual_channel_lvds;
8375 limit = &intel_limits_g4x_single_channel_lvds;
8376 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8377 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8378 limit = &intel_limits_g4x_hdmi;
8379 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8380 limit = &intel_limits_g4x_sdvo;
8382 /* The option is for other outputs */
8383 limit = &intel_limits_i9xx_sdvo;
8386 if (!crtc_state->clock_set &&
8387 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8388 refclk, NULL, &crtc_state->dpll)) {
8389 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8393 i9xx_compute_dpll(crtc, crtc_state, NULL);
8398 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8399 struct intel_crtc_state *crtc_state)
8401 struct drm_device *dev = crtc->base.dev;
8402 struct drm_i915_private *dev_priv = to_i915(dev);
8403 const struct intel_limit *limit;
8406 memset(&crtc_state->dpll_hw_state, 0,
8407 sizeof(crtc_state->dpll_hw_state));
8409 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8410 if (intel_panel_use_ssc(dev_priv)) {
8411 refclk = dev_priv->vbt.lvds_ssc_freq;
8412 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8415 limit = &intel_limits_pineview_lvds;
8417 limit = &intel_limits_pineview_sdvo;
8420 if (!crtc_state->clock_set &&
8421 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8422 refclk, NULL, &crtc_state->dpll)) {
8423 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8427 i9xx_compute_dpll(crtc, crtc_state, NULL);
8432 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8433 struct intel_crtc_state *crtc_state)
8435 struct drm_device *dev = crtc->base.dev;
8436 struct drm_i915_private *dev_priv = to_i915(dev);
8437 const struct intel_limit *limit;
8440 memset(&crtc_state->dpll_hw_state, 0,
8441 sizeof(crtc_state->dpll_hw_state));
8443 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8444 if (intel_panel_use_ssc(dev_priv)) {
8445 refclk = dev_priv->vbt.lvds_ssc_freq;
8446 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8449 limit = &intel_limits_i9xx_lvds;
8451 limit = &intel_limits_i9xx_sdvo;
8454 if (!crtc_state->clock_set &&
8455 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8456 refclk, NULL, &crtc_state->dpll)) {
8457 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8461 i9xx_compute_dpll(crtc, crtc_state, NULL);
8466 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8467 struct intel_crtc_state *crtc_state)
8469 int refclk = 100000;
8470 const struct intel_limit *limit = &intel_limits_chv;
8472 memset(&crtc_state->dpll_hw_state, 0,
8473 sizeof(crtc_state->dpll_hw_state));
8475 if (!crtc_state->clock_set &&
8476 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8477 refclk, NULL, &crtc_state->dpll)) {
8478 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8482 chv_compute_dpll(crtc, crtc_state);
8487 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8488 struct intel_crtc_state *crtc_state)
8490 int refclk = 100000;
8491 const struct intel_limit *limit = &intel_limits_vlv;
8493 memset(&crtc_state->dpll_hw_state, 0,
8494 sizeof(crtc_state->dpll_hw_state));
8496 if (!crtc_state->clock_set &&
8497 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8498 refclk, NULL, &crtc_state->dpll)) {
8499 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8503 vlv_compute_dpll(crtc, crtc_state);
8508 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
8510 if (IS_I830(dev_priv))
8513 return INTEL_GEN(dev_priv) >= 4 ||
8514 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
8517 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8518 struct intel_crtc_state *pipe_config)
8520 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8523 if (!i9xx_has_pfit(dev_priv))
8526 tmp = I915_READ(PFIT_CONTROL);
8527 if (!(tmp & PFIT_ENABLE))
8530 /* Check whether the pfit is attached to our pipe. */
8531 if (INTEL_GEN(dev_priv) < 4) {
8532 if (crtc->pipe != PIPE_B)
8535 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8539 pipe_config->gmch_pfit.control = tmp;
8540 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8543 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8544 struct intel_crtc_state *pipe_config)
8546 struct drm_device *dev = crtc->base.dev;
8547 struct drm_i915_private *dev_priv = to_i915(dev);
8548 enum pipe pipe = crtc->pipe;
8551 int refclk = 100000;
8553 /* In case of DSI, DPLL will not be used */
8554 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8557 vlv_dpio_get(dev_priv);
8558 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8559 vlv_dpio_put(dev_priv);
8561 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8562 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8563 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8564 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8565 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8567 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8571 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8572 struct intel_initial_plane_config *plane_config)
8574 struct drm_device *dev = crtc->base.dev;
8575 struct drm_i915_private *dev_priv = to_i915(dev);
8576 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8577 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8579 u32 val, base, offset;
8580 int fourcc, pixel_format;
8581 unsigned int aligned_height;
8582 struct drm_framebuffer *fb;
8583 struct intel_framebuffer *intel_fb;
8585 if (!plane->get_hw_state(plane, &pipe))
8588 WARN_ON(pipe != crtc->pipe);
8590 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8592 DRM_DEBUG_KMS("failed to alloc fb\n");
8596 fb = &intel_fb->base;
8600 val = I915_READ(DSPCNTR(i9xx_plane));
8602 if (INTEL_GEN(dev_priv) >= 4) {
8603 if (val & DISPPLANE_TILED) {
8604 plane_config->tiling = I915_TILING_X;
8605 fb->modifier = I915_FORMAT_MOD_X_TILED;
8608 if (val & DISPPLANE_ROTATE_180)
8609 plane_config->rotation = DRM_MODE_ROTATE_180;
8612 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
8613 val & DISPPLANE_MIRROR)
8614 plane_config->rotation |= DRM_MODE_REFLECT_X;
8616 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8617 fourcc = i9xx_format_to_fourcc(pixel_format);
8618 fb->format = drm_format_info(fourcc);
8620 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8621 offset = I915_READ(DSPOFFSET(i9xx_plane));
8622 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8623 } else if (INTEL_GEN(dev_priv) >= 4) {
8624 if (plane_config->tiling)
8625 offset = I915_READ(DSPTILEOFF(i9xx_plane));
8627 offset = I915_READ(DSPLINOFF(i9xx_plane));
8628 base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
8630 base = I915_READ(DSPADDR(i9xx_plane));
8632 plane_config->base = base;
8634 val = I915_READ(PIPESRC(pipe));
8635 fb->width = ((val >> 16) & 0xfff) + 1;
8636 fb->height = ((val >> 0) & 0xfff) + 1;
8638 val = I915_READ(DSPSTRIDE(i9xx_plane));
8639 fb->pitches[0] = val & 0xffffffc0;
8641 aligned_height = intel_fb_align_height(fb, 0, fb->height);
8643 plane_config->size = fb->pitches[0] * aligned_height;
8645 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8646 crtc->base.name, plane->base.name, fb->width, fb->height,
8647 fb->format->cpp[0] * 8, base, fb->pitches[0],
8648 plane_config->size);
8650 plane_config->fb = intel_fb;
8653 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8654 struct intel_crtc_state *pipe_config)
8656 struct drm_device *dev = crtc->base.dev;
8657 struct drm_i915_private *dev_priv = to_i915(dev);
8658 enum pipe pipe = crtc->pipe;
8659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8661 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8662 int refclk = 100000;
8664 /* In case of DSI, DPLL will not be used */
8665 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8668 vlv_dpio_get(dev_priv);
8669 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8670 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8671 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8672 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8673 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8674 vlv_dpio_put(dev_priv);
8676 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8677 clock.m2 = (pll_dw0 & 0xff) << 22;
8678 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8679 clock.m2 |= pll_dw2 & 0x3fffff;
8680 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8681 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8682 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8684 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8687 static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
8688 struct intel_crtc_state *pipe_config)
8690 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8691 enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
8693 pipe_config->lspcon_downsampling = false;
8695 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
8696 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
8698 if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
8699 bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
8700 bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
8702 if (ycbcr420_enabled) {
8703 /* We support 4:2:0 in full blend mode only */
8705 output = INTEL_OUTPUT_FORMAT_INVALID;
8706 else if (!(IS_GEMINILAKE(dev_priv) ||
8707 INTEL_GEN(dev_priv) >= 10))
8708 output = INTEL_OUTPUT_FORMAT_INVALID;
8710 output = INTEL_OUTPUT_FORMAT_YCBCR420;
8713 * Currently there is no interface defined to
8714 * check user preference between RGB/YCBCR444
8715 * or YCBCR420. So the only possible case for
8716 * YCBCR444 usage is driving YCBCR420 output
8717 * with LSPCON, when pipe is configured for
8718 * YCBCR444 output and LSPCON takes care of
8721 pipe_config->lspcon_downsampling = true;
8722 output = INTEL_OUTPUT_FORMAT_YCBCR444;
8727 pipe_config->output_format = output;
8730 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
8732 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
8733 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
8734 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8735 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
8738 tmp = I915_READ(DSPCNTR(i9xx_plane));
8740 if (tmp & DISPPLANE_GAMMA_ENABLE)
8741 crtc_state->gamma_enable = true;
8743 if (!HAS_GMCH(dev_priv) &&
8744 tmp & DISPPLANE_PIPE_CSC_ENABLE)
8745 crtc_state->csc_enable = true;
8748 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8749 struct intel_crtc_state *pipe_config)
8751 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8752 enum intel_display_power_domain power_domain;
8753 intel_wakeref_t wakeref;
8757 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8758 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
8762 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
8763 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8764 pipe_config->shared_dpll = NULL;
8768 tmp = I915_READ(PIPECONF(crtc->pipe));
8769 if (!(tmp & PIPECONF_ENABLE))
8772 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8773 IS_CHERRYVIEW(dev_priv)) {
8774 switch (tmp & PIPECONF_BPC_MASK) {
8776 pipe_config->pipe_bpp = 18;
8779 pipe_config->pipe_bpp = 24;
8781 case PIPECONF_10BPC:
8782 pipe_config->pipe_bpp = 30;
8789 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8790 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8791 pipe_config->limited_color_range = true;
8793 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
8794 PIPECONF_GAMMA_MODE_SHIFT;
8796 if (IS_CHERRYVIEW(dev_priv))
8797 pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
8799 i9xx_get_pipe_color_config(pipe_config);
8800 intel_color_get_config(pipe_config);
8802 if (INTEL_GEN(dev_priv) < 4)
8803 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8805 intel_get_pipe_timings(crtc, pipe_config);
8806 intel_get_pipe_src_size(crtc, pipe_config);
8808 i9xx_get_pfit_config(crtc, pipe_config);
8810 if (INTEL_GEN(dev_priv) >= 4) {
8811 /* No way to read it out on pipes B and C */
8812 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
8813 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8815 tmp = I915_READ(DPLL_MD(crtc->pipe));
8816 pipe_config->pixel_multiplier =
8817 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8818 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8819 pipe_config->dpll_hw_state.dpll_md = tmp;
8820 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8821 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8822 tmp = I915_READ(DPLL(crtc->pipe));
8823 pipe_config->pixel_multiplier =
8824 ((tmp & SDVO_MULTIPLIER_MASK)
8825 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8827 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8828 * port and will be fixed up in the encoder->get_config
8830 pipe_config->pixel_multiplier = 1;
8832 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8833 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
8834 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8835 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8837 /* Mask out read-only status bits. */
8838 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8839 DPLL_PORTC_READY_MASK |
8840 DPLL_PORTB_READY_MASK);
8843 if (IS_CHERRYVIEW(dev_priv))
8844 chv_crtc_clock_get(crtc, pipe_config);
8845 else if (IS_VALLEYVIEW(dev_priv))
8846 vlv_crtc_clock_get(crtc, pipe_config);
8848 i9xx_crtc_clock_get(crtc, pipe_config);
8851 * Normally the dotclock is filled in by the encoder .get_config()
8852 * but in case the pipe is enabled w/o any ports we need a sane
8855 pipe_config->base.adjusted_mode.crtc_clock =
8856 pipe_config->port_clock / pipe_config->pixel_multiplier;
8861 intel_display_power_put(dev_priv, power_domain, wakeref);
8866 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
8868 struct intel_encoder *encoder;
8871 bool has_lvds = false;
8872 bool has_cpu_edp = false;
8873 bool has_panel = false;
8874 bool has_ck505 = false;
8875 bool can_ssc = false;
8876 bool using_ssc_source = false;
8878 /* We need to take the global config into account */
8879 for_each_intel_encoder(&dev_priv->drm, encoder) {
8880 switch (encoder->type) {
8881 case INTEL_OUTPUT_LVDS:
8885 case INTEL_OUTPUT_EDP:
8887 if (encoder->port == PORT_A)
8895 if (HAS_PCH_IBX(dev_priv)) {
8896 has_ck505 = dev_priv->vbt.display_clock_mode;
8897 can_ssc = has_ck505;
8903 /* Check if any DPLLs are using the SSC source */
8904 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8905 u32 temp = I915_READ(PCH_DPLL(i));
8907 if (!(temp & DPLL_VCO_ENABLE))
8910 if ((temp & PLL_REF_INPUT_MASK) ==
8911 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8912 using_ssc_source = true;
8917 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8918 has_panel, has_lvds, has_ck505, using_ssc_source);
8920 /* Ironlake: try to setup display ref clock before DPLL
8921 * enabling. This is only under driver's control after
8922 * PCH B stepping, previous chipset stepping should be
8923 * ignoring this setting.
8925 val = I915_READ(PCH_DREF_CONTROL);
8927 /* As we must carefully and slowly disable/enable each source in turn,
8928 * compute the final state we want first and check if we need to
8929 * make any changes at all.
8932 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8934 final |= DREF_NONSPREAD_CK505_ENABLE;
8936 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8938 final &= ~DREF_SSC_SOURCE_MASK;
8939 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8940 final &= ~DREF_SSC1_ENABLE;
8943 final |= DREF_SSC_SOURCE_ENABLE;
8945 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8946 final |= DREF_SSC1_ENABLE;
8949 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8950 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8952 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8954 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8955 } else if (using_ssc_source) {
8956 final |= DREF_SSC_SOURCE_ENABLE;
8957 final |= DREF_SSC1_ENABLE;
8963 /* Always enable nonspread source */
8964 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8967 val |= DREF_NONSPREAD_CK505_ENABLE;
8969 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8972 val &= ~DREF_SSC_SOURCE_MASK;
8973 val |= DREF_SSC_SOURCE_ENABLE;
8975 /* SSC must be turned on before enabling the CPU output */
8976 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8977 DRM_DEBUG_KMS("Using SSC on panel\n");
8978 val |= DREF_SSC1_ENABLE;
8980 val &= ~DREF_SSC1_ENABLE;
8982 /* Get SSC going before enabling the outputs */
8983 I915_WRITE(PCH_DREF_CONTROL, val);
8984 POSTING_READ(PCH_DREF_CONTROL);
8987 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8989 /* Enable CPU source on CPU attached eDP */
8991 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8992 DRM_DEBUG_KMS("Using SSC on eDP\n");
8993 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8995 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8997 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8999 I915_WRITE(PCH_DREF_CONTROL, val);
9000 POSTING_READ(PCH_DREF_CONTROL);
9003 DRM_DEBUG_KMS("Disabling CPU source output\n");
9005 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9007 /* Turn off CPU output */
9008 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9010 I915_WRITE(PCH_DREF_CONTROL, val);
9011 POSTING_READ(PCH_DREF_CONTROL);
9014 if (!using_ssc_source) {
9015 DRM_DEBUG_KMS("Disabling SSC source\n");
9017 /* Turn off the SSC source */
9018 val &= ~DREF_SSC_SOURCE_MASK;
9019 val |= DREF_SSC_SOURCE_DISABLE;
9022 val &= ~DREF_SSC1_ENABLE;
9024 I915_WRITE(PCH_DREF_CONTROL, val);
9025 POSTING_READ(PCH_DREF_CONTROL);
9030 BUG_ON(val != final);
9033 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9037 tmp = I915_READ(SOUTH_CHICKEN2);
9038 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9039 I915_WRITE(SOUTH_CHICKEN2, tmp);
9041 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9042 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9043 DRM_ERROR("FDI mPHY reset assert timeout\n");
9045 tmp = I915_READ(SOUTH_CHICKEN2);
9046 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9047 I915_WRITE(SOUTH_CHICKEN2, tmp);
9049 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9050 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9051 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9054 /* WaMPhyProgramming:hsw */
9055 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9059 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9060 tmp &= ~(0xFF << 24);
9061 tmp |= (0x12 << 24);
9062 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9064 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9066 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9068 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9070 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9072 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9073 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9074 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9076 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9077 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9078 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9080 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9083 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9085 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9088 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9090 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9093 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9095 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9098 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9100 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9101 tmp &= ~(0xFF << 16);
9102 tmp |= (0x1C << 16);
9103 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9105 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9106 tmp &= ~(0xFF << 16);
9107 tmp |= (0x1C << 16);
9108 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9110 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9112 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9114 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9116 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9118 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9119 tmp &= ~(0xF << 28);
9121 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9123 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9124 tmp &= ~(0xF << 28);
9126 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9129 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9130 * Programming" based on the parameters passed:
9131 * - Sequence to enable CLKOUT_DP
9132 * - Sequence to enable CLKOUT_DP without spread
9133 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9135 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9136 bool with_spread, bool with_fdi)
9140 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9142 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
9143 with_fdi, "LP PCH doesn't have FDI\n"))
9146 mutex_lock(&dev_priv->sb_lock);
9148 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9149 tmp &= ~SBI_SSCCTL_DISABLE;
9150 tmp |= SBI_SSCCTL_PATHALT;
9151 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9156 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9157 tmp &= ~SBI_SSCCTL_PATHALT;
9158 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9161 lpt_reset_fdi_mphy(dev_priv);
9162 lpt_program_fdi_mphy(dev_priv);
9166 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9167 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9168 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9169 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9171 mutex_unlock(&dev_priv->sb_lock);
9174 /* Sequence to disable CLKOUT_DP */
9175 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9179 mutex_lock(&dev_priv->sb_lock);
9181 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9182 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9183 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9184 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9186 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9187 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9188 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9189 tmp |= SBI_SSCCTL_PATHALT;
9190 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9193 tmp |= SBI_SSCCTL_DISABLE;
9194 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9197 mutex_unlock(&dev_priv->sb_lock);
9200 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9202 static const u16 sscdivintphase[] = {
9203 [BEND_IDX( 50)] = 0x3B23,
9204 [BEND_IDX( 45)] = 0x3B23,
9205 [BEND_IDX( 40)] = 0x3C23,
9206 [BEND_IDX( 35)] = 0x3C23,
9207 [BEND_IDX( 30)] = 0x3D23,
9208 [BEND_IDX( 25)] = 0x3D23,
9209 [BEND_IDX( 20)] = 0x3E23,
9210 [BEND_IDX( 15)] = 0x3E23,
9211 [BEND_IDX( 10)] = 0x3F23,
9212 [BEND_IDX( 5)] = 0x3F23,
9213 [BEND_IDX( 0)] = 0x0025,
9214 [BEND_IDX( -5)] = 0x0025,
9215 [BEND_IDX(-10)] = 0x0125,
9216 [BEND_IDX(-15)] = 0x0125,
9217 [BEND_IDX(-20)] = 0x0225,
9218 [BEND_IDX(-25)] = 0x0225,
9219 [BEND_IDX(-30)] = 0x0325,
9220 [BEND_IDX(-35)] = 0x0325,
9221 [BEND_IDX(-40)] = 0x0425,
9222 [BEND_IDX(-45)] = 0x0425,
9223 [BEND_IDX(-50)] = 0x0525,
9228 * steps -50 to 50 inclusive, in steps of 5
9229 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9230 * change in clock period = -(steps / 10) * 5.787 ps
9232 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9235 int idx = BEND_IDX(steps);
9237 if (WARN_ON(steps % 5 != 0))
9240 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9243 mutex_lock(&dev_priv->sb_lock);
9245 if (steps % 10 != 0)
9249 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9251 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9253 tmp |= sscdivintphase[idx];
9254 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9256 mutex_unlock(&dev_priv->sb_lock);
9261 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9263 u32 fuse_strap = I915_READ(FUSE_STRAP);
9264 u32 ctl = I915_READ(SPLL_CTL);
9266 if ((ctl & SPLL_PLL_ENABLE) == 0)
9269 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9270 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9273 if (IS_BROADWELL(dev_priv) &&
9274 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9280 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9281 enum intel_dpll_id id)
9283 u32 fuse_strap = I915_READ(FUSE_STRAP);
9284 u32 ctl = I915_READ(WRPLL_CTL(id));
9286 if ((ctl & WRPLL_PLL_ENABLE) == 0)
9289 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9292 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9293 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9294 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9300 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9302 struct intel_encoder *encoder;
9303 bool pch_ssc_in_use = false;
9304 bool has_fdi = false;
9306 for_each_intel_encoder(&dev_priv->drm, encoder) {
9307 switch (encoder->type) {
9308 case INTEL_OUTPUT_ANALOG:
9317 * The BIOS may have decided to use the PCH SSC
9318 * reference so we must not disable it until the
9319 * relevant PLLs have stopped relying on it. We'll
9320 * just leave the PCH SSC reference enabled in case
9321 * any active PLL is using it. It will get disabled
9322 * after runtime suspend if we don't have FDI.
9324 * TODO: Move the whole reference clock handling
9325 * to the modeset sequence proper so that we can
9326 * actually enable/disable/reconfigure these things
9327 * safely. To do that we need to introduce a real
9328 * clock hierarchy. That would also allow us to do
9329 * clock bending finally.
9331 if (spll_uses_pch_ssc(dev_priv)) {
9332 DRM_DEBUG_KMS("SPLL using PCH SSC\n");
9333 pch_ssc_in_use = true;
9336 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9337 DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
9338 pch_ssc_in_use = true;
9341 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9342 DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
9343 pch_ssc_in_use = true;
9350 lpt_bend_clkout_dp(dev_priv, 0);
9351 lpt_enable_clkout_dp(dev_priv, true, true);
9353 lpt_disable_clkout_dp(dev_priv);
9358 * Initialize reference clocks when the driver loads
9360 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
9362 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
9363 ironlake_init_pch_refclk(dev_priv);
9364 else if (HAS_PCH_LPT(dev_priv))
9365 lpt_init_pch_refclk(dev_priv);
9368 static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
9370 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9371 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9372 enum pipe pipe = crtc->pipe;
9377 switch (crtc_state->pipe_bpp) {
9379 val |= PIPECONF_6BPC;
9382 val |= PIPECONF_8BPC;
9385 val |= PIPECONF_10BPC;
9388 val |= PIPECONF_12BPC;
9391 /* Case prevented by intel_choose_pipe_bpp_dither. */
9395 if (crtc_state->dither)
9396 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9398 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9399 val |= PIPECONF_INTERLACED_ILK;
9401 val |= PIPECONF_PROGRESSIVE;
9403 if (crtc_state->limited_color_range)
9404 val |= PIPECONF_COLOR_RANGE_SELECT;
9406 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9408 I915_WRITE(PIPECONF(pipe), val);
9409 POSTING_READ(PIPECONF(pipe));
9412 static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
9414 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9416 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
9419 if (IS_HASWELL(dev_priv) && crtc_state->dither)
9420 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9422 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9423 val |= PIPECONF_INTERLACED_ILK;
9425 val |= PIPECONF_PROGRESSIVE;
9427 I915_WRITE(PIPECONF(cpu_transcoder), val);
9428 POSTING_READ(PIPECONF(cpu_transcoder));
9431 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
9433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9434 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9437 switch (crtc_state->pipe_bpp) {
9439 val |= PIPEMISC_DITHER_6_BPC;
9442 val |= PIPEMISC_DITHER_8_BPC;
9445 val |= PIPEMISC_DITHER_10_BPC;
9448 val |= PIPEMISC_DITHER_12_BPC;
9451 MISSING_CASE(crtc_state->pipe_bpp);
9455 if (crtc_state->dither)
9456 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9458 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
9459 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
9460 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
9462 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
9463 val |= PIPEMISC_YUV420_ENABLE |
9464 PIPEMISC_YUV420_MODE_FULL_BLEND;
9466 if (INTEL_GEN(dev_priv) >= 11 &&
9467 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
9468 BIT(PLANE_CURSOR))) == 0)
9469 val |= PIPEMISC_HDR_MODE_PRECISION;
9471 I915_WRITE(PIPEMISC(crtc->pipe), val);
9474 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
9476 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9479 tmp = I915_READ(PIPEMISC(crtc->pipe));
9481 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
9482 case PIPEMISC_DITHER_6_BPC:
9484 case PIPEMISC_DITHER_8_BPC:
9486 case PIPEMISC_DITHER_10_BPC:
9488 case PIPEMISC_DITHER_12_BPC:
9496 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9499 * Account for spread spectrum to avoid
9500 * oversubscribing the link. Max center spread
9501 * is 2.5%; use 5% for safety's sake.
9503 u32 bps = target_clock * bpp * 21 / 20;
9504 return DIV_ROUND_UP(bps, link_bw * 8);
9507 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9509 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9512 static void ironlake_compute_dpll(struct intel_crtc *crtc,
9513 struct intel_crtc_state *crtc_state,
9514 struct dpll *reduced_clock)
9516 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9520 /* Enable autotuning of the PLL clock (if permissible) */
9522 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9523 if ((intel_panel_use_ssc(dev_priv) &&
9524 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9525 (HAS_PCH_IBX(dev_priv) &&
9526 intel_is_dual_link_lvds(dev_priv)))
9528 } else if (crtc_state->sdvo_tv_clock) {
9532 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9534 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9537 if (reduced_clock) {
9538 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9540 if (reduced_clock->m < factor * reduced_clock->n)
9548 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9549 dpll |= DPLLB_MODE_LVDS;
9551 dpll |= DPLLB_MODE_DAC_SERIAL;
9553 dpll |= (crtc_state->pixel_multiplier - 1)
9554 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9556 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9557 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9558 dpll |= DPLL_SDVO_HIGH_SPEED;
9560 if (intel_crtc_has_dp_encoder(crtc_state))
9561 dpll |= DPLL_SDVO_HIGH_SPEED;
9564 * The high speed IO clock is only really required for
9565 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9566 * possible to share the DPLL between CRT and HDMI. Enabling
9567 * the clock needlessly does no real harm, except use up a
9568 * bit of power potentially.
9570 * We'll limit this to IVB with 3 pipes, since it has only two
9571 * DPLLs and so DPLL sharing is the only way to get three pipes
9572 * driving PCH ports at the same time. On SNB we could do this,
9573 * and potentially avoid enabling the second DPLL, but it's not
9574 * clear if it''s a win or loss power wise. No point in doing
9575 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9577 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9578 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9579 dpll |= DPLL_SDVO_HIGH_SPEED;
9581 /* compute bitmask from p1 value */
9582 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9584 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9586 switch (crtc_state->dpll.p2) {
9588 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9591 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9594 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9597 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9601 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9602 intel_panel_use_ssc(dev_priv))
9603 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9605 dpll |= PLL_REF_INPUT_DREFCLK;
9607 dpll |= DPLL_VCO_ENABLE;
9609 crtc_state->dpll_hw_state.dpll = dpll;
9610 crtc_state->dpll_hw_state.fp0 = fp;
9611 crtc_state->dpll_hw_state.fp1 = fp2;
9614 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9615 struct intel_crtc_state *crtc_state)
9617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9618 struct intel_atomic_state *state =
9619 to_intel_atomic_state(crtc_state->base.state);
9620 const struct intel_limit *limit;
9621 int refclk = 120000;
9623 memset(&crtc_state->dpll_hw_state, 0,
9624 sizeof(crtc_state->dpll_hw_state));
9626 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9627 if (!crtc_state->has_pch_encoder)
9630 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9631 if (intel_panel_use_ssc(dev_priv)) {
9632 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9633 dev_priv->vbt.lvds_ssc_freq);
9634 refclk = dev_priv->vbt.lvds_ssc_freq;
9637 if (intel_is_dual_link_lvds(dev_priv)) {
9638 if (refclk == 100000)
9639 limit = &intel_limits_ironlake_dual_lvds_100m;
9641 limit = &intel_limits_ironlake_dual_lvds;
9643 if (refclk == 100000)
9644 limit = &intel_limits_ironlake_single_lvds_100m;
9646 limit = &intel_limits_ironlake_single_lvds;
9649 limit = &intel_limits_ironlake_dac;
9652 if (!crtc_state->clock_set &&
9653 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9654 refclk, NULL, &crtc_state->dpll)) {
9655 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9659 ironlake_compute_dpll(crtc, crtc_state, NULL);
9661 if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9662 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9663 pipe_name(crtc->pipe));
9670 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9671 struct intel_link_m_n *m_n)
9673 struct drm_device *dev = crtc->base.dev;
9674 struct drm_i915_private *dev_priv = to_i915(dev);
9675 enum pipe pipe = crtc->pipe;
9677 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9678 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9679 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9681 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9682 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9683 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9686 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9687 enum transcoder transcoder,
9688 struct intel_link_m_n *m_n,
9689 struct intel_link_m_n *m2_n2)
9691 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9692 enum pipe pipe = crtc->pipe;
9694 if (INTEL_GEN(dev_priv) >= 5) {
9695 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9696 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9697 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9699 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9700 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9701 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9703 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
9704 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9705 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9706 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9708 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9709 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9710 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9713 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9714 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9715 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9717 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9718 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9719 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9723 void intel_dp_get_m_n(struct intel_crtc *crtc,
9724 struct intel_crtc_state *pipe_config)
9726 if (pipe_config->has_pch_encoder)
9727 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9729 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9730 &pipe_config->dp_m_n,
9731 &pipe_config->dp_m2_n2);
9734 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9735 struct intel_crtc_state *pipe_config)
9737 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9738 &pipe_config->fdi_m_n, NULL);
9741 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9742 struct intel_crtc_state *pipe_config)
9744 struct drm_device *dev = crtc->base.dev;
9745 struct drm_i915_private *dev_priv = to_i915(dev);
9746 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9751 /* find scaler attached to this pipe */
9752 for (i = 0; i < crtc->num_scalers; i++) {
9753 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9754 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9756 pipe_config->pch_pfit.enabled = true;
9757 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9758 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9759 scaler_state->scalers[i].in_use = true;
9764 scaler_state->scaler_id = id;
9766 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9768 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9773 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9774 struct intel_initial_plane_config *plane_config)
9776 struct drm_device *dev = crtc->base.dev;
9777 struct drm_i915_private *dev_priv = to_i915(dev);
9778 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9779 enum plane_id plane_id = plane->id;
9781 u32 val, base, offset, stride_mult, tiling, alpha;
9782 int fourcc, pixel_format;
9783 unsigned int aligned_height;
9784 struct drm_framebuffer *fb;
9785 struct intel_framebuffer *intel_fb;
9787 if (!plane->get_hw_state(plane, &pipe))
9790 WARN_ON(pipe != crtc->pipe);
9792 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9794 DRM_DEBUG_KMS("failed to alloc fb\n");
9798 fb = &intel_fb->base;
9802 val = I915_READ(PLANE_CTL(pipe, plane_id));
9804 if (INTEL_GEN(dev_priv) >= 11)
9805 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
9807 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9809 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
9810 alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
9811 alpha &= PLANE_COLOR_ALPHA_MASK;
9813 alpha = val & PLANE_CTL_ALPHA_MASK;
9816 fourcc = skl_format_to_fourcc(pixel_format,
9817 val & PLANE_CTL_ORDER_RGBX, alpha);
9818 fb->format = drm_format_info(fourcc);
9820 tiling = val & PLANE_CTL_TILED_MASK;
9822 case PLANE_CTL_TILED_LINEAR:
9823 fb->modifier = DRM_FORMAT_MOD_LINEAR;
9825 case PLANE_CTL_TILED_X:
9826 plane_config->tiling = I915_TILING_X;
9827 fb->modifier = I915_FORMAT_MOD_X_TILED;
9829 case PLANE_CTL_TILED_Y:
9830 plane_config->tiling = I915_TILING_Y;
9831 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9832 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
9834 fb->modifier = I915_FORMAT_MOD_Y_TILED;
9836 case PLANE_CTL_TILED_YF:
9837 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
9838 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
9840 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
9843 MISSING_CASE(tiling);
9848 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
9849 * while i915 HW rotation is clockwise, thats why this swapping.
9851 switch (val & PLANE_CTL_ROTATE_MASK) {
9852 case PLANE_CTL_ROTATE_0:
9853 plane_config->rotation = DRM_MODE_ROTATE_0;
9855 case PLANE_CTL_ROTATE_90:
9856 plane_config->rotation = DRM_MODE_ROTATE_270;
9858 case PLANE_CTL_ROTATE_180:
9859 plane_config->rotation = DRM_MODE_ROTATE_180;
9861 case PLANE_CTL_ROTATE_270:
9862 plane_config->rotation = DRM_MODE_ROTATE_90;
9866 if (INTEL_GEN(dev_priv) >= 10 &&
9867 val & PLANE_CTL_FLIP_HORIZONTAL)
9868 plane_config->rotation |= DRM_MODE_REFLECT_X;
9870 base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
9871 plane_config->base = base;
9873 offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
9875 val = I915_READ(PLANE_SIZE(pipe, plane_id));
9876 fb->height = ((val >> 16) & 0xfff) + 1;
9877 fb->width = ((val >> 0) & 0x1fff) + 1;
9879 val = I915_READ(PLANE_STRIDE(pipe, plane_id));
9880 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
9881 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9883 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9885 plane_config->size = fb->pitches[0] * aligned_height;
9887 DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9888 crtc->base.name, plane->base.name, fb->width, fb->height,
9889 fb->format->cpp[0] * 8, base, fb->pitches[0],
9890 plane_config->size);
9892 plane_config->fb = intel_fb;
9899 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9900 struct intel_crtc_state *pipe_config)
9902 struct drm_device *dev = crtc->base.dev;
9903 struct drm_i915_private *dev_priv = to_i915(dev);
9906 tmp = I915_READ(PF_CTL(crtc->pipe));
9908 if (tmp & PF_ENABLE) {
9909 pipe_config->pch_pfit.enabled = true;
9910 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9911 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9913 /* We currently do not free assignements of panel fitters on
9914 * ivb/hsw (since we don't use the higher upscaling modes which
9915 * differentiates them) so just WARN about this case for now. */
9916 if (IS_GEN(dev_priv, 7)) {
9917 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9918 PF_PIPE_SEL_IVB(crtc->pipe));
9923 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9924 struct intel_crtc_state *pipe_config)
9926 struct drm_device *dev = crtc->base.dev;
9927 struct drm_i915_private *dev_priv = to_i915(dev);
9928 enum intel_display_power_domain power_domain;
9929 intel_wakeref_t wakeref;
9933 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9934 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9938 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9939 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9940 pipe_config->shared_dpll = NULL;
9943 tmp = I915_READ(PIPECONF(crtc->pipe));
9944 if (!(tmp & PIPECONF_ENABLE))
9947 switch (tmp & PIPECONF_BPC_MASK) {
9949 pipe_config->pipe_bpp = 18;
9952 pipe_config->pipe_bpp = 24;
9954 case PIPECONF_10BPC:
9955 pipe_config->pipe_bpp = 30;
9957 case PIPECONF_12BPC:
9958 pipe_config->pipe_bpp = 36;
9964 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9965 pipe_config->limited_color_range = true;
9967 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
9968 PIPECONF_GAMMA_MODE_SHIFT;
9970 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
9972 i9xx_get_pipe_color_config(pipe_config);
9973 intel_color_get_config(pipe_config);
9975 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9976 struct intel_shared_dpll *pll;
9977 enum intel_dpll_id pll_id;
9979 pipe_config->has_pch_encoder = true;
9981 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9982 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9983 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9985 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9987 if (HAS_PCH_IBX(dev_priv)) {
9989 * The pipe->pch transcoder and pch transcoder->pll
9992 pll_id = (enum intel_dpll_id) crtc->pipe;
9994 tmp = I915_READ(PCH_DPLL_SEL);
9995 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9996 pll_id = DPLL_ID_PCH_PLL_B;
9998 pll_id= DPLL_ID_PCH_PLL_A;
10001 pipe_config->shared_dpll =
10002 intel_get_shared_dpll_by_id(dev_priv, pll_id);
10003 pll = pipe_config->shared_dpll;
10005 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10006 &pipe_config->dpll_hw_state));
10008 tmp = pipe_config->dpll_hw_state.dpll;
10009 pipe_config->pixel_multiplier =
10010 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10011 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10013 ironlake_pch_clock_get(crtc, pipe_config);
10015 pipe_config->pixel_multiplier = 1;
10018 intel_get_pipe_timings(crtc, pipe_config);
10019 intel_get_pipe_src_size(crtc, pipe_config);
10021 ironlake_get_pfit_config(crtc, pipe_config);
10026 intel_display_power_put(dev_priv, power_domain, wakeref);
10030 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10031 struct intel_crtc_state *crtc_state)
10033 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10034 struct intel_atomic_state *state =
10035 to_intel_atomic_state(crtc_state->base.state);
10037 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10038 INTEL_GEN(dev_priv) >= 11) {
10039 struct intel_encoder *encoder =
10040 intel_get_crtc_new_encoder(state, crtc_state);
10042 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10043 DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
10044 pipe_name(crtc->pipe));
10052 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
10054 struct intel_crtc_state *pipe_config)
10056 enum intel_dpll_id id;
10059 temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10060 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10062 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
10065 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10068 static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
10070 struct intel_crtc_state *pipe_config)
10072 enum phy phy = intel_port_to_phy(dev_priv, port);
10073 enum icl_port_dpll_id port_dpll_id;
10074 enum intel_dpll_id id;
10077 if (intel_phy_is_combo(dev_priv, phy)) {
10078 temp = I915_READ(ICL_DPCLKA_CFGCR0) &
10079 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10080 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10081 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10082 } else if (intel_phy_is_tc(dev_priv, phy)) {
10083 u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10085 if (clk_sel == DDI_CLK_SEL_MG) {
10086 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10088 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10090 WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
10091 id = DPLL_ID_ICL_TBTPLL;
10092 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10095 WARN(1, "Invalid port %x\n", port);
10099 pipe_config->icl_port_dplls[port_dpll_id].pll =
10100 intel_get_shared_dpll_by_id(dev_priv, id);
10102 icl_set_active_port_dpll(pipe_config, port_dpll_id);
10105 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10107 struct intel_crtc_state *pipe_config)
10109 enum intel_dpll_id id;
10113 id = DPLL_ID_SKL_DPLL0;
10116 id = DPLL_ID_SKL_DPLL1;
10119 id = DPLL_ID_SKL_DPLL2;
10122 DRM_ERROR("Incorrect port type\n");
10126 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10129 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10131 struct intel_crtc_state *pipe_config)
10133 enum intel_dpll_id id;
10136 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10137 id = temp >> (port * 3 + 1);
10139 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10142 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10145 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10147 struct intel_crtc_state *pipe_config)
10149 enum intel_dpll_id id;
10150 u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10152 switch (ddi_pll_sel) {
10153 case PORT_CLK_SEL_WRPLL1:
10154 id = DPLL_ID_WRPLL1;
10156 case PORT_CLK_SEL_WRPLL2:
10157 id = DPLL_ID_WRPLL2;
10159 case PORT_CLK_SEL_SPLL:
10162 case PORT_CLK_SEL_LCPLL_810:
10163 id = DPLL_ID_LCPLL_810;
10165 case PORT_CLK_SEL_LCPLL_1350:
10166 id = DPLL_ID_LCPLL_1350;
10168 case PORT_CLK_SEL_LCPLL_2700:
10169 id = DPLL_ID_LCPLL_2700;
10172 MISSING_CASE(ddi_pll_sel);
10174 case PORT_CLK_SEL_NONE:
10178 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10181 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10182 struct intel_crtc_state *pipe_config,
10183 u64 *power_domain_mask,
10184 intel_wakeref_t *wakerefs)
10186 struct drm_device *dev = crtc->base.dev;
10187 struct drm_i915_private *dev_priv = to_i915(dev);
10188 enum intel_display_power_domain power_domain;
10189 unsigned long panel_transcoder_mask = 0;
10190 unsigned long enabled_panel_transcoders = 0;
10191 enum transcoder panel_transcoder;
10192 intel_wakeref_t wf;
10195 if (INTEL_GEN(dev_priv) >= 11)
10196 panel_transcoder_mask |=
10197 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10199 if (HAS_TRANSCODER_EDP(dev_priv))
10200 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10203 * The pipe->transcoder mapping is fixed with the exception of the eDP
10204 * and DSI transcoders handled below.
10206 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10209 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10210 * consistency and less surprising code; it's in always on power).
10212 for_each_set_bit(panel_transcoder,
10213 &panel_transcoder_mask,
10214 ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10215 bool force_thru = false;
10216 enum pipe trans_pipe;
10218 tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder));
10219 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10223 * Log all enabled ones, only use the first one.
10225 * FIXME: This won't work for two separate DSI displays.
10227 enabled_panel_transcoders |= BIT(panel_transcoder);
10228 if (enabled_panel_transcoders != BIT(panel_transcoder))
10231 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10233 WARN(1, "unknown pipe linked to transcoder %s\n",
10234 transcoder_name(panel_transcoder));
10236 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10239 case TRANS_DDI_EDP_INPUT_A_ON:
10240 trans_pipe = PIPE_A;
10242 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10243 trans_pipe = PIPE_B;
10245 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10246 trans_pipe = PIPE_C;
10250 if (trans_pipe == crtc->pipe) {
10251 pipe_config->cpu_transcoder = panel_transcoder;
10252 pipe_config->pch_pfit.force_thru = force_thru;
10257 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10259 WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10260 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10262 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10263 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10265 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10269 wakerefs[power_domain] = wf;
10270 *power_domain_mask |= BIT_ULL(power_domain);
10272 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10274 return tmp & PIPECONF_ENABLE;
10277 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10278 struct intel_crtc_state *pipe_config,
10279 u64 *power_domain_mask,
10280 intel_wakeref_t *wakerefs)
10282 struct drm_device *dev = crtc->base.dev;
10283 struct drm_i915_private *dev_priv = to_i915(dev);
10284 enum intel_display_power_domain power_domain;
10285 enum transcoder cpu_transcoder;
10286 intel_wakeref_t wf;
10290 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10291 if (port == PORT_A)
10292 cpu_transcoder = TRANSCODER_DSI_A;
10294 cpu_transcoder = TRANSCODER_DSI_C;
10296 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10297 WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
10299 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10303 wakerefs[power_domain] = wf;
10304 *power_domain_mask |= BIT_ULL(power_domain);
10307 * The PLL needs to be enabled with a valid divider
10308 * configuration, otherwise accessing DSI registers will hang
10309 * the machine. See BSpec North Display Engine
10310 * registers/MIPI[BXT]. We can break out here early, since we
10311 * need the same DSI PLL to be enabled for both DSI ports.
10313 if (!bxt_dsi_pll_is_enabled(dev_priv))
10316 /* XXX: this works for video mode only */
10317 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10318 if (!(tmp & DPI_ENABLE))
10321 tmp = I915_READ(MIPI_CTRL(port));
10322 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10325 pipe_config->cpu_transcoder = cpu_transcoder;
10329 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10332 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10333 struct intel_crtc_state *pipe_config)
10335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10336 struct intel_shared_dpll *pll;
10340 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10342 if (INTEL_GEN(dev_priv) >= 12)
10343 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10345 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
10347 if (INTEL_GEN(dev_priv) >= 11)
10348 icelake_get_ddi_pll(dev_priv, port, pipe_config);
10349 else if (IS_CANNONLAKE(dev_priv))
10350 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
10351 else if (IS_GEN9_BC(dev_priv))
10352 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10353 else if (IS_GEN9_LP(dev_priv))
10354 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10356 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10358 pll = pipe_config->shared_dpll;
10360 WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
10361 &pipe_config->dpll_hw_state));
10365 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10366 * DDI E. So just check whether this pipe is wired to DDI E and whether
10367 * the PCH transcoder is on.
10369 if (INTEL_GEN(dev_priv) < 9 &&
10370 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10371 pipe_config->has_pch_encoder = true;
10373 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10374 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10375 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10377 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10381 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10382 struct intel_crtc_state *pipe_config)
10384 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10385 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
10386 enum intel_display_power_domain power_domain;
10387 u64 power_domain_mask;
10390 intel_crtc_init_scalers(crtc, pipe_config);
10392 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10393 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10397 wakerefs[power_domain] = wf;
10398 power_domain_mask = BIT_ULL(power_domain);
10400 pipe_config->shared_dpll = NULL;
10402 active = hsw_get_transcoder_state(crtc, pipe_config,
10403 &power_domain_mask, wakerefs);
10405 if (IS_GEN9_LP(dev_priv) &&
10406 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10407 &power_domain_mask, wakerefs)) {
10415 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
10416 INTEL_GEN(dev_priv) >= 11) {
10417 haswell_get_ddi_port_state(crtc, pipe_config);
10418 intel_get_pipe_timings(crtc, pipe_config);
10421 intel_get_pipe_src_size(crtc, pipe_config);
10422 intel_get_crtc_ycbcr_config(crtc, pipe_config);
10424 pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
10426 pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
10428 if (INTEL_GEN(dev_priv) >= 9) {
10429 u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
10431 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
10432 pipe_config->gamma_enable = true;
10434 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
10435 pipe_config->csc_enable = true;
10437 i9xx_get_pipe_color_config(pipe_config);
10440 intel_color_get_config(pipe_config);
10442 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10443 WARN_ON(power_domain_mask & BIT_ULL(power_domain));
10445 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10447 wakerefs[power_domain] = wf;
10448 power_domain_mask |= BIT_ULL(power_domain);
10450 if (INTEL_GEN(dev_priv) >= 9)
10451 skylake_get_pfit_config(crtc, pipe_config);
10453 ironlake_get_pfit_config(crtc, pipe_config);
10456 if (hsw_crtc_supports_ips(crtc)) {
10457 if (IS_HASWELL(dev_priv))
10458 pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
10461 * We cannot readout IPS state on broadwell, set to
10462 * true so we can set it to a defined state on first
10465 pipe_config->ips_enabled = true;
10469 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10470 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10471 pipe_config->pixel_multiplier =
10472 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10474 pipe_config->pixel_multiplier = 1;
10478 for_each_power_domain(power_domain, power_domain_mask)
10479 intel_display_power_put(dev_priv,
10480 power_domain, wakerefs[power_domain]);
10485 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
10487 struct drm_i915_private *dev_priv =
10488 to_i915(plane_state->base.plane->dev);
10489 const struct drm_framebuffer *fb = plane_state->base.fb;
10490 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10493 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
10494 base = obj->phys_handle->busaddr;
10496 base = intel_plane_ggtt_offset(plane_state);
10498 base += plane_state->color_plane[0].offset;
10500 /* ILK+ do this automagically */
10501 if (HAS_GMCH(dev_priv) &&
10502 plane_state->base.rotation & DRM_MODE_ROTATE_180)
10503 base += (plane_state->base.crtc_h *
10504 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
10509 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
10511 int x = plane_state->base.crtc_x;
10512 int y = plane_state->base.crtc_y;
10516 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10519 pos |= x << CURSOR_X_SHIFT;
10522 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10525 pos |= y << CURSOR_Y_SHIFT;
10530 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
10532 const struct drm_mode_config *config =
10533 &plane_state->base.plane->dev->mode_config;
10534 int width = plane_state->base.crtc_w;
10535 int height = plane_state->base.crtc_h;
10537 return width > 0 && width <= config->cursor_width &&
10538 height > 0 && height <= config->cursor_height;
10541 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
10547 ret = intel_plane_compute_gtt(plane_state);
10551 if (!plane_state->base.visible)
10554 src_x = plane_state->base.src_x >> 16;
10555 src_y = plane_state->base.src_y >> 16;
10557 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
10558 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
10561 if (src_x != 0 || src_y != 0) {
10562 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
10566 plane_state->color_plane[0].offset = offset;
10571 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
10572 struct intel_plane_state *plane_state)
10574 const struct drm_framebuffer *fb = plane_state->base.fb;
10577 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
10578 DRM_DEBUG_KMS("cursor cannot be tiled\n");
10582 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
10584 DRM_PLANE_HELPER_NO_SCALING,
10585 DRM_PLANE_HELPER_NO_SCALING,
10590 ret = intel_cursor_check_surface(plane_state);
10594 if (!plane_state->base.visible)
10597 ret = intel_plane_check_src_coordinates(plane_state);
10604 static unsigned int
10605 i845_cursor_max_stride(struct intel_plane *plane,
10606 u32 pixel_format, u64 modifier,
10607 unsigned int rotation)
10612 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10616 if (crtc_state->gamma_enable)
10617 cntl |= CURSOR_GAMMA_ENABLE;
10622 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
10623 const struct intel_plane_state *plane_state)
10625 return CURSOR_ENABLE |
10626 CURSOR_FORMAT_ARGB |
10627 CURSOR_STRIDE(plane_state->color_plane[0].stride);
10630 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
10632 int width = plane_state->base.crtc_w;
10635 * 845g/865g are only limited by the width of their cursors,
10636 * the height is arbitrary up to the precision of the register.
10638 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
10641 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
10642 struct intel_plane_state *plane_state)
10644 const struct drm_framebuffer *fb = plane_state->base.fb;
10647 ret = intel_check_cursor(crtc_state, plane_state);
10651 /* if we want to turn off the cursor ignore width and height */
10655 /* Check for which cursor types we support */
10656 if (!i845_cursor_size_ok(plane_state)) {
10657 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10658 plane_state->base.crtc_w,
10659 plane_state->base.crtc_h);
10663 WARN_ON(plane_state->base.visible &&
10664 plane_state->color_plane[0].stride != fb->pitches[0]);
10666 switch (fb->pitches[0]) {
10673 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
10678 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
10683 static void i845_update_cursor(struct intel_plane *plane,
10684 const struct intel_crtc_state *crtc_state,
10685 const struct intel_plane_state *plane_state)
10687 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10688 u32 cntl = 0, base = 0, pos = 0, size = 0;
10689 unsigned long irqflags;
10691 if (plane_state && plane_state->base.visible) {
10692 unsigned int width = plane_state->base.crtc_w;
10693 unsigned int height = plane_state->base.crtc_h;
10695 cntl = plane_state->ctl |
10696 i845_cursor_ctl_crtc(crtc_state);
10698 size = (height << 12) | width;
10700 base = intel_cursor_base(plane_state);
10701 pos = intel_cursor_position(plane_state);
10704 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10706 /* On these chipsets we can only modify the base/size/stride
10707 * whilst the cursor is disabled.
10709 if (plane->cursor.base != base ||
10710 plane->cursor.size != size ||
10711 plane->cursor.cntl != cntl) {
10712 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
10713 I915_WRITE_FW(CURBASE(PIPE_A), base);
10714 I915_WRITE_FW(CURSIZE, size);
10715 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10716 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
10718 plane->cursor.base = base;
10719 plane->cursor.size = size;
10720 plane->cursor.cntl = cntl;
10722 I915_WRITE_FW(CURPOS(PIPE_A), pos);
10725 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10728 static void i845_disable_cursor(struct intel_plane *plane,
10729 const struct intel_crtc_state *crtc_state)
10731 i845_update_cursor(plane, crtc_state, NULL);
10734 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
10737 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10738 enum intel_display_power_domain power_domain;
10739 intel_wakeref_t wakeref;
10742 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
10743 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10747 ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
10751 intel_display_power_put(dev_priv, power_domain, wakeref);
10756 static unsigned int
10757 i9xx_cursor_max_stride(struct intel_plane *plane,
10758 u32 pixel_format, u64 modifier,
10759 unsigned int rotation)
10761 return plane->base.dev->mode_config.cursor_width * 4;
10764 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
10766 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
10767 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10770 if (INTEL_GEN(dev_priv) >= 11)
10773 if (crtc_state->gamma_enable)
10774 cntl = MCURSOR_GAMMA_ENABLE;
10776 if (crtc_state->csc_enable)
10777 cntl |= MCURSOR_PIPE_CSC_ENABLE;
10779 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10780 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
10785 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
10786 const struct intel_plane_state *plane_state)
10788 struct drm_i915_private *dev_priv =
10789 to_i915(plane_state->base.plane->dev);
10792 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
10793 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
10795 switch (plane_state->base.crtc_w) {
10797 cntl |= MCURSOR_MODE_64_ARGB_AX;
10800 cntl |= MCURSOR_MODE_128_ARGB_AX;
10803 cntl |= MCURSOR_MODE_256_ARGB_AX;
10806 MISSING_CASE(plane_state->base.crtc_w);
10810 if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
10811 cntl |= MCURSOR_ROTATE_180;
10816 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
10818 struct drm_i915_private *dev_priv =
10819 to_i915(plane_state->base.plane->dev);
10820 int width = plane_state->base.crtc_w;
10821 int height = plane_state->base.crtc_h;
10823 if (!intel_cursor_size_ok(plane_state))
10826 /* Cursor width is limited to a few power-of-two sizes */
10837 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
10838 * height from 8 lines up to the cursor width, when the
10839 * cursor is not rotated. Everything else requires square
10842 if (HAS_CUR_FBC(dev_priv) &&
10843 plane_state->base.rotation & DRM_MODE_ROTATE_0) {
10844 if (height < 8 || height > width)
10847 if (height != width)
10854 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
10855 struct intel_plane_state *plane_state)
10857 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
10858 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10859 const struct drm_framebuffer *fb = plane_state->base.fb;
10860 enum pipe pipe = plane->pipe;
10863 ret = intel_check_cursor(crtc_state, plane_state);
10867 /* if we want to turn off the cursor ignore width and height */
10871 /* Check for which cursor types we support */
10872 if (!i9xx_cursor_size_ok(plane_state)) {
10873 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
10874 plane_state->base.crtc_w,
10875 plane_state->base.crtc_h);
10879 WARN_ON(plane_state->base.visible &&
10880 plane_state->color_plane[0].stride != fb->pitches[0]);
10882 if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
10883 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
10884 fb->pitches[0], plane_state->base.crtc_w);
10889 * There's something wrong with the cursor on CHV pipe C.
10890 * If it straddles the left edge of the screen then
10891 * moving it away from the edge or disabling it often
10892 * results in a pipe underrun, and often that can lead to
10893 * dead pipe (constant underrun reported, and it scans
10894 * out just a solid color). To recover from that, the
10895 * display power well must be turned off and on again.
10896 * Refuse the put the cursor into that compromised position.
10898 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
10899 plane_state->base.visible && plane_state->base.crtc_x < 0) {
10900 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
10904 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
10909 static void i9xx_update_cursor(struct intel_plane *plane,
10910 const struct intel_crtc_state *crtc_state,
10911 const struct intel_plane_state *plane_state)
10913 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10914 enum pipe pipe = plane->pipe;
10915 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
10916 unsigned long irqflags;
10918 if (plane_state && plane_state->base.visible) {
10919 cntl = plane_state->ctl |
10920 i9xx_cursor_ctl_crtc(crtc_state);
10922 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
10923 fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
10925 base = intel_cursor_base(plane_state);
10926 pos = intel_cursor_position(plane_state);
10929 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
10932 * On some platforms writing CURCNTR first will also
10933 * cause CURPOS to be armed by the CURBASE write.
10934 * Without the CURCNTR write the CURPOS write would
10935 * arm itself. Thus we always update CURCNTR before
10938 * On other platforms CURPOS always requires the
10939 * CURBASE write to arm the update. Additonally
10940 * a write to any of the cursor register will cancel
10941 * an already armed cursor update. Thus leaving out
10942 * the CURBASE write after CURPOS could lead to a
10943 * cursor that doesn't appear to move, or even change
10944 * shape. Thus we always write CURBASE.
10946 * The other registers are armed by by the CURBASE write
10947 * except when the plane is getting enabled at which time
10948 * the CURCNTR write arms the update.
10951 if (INTEL_GEN(dev_priv) >= 9)
10952 skl_write_cursor_wm(plane, crtc_state);
10954 if (plane->cursor.base != base ||
10955 plane->cursor.size != fbc_ctl ||
10956 plane->cursor.cntl != cntl) {
10957 if (HAS_CUR_FBC(dev_priv))
10958 I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
10959 I915_WRITE_FW(CURCNTR(pipe), cntl);
10960 I915_WRITE_FW(CURPOS(pipe), pos);
10961 I915_WRITE_FW(CURBASE(pipe), base);
10963 plane->cursor.base = base;
10964 plane->cursor.size = fbc_ctl;
10965 plane->cursor.cntl = cntl;
10967 I915_WRITE_FW(CURPOS(pipe), pos);
10968 I915_WRITE_FW(CURBASE(pipe), base);
10971 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
10974 static void i9xx_disable_cursor(struct intel_plane *plane,
10975 const struct intel_crtc_state *crtc_state)
10977 i9xx_update_cursor(plane, crtc_state, NULL);
10980 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
10983 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10984 enum intel_display_power_domain power_domain;
10985 intel_wakeref_t wakeref;
10990 * Not 100% correct for planes that can move between pipes,
10991 * but that's only the case for gen2-3 which don't have any
10992 * display power wells.
10994 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
10995 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10999 val = I915_READ(CURCNTR(plane->pipe));
11001 ret = val & MCURSOR_MODE;
11003 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11004 *pipe = plane->pipe;
11006 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11007 MCURSOR_PIPE_SELECT_SHIFT;
11009 intel_display_power_put(dev_priv, power_domain, wakeref);
11014 /* VESA 640x480x72Hz mode to set on the pipe */
11015 static const struct drm_display_mode load_detect_mode = {
11016 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11017 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11020 struct drm_framebuffer *
11021 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11022 struct drm_mode_fb_cmd2 *mode_cmd)
11024 struct intel_framebuffer *intel_fb;
11027 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11029 return ERR_PTR(-ENOMEM);
11031 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11035 return &intel_fb->base;
11039 return ERR_PTR(ret);
11042 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11043 struct drm_crtc *crtc)
11045 struct drm_plane *plane;
11046 struct drm_plane_state *plane_state;
11049 ret = drm_atomic_add_affected_planes(state, crtc);
11053 for_each_new_plane_in_state(state, plane, plane_state, i) {
11054 if (plane_state->crtc != crtc)
11057 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11061 drm_atomic_set_fb_for_plane(plane_state, NULL);
11067 int intel_get_load_detect_pipe(struct drm_connector *connector,
11068 const struct drm_display_mode *mode,
11069 struct intel_load_detect_pipe *old,
11070 struct drm_modeset_acquire_ctx *ctx)
11072 struct intel_crtc *intel_crtc;
11073 struct intel_encoder *intel_encoder =
11074 intel_attached_encoder(connector);
11075 struct drm_crtc *possible_crtc;
11076 struct drm_encoder *encoder = &intel_encoder->base;
11077 struct drm_crtc *crtc = NULL;
11078 struct drm_device *dev = encoder->dev;
11079 struct drm_i915_private *dev_priv = to_i915(dev);
11080 struct drm_mode_config *config = &dev->mode_config;
11081 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11082 struct drm_connector_state *connector_state;
11083 struct intel_crtc_state *crtc_state;
11086 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11087 connector->base.id, connector->name,
11088 encoder->base.id, encoder->name);
11090 old->restore_state = NULL;
11092 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
11095 * Algorithm gets a little messy:
11097 * - if the connector already has an assigned crtc, use it (but make
11098 * sure it's on first)
11100 * - try to find the first unused crtc that can drive this connector,
11101 * and use that if we find one
11104 /* See if we already have a CRTC for this connector */
11105 if (connector->state->crtc) {
11106 crtc = connector->state->crtc;
11108 ret = drm_modeset_lock(&crtc->mutex, ctx);
11112 /* Make sure the crtc and connector are running */
11116 /* Find an unused one (if possible) */
11117 for_each_crtc(dev, possible_crtc) {
11119 if (!(encoder->possible_crtcs & (1 << i)))
11122 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11126 if (possible_crtc->state->enable) {
11127 drm_modeset_unlock(&possible_crtc->mutex);
11131 crtc = possible_crtc;
11136 * If we didn't find an unused CRTC, don't use any.
11139 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11145 intel_crtc = to_intel_crtc(crtc);
11147 state = drm_atomic_state_alloc(dev);
11148 restore_state = drm_atomic_state_alloc(dev);
11149 if (!state || !restore_state) {
11154 state->acquire_ctx = ctx;
11155 restore_state->acquire_ctx = ctx;
11157 connector_state = drm_atomic_get_connector_state(state, connector);
11158 if (IS_ERR(connector_state)) {
11159 ret = PTR_ERR(connector_state);
11163 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11167 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11168 if (IS_ERR(crtc_state)) {
11169 ret = PTR_ERR(crtc_state);
11173 crtc_state->base.active = crtc_state->base.enable = true;
11176 mode = &load_detect_mode;
11178 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11182 ret = intel_modeset_disable_planes(state, crtc);
11186 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11188 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11190 ret = drm_atomic_add_affected_planes(restore_state, crtc);
11192 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11196 ret = drm_atomic_commit(state);
11198 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11202 old->restore_state = restore_state;
11203 drm_atomic_state_put(state);
11205 /* let the connector get through one full cycle before testing */
11206 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
11211 drm_atomic_state_put(state);
11214 if (restore_state) {
11215 drm_atomic_state_put(restore_state);
11216 restore_state = NULL;
11219 if (ret == -EDEADLK)
11225 void intel_release_load_detect_pipe(struct drm_connector *connector,
11226 struct intel_load_detect_pipe *old,
11227 struct drm_modeset_acquire_ctx *ctx)
11229 struct intel_encoder *intel_encoder =
11230 intel_attached_encoder(connector);
11231 struct drm_encoder *encoder = &intel_encoder->base;
11232 struct drm_atomic_state *state = old->restore_state;
11235 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11236 connector->base.id, connector->name,
11237 encoder->base.id, encoder->name);
11242 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
11244 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11245 drm_atomic_state_put(state);
11248 static int i9xx_pll_refclk(struct drm_device *dev,
11249 const struct intel_crtc_state *pipe_config)
11251 struct drm_i915_private *dev_priv = to_i915(dev);
11252 u32 dpll = pipe_config->dpll_hw_state.dpll;
11254 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11255 return dev_priv->vbt.lvds_ssc_freq;
11256 else if (HAS_PCH_SPLIT(dev_priv))
11258 else if (!IS_GEN(dev_priv, 2))
11264 /* Returns the clock of the currently programmed mode of the given pipe. */
11265 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11266 struct intel_crtc_state *pipe_config)
11268 struct drm_device *dev = crtc->base.dev;
11269 struct drm_i915_private *dev_priv = to_i915(dev);
11270 enum pipe pipe = crtc->pipe;
11271 u32 dpll = pipe_config->dpll_hw_state.dpll;
11275 int refclk = i9xx_pll_refclk(dev, pipe_config);
11277 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11278 fp = pipe_config->dpll_hw_state.fp0;
11280 fp = pipe_config->dpll_hw_state.fp1;
11282 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11283 if (IS_PINEVIEW(dev_priv)) {
11284 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11285 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11287 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11288 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11291 if (!IS_GEN(dev_priv, 2)) {
11292 if (IS_PINEVIEW(dev_priv))
11293 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11294 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11296 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11297 DPLL_FPA01_P1_POST_DIV_SHIFT);
11299 switch (dpll & DPLL_MODE_MASK) {
11300 case DPLLB_MODE_DAC_SERIAL:
11301 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11304 case DPLLB_MODE_LVDS:
11305 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11309 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11310 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11314 if (IS_PINEVIEW(dev_priv))
11315 port_clock = pnv_calc_dpll_params(refclk, &clock);
11317 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11319 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
11320 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11323 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11324 DPLL_FPA01_P1_POST_DIV_SHIFT);
11326 if (lvds & LVDS_CLKB_POWER_UP)
11331 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11334 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11335 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11337 if (dpll & PLL_P2_DIVIDE_BY_4)
11343 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11347 * This value includes pixel_multiplier. We will use
11348 * port_clock to compute adjusted_mode.crtc_clock in the
11349 * encoder's get_config() function.
11351 pipe_config->port_clock = port_clock;
11354 int intel_dotclock_calculate(int link_freq,
11355 const struct intel_link_m_n *m_n)
11358 * The calculation for the data clock is:
11359 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11360 * But we want to avoid losing precison if possible, so:
11361 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11363 * and the link clock is simpler:
11364 * link_clock = (m * link_clock) / n
11370 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
11373 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11374 struct intel_crtc_state *pipe_config)
11376 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11378 /* read out port_clock from the DPLL */
11379 i9xx_crtc_clock_get(crtc, pipe_config);
11382 * In case there is an active pipe without active ports,
11383 * we may need some idea for the dotclock anyway.
11384 * Calculate one based on the FDI configuration.
11386 pipe_config->base.adjusted_mode.crtc_clock =
11387 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11388 &pipe_config->fdi_m_n);
11391 /* Returns the currently programmed mode of the given encoder. */
11392 struct drm_display_mode *
11393 intel_encoder_current_mode(struct intel_encoder *encoder)
11395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11396 struct intel_crtc_state *crtc_state;
11397 struct drm_display_mode *mode;
11398 struct intel_crtc *crtc;
11401 if (!encoder->get_hw_state(encoder, &pipe))
11404 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
11406 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11410 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
11416 crtc_state->base.crtc = &crtc->base;
11418 if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
11424 encoder->get_config(encoder, crtc_state);
11426 intel_mode_from_pipe_config(mode, crtc_state);
11433 static void intel_crtc_destroy(struct drm_crtc *crtc)
11435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11437 drm_crtc_cleanup(crtc);
11442 * intel_wm_need_update - Check whether watermarks need updating
11443 * @cur: current plane state
11444 * @new: new plane state
11446 * Check current plane state versus the new one to determine whether
11447 * watermarks need to be recalculated.
11449 * Returns true or false.
11451 static bool intel_wm_need_update(const struct intel_plane_state *cur,
11452 struct intel_plane_state *new)
11454 /* Update watermarks on tiling or size changes. */
11455 if (new->base.visible != cur->base.visible)
11458 if (!cur->base.fb || !new->base.fb)
11461 if (cur->base.fb->modifier != new->base.fb->modifier ||
11462 cur->base.rotation != new->base.rotation ||
11463 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
11464 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
11465 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
11466 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
11472 static bool needs_scaling(const struct intel_plane_state *state)
11474 int src_w = drm_rect_width(&state->base.src) >> 16;
11475 int src_h = drm_rect_height(&state->base.src) >> 16;
11476 int dst_w = drm_rect_width(&state->base.dst);
11477 int dst_h = drm_rect_height(&state->base.dst);
11479 return (src_w != dst_w || src_h != dst_h);
11482 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11483 struct intel_crtc_state *crtc_state,
11484 const struct intel_plane_state *old_plane_state,
11485 struct intel_plane_state *plane_state)
11487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11488 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
11489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11490 bool mode_changed = needs_modeset(crtc_state);
11491 bool was_crtc_enabled = old_crtc_state->base.active;
11492 bool is_crtc_enabled = crtc_state->base.active;
11493 bool turn_off, turn_on, visible, was_visible;
11494 struct drm_framebuffer *fb = plane_state->base.fb;
11497 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11498 ret = skl_update_scaler_plane(crtc_state, plane_state);
11503 was_visible = old_plane_state->base.visible;
11504 visible = plane_state->base.visible;
11506 if (!was_crtc_enabled && WARN_ON(was_visible))
11507 was_visible = false;
11510 * Visibility is calculated as if the crtc was on, but
11511 * after scaler setup everything depends on it being off
11512 * when the crtc isn't active.
11514 * FIXME this is wrong for watermarks. Watermarks should also
11515 * be computed as if the pipe would be active. Perhaps move
11516 * per-plane wm computation to the .check_plane() hook, and
11517 * only combine the results from all planes in the current place?
11519 if (!is_crtc_enabled) {
11520 plane_state->base.visible = visible = false;
11521 crtc_state->active_planes &= ~BIT(plane->id);
11522 crtc_state->data_rate[plane->id] = 0;
11525 if (!was_visible && !visible)
11528 if (fb != old_plane_state->base.fb)
11529 crtc_state->fb_changed = true;
11531 turn_off = was_visible && (!visible || mode_changed);
11532 turn_on = visible && (!was_visible || mode_changed);
11534 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11535 crtc->base.base.id, crtc->base.name,
11536 plane->base.base.id, plane->base.name,
11537 fb ? fb->base.id : -1);
11539 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11540 plane->base.base.id, plane->base.name,
11541 was_visible, visible,
11542 turn_off, turn_on, mode_changed);
11545 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11546 crtc_state->update_wm_pre = true;
11548 /* must disable cxsr around plane enable/disable */
11549 if (plane->id != PLANE_CURSOR)
11550 crtc_state->disable_cxsr = true;
11551 } else if (turn_off) {
11552 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11553 crtc_state->update_wm_post = true;
11555 /* must disable cxsr around plane enable/disable */
11556 if (plane->id != PLANE_CURSOR)
11557 crtc_state->disable_cxsr = true;
11558 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
11559 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11560 /* FIXME bollocks */
11561 crtc_state->update_wm_pre = true;
11562 crtc_state->update_wm_post = true;
11566 if (visible || was_visible)
11567 crtc_state->fb_bits |= plane->frontbuffer_bit;
11570 * ILK/SNB DVSACNTR/Sprite Enable
11571 * IVB SPR_CTL/Sprite Enable
11572 * "When in Self Refresh Big FIFO mode, a write to enable the
11573 * plane will be internally buffered and delayed while Big FIFO
11574 * mode is exiting."
11576 * Which means that enabling the sprite can take an extra frame
11577 * when we start in big FIFO mode (LP1+). Thus we need to drop
11578 * down to LP0 and wait for vblank in order to make sure the
11579 * sprite gets enabled on the next vblank after the register write.
11580 * Doing otherwise would risk enabling the sprite one frame after
11581 * we've already signalled flip completion. We can resume LP1+
11582 * once the sprite has been enabled.
11585 * WaCxSRDisabledForSpriteScaling:ivb
11586 * IVB SPR_SCALE/Scaling Enable
11587 * "Low Power watermarks must be disabled for at least one
11588 * frame before enabling sprite scaling, and kept disabled
11589 * until sprite scaling is disabled."
11591 * ILK/SNB DVSASCALE/Scaling Enable
11592 * "When in Self Refresh Big FIFO mode, scaling enable will be
11593 * masked off while Big FIFO mode is exiting."
11595 * Despite the w/a only being listed for IVB we assume that
11596 * the ILK/SNB note has similar ramifications, hence we apply
11597 * the w/a on all three platforms.
11599 * With experimental results seems this is needed also for primary
11600 * plane, not only sprite plane.
11602 if (plane->id != PLANE_CURSOR &&
11603 (IS_GEN_RANGE(dev_priv, 5, 6) ||
11604 IS_IVYBRIDGE(dev_priv)) &&
11605 (turn_on || (!needs_scaling(old_plane_state) &&
11606 needs_scaling(plane_state))))
11607 crtc_state->disable_lp_wm = true;
11612 static bool encoders_cloneable(const struct intel_encoder *a,
11613 const struct intel_encoder *b)
11615 /* masks could be asymmetric, so check both ways */
11616 return a == b || (a->cloneable & (1 << b->type) &&
11617 b->cloneable & (1 << a->type));
11620 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11621 struct intel_crtc *crtc,
11622 struct intel_encoder *encoder)
11624 struct intel_encoder *source_encoder;
11625 struct drm_connector *connector;
11626 struct drm_connector_state *connector_state;
11629 for_each_new_connector_in_state(state, connector, connector_state, i) {
11630 if (connector_state->crtc != &crtc->base)
11634 to_intel_encoder(connector_state->best_encoder);
11635 if (!encoders_cloneable(encoder, source_encoder))
11642 static int icl_add_linked_planes(struct intel_atomic_state *state)
11644 struct intel_plane *plane, *linked;
11645 struct intel_plane_state *plane_state, *linked_plane_state;
11648 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11649 linked = plane_state->linked_plane;
11654 linked_plane_state = intel_atomic_get_plane_state(state, linked);
11655 if (IS_ERR(linked_plane_state))
11656 return PTR_ERR(linked_plane_state);
11658 WARN_ON(linked_plane_state->linked_plane != plane);
11659 WARN_ON(linked_plane_state->slave == plane_state->slave);
11665 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
11667 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11668 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11669 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
11670 struct intel_plane *plane, *linked;
11671 struct intel_plane_state *plane_state;
11674 if (INTEL_GEN(dev_priv) < 11)
11678 * Destroy all old plane links and make the slave plane invisible
11679 * in the crtc_state->active_planes mask.
11681 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11682 if (plane->pipe != crtc->pipe || !plane_state->linked_plane)
11685 plane_state->linked_plane = NULL;
11686 if (plane_state->slave && !plane_state->base.visible) {
11687 crtc_state->active_planes &= ~BIT(plane->id);
11688 crtc_state->update_planes |= BIT(plane->id);
11691 plane_state->slave = false;
11694 if (!crtc_state->nv12_planes)
11697 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
11698 struct intel_plane_state *linked_state = NULL;
11700 if (plane->pipe != crtc->pipe ||
11701 !(crtc_state->nv12_planes & BIT(plane->id)))
11704 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
11705 if (!icl_is_nv12_y_plane(linked->id))
11708 if (crtc_state->active_planes & BIT(linked->id))
11711 linked_state = intel_atomic_get_plane_state(state, linked);
11712 if (IS_ERR(linked_state))
11713 return PTR_ERR(linked_state);
11718 if (!linked_state) {
11719 DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
11720 hweight8(crtc_state->nv12_planes));
11725 plane_state->linked_plane = linked;
11727 linked_state->slave = true;
11728 linked_state->linked_plane = plane;
11729 crtc_state->active_planes |= BIT(linked->id);
11730 crtc_state->update_planes |= BIT(linked->id);
11731 DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name);
11737 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
11739 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
11740 struct intel_atomic_state *state =
11741 to_intel_atomic_state(new_crtc_state->base.state);
11742 const struct intel_crtc_state *old_crtc_state =
11743 intel_atomic_get_old_crtc_state(state, crtc);
11745 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
11748 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11749 struct drm_crtc_state *crtc_state)
11751 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11753 struct intel_crtc_state *pipe_config =
11754 to_intel_crtc_state(crtc_state);
11756 bool mode_changed = needs_modeset(pipe_config);
11758 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
11759 mode_changed && !crtc_state->active)
11760 pipe_config->update_wm_post = true;
11762 if (mode_changed && crtc_state->enable &&
11763 dev_priv->display.crtc_compute_clock &&
11764 !WARN_ON(pipe_config->shared_dpll)) {
11765 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11772 * May need to update pipe gamma enable bits
11773 * when C8 planes are getting enabled/disabled.
11775 if (c8_planes_changed(pipe_config))
11776 crtc_state->color_mgmt_changed = true;
11778 if (mode_changed || pipe_config->update_pipe ||
11779 crtc_state->color_mgmt_changed) {
11780 ret = intel_color_check(pipe_config);
11786 if (dev_priv->display.compute_pipe_wm) {
11787 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11789 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11794 if (dev_priv->display.compute_intermediate_wm) {
11795 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11799 * Calculate 'intermediate' watermarks that satisfy both the
11800 * old state and the new state. We can program these
11803 ret = dev_priv->display.compute_intermediate_wm(pipe_config);
11805 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11810 if (INTEL_GEN(dev_priv) >= 9) {
11811 if (mode_changed || pipe_config->update_pipe)
11812 ret = skl_update_scaler_crtc(pipe_config);
11815 ret = icl_check_nv12_planes(pipe_config);
11817 ret = skl_check_pipe_max_pixel_rate(intel_crtc,
11820 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11824 if (HAS_IPS(dev_priv))
11825 pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config);
11830 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11831 .atomic_check = intel_crtc_atomic_check,
11834 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11836 struct intel_connector *connector;
11837 struct drm_connector_list_iter conn_iter;
11839 drm_connector_list_iter_begin(dev, &conn_iter);
11840 for_each_intel_connector_iter(connector, &conn_iter) {
11841 if (connector->base.state->crtc)
11842 drm_connector_put(&connector->base);
11844 if (connector->base.encoder) {
11845 connector->base.state->best_encoder =
11846 connector->base.encoder;
11847 connector->base.state->crtc =
11848 connector->base.encoder->crtc;
11850 drm_connector_get(&connector->base);
11852 connector->base.state->best_encoder = NULL;
11853 connector->base.state->crtc = NULL;
11856 drm_connector_list_iter_end(&conn_iter);
11860 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
11861 struct intel_crtc_state *pipe_config)
11863 struct drm_connector *connector = conn_state->connector;
11864 const struct drm_display_info *info = &connector->display_info;
11867 switch (conn_state->max_bpc) {
11884 if (bpp < pipe_config->pipe_bpp) {
11885 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
11886 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
11887 connector->base.id, connector->name,
11888 bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc,
11889 pipe_config->pipe_bpp);
11891 pipe_config->pipe_bpp = bpp;
11898 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11899 struct intel_crtc_state *pipe_config)
11901 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11902 struct drm_atomic_state *state = pipe_config->base.state;
11903 struct drm_connector *connector;
11904 struct drm_connector_state *connector_state;
11907 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11908 IS_CHERRYVIEW(dev_priv)))
11910 else if (INTEL_GEN(dev_priv) >= 5)
11915 pipe_config->pipe_bpp = bpp;
11917 /* Clamp display bpp to connector max bpp */
11918 for_each_new_connector_in_state(state, connector, connector_state, i) {
11921 if (connector_state->crtc != &crtc->base)
11924 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
11932 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11934 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11935 "type: 0x%x flags: 0x%x\n",
11937 mode->crtc_hdisplay, mode->crtc_hsync_start,
11938 mode->crtc_hsync_end, mode->crtc_htotal,
11939 mode->crtc_vdisplay, mode->crtc_vsync_start,
11940 mode->crtc_vsync_end, mode->crtc_vtotal,
11941 mode->type, mode->flags);
11945 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
11946 const char *id, unsigned int lane_count,
11947 const struct intel_link_m_n *m_n)
11949 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11951 m_n->gmch_m, m_n->gmch_n,
11952 m_n->link_m, m_n->link_n, m_n->tu);
11956 intel_dump_infoframe(struct drm_i915_private *dev_priv,
11957 const union hdmi_infoframe *frame)
11959 if ((drm_debug & DRM_UT_KMS) == 0)
11962 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
11965 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
11967 static const char * const output_type_str[] = {
11968 OUTPUT_TYPE(UNUSED),
11969 OUTPUT_TYPE(ANALOG),
11973 OUTPUT_TYPE(TVOUT),
11979 OUTPUT_TYPE(DP_MST),
11984 static void snprintf_output_types(char *buf, size_t len,
11985 unsigned int output_types)
11992 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
11995 if ((output_types & BIT(i)) == 0)
11998 r = snprintf(str, len, "%s%s",
11999 str != buf ? "," : "", output_type_str[i]);
12005 output_types &= ~BIT(i);
12008 WARN_ON_ONCE(output_types != 0);
12011 static const char * const output_format_str[] = {
12012 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12013 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12014 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12015 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12018 static const char *output_formats(enum intel_output_format format)
12020 if (format >= ARRAY_SIZE(output_format_str))
12021 format = INTEL_OUTPUT_FORMAT_INVALID;
12022 return output_format_str[format];
12025 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12027 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
12028 const struct drm_framebuffer *fb = plane_state->base.fb;
12029 struct drm_format_name_buf format_name;
12032 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12033 plane->base.base.id, plane->base.name,
12034 yesno(plane_state->base.visible));
12038 DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
12039 plane->base.base.id, plane->base.name,
12040 fb->base.id, fb->width, fb->height,
12041 drm_get_format_name(fb->format->format, &format_name),
12042 yesno(plane_state->base.visible));
12043 DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n",
12044 plane_state->base.rotation, plane_state->scaler_id);
12045 if (plane_state->base.visible)
12046 DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
12047 DRM_RECT_FP_ARG(&plane_state->base.src),
12048 DRM_RECT_ARG(&plane_state->base.dst));
12051 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
12052 struct intel_atomic_state *state,
12053 const char *context)
12055 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
12056 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12057 const struct intel_plane_state *plane_state;
12058 struct intel_plane *plane;
12062 DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
12063 crtc->base.base.id, crtc->base.name,
12064 yesno(pipe_config->base.enable), context);
12066 if (!pipe_config->base.enable)
12069 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
12070 DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
12071 yesno(pipe_config->base.active),
12072 buf, pipe_config->output_types,
12073 output_formats(pipe_config->output_format));
12075 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
12076 transcoder_name(pipe_config->cpu_transcoder),
12077 pipe_config->pipe_bpp, pipe_config->dither);
12079 if (pipe_config->has_pch_encoder)
12080 intel_dump_m_n_config(pipe_config, "fdi",
12081 pipe_config->fdi_lanes,
12082 &pipe_config->fdi_m_n);
12084 if (intel_crtc_has_dp_encoder(pipe_config)) {
12085 intel_dump_m_n_config(pipe_config, "dp m_n",
12086 pipe_config->lane_count, &pipe_config->dp_m_n);
12087 if (pipe_config->has_drrs)
12088 intel_dump_m_n_config(pipe_config, "dp m2_n2",
12089 pipe_config->lane_count,
12090 &pipe_config->dp_m2_n2);
12093 DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
12094 pipe_config->has_audio, pipe_config->has_infoframe,
12095 pipe_config->infoframes.enable);
12097 if (pipe_config->infoframes.enable &
12098 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
12099 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
12100 if (pipe_config->infoframes.enable &
12101 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
12102 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
12103 if (pipe_config->infoframes.enable &
12104 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
12105 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
12106 if (pipe_config->infoframes.enable &
12107 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
12108 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
12110 DRM_DEBUG_KMS("requested mode:\n");
12111 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12112 DRM_DEBUG_KMS("adjusted mode:\n");
12113 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12114 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12115 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
12116 pipe_config->port_clock,
12117 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
12118 pipe_config->pixel_rate);
12120 if (INTEL_GEN(dev_priv) >= 9)
12121 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12123 pipe_config->scaler_state.scaler_users,
12124 pipe_config->scaler_state.scaler_id);
12126 if (HAS_GMCH(dev_priv))
12127 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12128 pipe_config->gmch_pfit.control,
12129 pipe_config->gmch_pfit.pgm_ratios,
12130 pipe_config->gmch_pfit.lvds_border_bits);
12132 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
12133 pipe_config->pch_pfit.pos,
12134 pipe_config->pch_pfit.size,
12135 enableddisabled(pipe_config->pch_pfit.enabled),
12136 yesno(pipe_config->pch_pfit.force_thru));
12138 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
12139 pipe_config->ips_enabled, pipe_config->double_wide);
12141 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
12143 if (IS_CHERRYVIEW(dev_priv))
12144 DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12145 pipe_config->cgm_mode, pipe_config->gamma_mode,
12146 pipe_config->gamma_enable, pipe_config->csc_enable);
12148 DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
12149 pipe_config->csc_mode, pipe_config->gamma_mode,
12150 pipe_config->gamma_enable, pipe_config->csc_enable);
12156 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12157 if (plane->pipe == crtc->pipe)
12158 intel_dump_plane_state(plane_state);
12162 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
12164 struct drm_device *dev = state->base.dev;
12165 struct drm_connector *connector;
12166 struct drm_connector_list_iter conn_iter;
12167 unsigned int used_ports = 0;
12168 unsigned int used_mst_ports = 0;
12172 * Walk the connector list instead of the encoder
12173 * list to detect the problem on ddi platforms
12174 * where there's just one encoder per digital port.
12176 drm_connector_list_iter_begin(dev, &conn_iter);
12177 drm_for_each_connector_iter(connector, &conn_iter) {
12178 struct drm_connector_state *connector_state;
12179 struct intel_encoder *encoder;
12182 drm_atomic_get_new_connector_state(&state->base,
12184 if (!connector_state)
12185 connector_state = connector->state;
12187 if (!connector_state->best_encoder)
12190 encoder = to_intel_encoder(connector_state->best_encoder);
12192 WARN_ON(!connector_state->crtc);
12194 switch (encoder->type) {
12195 unsigned int port_mask;
12196 case INTEL_OUTPUT_DDI:
12197 if (WARN_ON(!HAS_DDI(to_i915(dev))))
12199 /* else, fall through */
12200 case INTEL_OUTPUT_DP:
12201 case INTEL_OUTPUT_HDMI:
12202 case INTEL_OUTPUT_EDP:
12203 port_mask = 1 << encoder->port;
12205 /* the same port mustn't appear more than once */
12206 if (used_ports & port_mask)
12209 used_ports |= port_mask;
12211 case INTEL_OUTPUT_DP_MST:
12213 1 << encoder->port;
12219 drm_connector_list_iter_end(&conn_iter);
12221 /* can't mix MST and SST/HDMI on the same port */
12222 if (used_ports & used_mst_ports)
12229 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12231 struct drm_i915_private *dev_priv =
12232 to_i915(crtc_state->base.crtc->dev);
12233 struct intel_crtc_state *saved_state;
12235 saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
12239 /* FIXME: before the switch to atomic started, a new pipe_config was
12240 * kzalloc'd. Code that depends on any field being zero should be
12241 * fixed, so that the crtc_state can be safely duplicated. For now,
12242 * only fields that are know to not cause problems are preserved. */
12244 saved_state->scaler_state = crtc_state->scaler_state;
12245 saved_state->shared_dpll = crtc_state->shared_dpll;
12246 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
12247 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
12248 sizeof(saved_state->icl_port_dplls));
12249 saved_state->crc_enabled = crtc_state->crc_enabled;
12250 if (IS_G4X(dev_priv) ||
12251 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12252 saved_state->wm = crtc_state->wm;
12254 /* Keep base drm_crtc_state intact, only clear our extended struct */
12255 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
12256 memcpy(&crtc_state->base + 1, &saved_state->base + 1,
12257 sizeof(*crtc_state) - sizeof(crtc_state->base));
12259 kfree(saved_state);
12264 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
12266 struct drm_crtc *crtc = pipe_config->base.crtc;
12267 struct drm_atomic_state *state = pipe_config->base.state;
12268 struct intel_encoder *encoder;
12269 struct drm_connector *connector;
12270 struct drm_connector_state *connector_state;
12275 ret = clear_intel_crtc_state(pipe_config);
12279 pipe_config->cpu_transcoder =
12280 (enum transcoder) to_intel_crtc(crtc)->pipe;
12283 * Sanitize sync polarity flags based on requested ones. If neither
12284 * positive or negative polarity is requested, treat this as meaning
12285 * negative polarity.
12287 if (!(pipe_config->base.adjusted_mode.flags &
12288 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12289 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12291 if (!(pipe_config->base.adjusted_mode.flags &
12292 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12293 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12295 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12300 base_bpp = pipe_config->pipe_bpp;
12303 * Determine the real pipe dimensions. Note that stereo modes can
12304 * increase the actual pipe size due to the frame doubling and
12305 * insertion of additional space for blanks between the frame. This
12306 * is stored in the crtc timings. We use the requested mode to do this
12307 * computation to clearly distinguish it from the adjusted mode, which
12308 * can be changed by the connectors in the below retry loop.
12310 drm_mode_get_hv_timing(&pipe_config->base.mode,
12311 &pipe_config->pipe_src_w,
12312 &pipe_config->pipe_src_h);
12314 for_each_new_connector_in_state(state, connector, connector_state, i) {
12315 if (connector_state->crtc != crtc)
12318 encoder = to_intel_encoder(connector_state->best_encoder);
12320 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
12321 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12326 * Determine output_types before calling the .compute_config()
12327 * hooks so that the hooks can use this information safely.
12329 if (encoder->compute_output_type)
12330 pipe_config->output_types |=
12331 BIT(encoder->compute_output_type(encoder, pipe_config,
12334 pipe_config->output_types |= BIT(encoder->type);
12338 /* Ensure the port clock defaults are reset when retrying. */
12339 pipe_config->port_clock = 0;
12340 pipe_config->pixel_multiplier = 1;
12342 /* Fill in default crtc timings, allow encoders to overwrite them. */
12343 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12344 CRTC_STEREO_DOUBLE);
12346 /* Pass our mode to the connectors and the CRTC to give them a chance to
12347 * adjust it according to limitations or connector properties, and also
12348 * a chance to reject the mode entirely.
12350 for_each_new_connector_in_state(state, connector, connector_state, i) {
12351 if (connector_state->crtc != crtc)
12354 encoder = to_intel_encoder(connector_state->best_encoder);
12355 ret = encoder->compute_config(encoder, pipe_config,
12358 if (ret != -EDEADLK)
12359 DRM_DEBUG_KMS("Encoder config failure: %d\n",
12365 /* Set default port clock if not overwritten by the encoder. Needs to be
12366 * done afterwards in case the encoder adjusts the mode. */
12367 if (!pipe_config->port_clock)
12368 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12369 * pipe_config->pixel_multiplier;
12371 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12372 if (ret == -EDEADLK)
12375 DRM_DEBUG_KMS("CRTC fixup failed\n");
12379 if (ret == RETRY) {
12380 if (WARN(!retry, "loop in pipe configuration computation\n"))
12383 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12385 goto encoder_retry;
12388 /* Dithering seems to not pass-through bits correctly when it should, so
12389 * only enable it on 6bpc panels and when its not a compliance
12390 * test requesting 6bpc video pattern.
12392 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
12393 !pipe_config->dither_force_disable;
12394 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12395 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12400 bool intel_fuzzy_clock_check(int clock1, int clock2)
12404 if (clock1 == clock2)
12407 if (!clock1 || !clock2)
12410 diff = abs(clock1 - clock2);
12412 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12419 intel_compare_m_n(unsigned int m, unsigned int n,
12420 unsigned int m2, unsigned int n2,
12423 if (m == m2 && n == n2)
12426 if (exact || !m || !n || !m2 || !n2)
12429 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12436 } else if (n < n2) {
12446 return intel_fuzzy_clock_check(m, m2);
12450 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12451 const struct intel_link_m_n *m2_n2,
12454 return m_n->tu == m2_n2->tu &&
12455 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12456 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
12457 intel_compare_m_n(m_n->link_m, m_n->link_n,
12458 m2_n2->link_m, m2_n2->link_n, exact);
12462 intel_compare_infoframe(const union hdmi_infoframe *a,
12463 const union hdmi_infoframe *b)
12465 return memcmp(a, b, sizeof(*a)) == 0;
12469 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
12470 bool fastset, const char *name,
12471 const union hdmi_infoframe *a,
12472 const union hdmi_infoframe *b)
12475 if ((drm_debug & DRM_UT_KMS) == 0)
12478 drm_dbg(DRM_UT_KMS, "fastset mismatch in %s infoframe", name);
12479 drm_dbg(DRM_UT_KMS, "expected:");
12480 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
12481 drm_dbg(DRM_UT_KMS, "found");
12482 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
12484 drm_err("mismatch in %s infoframe", name);
12485 drm_err("expected:");
12486 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
12488 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
12492 static void __printf(3, 4)
12493 pipe_config_mismatch(bool fastset, const char *name, const char *format, ...)
12495 struct va_format vaf;
12498 va_start(args, format);
12503 drm_dbg(DRM_UT_KMS, "fastset mismatch in %s %pV", name, &vaf);
12505 drm_err("mismatch in %s %pV", name, &vaf);
12510 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
12512 if (i915_modparams.fastboot != -1)
12513 return i915_modparams.fastboot;
12515 /* Enable fastboot by default on Skylake and newer */
12516 if (INTEL_GEN(dev_priv) >= 9)
12519 /* Enable fastboot by default on VLV and CHV */
12520 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12523 /* Disabled by default on all others */
12528 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
12529 const struct intel_crtc_state *pipe_config,
12532 struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev);
12535 bool fixup_inherited = fastset &&
12536 (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
12537 !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
12539 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
12540 DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
12544 #define PIPE_CONF_CHECK_X(name) do { \
12545 if (current_config->name != pipe_config->name) { \
12546 pipe_config_mismatch(fastset, __stringify(name), \
12547 "(expected 0x%08x, found 0x%08x)\n", \
12548 current_config->name, \
12549 pipe_config->name); \
12554 #define PIPE_CONF_CHECK_I(name) do { \
12555 if (current_config->name != pipe_config->name) { \
12556 pipe_config_mismatch(fastset, __stringify(name), \
12557 "(expected %i, found %i)\n", \
12558 current_config->name, \
12559 pipe_config->name); \
12564 #define PIPE_CONF_CHECK_BOOL(name) do { \
12565 if (current_config->name != pipe_config->name) { \
12566 pipe_config_mismatch(fastset, __stringify(name), \
12567 "(expected %s, found %s)\n", \
12568 yesno(current_config->name), \
12569 yesno(pipe_config->name)); \
12575 * Checks state where we only read out the enabling, but not the entire
12576 * state itself (like full infoframes or ELD for audio). These states
12577 * require a full modeset on bootup to fix up.
12579 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
12580 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
12581 PIPE_CONF_CHECK_BOOL(name); \
12583 pipe_config_mismatch(fastset, __stringify(name), \
12584 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)\n", \
12585 yesno(current_config->name), \
12586 yesno(pipe_config->name)); \
12591 #define PIPE_CONF_CHECK_P(name) do { \
12592 if (current_config->name != pipe_config->name) { \
12593 pipe_config_mismatch(fastset, __stringify(name), \
12594 "(expected %p, found %p)\n", \
12595 current_config->name, \
12596 pipe_config->name); \
12601 #define PIPE_CONF_CHECK_M_N(name) do { \
12602 if (!intel_compare_link_m_n(¤t_config->name, \
12603 &pipe_config->name,\
12605 pipe_config_mismatch(fastset, __stringify(name), \
12606 "(expected tu %i gmch %i/%i link %i/%i, " \
12607 "found tu %i, gmch %i/%i link %i/%i)\n", \
12608 current_config->name.tu, \
12609 current_config->name.gmch_m, \
12610 current_config->name.gmch_n, \
12611 current_config->name.link_m, \
12612 current_config->name.link_n, \
12613 pipe_config->name.tu, \
12614 pipe_config->name.gmch_m, \
12615 pipe_config->name.gmch_n, \
12616 pipe_config->name.link_m, \
12617 pipe_config->name.link_n); \
12622 /* This is required for BDW+ where there is only one set of registers for
12623 * switching between high and low RR.
12624 * This macro can be used whenever a comparison has to be made between one
12625 * hw state and multiple sw state variables.
12627 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
12628 if (!intel_compare_link_m_n(¤t_config->name, \
12629 &pipe_config->name, !fastset) && \
12630 !intel_compare_link_m_n(¤t_config->alt_name, \
12631 &pipe_config->name, !fastset)) { \
12632 pipe_config_mismatch(fastset, __stringify(name), \
12633 "(expected tu %i gmch %i/%i link %i/%i, " \
12634 "or tu %i gmch %i/%i link %i/%i, " \
12635 "found tu %i, gmch %i/%i link %i/%i)\n", \
12636 current_config->name.tu, \
12637 current_config->name.gmch_m, \
12638 current_config->name.gmch_n, \
12639 current_config->name.link_m, \
12640 current_config->name.link_n, \
12641 current_config->alt_name.tu, \
12642 current_config->alt_name.gmch_m, \
12643 current_config->alt_name.gmch_n, \
12644 current_config->alt_name.link_m, \
12645 current_config->alt_name.link_n, \
12646 pipe_config->name.tu, \
12647 pipe_config->name.gmch_m, \
12648 pipe_config->name.gmch_n, \
12649 pipe_config->name.link_m, \
12650 pipe_config->name.link_n); \
12655 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
12656 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12657 pipe_config_mismatch(fastset, __stringify(name), \
12658 "(%x) (expected %i, found %i)\n", \
12660 current_config->name & (mask), \
12661 pipe_config->name & (mask)); \
12666 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
12667 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12668 pipe_config_mismatch(fastset, __stringify(name), \
12669 "(expected %i, found %i)\n", \
12670 current_config->name, \
12671 pipe_config->name); \
12676 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
12677 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
12678 &pipe_config->infoframes.name)) { \
12679 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
12680 ¤t_config->infoframes.name, \
12681 &pipe_config->infoframes.name); \
12686 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
12687 if (current_config->name1 != pipe_config->name1) { \
12688 pipe_config_mismatch(fastset, __stringify(name1), \
12689 "(expected %i, found %i, won't compare lut values)\n", \
12690 current_config->name1, \
12691 pipe_config->name1); \
12694 if (!intel_color_lut_equal(current_config->name2, \
12695 pipe_config->name2, pipe_config->name1, \
12696 bit_precision)) { \
12697 pipe_config_mismatch(fastset, __stringify(name2), \
12698 "hw_state doesn't match sw_state\n"); \
12704 #define PIPE_CONF_QUIRK(quirk) \
12705 ((current_config->quirks | pipe_config->quirks) & (quirk))
12707 PIPE_CONF_CHECK_I(cpu_transcoder);
12709 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
12710 PIPE_CONF_CHECK_I(fdi_lanes);
12711 PIPE_CONF_CHECK_M_N(fdi_m_n);
12713 PIPE_CONF_CHECK_I(lane_count);
12714 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12716 if (INTEL_GEN(dev_priv) < 8) {
12717 PIPE_CONF_CHECK_M_N(dp_m_n);
12719 if (current_config->has_drrs)
12720 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12722 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12724 PIPE_CONF_CHECK_X(output_types);
12726 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12727 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12728 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12729 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12730 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12731 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12733 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12734 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12735 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12736 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12737 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12738 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12740 PIPE_CONF_CHECK_I(pixel_multiplier);
12741 PIPE_CONF_CHECK_I(output_format);
12742 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
12743 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
12744 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
12745 PIPE_CONF_CHECK_BOOL(limited_color_range);
12747 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
12748 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
12749 PIPE_CONF_CHECK_BOOL(has_infoframe);
12751 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
12753 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12754 DRM_MODE_FLAG_INTERLACE);
12756 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12757 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12758 DRM_MODE_FLAG_PHSYNC);
12759 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12760 DRM_MODE_FLAG_NHSYNC);
12761 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12762 DRM_MODE_FLAG_PVSYNC);
12763 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12764 DRM_MODE_FLAG_NVSYNC);
12767 PIPE_CONF_CHECK_X(gmch_pfit.control);
12768 /* pfit ratios are autocomputed by the hw on gen4+ */
12769 if (INTEL_GEN(dev_priv) < 4)
12770 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12771 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12774 * Changing the EDP transcoder input mux
12775 * (A_ONOFF vs. A_ON) requires a full modeset.
12777 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
12780 PIPE_CONF_CHECK_I(pipe_src_w);
12781 PIPE_CONF_CHECK_I(pipe_src_h);
12783 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
12784 if (current_config->pch_pfit.enabled) {
12785 PIPE_CONF_CHECK_X(pch_pfit.pos);
12786 PIPE_CONF_CHECK_X(pch_pfit.size);
12789 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12790 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
12792 PIPE_CONF_CHECK_X(gamma_mode);
12793 if (IS_CHERRYVIEW(dev_priv))
12794 PIPE_CONF_CHECK_X(cgm_mode);
12796 PIPE_CONF_CHECK_X(csc_mode);
12797 PIPE_CONF_CHECK_BOOL(gamma_enable);
12798 PIPE_CONF_CHECK_BOOL(csc_enable);
12800 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
12802 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
12806 PIPE_CONF_CHECK_BOOL(double_wide);
12808 PIPE_CONF_CHECK_P(shared_dpll);
12809 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12810 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12811 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12812 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12813 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12814 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12815 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12816 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12817 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12818 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
12819 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
12820 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
12821 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
12822 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
12823 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
12824 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
12825 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
12826 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
12827 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
12828 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
12829 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
12830 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
12831 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
12832 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
12833 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
12834 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
12835 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
12836 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
12837 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
12838 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
12839 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
12841 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12842 PIPE_CONF_CHECK_X(dsi_pll.div);
12844 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
12845 PIPE_CONF_CHECK_I(pipe_bpp);
12847 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12848 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12850 PIPE_CONF_CHECK_I(min_voltage_level);
12852 PIPE_CONF_CHECK_X(infoframes.enable);
12853 PIPE_CONF_CHECK_X(infoframes.gcp);
12854 PIPE_CONF_CHECK_INFOFRAME(avi);
12855 PIPE_CONF_CHECK_INFOFRAME(spd);
12856 PIPE_CONF_CHECK_INFOFRAME(hdmi);
12857 PIPE_CONF_CHECK_INFOFRAME(drm);
12859 #undef PIPE_CONF_CHECK_X
12860 #undef PIPE_CONF_CHECK_I
12861 #undef PIPE_CONF_CHECK_BOOL
12862 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
12863 #undef PIPE_CONF_CHECK_P
12864 #undef PIPE_CONF_CHECK_FLAGS
12865 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12866 #undef PIPE_CONF_CHECK_COLOR_LUT
12867 #undef PIPE_CONF_QUIRK
12872 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12873 const struct intel_crtc_state *pipe_config)
12875 if (pipe_config->has_pch_encoder) {
12876 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12877 &pipe_config->fdi_m_n);
12878 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12881 * FDI already provided one idea for the dotclock.
12882 * Yell if the encoder disagrees.
12884 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12885 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12886 fdi_dotclock, dotclock);
12890 static void verify_wm_state(struct intel_crtc *crtc,
12891 struct intel_crtc_state *new_crtc_state)
12893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12894 struct skl_hw_state {
12895 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
12896 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
12897 struct skl_ddb_allocation ddb;
12898 struct skl_pipe_wm wm;
12900 struct skl_ddb_allocation *sw_ddb;
12901 struct skl_pipe_wm *sw_wm;
12902 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
12903 const enum pipe pipe = crtc->pipe;
12904 int plane, level, max_level = ilk_wm_max_level(dev_priv);
12906 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
12909 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
12913 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
12914 sw_wm = &new_crtc_state->wm.skl.optimal;
12916 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
12918 skl_ddb_get_hw_state(dev_priv, &hw->ddb);
12919 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12921 if (INTEL_GEN(dev_priv) >= 11 &&
12922 hw->ddb.enabled_slices != sw_ddb->enabled_slices)
12923 DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
12924 sw_ddb->enabled_slices,
12925 hw->ddb.enabled_slices);
12928 for_each_universal_plane(dev_priv, pipe, plane) {
12929 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12931 hw_plane_wm = &hw->wm.planes[plane];
12932 sw_plane_wm = &sw_wm->planes[plane];
12935 for (level = 0; level <= max_level; level++) {
12936 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12937 &sw_plane_wm->wm[level]))
12940 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12941 pipe_name(pipe), plane + 1, level,
12942 sw_plane_wm->wm[level].plane_en,
12943 sw_plane_wm->wm[level].plane_res_b,
12944 sw_plane_wm->wm[level].plane_res_l,
12945 hw_plane_wm->wm[level].plane_en,
12946 hw_plane_wm->wm[level].plane_res_b,
12947 hw_plane_wm->wm[level].plane_res_l);
12950 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
12951 &sw_plane_wm->trans_wm)) {
12952 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12953 pipe_name(pipe), plane + 1,
12954 sw_plane_wm->trans_wm.plane_en,
12955 sw_plane_wm->trans_wm.plane_res_b,
12956 sw_plane_wm->trans_wm.plane_res_l,
12957 hw_plane_wm->trans_wm.plane_en,
12958 hw_plane_wm->trans_wm.plane_res_b,
12959 hw_plane_wm->trans_wm.plane_res_l);
12963 hw_ddb_entry = &hw->ddb_y[plane];
12964 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
12966 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12967 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
12968 pipe_name(pipe), plane + 1,
12969 sw_ddb_entry->start, sw_ddb_entry->end,
12970 hw_ddb_entry->start, hw_ddb_entry->end);
12976 * If the cursor plane isn't active, we may not have updated it's ddb
12977 * allocation. In that case since the ddb allocation will be updated
12978 * once the plane becomes visible, we can skip this check
12981 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
12983 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
12984 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
12987 for (level = 0; level <= max_level; level++) {
12988 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
12989 &sw_plane_wm->wm[level]))
12992 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
12993 pipe_name(pipe), level,
12994 sw_plane_wm->wm[level].plane_en,
12995 sw_plane_wm->wm[level].plane_res_b,
12996 sw_plane_wm->wm[level].plane_res_l,
12997 hw_plane_wm->wm[level].plane_en,
12998 hw_plane_wm->wm[level].plane_res_b,
12999 hw_plane_wm->wm[level].plane_res_l);
13002 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
13003 &sw_plane_wm->trans_wm)) {
13004 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
13006 sw_plane_wm->trans_wm.plane_en,
13007 sw_plane_wm->trans_wm.plane_res_b,
13008 sw_plane_wm->trans_wm.plane_res_l,
13009 hw_plane_wm->trans_wm.plane_en,
13010 hw_plane_wm->trans_wm.plane_res_b,
13011 hw_plane_wm->trans_wm.plane_res_l);
13015 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
13016 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
13018 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
13019 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
13021 sw_ddb_entry->start, sw_ddb_entry->end,
13022 hw_ddb_entry->start, hw_ddb_entry->end);
13030 verify_connector_state(struct intel_atomic_state *state,
13031 struct intel_crtc *crtc)
13033 struct drm_connector *connector;
13034 struct drm_connector_state *new_conn_state;
13037 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
13038 struct drm_encoder *encoder = connector->encoder;
13039 struct intel_crtc_state *crtc_state = NULL;
13041 if (new_conn_state->crtc != &crtc->base)
13045 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13047 intel_connector_verify_state(crtc_state, new_conn_state);
13049 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
13050 "connector's atomic encoder doesn't match legacy encoder\n");
13055 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
13057 struct intel_encoder *encoder;
13058 struct drm_connector *connector;
13059 struct drm_connector_state *old_conn_state, *new_conn_state;
13062 for_each_intel_encoder(&dev_priv->drm, encoder) {
13063 bool enabled = false, found = false;
13066 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13067 encoder->base.base.id,
13068 encoder->base.name);
13070 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
13071 new_conn_state, i) {
13072 if (old_conn_state->best_encoder == &encoder->base)
13075 if (new_conn_state->best_encoder != &encoder->base)
13077 found = enabled = true;
13079 I915_STATE_WARN(new_conn_state->crtc !=
13080 encoder->base.crtc,
13081 "connector's crtc doesn't match encoder crtc\n");
13087 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13088 "encoder's enabled state mismatch "
13089 "(expected %i, found %i)\n",
13090 !!encoder->base.crtc, enabled);
13092 if (!encoder->base.crtc) {
13095 active = encoder->get_hw_state(encoder, &pipe);
13096 I915_STATE_WARN(active,
13097 "encoder detached but still enabled on pipe %c.\n",
13104 verify_crtc_state(struct intel_crtc *crtc,
13105 struct intel_crtc_state *old_crtc_state,
13106 struct intel_crtc_state *new_crtc_state)
13108 struct drm_device *dev = crtc->base.dev;
13109 struct drm_i915_private *dev_priv = to_i915(dev);
13110 struct intel_encoder *encoder;
13111 struct intel_crtc_state *pipe_config;
13112 struct drm_atomic_state *state;
13115 state = old_crtc_state->base.state;
13116 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
13117 pipe_config = old_crtc_state;
13118 memset(pipe_config, 0, sizeof(*pipe_config));
13119 pipe_config->base.crtc = &crtc->base;
13120 pipe_config->base.state = state;
13122 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
13124 active = dev_priv->display.get_pipe_config(crtc, pipe_config);
13126 /* we keep both pipes enabled on 830 */
13127 if (IS_I830(dev_priv))
13128 active = new_crtc_state->base.active;
13130 I915_STATE_WARN(new_crtc_state->base.active != active,
13131 "crtc active state doesn't match with hw state "
13132 "(expected %i, found %i)\n", new_crtc_state->base.active, active);
13134 I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
13135 "transitional active state does not match atomic hw state "
13136 "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
13138 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13141 active = encoder->get_hw_state(encoder, &pipe);
13142 I915_STATE_WARN(active != new_crtc_state->base.active,
13143 "[ENCODER:%i] active %i with crtc active %i\n",
13144 encoder->base.base.id, active, new_crtc_state->base.active);
13146 I915_STATE_WARN(active && crtc->pipe != pipe,
13147 "Encoder connected to wrong pipe %c\n",
13151 encoder->get_config(encoder, pipe_config);
13154 intel_crtc_compute_pixel_rate(pipe_config);
13156 if (!new_crtc_state->base.active)
13159 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13161 if (!intel_pipe_config_compare(new_crtc_state,
13162 pipe_config, false)) {
13163 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13164 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
13165 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
13170 intel_verify_planes(struct intel_atomic_state *state)
13172 struct intel_plane *plane;
13173 const struct intel_plane_state *plane_state;
13176 for_each_new_intel_plane_in_state(state, plane,
13178 assert_plane(plane, plane_state->slave ||
13179 plane_state->base.visible);
13183 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13184 struct intel_shared_dpll *pll,
13185 struct intel_crtc *crtc,
13186 struct intel_crtc_state *new_crtc_state)
13188 struct intel_dpll_hw_state dpll_hw_state;
13189 unsigned int crtc_mask;
13192 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13194 DRM_DEBUG_KMS("%s\n", pll->info->name);
13196 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
13198 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
13199 I915_STATE_WARN(!pll->on && pll->active_mask,
13200 "pll in active use but not on in sw tracking\n");
13201 I915_STATE_WARN(pll->on && !pll->active_mask,
13202 "pll is on but not used by any active crtc\n");
13203 I915_STATE_WARN(pll->on != active,
13204 "pll on state mismatch (expected %i, found %i)\n",
13209 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
13210 "more active pll users than references: %x vs %x\n",
13211 pll->active_mask, pll->state.crtc_mask);
13216 crtc_mask = drm_crtc_mask(&crtc->base);
13218 if (new_crtc_state->base.active)
13219 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13220 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13221 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13223 I915_STATE_WARN(pll->active_mask & crtc_mask,
13224 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13225 pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13227 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13228 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13229 crtc_mask, pll->state.crtc_mask);
13231 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
13233 sizeof(dpll_hw_state)),
13234 "pll hw state mismatch\n");
13238 verify_shared_dpll_state(struct intel_crtc *crtc,
13239 struct intel_crtc_state *old_crtc_state,
13240 struct intel_crtc_state *new_crtc_state)
13242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13244 if (new_crtc_state->shared_dpll)
13245 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13247 if (old_crtc_state->shared_dpll &&
13248 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13249 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13250 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13252 I915_STATE_WARN(pll->active_mask & crtc_mask,
13253 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13254 pipe_name(drm_crtc_index(&crtc->base)));
13255 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13256 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13257 pipe_name(drm_crtc_index(&crtc->base)));
13262 intel_modeset_verify_crtc(struct intel_crtc *crtc,
13263 struct intel_atomic_state *state,
13264 struct intel_crtc_state *old_crtc_state,
13265 struct intel_crtc_state *new_crtc_state)
13267 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13270 verify_wm_state(crtc, new_crtc_state);
13271 verify_connector_state(state, crtc);
13272 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13273 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13277 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13281 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13282 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13286 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13287 struct intel_atomic_state *state)
13289 verify_encoder_state(dev_priv, state);
13290 verify_connector_state(state, NULL);
13291 verify_disabled_dpll_state(dev_priv);
13294 static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
13296 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
13297 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13300 * The scanline counter increments at the leading edge of hsync.
13302 * On most platforms it starts counting from vtotal-1 on the
13303 * first active line. That means the scanline counter value is
13304 * always one less than what we would expect. Ie. just after
13305 * start of vblank, which also occurs at start of hsync (on the
13306 * last active line), the scanline counter will read vblank_start-1.
13308 * On gen2 the scanline counter starts counting from 1 instead
13309 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13310 * to keep the value positive), instead of adding one.
13312 * On HSW+ the behaviour of the scanline counter depends on the output
13313 * type. For DP ports it behaves like most other platforms, but on HDMI
13314 * there's an extra 1 line difference. So we need to add two instead of
13315 * one to the value.
13317 * On VLV/CHV DSI the scanline counter would appear to increment
13318 * approx. 1/3 of a scanline before start of vblank. Unfortunately
13319 * that means we can't tell whether we're in vblank or not while
13320 * we're on that particular line. We must still set scanline_offset
13321 * to 1 so that the vblank timestamps come out correct when we query
13322 * the scanline counter from within the vblank interrupt handler.
13323 * However if queried just before the start of vblank we'll get an
13324 * answer that's slightly in the future.
13326 if (IS_GEN(dev_priv, 2)) {
13327 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
13330 vtotal = adjusted_mode->crtc_vtotal;
13331 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13334 crtc->scanline_offset = vtotal - 1;
13335 } else if (HAS_DDI(dev_priv) &&
13336 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
13337 crtc->scanline_offset = 2;
13339 crtc->scanline_offset = 1;
13342 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13344 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13345 struct intel_crtc_state *new_crtc_state;
13346 struct intel_crtc *crtc;
13349 if (!dev_priv->display.crtc_compute_clock)
13352 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13353 if (!needs_modeset(new_crtc_state))
13356 intel_release_shared_dplls(state, crtc);
13361 * This implements the workaround described in the "notes" section of the mode
13362 * set sequence documentation. When going from no pipes or single pipe to
13363 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13364 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13366 static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
13368 struct intel_crtc_state *crtc_state;
13369 struct intel_crtc *crtc;
13370 struct intel_crtc_state *first_crtc_state = NULL;
13371 struct intel_crtc_state *other_crtc_state = NULL;
13372 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13375 /* look at all crtc's that are going to be enabled in during modeset */
13376 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13377 if (!crtc_state->base.active ||
13378 !needs_modeset(crtc_state))
13381 if (first_crtc_state) {
13382 other_crtc_state = crtc_state;
13385 first_crtc_state = crtc_state;
13386 first_pipe = crtc->pipe;
13390 /* No workaround needed? */
13391 if (!first_crtc_state)
13394 /* w/a possibly needed, check how many crtc's are already enabled. */
13395 for_each_intel_crtc(state->base.dev, crtc) {
13396 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13397 if (IS_ERR(crtc_state))
13398 return PTR_ERR(crtc_state);
13400 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13402 if (!crtc_state->base.active ||
13403 needs_modeset(crtc_state))
13406 /* 2 or more enabled crtcs means no need for w/a */
13407 if (enabled_pipe != INVALID_PIPE)
13410 enabled_pipe = crtc->pipe;
13413 if (enabled_pipe != INVALID_PIPE)
13414 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13415 else if (other_crtc_state)
13416 other_crtc_state->hsw_workaround_pipe = first_pipe;
13421 static int intel_lock_all_pipes(struct intel_atomic_state *state)
13423 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13424 struct intel_crtc *crtc;
13426 /* Add all pipes to the state */
13427 for_each_intel_crtc(&dev_priv->drm, crtc) {
13428 struct intel_crtc_state *crtc_state;
13430 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13431 if (IS_ERR(crtc_state))
13432 return PTR_ERR(crtc_state);
13438 static int intel_modeset_all_pipes(struct intel_atomic_state *state)
13440 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13441 struct intel_crtc *crtc;
13444 * Add all pipes to the state, and force
13445 * a modeset on all the active ones.
13447 for_each_intel_crtc(&dev_priv->drm, crtc) {
13448 struct intel_crtc_state *crtc_state;
13451 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13452 if (IS_ERR(crtc_state))
13453 return PTR_ERR(crtc_state);
13455 if (!crtc_state->base.active || needs_modeset(crtc_state))
13458 crtc_state->base.mode_changed = true;
13460 ret = drm_atomic_add_affected_connectors(&state->base,
13465 ret = drm_atomic_add_affected_planes(&state->base,
13474 static int intel_modeset_checks(struct intel_atomic_state *state)
13476 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13477 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13478 struct intel_crtc *crtc;
13481 if (!check_digital_port_conflicts(state)) {
13482 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13486 /* keep the current setting */
13487 if (!state->cdclk.force_min_cdclk_changed)
13488 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
13490 state->modeset = true;
13491 state->active_pipes = dev_priv->active_pipes;
13492 state->cdclk.logical = dev_priv->cdclk.logical;
13493 state->cdclk.actual = dev_priv->cdclk.actual;
13494 state->cdclk.pipe = INVALID_PIPE;
13496 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13497 new_crtc_state, i) {
13498 if (new_crtc_state->base.active)
13499 state->active_pipes |= BIT(crtc->pipe);
13501 state->active_pipes &= ~BIT(crtc->pipe);
13503 if (old_crtc_state->base.active != new_crtc_state->base.active)
13504 state->active_pipe_changes |= BIT(crtc->pipe);
13508 * See if the config requires any additional preparation, e.g.
13509 * to adjust global state with pipes off. We need to do this
13510 * here so we can get the modeset_pipe updated config for the new
13511 * mode set on this crtc. For other crtcs we need to use the
13512 * adjusted_mode bits in the crtc directly.
13514 if (dev_priv->display.modeset_calc_cdclk) {
13517 ret = dev_priv->display.modeset_calc_cdclk(state);
13522 * Writes to dev_priv->cdclk.logical must protected by
13523 * holding all the crtc locks, even if we don't end up
13524 * touching the hardware
13526 if (intel_cdclk_changed(&dev_priv->cdclk.logical,
13527 &state->cdclk.logical)) {
13528 ret = intel_lock_all_pipes(state);
13533 if (is_power_of_2(state->active_pipes)) {
13534 struct intel_crtc *crtc;
13535 struct intel_crtc_state *crtc_state;
13537 pipe = ilog2(state->active_pipes);
13538 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
13539 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13540 if (crtc_state && needs_modeset(crtc_state))
13541 pipe = INVALID_PIPE;
13543 pipe = INVALID_PIPE;
13546 /* All pipes must be switched off while we change the cdclk. */
13547 if (pipe != INVALID_PIPE &&
13548 intel_cdclk_needs_cd2x_update(dev_priv,
13549 &dev_priv->cdclk.actual,
13550 &state->cdclk.actual)) {
13551 ret = intel_lock_all_pipes(state);
13555 state->cdclk.pipe = pipe;
13556 } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
13557 &state->cdclk.actual)) {
13558 ret = intel_modeset_all_pipes(state);
13562 state->cdclk.pipe = INVALID_PIPE;
13565 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
13566 state->cdclk.logical.cdclk,
13567 state->cdclk.actual.cdclk);
13568 DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
13569 state->cdclk.logical.voltage_level,
13570 state->cdclk.actual.voltage_level);
13573 intel_modeset_clear_plls(state);
13575 if (IS_HASWELL(dev_priv))
13576 return haswell_mode_set_planes_workaround(state);
13582 * Handle calculation of various watermark data at the end of the atomic check
13583 * phase. The code here should be run after the per-crtc and per-plane 'check'
13584 * handlers to ensure that all derived state has been updated.
13586 static int calc_watermark_data(struct intel_atomic_state *state)
13588 struct drm_device *dev = state->base.dev;
13589 struct drm_i915_private *dev_priv = to_i915(dev);
13591 /* Is there platform-specific watermark information to calculate? */
13592 if (dev_priv->display.compute_global_watermarks)
13593 return dev_priv->display.compute_global_watermarks(state);
13598 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
13599 struct intel_crtc_state *new_crtc_state)
13601 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
13604 new_crtc_state->base.mode_changed = false;
13605 new_crtc_state->update_pipe = true;
13608 * If we're not doing the full modeset we want to
13609 * keep the current M/N values as they may be
13610 * sufficiently different to the computed values
13611 * to cause problems.
13613 * FIXME: should really copy more fuzzy state here
13615 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
13616 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
13617 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
13618 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
13622 * intel_atomic_check - validate state object
13624 * @_state: state to validate
13626 static int intel_atomic_check(struct drm_device *dev,
13627 struct drm_atomic_state *_state)
13629 struct drm_i915_private *dev_priv = to_i915(dev);
13630 struct intel_atomic_state *state = to_intel_atomic_state(_state);
13631 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13632 struct intel_crtc *crtc;
13634 bool any_ms = state->cdclk.force_min_cdclk_changed;
13636 /* Catch I915_MODE_FLAG_INHERITED */
13637 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13638 new_crtc_state, i) {
13639 if (new_crtc_state->base.mode.private_flags !=
13640 old_crtc_state->base.mode.private_flags)
13641 new_crtc_state->base.mode_changed = true;
13644 ret = drm_atomic_helper_check_modeset(dev, &state->base);
13648 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13649 new_crtc_state, i) {
13650 if (!needs_modeset(new_crtc_state))
13653 if (!new_crtc_state->base.enable) {
13658 ret = intel_modeset_pipe_config(new_crtc_state);
13662 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
13664 if (needs_modeset(new_crtc_state))
13668 ret = drm_dp_mst_atomic_check(&state->base);
13673 ret = intel_modeset_checks(state);
13677 state->cdclk.logical = dev_priv->cdclk.logical;
13680 ret = icl_add_linked_planes(state);
13684 ret = drm_atomic_helper_check_planes(dev, &state->base);
13688 intel_fbc_choose_crtc(dev_priv, state);
13689 ret = calc_watermark_data(state);
13693 ret = intel_bw_atomic_check(state);
13697 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13698 new_crtc_state, i) {
13699 if (!needs_modeset(new_crtc_state) &&
13700 !new_crtc_state->update_pipe)
13703 intel_dump_pipe_config(new_crtc_state, state,
13704 needs_modeset(new_crtc_state) ?
13705 "[modeset]" : "[fastset]");
13711 if (ret == -EDEADLK)
13715 * FIXME would probably be nice to know which crtc specifically
13716 * caused the failure, in cases where we can pinpoint it.
13718 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13720 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
13725 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
13727 return drm_atomic_helper_prepare_planes(state->base.dev,
13731 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13733 struct drm_device *dev = crtc->base.dev;
13734 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
13736 if (!vblank->max_vblank_count)
13737 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
13739 return crtc->base.funcs->get_vblank_counter(&crtc->base);
13742 static void intel_update_crtc(struct intel_crtc *crtc,
13743 struct intel_atomic_state *state,
13744 struct intel_crtc_state *old_crtc_state,
13745 struct intel_crtc_state *new_crtc_state)
13747 struct drm_device *dev = state->base.dev;
13748 struct drm_i915_private *dev_priv = to_i915(dev);
13749 bool modeset = needs_modeset(new_crtc_state);
13750 struct intel_plane_state *new_plane_state =
13751 intel_atomic_get_new_plane_state(state,
13752 to_intel_plane(crtc->base.primary));
13755 update_scanline_offset(new_crtc_state);
13756 dev_priv->display.crtc_enable(new_crtc_state, state);
13758 /* vblanks work again, re-enable pipe CRC. */
13759 intel_crtc_enable_pipe_crc(crtc);
13761 intel_pre_plane_update(old_crtc_state, new_crtc_state);
13763 if (new_crtc_state->update_pipe)
13764 intel_encoders_update_pipe(crtc, new_crtc_state, state);
13767 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
13768 intel_fbc_disable(crtc);
13769 else if (new_plane_state)
13770 intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
13772 intel_begin_crtc_commit(state, crtc);
13774 if (INTEL_GEN(dev_priv) >= 9)
13775 skl_update_planes_on_crtc(state, crtc);
13777 i9xx_update_planes_on_crtc(state, crtc);
13779 intel_finish_crtc_commit(state, crtc);
13782 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
13783 struct intel_crtc_state *old_crtc_state,
13784 struct intel_crtc_state *new_crtc_state,
13785 struct intel_crtc *crtc)
13787 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13789 intel_crtc_disable_planes(state, crtc);
13792 * We need to disable pipe CRC before disabling the pipe,
13793 * or we race against vblank off.
13795 intel_crtc_disable_pipe_crc(crtc);
13797 dev_priv->display.crtc_disable(old_crtc_state, state);
13798 crtc->active = false;
13799 intel_fbc_disable(crtc);
13800 intel_disable_shared_dpll(old_crtc_state);
13803 * Underruns don't always raise interrupts,
13804 * so check manually.
13806 intel_check_cpu_fifo_underruns(dev_priv);
13807 intel_check_pch_fifo_underruns(dev_priv);
13809 /* FIXME unify this for all platforms */
13810 if (!new_crtc_state->base.active &&
13811 !HAS_GMCH(dev_priv) &&
13812 dev_priv->display.initial_watermarks)
13813 dev_priv->display.initial_watermarks(state,
13817 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
13819 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
13820 struct intel_crtc *crtc;
13824 * Disable CRTC/pipes in reverse order because some features(MST in
13825 * TGL+) requires master and slave relationship between pipes, so it
13826 * should always pick the lowest pipe as master as it will be enabled
13827 * first and disable in the reverse order so the master will be the
13828 * last one to be disabled.
13830 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
13831 new_crtc_state, i) {
13832 if (!needs_modeset(new_crtc_state))
13835 intel_pre_plane_update(old_crtc_state, new_crtc_state);
13837 if (old_crtc_state->base.active)
13838 intel_old_crtc_state_disables(state,
13845 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
13847 struct intel_crtc *crtc;
13848 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13851 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13852 if (!new_crtc_state->base.active)
13855 intel_update_crtc(crtc, state, old_crtc_state,
13860 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
13862 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13863 struct intel_crtc *crtc;
13864 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
13865 unsigned int updated = 0;
13869 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
13870 u8 required_slices = state->wm_results.ddb.enabled_slices;
13871 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
13873 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
13874 /* ignore allocations for crtc's that have been turned off. */
13875 if (new_crtc_state->base.active)
13876 entries[i] = old_crtc_state->wm.skl.ddb;
13878 /* If 2nd DBuf slice required, enable it here */
13879 if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
13880 icl_dbuf_slices_update(dev_priv, required_slices);
13883 * Whenever the number of active pipes changes, we need to make sure we
13884 * update the pipes in the right order so that their ddb allocations
13885 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
13886 * cause pipe underruns and other bad stuff.
13891 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13892 bool vbl_wait = false;
13893 unsigned int cmask = drm_crtc_mask(&crtc->base);
13897 if (updated & cmask || !new_crtc_state->base.active)
13900 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
13902 INTEL_INFO(dev_priv)->num_pipes, i))
13906 entries[i] = new_crtc_state->wm.skl.ddb;
13909 * If this is an already active pipe, it's DDB changed,
13910 * and this isn't the last pipe that needs updating
13911 * then we need to wait for a vblank to pass for the
13912 * new ddb allocation to take effect.
13914 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
13915 &old_crtc_state->wm.skl.ddb) &&
13916 !new_crtc_state->base.active_changed &&
13917 state->wm_results.dirty_pipes != updated)
13920 intel_update_crtc(crtc, state, old_crtc_state,
13924 intel_wait_for_vblank(dev_priv, pipe);
13928 } while (progress);
13930 /* If 2nd DBuf slice is no more required disable it */
13931 if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
13932 icl_dbuf_slices_update(dev_priv, required_slices);
13935 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
13937 struct intel_atomic_state *state, *next;
13938 struct llist_node *freed;
13940 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
13941 llist_for_each_entry_safe(state, next, freed, freed)
13942 drm_atomic_state_put(&state->base);
13945 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
13947 struct drm_i915_private *dev_priv =
13948 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
13950 intel_atomic_helper_free_state(dev_priv);
13953 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
13955 struct wait_queue_entry wait_fence, wait_reset;
13956 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
13958 init_wait_entry(&wait_fence, 0);
13959 init_wait_entry(&wait_reset, 0);
13961 prepare_to_wait(&intel_state->commit_ready.wait,
13962 &wait_fence, TASK_UNINTERRUPTIBLE);
13963 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
13964 I915_RESET_MODESET),
13965 &wait_reset, TASK_UNINTERRUPTIBLE);
13968 if (i915_sw_fence_done(&intel_state->commit_ready) ||
13969 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
13974 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
13975 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
13976 I915_RESET_MODESET),
13980 static void intel_atomic_cleanup_work(struct work_struct *work)
13982 struct drm_atomic_state *state =
13983 container_of(work, struct drm_atomic_state, commit_work);
13984 struct drm_i915_private *i915 = to_i915(state->dev);
13986 drm_atomic_helper_cleanup_planes(&i915->drm, state);
13987 drm_atomic_helper_commit_cleanup_done(state);
13988 drm_atomic_state_put(state);
13990 intel_atomic_helper_free_state(i915);
13993 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
13995 struct drm_device *dev = state->base.dev;
13996 struct drm_i915_private *dev_priv = to_i915(dev);
13997 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
13998 struct intel_crtc *crtc;
13999 u64 put_domains[I915_MAX_PIPES] = {};
14000 intel_wakeref_t wakeref = 0;
14003 intel_atomic_commit_fence_wait(state);
14005 drm_atomic_helper_wait_for_dependencies(&state->base);
14007 if (state->modeset)
14008 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14010 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14011 new_crtc_state, i) {
14012 if (needs_modeset(new_crtc_state) ||
14013 new_crtc_state->update_pipe) {
14015 put_domains[crtc->pipe] =
14016 modeset_get_crtc_power_domains(new_crtc_state);
14020 intel_commit_modeset_disables(state);
14022 /* FIXME: Eventually get rid of our crtc->config pointer */
14023 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14024 crtc->config = new_crtc_state;
14026 if (state->modeset) {
14027 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
14029 intel_set_cdclk_pre_plane_update(dev_priv,
14030 &state->cdclk.actual,
14031 &dev_priv->cdclk.actual,
14032 state->cdclk.pipe);
14035 * SKL workaround: bspec recommends we disable the SAGV when we
14036 * have more then one pipe enabled
14038 if (!intel_can_enable_sagv(state))
14039 intel_disable_sagv(dev_priv);
14041 intel_modeset_verify_disabled(dev_priv, state);
14044 /* Complete the events for pipes that have now been disabled */
14045 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14046 bool modeset = needs_modeset(new_crtc_state);
14048 /* Complete events for now disable pipes here. */
14049 if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
14050 spin_lock_irq(&dev->event_lock);
14051 drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
14052 spin_unlock_irq(&dev->event_lock);
14054 new_crtc_state->base.event = NULL;
14058 if (state->modeset)
14059 intel_encoders_update_prepare(state);
14061 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14062 dev_priv->display.commit_modeset_enables(state);
14064 if (state->modeset) {
14065 intel_encoders_update_complete(state);
14067 intel_set_cdclk_post_plane_update(dev_priv,
14068 &state->cdclk.actual,
14069 &dev_priv->cdclk.actual,
14070 state->cdclk.pipe);
14073 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14074 * already, but still need the state for the delayed optimization. To
14076 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14077 * - schedule that vblank worker _before_ calling hw_done
14078 * - at the start of commit_tail, cancel it _synchrously
14079 * - switch over to the vblank wait helper in the core after that since
14080 * we don't need out special handling any more.
14082 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
14084 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14085 if (new_crtc_state->base.active &&
14086 !needs_modeset(new_crtc_state) &&
14087 (new_crtc_state->base.color_mgmt_changed ||
14088 new_crtc_state->update_pipe))
14089 intel_color_load_luts(new_crtc_state);
14093 * Now that the vblank has passed, we can go ahead and program the
14094 * optimal watermarks on platforms that need two-step watermark
14097 * TODO: Move this (and other cleanup) to an async worker eventually.
14099 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14100 if (dev_priv->display.optimize_watermarks)
14101 dev_priv->display.optimize_watermarks(state,
14105 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
14106 intel_post_plane_update(old_crtc_state);
14108 if (put_domains[i])
14109 modeset_put_power_domains(dev_priv, put_domains[i]);
14111 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
14114 if (state->modeset)
14115 intel_verify_planes(state);
14117 if (state->modeset && intel_can_enable_sagv(state))
14118 intel_enable_sagv(dev_priv);
14120 drm_atomic_helper_commit_hw_done(&state->base);
14122 if (state->modeset) {
14123 /* As one of the primary mmio accessors, KMS has a high
14124 * likelihood of triggering bugs in unclaimed access. After we
14125 * finish modesetting, see if an error has been flagged, and if
14126 * so enable debugging for the next modeset - and hope we catch
14129 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
14130 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
14132 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14135 * Defer the cleanup of the old state to a separate worker to not
14136 * impede the current task (userspace for blocking modesets) that
14137 * are executed inline. For out-of-line asynchronous modesets/flips,
14138 * deferring to a new worker seems overkill, but we would place a
14139 * schedule point (cond_resched()) here anyway to keep latencies
14142 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
14143 queue_work(system_highpri_wq, &state->base.commit_work);
14146 static void intel_atomic_commit_work(struct work_struct *work)
14148 struct intel_atomic_state *state =
14149 container_of(work, struct intel_atomic_state, base.commit_work);
14151 intel_atomic_commit_tail(state);
14154 static int __i915_sw_fence_call
14155 intel_atomic_commit_ready(struct i915_sw_fence *fence,
14156 enum i915_sw_fence_notify notify)
14158 struct intel_atomic_state *state =
14159 container_of(fence, struct intel_atomic_state, commit_ready);
14162 case FENCE_COMPLETE:
14163 /* we do blocking waits in the worker, nothing to do here */
14167 struct intel_atomic_helper *helper =
14168 &to_i915(state->base.dev)->atomic_helper;
14170 if (llist_add(&state->freed, &helper->free_list))
14171 schedule_work(&helper->free_work);
14176 return NOTIFY_DONE;
14179 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
14181 struct intel_plane_state *old_plane_state, *new_plane_state;
14182 struct intel_plane *plane;
14185 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
14186 new_plane_state, i)
14187 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb),
14188 to_intel_frontbuffer(new_plane_state->base.fb),
14189 plane->frontbuffer_bit);
14192 static int intel_atomic_commit(struct drm_device *dev,
14193 struct drm_atomic_state *_state,
14196 struct intel_atomic_state *state = to_intel_atomic_state(_state);
14197 struct drm_i915_private *dev_priv = to_i915(dev);
14200 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
14202 drm_atomic_state_get(&state->base);
14203 i915_sw_fence_init(&state->commit_ready,
14204 intel_atomic_commit_ready);
14207 * The intel_legacy_cursor_update() fast path takes care
14208 * of avoiding the vblank waits for simple cursor
14209 * movement and flips. For cursor on/off and size changes,
14210 * we want to perform the vblank waits so that watermark
14211 * updates happen during the correct frames. Gen9+ have
14212 * double buffered watermarks and so shouldn't need this.
14214 * Unset state->legacy_cursor_update before the call to
14215 * drm_atomic_helper_setup_commit() because otherwise
14216 * drm_atomic_helper_wait_for_flip_done() is a noop and
14217 * we get FIFO underruns because we didn't wait
14220 * FIXME doing watermarks and fb cleanup from a vblank worker
14221 * (assuming we had any) would solve these problems.
14223 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
14224 struct intel_crtc_state *new_crtc_state;
14225 struct intel_crtc *crtc;
14228 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14229 if (new_crtc_state->wm.need_postvbl_update ||
14230 new_crtc_state->update_wm_post)
14231 state->base.legacy_cursor_update = false;
14234 ret = intel_atomic_prepare_commit(state);
14236 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14237 i915_sw_fence_commit(&state->commit_ready);
14238 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14242 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
14244 ret = drm_atomic_helper_swap_state(&state->base, true);
14247 i915_sw_fence_commit(&state->commit_ready);
14249 drm_atomic_helper_cleanup_planes(dev, &state->base);
14250 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14253 dev_priv->wm.distrust_bios_wm = false;
14254 intel_shared_dpll_swap_state(state);
14255 intel_atomic_track_fbs(state);
14257 if (state->modeset) {
14258 memcpy(dev_priv->min_cdclk, state->min_cdclk,
14259 sizeof(state->min_cdclk));
14260 memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
14261 sizeof(state->min_voltage_level));
14262 dev_priv->active_pipes = state->active_pipes;
14263 dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
14265 intel_cdclk_swap_state(state);
14268 drm_atomic_state_get(&state->base);
14269 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
14271 i915_sw_fence_commit(&state->commit_ready);
14272 if (nonblock && state->modeset) {
14273 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
14274 } else if (nonblock) {
14275 queue_work(dev_priv->flip_wq, &state->base.commit_work);
14277 if (state->modeset)
14278 flush_workqueue(dev_priv->modeset_wq);
14279 intel_atomic_commit_tail(state);
14285 struct wait_rps_boost {
14286 struct wait_queue_entry wait;
14288 struct drm_crtc *crtc;
14289 struct i915_request *request;
14292 static int do_rps_boost(struct wait_queue_entry *_wait,
14293 unsigned mode, int sync, void *key)
14295 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
14296 struct i915_request *rq = wait->request;
14299 * If we missed the vblank, but the request is already running it
14300 * is reasonable to assume that it will complete before the next
14301 * vblank without our intervention, so leave RPS alone.
14303 if (!i915_request_started(rq))
14304 gen6_rps_boost(rq);
14305 i915_request_put(rq);
14307 drm_crtc_vblank_put(wait->crtc);
14309 list_del(&wait->wait.entry);
14314 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
14315 struct dma_fence *fence)
14317 struct wait_rps_boost *wait;
14319 if (!dma_fence_is_i915(fence))
14322 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
14325 if (drm_crtc_vblank_get(crtc))
14328 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
14330 drm_crtc_vblank_put(crtc);
14334 wait->request = to_request(dma_fence_get(fence));
14337 wait->wait.func = do_rps_boost;
14338 wait->wait.flags = 0;
14340 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
14343 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
14345 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
14346 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14347 struct drm_framebuffer *fb = plane_state->base.fb;
14348 struct i915_vma *vma;
14350 if (plane->id == PLANE_CURSOR &&
14351 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
14352 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14353 const int align = intel_cursor_alignment(dev_priv);
14356 err = i915_gem_object_attach_phys(obj, align);
14361 vma = intel_pin_and_fence_fb_obj(fb,
14362 &plane_state->view,
14363 intel_plane_uses_fence(plane_state),
14364 &plane_state->flags);
14366 return PTR_ERR(vma);
14368 plane_state->vma = vma;
14373 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
14375 struct i915_vma *vma;
14377 vma = fetch_and_zero(&old_plane_state->vma);
14379 intel_unpin_fb_vma(vma, old_plane_state->flags);
14382 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
14384 struct i915_sched_attr attr = {
14385 .priority = I915_PRIORITY_DISPLAY,
14388 i915_gem_object_wait_priority(obj, 0, &attr);
14392 * intel_prepare_plane_fb - Prepare fb for usage on plane
14393 * @plane: drm plane to prepare for
14394 * @new_state: the plane state being prepared
14396 * Prepares a framebuffer for usage on a display plane. Generally this
14397 * involves pinning the underlying object and updating the frontbuffer tracking
14398 * bits. Some older platforms need special physical address handling for
14401 * Must be called with struct_mutex held.
14403 * Returns 0 on success, negative error code on failure.
14406 intel_prepare_plane_fb(struct drm_plane *plane,
14407 struct drm_plane_state *new_state)
14409 struct intel_atomic_state *intel_state =
14410 to_intel_atomic_state(new_state->state);
14411 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14412 struct drm_framebuffer *fb = new_state->fb;
14413 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14414 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14418 struct intel_crtc_state *crtc_state =
14419 intel_atomic_get_new_crtc_state(intel_state,
14420 to_intel_crtc(plane->state->crtc));
14422 /* Big Hammer, we also need to ensure that any pending
14423 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14424 * current scanout is retired before unpinning the old
14425 * framebuffer. Note that we rely on userspace rendering
14426 * into the buffer attached to the pipe they are waiting
14427 * on. If not, userspace generates a GPU hang with IPEHR
14428 * point to the MI_WAIT_FOR_EVENT.
14430 * This should only fail upon a hung GPU, in which case we
14431 * can safely continue.
14433 if (needs_modeset(crtc_state)) {
14434 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14435 old_obj->base.resv, NULL,
14443 if (new_state->fence) { /* explicit fencing */
14444 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
14446 I915_FENCE_TIMEOUT,
14455 ret = i915_gem_object_pin_pages(obj);
14459 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
14461 i915_gem_object_unpin_pages(obj);
14465 ret = intel_plane_pin_fb(to_intel_plane_state(new_state));
14467 mutex_unlock(&dev_priv->drm.struct_mutex);
14468 i915_gem_object_unpin_pages(obj);
14472 fb_obj_bump_render_priority(obj);
14473 intel_frontbuffer_flush(obj->frontbuffer, ORIGIN_DIRTYFB);
14475 if (!new_state->fence) { /* implicit fencing */
14476 struct dma_fence *fence;
14478 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
14479 obj->base.resv, NULL,
14480 false, I915_FENCE_TIMEOUT,
14485 fence = dma_resv_get_excl_rcu(obj->base.resv);
14487 add_rps_boost_after_vblank(new_state->crtc, fence);
14488 dma_fence_put(fence);
14491 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
14495 * We declare pageflips to be interactive and so merit a small bias
14496 * towards upclocking to deliver the frame on time. By only changing
14497 * the RPS thresholds to sample more regularly and aim for higher
14498 * clocks we can hopefully deliver low power workloads (like kodi)
14499 * that are not quite steady state without resorting to forcing
14500 * maximum clocks following a vblank miss (see do_rps_boost()).
14502 if (!intel_state->rps_interactive) {
14503 intel_rps_mark_interactive(dev_priv, true);
14504 intel_state->rps_interactive = true;
14511 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14512 * @plane: drm plane to clean up for
14513 * @old_state: the state from the previous modeset
14515 * Cleans up a framebuffer that has just been removed from a plane.
14517 * Must be called with struct_mutex held.
14520 intel_cleanup_plane_fb(struct drm_plane *plane,
14521 struct drm_plane_state *old_state)
14523 struct intel_atomic_state *intel_state =
14524 to_intel_atomic_state(old_state->state);
14525 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14527 if (intel_state->rps_interactive) {
14528 intel_rps_mark_interactive(dev_priv, false);
14529 intel_state->rps_interactive = false;
14532 /* Should only be called after a successful intel_prepare_plane_fb()! */
14533 mutex_lock(&dev_priv->drm.struct_mutex);
14534 intel_plane_unpin_fb(to_intel_plane_state(old_state));
14535 mutex_unlock(&dev_priv->drm.struct_mutex);
14539 skl_max_scale(const struct intel_crtc_state *crtc_state,
14542 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
14543 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14544 int max_scale, mult;
14545 int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
14547 if (!crtc_state->base.enable)
14548 return DRM_PLANE_HELPER_NO_SCALING;
14550 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14551 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
14553 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
14556 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
14557 return DRM_PLANE_HELPER_NO_SCALING;
14560 * skl max scale is lower of:
14561 * close to 3 but not 3, -1 is for that purpose
14565 mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
14566 tmpclk1 = (1 << 16) * mult - 1;
14567 tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
14568 max_scale = min(tmpclk1, tmpclk2);
14573 static void intel_begin_crtc_commit(struct intel_atomic_state *state,
14574 struct intel_crtc *crtc)
14576 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14577 struct intel_crtc_state *old_crtc_state =
14578 intel_atomic_get_old_crtc_state(state, crtc);
14579 struct intel_crtc_state *new_crtc_state =
14580 intel_atomic_get_new_crtc_state(state, crtc);
14581 bool modeset = needs_modeset(new_crtc_state);
14583 /* Perform vblank evasion around commit operation */
14584 intel_pipe_update_start(new_crtc_state);
14589 if (new_crtc_state->base.color_mgmt_changed ||
14590 new_crtc_state->update_pipe)
14591 intel_color_commit(new_crtc_state);
14593 if (new_crtc_state->update_pipe)
14594 intel_update_pipe_config(old_crtc_state, new_crtc_state);
14595 else if (INTEL_GEN(dev_priv) >= 9)
14596 skl_detach_scalers(new_crtc_state);
14598 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
14599 bdw_set_pipemisc(new_crtc_state);
14602 if (dev_priv->display.atomic_update_watermarks)
14603 dev_priv->display.atomic_update_watermarks(state,
14607 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14608 struct intel_crtc_state *crtc_state)
14610 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14612 if (!IS_GEN(dev_priv, 2))
14613 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14615 if (crtc_state->has_pch_encoder) {
14616 enum pipe pch_transcoder =
14617 intel_crtc_pch_transcoder(crtc);
14619 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14623 static void intel_finish_crtc_commit(struct intel_atomic_state *state,
14624 struct intel_crtc *crtc)
14626 struct intel_crtc_state *old_crtc_state =
14627 intel_atomic_get_old_crtc_state(state, crtc);
14628 struct intel_crtc_state *new_crtc_state =
14629 intel_atomic_get_new_crtc_state(state, crtc);
14631 intel_pipe_update_end(new_crtc_state);
14633 if (new_crtc_state->update_pipe &&
14634 !needs_modeset(new_crtc_state) &&
14635 old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
14636 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14640 * intel_plane_destroy - destroy a plane
14641 * @plane: plane to destroy
14643 * Common destruction function for all types of planes (primary, cursor,
14646 void intel_plane_destroy(struct drm_plane *plane)
14648 drm_plane_cleanup(plane);
14649 kfree(to_intel_plane(plane));
14652 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
14653 u32 format, u64 modifier)
14655 switch (modifier) {
14656 case DRM_FORMAT_MOD_LINEAR:
14657 case I915_FORMAT_MOD_X_TILED:
14664 case DRM_FORMAT_C8:
14665 case DRM_FORMAT_RGB565:
14666 case DRM_FORMAT_XRGB1555:
14667 case DRM_FORMAT_XRGB8888:
14668 return modifier == DRM_FORMAT_MOD_LINEAR ||
14669 modifier == I915_FORMAT_MOD_X_TILED;
14675 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
14676 u32 format, u64 modifier)
14678 switch (modifier) {
14679 case DRM_FORMAT_MOD_LINEAR:
14680 case I915_FORMAT_MOD_X_TILED:
14687 case DRM_FORMAT_C8:
14688 case DRM_FORMAT_RGB565:
14689 case DRM_FORMAT_XRGB8888:
14690 case DRM_FORMAT_XBGR8888:
14691 case DRM_FORMAT_XRGB2101010:
14692 case DRM_FORMAT_XBGR2101010:
14693 return modifier == DRM_FORMAT_MOD_LINEAR ||
14694 modifier == I915_FORMAT_MOD_X_TILED;
14700 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
14701 u32 format, u64 modifier)
14703 return modifier == DRM_FORMAT_MOD_LINEAR &&
14704 format == DRM_FORMAT_ARGB8888;
14707 static const struct drm_plane_funcs i965_plane_funcs = {
14708 .update_plane = drm_atomic_helper_update_plane,
14709 .disable_plane = drm_atomic_helper_disable_plane,
14710 .destroy = intel_plane_destroy,
14711 .atomic_duplicate_state = intel_plane_duplicate_state,
14712 .atomic_destroy_state = intel_plane_destroy_state,
14713 .format_mod_supported = i965_plane_format_mod_supported,
14716 static const struct drm_plane_funcs i8xx_plane_funcs = {
14717 .update_plane = drm_atomic_helper_update_plane,
14718 .disable_plane = drm_atomic_helper_disable_plane,
14719 .destroy = intel_plane_destroy,
14720 .atomic_duplicate_state = intel_plane_duplicate_state,
14721 .atomic_destroy_state = intel_plane_destroy_state,
14722 .format_mod_supported = i8xx_plane_format_mod_supported,
14726 intel_legacy_cursor_update(struct drm_plane *plane,
14727 struct drm_crtc *crtc,
14728 struct drm_framebuffer *fb,
14729 int crtc_x, int crtc_y,
14730 unsigned int crtc_w, unsigned int crtc_h,
14731 u32 src_x, u32 src_y,
14732 u32 src_w, u32 src_h,
14733 struct drm_modeset_acquire_ctx *ctx)
14735 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
14736 struct drm_plane_state *old_plane_state, *new_plane_state;
14737 struct intel_plane *intel_plane = to_intel_plane(plane);
14738 struct intel_crtc_state *crtc_state =
14739 to_intel_crtc_state(crtc->state);
14740 struct intel_crtc_state *new_crtc_state;
14744 * When crtc is inactive or there is a modeset pending,
14745 * wait for it to complete in the slowpath
14747 if (!crtc_state->base.active || needs_modeset(crtc_state) ||
14748 crtc_state->update_pipe)
14751 old_plane_state = plane->state;
14753 * Don't do an async update if there is an outstanding commit modifying
14754 * the plane. This prevents our async update's changes from getting
14755 * overridden by a previous synchronous update's state.
14757 if (old_plane_state->commit &&
14758 !try_wait_for_completion(&old_plane_state->commit->hw_done))
14762 * If any parameters change that may affect watermarks,
14763 * take the slowpath. Only changing fb or position should be
14766 if (old_plane_state->crtc != crtc ||
14767 old_plane_state->src_w != src_w ||
14768 old_plane_state->src_h != src_h ||
14769 old_plane_state->crtc_w != crtc_w ||
14770 old_plane_state->crtc_h != crtc_h ||
14771 !old_plane_state->fb != !fb)
14774 new_plane_state = intel_plane_duplicate_state(plane);
14775 if (!new_plane_state)
14778 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(crtc));
14779 if (!new_crtc_state) {
14784 drm_atomic_set_fb_for_plane(new_plane_state, fb);
14786 new_plane_state->src_x = src_x;
14787 new_plane_state->src_y = src_y;
14788 new_plane_state->src_w = src_w;
14789 new_plane_state->src_h = src_h;
14790 new_plane_state->crtc_x = crtc_x;
14791 new_plane_state->crtc_y = crtc_y;
14792 new_plane_state->crtc_w = crtc_w;
14793 new_plane_state->crtc_h = crtc_h;
14795 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
14796 to_intel_plane_state(old_plane_state),
14797 to_intel_plane_state(new_plane_state));
14801 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
14805 ret = intel_plane_pin_fb(to_intel_plane_state(new_plane_state));
14809 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_FLIP);
14810 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->fb),
14811 to_intel_frontbuffer(fb),
14812 intel_plane->frontbuffer_bit);
14814 /* Swap plane state */
14815 plane->state = new_plane_state;
14818 * We cannot swap crtc_state as it may be in use by an atomic commit or
14819 * page flip that's running simultaneously. If we swap crtc_state and
14820 * destroy the old state, we will cause a use-after-free there.
14822 * Only update active_planes, which is needed for our internal
14823 * bookkeeping. Either value will do the right thing when updating
14824 * planes atomically. If the cursor was part of the atomic update then
14825 * we would have taken the slowpath.
14827 crtc_state->active_planes = new_crtc_state->active_planes;
14829 if (plane->state->visible)
14830 intel_update_plane(intel_plane, crtc_state,
14831 to_intel_plane_state(plane->state));
14833 intel_disable_plane(intel_plane, crtc_state);
14835 intel_plane_unpin_fb(to_intel_plane_state(old_plane_state));
14838 mutex_unlock(&dev_priv->drm.struct_mutex);
14840 if (new_crtc_state)
14841 intel_crtc_destroy_state(crtc, &new_crtc_state->base);
14843 intel_plane_destroy_state(plane, new_plane_state);
14845 intel_plane_destroy_state(plane, old_plane_state);
14849 return drm_atomic_helper_update_plane(plane, crtc, fb,
14850 crtc_x, crtc_y, crtc_w, crtc_h,
14851 src_x, src_y, src_w, src_h, ctx);
14854 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
14855 .update_plane = intel_legacy_cursor_update,
14856 .disable_plane = drm_atomic_helper_disable_plane,
14857 .destroy = intel_plane_destroy,
14858 .atomic_duplicate_state = intel_plane_duplicate_state,
14859 .atomic_destroy_state = intel_plane_destroy_state,
14860 .format_mod_supported = intel_cursor_format_mod_supported,
14863 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
14864 enum i9xx_plane_id i9xx_plane)
14866 if (!HAS_FBC(dev_priv))
14869 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
14870 return i9xx_plane == PLANE_A; /* tied to pipe A */
14871 else if (IS_IVYBRIDGE(dev_priv))
14872 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
14873 i9xx_plane == PLANE_C;
14874 else if (INTEL_GEN(dev_priv) >= 4)
14875 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
14877 return i9xx_plane == PLANE_A;
14880 static struct intel_plane *
14881 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
14883 struct intel_plane *plane;
14884 const struct drm_plane_funcs *plane_funcs;
14885 unsigned int supported_rotations;
14886 unsigned int possible_crtcs;
14887 const u64 *modifiers;
14888 const u32 *formats;
14892 if (INTEL_GEN(dev_priv) >= 9)
14893 return skl_universal_plane_create(dev_priv, pipe,
14896 plane = intel_plane_alloc();
14900 plane->pipe = pipe;
14902 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
14903 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
14905 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
14906 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
14908 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
14909 plane->id = PLANE_PRIMARY;
14910 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
14912 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
14913 if (plane->has_fbc) {
14914 struct intel_fbc *fbc = &dev_priv->fbc;
14916 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
14919 if (INTEL_GEN(dev_priv) >= 4) {
14920 formats = i965_primary_formats;
14921 num_formats = ARRAY_SIZE(i965_primary_formats);
14922 modifiers = i9xx_format_modifiers;
14924 plane->max_stride = i9xx_plane_max_stride;
14925 plane->update_plane = i9xx_update_plane;
14926 plane->disable_plane = i9xx_disable_plane;
14927 plane->get_hw_state = i9xx_plane_get_hw_state;
14928 plane->check_plane = i9xx_plane_check;
14930 plane_funcs = &i965_plane_funcs;
14932 formats = i8xx_primary_formats;
14933 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14934 modifiers = i9xx_format_modifiers;
14936 plane->max_stride = i9xx_plane_max_stride;
14937 plane->update_plane = i9xx_update_plane;
14938 plane->disable_plane = i9xx_disable_plane;
14939 plane->get_hw_state = i9xx_plane_get_hw_state;
14940 plane->check_plane = i9xx_plane_check;
14942 plane_funcs = &i8xx_plane_funcs;
14945 possible_crtcs = BIT(pipe);
14947 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
14948 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14949 possible_crtcs, plane_funcs,
14950 formats, num_formats, modifiers,
14951 DRM_PLANE_TYPE_PRIMARY,
14952 "primary %c", pipe_name(pipe));
14954 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
14955 possible_crtcs, plane_funcs,
14956 formats, num_formats, modifiers,
14957 DRM_PLANE_TYPE_PRIMARY,
14959 plane_name(plane->i9xx_plane));
14963 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
14964 supported_rotations =
14965 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
14966 DRM_MODE_REFLECT_X;
14967 } else if (INTEL_GEN(dev_priv) >= 4) {
14968 supported_rotations =
14969 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
14971 supported_rotations = DRM_MODE_ROTATE_0;
14974 if (INTEL_GEN(dev_priv) >= 4)
14975 drm_plane_create_rotation_property(&plane->base,
14977 supported_rotations);
14980 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
14982 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
14987 intel_plane_free(plane);
14989 return ERR_PTR(ret);
14992 static struct intel_plane *
14993 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
14996 unsigned int possible_crtcs;
14997 struct intel_plane *cursor;
15000 cursor = intel_plane_alloc();
15001 if (IS_ERR(cursor))
15004 cursor->pipe = pipe;
15005 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
15006 cursor->id = PLANE_CURSOR;
15007 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
15009 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15010 cursor->max_stride = i845_cursor_max_stride;
15011 cursor->update_plane = i845_update_cursor;
15012 cursor->disable_plane = i845_disable_cursor;
15013 cursor->get_hw_state = i845_cursor_get_hw_state;
15014 cursor->check_plane = i845_check_cursor;
15016 cursor->max_stride = i9xx_cursor_max_stride;
15017 cursor->update_plane = i9xx_update_cursor;
15018 cursor->disable_plane = i9xx_disable_cursor;
15019 cursor->get_hw_state = i9xx_cursor_get_hw_state;
15020 cursor->check_plane = i9xx_check_cursor;
15023 cursor->cursor.base = ~0;
15024 cursor->cursor.cntl = ~0;
15026 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
15027 cursor->cursor.size = ~0;
15029 possible_crtcs = BIT(pipe);
15031 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
15032 possible_crtcs, &intel_cursor_plane_funcs,
15033 intel_cursor_formats,
15034 ARRAY_SIZE(intel_cursor_formats),
15035 cursor_format_modifiers,
15036 DRM_PLANE_TYPE_CURSOR,
15037 "cursor %c", pipe_name(pipe));
15041 if (INTEL_GEN(dev_priv) >= 4)
15042 drm_plane_create_rotation_property(&cursor->base,
15044 DRM_MODE_ROTATE_0 |
15045 DRM_MODE_ROTATE_180);
15047 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
15048 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
15050 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15055 intel_plane_free(cursor);
15057 return ERR_PTR(ret);
15060 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
15061 struct intel_crtc_state *crtc_state)
15063 struct intel_crtc_scaler_state *scaler_state =
15064 &crtc_state->scaler_state;
15065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15068 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
15069 if (!crtc->num_scalers)
15072 for (i = 0; i < crtc->num_scalers; i++) {
15073 struct intel_scaler *scaler = &scaler_state->scalers[i];
15075 scaler->in_use = 0;
15079 scaler_state->scaler_id = -1;
15082 #define INTEL_CRTC_FUNCS \
15083 .gamma_set = drm_atomic_helper_legacy_gamma_set, \
15084 .set_config = drm_atomic_helper_set_config, \
15085 .destroy = intel_crtc_destroy, \
15086 .page_flip = drm_atomic_helper_page_flip, \
15087 .atomic_duplicate_state = intel_crtc_duplicate_state, \
15088 .atomic_destroy_state = intel_crtc_destroy_state, \
15089 .set_crc_source = intel_crtc_set_crc_source, \
15090 .verify_crc_source = intel_crtc_verify_crc_source, \
15091 .get_crc_sources = intel_crtc_get_crc_sources
15093 static const struct drm_crtc_funcs bdw_crtc_funcs = {
15096 .get_vblank_counter = g4x_get_vblank_counter,
15097 .enable_vblank = bdw_enable_vblank,
15098 .disable_vblank = bdw_disable_vblank,
15101 static const struct drm_crtc_funcs ilk_crtc_funcs = {
15104 .get_vblank_counter = g4x_get_vblank_counter,
15105 .enable_vblank = ilk_enable_vblank,
15106 .disable_vblank = ilk_disable_vblank,
15109 static const struct drm_crtc_funcs g4x_crtc_funcs = {
15112 .get_vblank_counter = g4x_get_vblank_counter,
15113 .enable_vblank = i965_enable_vblank,
15114 .disable_vblank = i965_disable_vblank,
15117 static const struct drm_crtc_funcs i965_crtc_funcs = {
15120 .get_vblank_counter = i915_get_vblank_counter,
15121 .enable_vblank = i965_enable_vblank,
15122 .disable_vblank = i965_disable_vblank,
15125 static const struct drm_crtc_funcs i945gm_crtc_funcs = {
15128 .get_vblank_counter = i915_get_vblank_counter,
15129 .enable_vblank = i945gm_enable_vblank,
15130 .disable_vblank = i945gm_disable_vblank,
15133 static const struct drm_crtc_funcs i915_crtc_funcs = {
15136 .get_vblank_counter = i915_get_vblank_counter,
15137 .enable_vblank = i8xx_enable_vblank,
15138 .disable_vblank = i8xx_disable_vblank,
15141 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
15144 /* no hw vblank counter */
15145 .enable_vblank = i8xx_enable_vblank,
15146 .disable_vblank = i8xx_disable_vblank,
15149 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
15151 const struct drm_crtc_funcs *funcs;
15152 struct intel_crtc *intel_crtc;
15153 struct intel_crtc_state *crtc_state = NULL;
15154 struct intel_plane *primary = NULL;
15155 struct intel_plane *cursor = NULL;
15158 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15162 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15167 __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
15168 intel_crtc->config = crtc_state;
15170 primary = intel_primary_plane_create(dev_priv, pipe);
15171 if (IS_ERR(primary)) {
15172 ret = PTR_ERR(primary);
15175 intel_crtc->plane_ids_mask |= BIT(primary->id);
15177 for_each_sprite(dev_priv, pipe, sprite) {
15178 struct intel_plane *plane;
15180 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
15181 if (IS_ERR(plane)) {
15182 ret = PTR_ERR(plane);
15185 intel_crtc->plane_ids_mask |= BIT(plane->id);
15188 cursor = intel_cursor_plane_create(dev_priv, pipe);
15189 if (IS_ERR(cursor)) {
15190 ret = PTR_ERR(cursor);
15193 intel_crtc->plane_ids_mask |= BIT(cursor->id);
15195 if (HAS_GMCH(dev_priv)) {
15196 if (IS_CHERRYVIEW(dev_priv) ||
15197 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
15198 funcs = &g4x_crtc_funcs;
15199 else if (IS_GEN(dev_priv, 4))
15200 funcs = &i965_crtc_funcs;
15201 else if (IS_I945GM(dev_priv))
15202 funcs = &i945gm_crtc_funcs;
15203 else if (IS_GEN(dev_priv, 3))
15204 funcs = &i915_crtc_funcs;
15206 funcs = &i8xx_crtc_funcs;
15208 if (INTEL_GEN(dev_priv) >= 8)
15209 funcs = &bdw_crtc_funcs;
15211 funcs = &ilk_crtc_funcs;
15214 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
15215 &primary->base, &cursor->base,
15216 funcs, "pipe %c", pipe_name(pipe));
15220 intel_crtc->pipe = pipe;
15222 /* initialize shared scalers */
15223 intel_crtc_init_scalers(intel_crtc, crtc_state);
15225 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
15226 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
15227 dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;
15229 if (INTEL_GEN(dev_priv) < 9) {
15230 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
15232 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15233 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
15234 dev_priv->plane_to_crtc_mapping[i9xx_plane] = intel_crtc;
15237 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15239 intel_color_init(intel_crtc);
15241 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15247 * drm_mode_config_cleanup() will free up any
15248 * crtcs/planes already initialized.
15256 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
15257 struct drm_file *file)
15259 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15260 struct drm_crtc *drmmode_crtc;
15261 struct intel_crtc *crtc;
15263 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
15267 crtc = to_intel_crtc(drmmode_crtc);
15268 pipe_from_crtc_id->pipe = crtc->pipe;
15273 static int intel_encoder_clones(struct intel_encoder *encoder)
15275 struct drm_device *dev = encoder->base.dev;
15276 struct intel_encoder *source_encoder;
15277 int index_mask = 0;
15280 for_each_intel_encoder(dev, source_encoder) {
15281 if (encoders_cloneable(encoder, source_encoder))
15282 index_mask |= (1 << entry);
15290 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
15292 if (!IS_MOBILE(dev_priv))
15295 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15298 if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15304 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
15306 if (INTEL_GEN(dev_priv) >= 9)
15309 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
15312 if (HAS_PCH_LPT_H(dev_priv) &&
15313 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15316 /* DDI E can't be used if DDI A requires 4 lanes */
15317 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15320 if (!dev_priv->vbt.int_crt_support)
15326 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15331 if (HAS_DDI(dev_priv))
15334 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15335 * everywhere where registers can be write protected.
15337 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15342 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15343 u32 val = I915_READ(PP_CONTROL(pps_idx));
15345 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15346 I915_WRITE(PP_CONTROL(pps_idx), val);
15350 static void intel_pps_init(struct drm_i915_private *dev_priv)
15352 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
15353 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15354 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15355 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15357 dev_priv->pps_mmio_base = PPS_BASE;
15359 intel_pps_unlock_regs_wa(dev_priv);
15362 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
15364 struct intel_encoder *encoder;
15365 bool dpd_is_edp = false;
15367 intel_pps_init(dev_priv);
15369 if (!HAS_DISPLAY(dev_priv))
15372 if (INTEL_GEN(dev_priv) >= 12) {
15373 /* TODO: initialize TC ports as well */
15374 intel_ddi_init(dev_priv, PORT_A);
15375 intel_ddi_init(dev_priv, PORT_B);
15376 icl_dsi_init(dev_priv);
15377 } else if (IS_ELKHARTLAKE(dev_priv)) {
15378 intel_ddi_init(dev_priv, PORT_A);
15379 intel_ddi_init(dev_priv, PORT_B);
15380 intel_ddi_init(dev_priv, PORT_C);
15381 intel_ddi_init(dev_priv, PORT_D);
15382 icl_dsi_init(dev_priv);
15383 } else if (IS_GEN(dev_priv, 11)) {
15384 intel_ddi_init(dev_priv, PORT_A);
15385 intel_ddi_init(dev_priv, PORT_B);
15386 intel_ddi_init(dev_priv, PORT_C);
15387 intel_ddi_init(dev_priv, PORT_D);
15388 intel_ddi_init(dev_priv, PORT_E);
15390 * On some ICL SKUs port F is not present. No strap bits for
15391 * this, so rely on VBT.
15392 * Work around broken VBTs on SKUs known to have no port F.
15394 if (IS_ICL_WITH_PORT_F(dev_priv) &&
15395 intel_bios_is_port_present(dev_priv, PORT_F))
15396 intel_ddi_init(dev_priv, PORT_F);
15398 icl_dsi_init(dev_priv);
15399 } else if (IS_GEN9_LP(dev_priv)) {
15401 * FIXME: Broxton doesn't support port detection via the
15402 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15403 * detect the ports.
15405 intel_ddi_init(dev_priv, PORT_A);
15406 intel_ddi_init(dev_priv, PORT_B);
15407 intel_ddi_init(dev_priv, PORT_C);
15409 vlv_dsi_init(dev_priv);
15410 } else if (HAS_DDI(dev_priv)) {
15413 if (intel_ddi_crt_present(dev_priv))
15414 intel_crt_init(dev_priv);
15417 * Haswell uses DDI functions to detect digital outputs.
15418 * On SKL pre-D0 the strap isn't connected, so we assume
15421 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15422 /* WaIgnoreDDIAStrap: skl */
15423 if (found || IS_GEN9_BC(dev_priv))
15424 intel_ddi_init(dev_priv, PORT_A);
15426 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
15428 found = I915_READ(SFUSE_STRAP);
15430 if (found & SFUSE_STRAP_DDIB_DETECTED)
15431 intel_ddi_init(dev_priv, PORT_B);
15432 if (found & SFUSE_STRAP_DDIC_DETECTED)
15433 intel_ddi_init(dev_priv, PORT_C);
15434 if (found & SFUSE_STRAP_DDID_DETECTED)
15435 intel_ddi_init(dev_priv, PORT_D);
15436 if (found & SFUSE_STRAP_DDIF_DETECTED)
15437 intel_ddi_init(dev_priv, PORT_F);
15439 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15441 if (IS_GEN9_BC(dev_priv) &&
15442 intel_bios_is_port_present(dev_priv, PORT_E))
15443 intel_ddi_init(dev_priv, PORT_E);
15445 } else if (HAS_PCH_SPLIT(dev_priv)) {
15449 * intel_edp_init_connector() depends on this completing first,
15450 * to prevent the registration of both eDP and LVDS and the
15451 * incorrect sharing of the PPS.
15453 intel_lvds_init(dev_priv);
15454 intel_crt_init(dev_priv);
15456 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
15458 if (ilk_has_edp_a(dev_priv))
15459 intel_dp_init(dev_priv, DP_A, PORT_A);
15461 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15462 /* PCH SDVOB multiplex with HDMIB */
15463 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
15465 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
15466 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15467 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
15470 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15471 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
15473 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15474 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
15476 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15477 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
15479 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15480 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
15481 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15482 bool has_edp, has_port;
15484 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
15485 intel_crt_init(dev_priv);
15488 * The DP_DETECTED bit is the latched state of the DDC
15489 * SDA pin at boot. However since eDP doesn't require DDC
15490 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15491 * eDP ports may have been muxed to an alternate function.
15492 * Thus we can't rely on the DP_DETECTED bit alone to detect
15493 * eDP ports. Consult the VBT as well as DP_DETECTED to
15494 * detect eDP ports.
15496 * Sadly the straps seem to be missing sometimes even for HDMI
15497 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15498 * and VBT for the presence of the port. Additionally we can't
15499 * trust the port type the VBT declares as we've seen at least
15500 * HDMI ports that the VBT claim are DP or eDP.
15502 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
15503 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15504 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15505 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
15506 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15507 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
15509 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
15510 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15511 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15512 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
15513 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15514 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
15516 if (IS_CHERRYVIEW(dev_priv)) {
15518 * eDP not supported on port D,
15519 * so no need to worry about it
15521 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15522 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15523 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
15524 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15525 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
15528 vlv_dsi_init(dev_priv);
15529 } else if (IS_PINEVIEW(dev_priv)) {
15530 intel_lvds_init(dev_priv);
15531 intel_crt_init(dev_priv);
15532 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
15533 bool found = false;
15535 if (IS_MOBILE(dev_priv))
15536 intel_lvds_init(dev_priv);
15538 intel_crt_init(dev_priv);
15540 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15541 DRM_DEBUG_KMS("probing SDVOB\n");
15542 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
15543 if (!found && IS_G4X(dev_priv)) {
15544 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15545 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
15548 if (!found && IS_G4X(dev_priv))
15549 intel_dp_init(dev_priv, DP_B, PORT_B);
15552 /* Before G4X SDVOC doesn't have its own detect register */
15554 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15555 DRM_DEBUG_KMS("probing SDVOC\n");
15556 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
15559 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15561 if (IS_G4X(dev_priv)) {
15562 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15563 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
15565 if (IS_G4X(dev_priv))
15566 intel_dp_init(dev_priv, DP_C, PORT_C);
15569 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
15570 intel_dp_init(dev_priv, DP_D, PORT_D);
15572 if (SUPPORTS_TV(dev_priv))
15573 intel_tv_init(dev_priv);
15574 } else if (IS_GEN(dev_priv, 2)) {
15575 if (IS_I85X(dev_priv))
15576 intel_lvds_init(dev_priv);
15578 intel_crt_init(dev_priv);
15579 intel_dvo_init(dev_priv);
15582 intel_psr_init(dev_priv);
15584 for_each_intel_encoder(&dev_priv->drm, encoder) {
15585 encoder->base.possible_crtcs = encoder->crtc_mask;
15586 encoder->base.possible_clones =
15587 intel_encoder_clones(encoder);
15590 intel_init_pch_refclk(dev_priv);
15592 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
15595 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15597 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15599 drm_framebuffer_cleanup(fb);
15600 intel_frontbuffer_put(intel_fb->frontbuffer);
15605 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15606 struct drm_file *file,
15607 unsigned int *handle)
15609 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15611 if (obj->userptr.mm) {
15612 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15616 return drm_gem_handle_create(file, &obj->base, handle);
15619 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15620 struct drm_file *file,
15621 unsigned flags, unsigned color,
15622 struct drm_clip_rect *clips,
15623 unsigned num_clips)
15625 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15627 i915_gem_object_flush_if_display(obj);
15628 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
15633 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15634 .destroy = intel_user_framebuffer_destroy,
15635 .create_handle = intel_user_framebuffer_create_handle,
15636 .dirty = intel_user_framebuffer_dirty,
15639 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
15640 struct drm_i915_gem_object *obj,
15641 struct drm_mode_fb_cmd2 *mode_cmd)
15643 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
15644 struct drm_framebuffer *fb = &intel_fb->base;
15646 unsigned int tiling, stride;
15650 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
15651 if (!intel_fb->frontbuffer)
15654 i915_gem_object_lock(obj);
15655 tiling = i915_gem_object_get_tiling(obj);
15656 stride = i915_gem_object_get_stride(obj);
15657 i915_gem_object_unlock(obj);
15659 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15661 * If there's a fence, enforce that
15662 * the fb modifier and tiling mode match.
15664 if (tiling != I915_TILING_NONE &&
15665 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15666 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
15670 if (tiling == I915_TILING_X) {
15671 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15672 } else if (tiling == I915_TILING_Y) {
15673 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
15678 if (!drm_any_plane_has_format(&dev_priv->drm,
15679 mode_cmd->pixel_format,
15680 mode_cmd->modifier[0])) {
15681 struct drm_format_name_buf format_name;
15683 DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n",
15684 drm_get_format_name(mode_cmd->pixel_format,
15686 mode_cmd->modifier[0]);
15691 * gen2/3 display engine uses the fence if present,
15692 * so the tiling mode must match the fb modifier exactly.
15694 if (INTEL_GEN(dev_priv) < 4 &&
15695 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15696 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
15700 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
15701 mode_cmd->modifier[0]);
15702 if (mode_cmd->pitches[0] > max_stride) {
15703 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
15704 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
15705 "tiled" : "linear",
15706 mode_cmd->pitches[0], max_stride);
15711 * If there's a fence, enforce that
15712 * the fb pitch and fence stride match.
15714 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
15715 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
15716 mode_cmd->pitches[0], stride);
15720 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15721 if (mode_cmd->offsets[0] != 0)
15724 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
15726 for (i = 0; i < fb->format->num_planes; i++) {
15727 u32 stride_alignment;
15729 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
15730 DRM_DEBUG_KMS("bad plane %d handle\n", i);
15734 stride_alignment = intel_fb_stride_alignment(fb, i);
15737 * Display WA #0531: skl,bxt,kbl,glk
15739 * Render decompression and plane width > 3840
15740 * combined with horizontal panning requires the
15741 * plane stride to be a multiple of 4. We'll just
15742 * require the entire fb to accommodate that to avoid
15743 * potential runtime errors at plane configuration time.
15745 if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
15746 is_ccs_modifier(fb->modifier))
15747 stride_alignment *= 4;
15749 if (fb->pitches[i] & (stride_alignment - 1)) {
15750 DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
15751 i, fb->pitches[i], stride_alignment);
15755 fb->obj[i] = &obj->base;
15758 ret = intel_fill_fb_info(dev_priv, fb);
15762 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
15764 DRM_ERROR("framebuffer init failed %d\n", ret);
15771 intel_frontbuffer_put(intel_fb->frontbuffer);
15775 static struct drm_framebuffer *
15776 intel_user_framebuffer_create(struct drm_device *dev,
15777 struct drm_file *filp,
15778 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15780 struct drm_framebuffer *fb;
15781 struct drm_i915_gem_object *obj;
15782 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15784 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15786 return ERR_PTR(-ENOENT);
15788 fb = intel_framebuffer_create(obj, &mode_cmd);
15789 i915_gem_object_put(obj);
15794 static void intel_atomic_state_free(struct drm_atomic_state *state)
15796 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
15798 drm_atomic_state_default_release(state);
15800 i915_sw_fence_fini(&intel_state->commit_ready);
15805 static enum drm_mode_status
15806 intel_mode_valid(struct drm_device *dev,
15807 const struct drm_display_mode *mode)
15809 struct drm_i915_private *dev_priv = to_i915(dev);
15810 int hdisplay_max, htotal_max;
15811 int vdisplay_max, vtotal_max;
15814 * Can't reject DBLSCAN here because Xorg ddxen can add piles
15815 * of DBLSCAN modes to the output's mode list when they detect
15816 * the scaling mode property on the connector. And they don't
15817 * ask the kernel to validate those modes in any way until
15818 * modeset time at which point the client gets a protocol error.
15819 * So in order to not upset those clients we silently ignore the
15820 * DBLSCAN flag on such connectors. For other connectors we will
15821 * reject modes with the DBLSCAN flag in encoder->compute_config().
15822 * And we always reject DBLSCAN modes in connector->mode_valid()
15823 * as we never want such modes on the connector's mode list.
15826 if (mode->vscan > 1)
15827 return MODE_NO_VSCAN;
15829 if (mode->flags & DRM_MODE_FLAG_HSKEW)
15830 return MODE_H_ILLEGAL;
15832 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
15833 DRM_MODE_FLAG_NCSYNC |
15834 DRM_MODE_FLAG_PCSYNC))
15837 if (mode->flags & (DRM_MODE_FLAG_BCAST |
15838 DRM_MODE_FLAG_PIXMUX |
15839 DRM_MODE_FLAG_CLKDIV2))
15842 if (INTEL_GEN(dev_priv) >= 9 ||
15843 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
15844 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
15845 vdisplay_max = 4096;
15848 } else if (INTEL_GEN(dev_priv) >= 3) {
15849 hdisplay_max = 4096;
15850 vdisplay_max = 4096;
15854 hdisplay_max = 2048;
15855 vdisplay_max = 2048;
15860 if (mode->hdisplay > hdisplay_max ||
15861 mode->hsync_start > htotal_max ||
15862 mode->hsync_end > htotal_max ||
15863 mode->htotal > htotal_max)
15864 return MODE_H_ILLEGAL;
15866 if (mode->vdisplay > vdisplay_max ||
15867 mode->vsync_start > vtotal_max ||
15868 mode->vsync_end > vtotal_max ||
15869 mode->vtotal > vtotal_max)
15870 return MODE_V_ILLEGAL;
15875 static const struct drm_mode_config_funcs intel_mode_funcs = {
15876 .fb_create = intel_user_framebuffer_create,
15877 .get_format_info = intel_get_format_info,
15878 .output_poll_changed = intel_fbdev_output_poll_changed,
15879 .mode_valid = intel_mode_valid,
15880 .atomic_check = intel_atomic_check,
15881 .atomic_commit = intel_atomic_commit,
15882 .atomic_state_alloc = intel_atomic_state_alloc,
15883 .atomic_state_clear = intel_atomic_state_clear,
15884 .atomic_state_free = intel_atomic_state_free,
15888 * intel_init_display_hooks - initialize the display modesetting hooks
15889 * @dev_priv: device private
15891 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15893 intel_init_cdclk_hooks(dev_priv);
15895 if (INTEL_GEN(dev_priv) >= 9) {
15896 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15897 dev_priv->display.get_initial_plane_config =
15898 skylake_get_initial_plane_config;
15899 dev_priv->display.crtc_compute_clock =
15900 haswell_crtc_compute_clock;
15901 dev_priv->display.crtc_enable = haswell_crtc_enable;
15902 dev_priv->display.crtc_disable = haswell_crtc_disable;
15903 } else if (HAS_DDI(dev_priv)) {
15904 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15905 dev_priv->display.get_initial_plane_config =
15906 i9xx_get_initial_plane_config;
15907 dev_priv->display.crtc_compute_clock =
15908 haswell_crtc_compute_clock;
15909 dev_priv->display.crtc_enable = haswell_crtc_enable;
15910 dev_priv->display.crtc_disable = haswell_crtc_disable;
15911 } else if (HAS_PCH_SPLIT(dev_priv)) {
15912 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15913 dev_priv->display.get_initial_plane_config =
15914 i9xx_get_initial_plane_config;
15915 dev_priv->display.crtc_compute_clock =
15916 ironlake_crtc_compute_clock;
15917 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15918 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15919 } else if (IS_CHERRYVIEW(dev_priv)) {
15920 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15921 dev_priv->display.get_initial_plane_config =
15922 i9xx_get_initial_plane_config;
15923 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15924 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15925 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15926 } else if (IS_VALLEYVIEW(dev_priv)) {
15927 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15928 dev_priv->display.get_initial_plane_config =
15929 i9xx_get_initial_plane_config;
15930 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15931 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15932 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15933 } else if (IS_G4X(dev_priv)) {
15934 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15935 dev_priv->display.get_initial_plane_config =
15936 i9xx_get_initial_plane_config;
15937 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15938 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15939 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15940 } else if (IS_PINEVIEW(dev_priv)) {
15941 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15942 dev_priv->display.get_initial_plane_config =
15943 i9xx_get_initial_plane_config;
15944 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15945 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15946 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15947 } else if (!IS_GEN(dev_priv, 2)) {
15948 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15949 dev_priv->display.get_initial_plane_config =
15950 i9xx_get_initial_plane_config;
15951 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15952 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15953 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15955 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15956 dev_priv->display.get_initial_plane_config =
15957 i9xx_get_initial_plane_config;
15958 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15959 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15960 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15963 if (IS_GEN(dev_priv, 5)) {
15964 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15965 } else if (IS_GEN(dev_priv, 6)) {
15966 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15967 } else if (IS_IVYBRIDGE(dev_priv)) {
15968 /* FIXME: detect B0+ stepping and use auto training */
15969 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15970 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15971 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15974 if (INTEL_GEN(dev_priv) >= 9)
15975 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
15977 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
15981 static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
15983 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15984 return VLV_VGACNTRL;
15985 else if (INTEL_GEN(dev_priv) >= 5)
15986 return CPU_VGACNTRL;
15991 /* Disable the VGA plane that we never use */
15992 static void i915_disable_vga(struct drm_i915_private *dev_priv)
15994 struct pci_dev *pdev = dev_priv->drm.pdev;
15996 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15998 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15999 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16000 outb(SR01, VGA_SR_INDEX);
16001 sr1 = inb(VGA_SR_DATA);
16002 outb(sr1 | 1<<5, VGA_SR_DATA);
16003 vga_put(pdev, VGA_RSRC_LEGACY_IO);
16006 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16007 POSTING_READ(vga_reg);
16010 void intel_modeset_init_hw(struct drm_device *dev)
16012 struct drm_i915_private *dev_priv = to_i915(dev);
16014 intel_update_cdclk(dev_priv);
16015 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
16016 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
16020 * Calculate what we think the watermarks should be for the state we've read
16021 * out of the hardware and then immediately program those watermarks so that
16022 * we ensure the hardware settings match our internal state.
16024 * We can calculate what we think WM's should be by creating a duplicate of the
16025 * current state (which was constructed during hardware readout) and running it
16026 * through the atomic check code to calculate new watermark values in the
16029 static void sanitize_watermarks(struct drm_device *dev)
16031 struct drm_i915_private *dev_priv = to_i915(dev);
16032 struct drm_atomic_state *state;
16033 struct intel_atomic_state *intel_state;
16034 struct intel_crtc *crtc;
16035 struct intel_crtc_state *crtc_state;
16036 struct drm_modeset_acquire_ctx ctx;
16040 /* Only supported on platforms that use atomic watermark design */
16041 if (!dev_priv->display.optimize_watermarks)
16045 * We need to hold connection_mutex before calling duplicate_state so
16046 * that the connector loop is protected.
16048 drm_modeset_acquire_init(&ctx, 0);
16050 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16051 if (ret == -EDEADLK) {
16052 drm_modeset_backoff(&ctx);
16054 } else if (WARN_ON(ret)) {
16058 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16059 if (WARN_ON(IS_ERR(state)))
16062 intel_state = to_intel_atomic_state(state);
16065 * Hardware readout is the only time we don't want to calculate
16066 * intermediate watermarks (since we don't trust the current
16069 if (!HAS_GMCH(dev_priv))
16070 intel_state->skip_intermediate_wm = true;
16072 ret = intel_atomic_check(dev, state);
16075 * If we fail here, it means that the hardware appears to be
16076 * programmed in a way that shouldn't be possible, given our
16077 * understanding of watermark requirements. This might mean a
16078 * mistake in the hardware readout code or a mistake in the
16079 * watermark calculations for a given platform. Raise a WARN
16080 * so that this is noticeable.
16082 * If this actually happens, we'll have to just leave the
16083 * BIOS-programmed watermarks untouched and hope for the best.
16085 WARN(true, "Could not determine valid watermarks for inherited state\n");
16089 /* Write calculated watermark values back */
16090 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
16091 crtc_state->wm.need_postvbl_update = true;
16092 dev_priv->display.optimize_watermarks(intel_state, crtc_state);
16094 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
16098 drm_atomic_state_put(state);
16100 drm_modeset_drop_locks(&ctx);
16101 drm_modeset_acquire_fini(&ctx);
16104 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
16106 if (IS_GEN(dev_priv, 5)) {
16108 I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
16110 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
16111 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
16112 dev_priv->fdi_pll_freq = 270000;
16117 DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
16120 static int intel_initial_commit(struct drm_device *dev)
16122 struct drm_atomic_state *state = NULL;
16123 struct drm_modeset_acquire_ctx ctx;
16124 struct drm_crtc *crtc;
16125 struct drm_crtc_state *crtc_state;
16128 state = drm_atomic_state_alloc(dev);
16132 drm_modeset_acquire_init(&ctx, 0);
16135 state->acquire_ctx = &ctx;
16137 drm_for_each_crtc(crtc, dev) {
16138 crtc_state = drm_atomic_get_crtc_state(state, crtc);
16139 if (IS_ERR(crtc_state)) {
16140 ret = PTR_ERR(crtc_state);
16144 if (crtc_state->active) {
16145 ret = drm_atomic_add_affected_planes(state, crtc);
16150 * FIXME hack to force a LUT update to avoid the
16151 * plane update forcing the pipe gamma on without
16152 * having a proper LUT loaded. Remove once we
16153 * have readout for pipe gamma enable.
16155 crtc_state->color_mgmt_changed = true;
16159 ret = drm_atomic_commit(state);
16162 if (ret == -EDEADLK) {
16163 drm_atomic_state_clear(state);
16164 drm_modeset_backoff(&ctx);
16168 drm_atomic_state_put(state);
16170 drm_modeset_drop_locks(&ctx);
16171 drm_modeset_acquire_fini(&ctx);
16176 int intel_modeset_init(struct drm_device *dev)
16178 struct drm_i915_private *dev_priv = to_i915(dev);
16180 struct intel_crtc *crtc;
16183 dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
16184 dev_priv->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
16185 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
16187 drm_mode_config_init(dev);
16189 ret = intel_bw_init(dev_priv);
16193 dev->mode_config.min_width = 0;
16194 dev->mode_config.min_height = 0;
16196 dev->mode_config.preferred_depth = 24;
16197 dev->mode_config.prefer_shadow = 1;
16199 dev->mode_config.allow_fb_modifiers = true;
16201 dev->mode_config.funcs = &intel_mode_funcs;
16203 init_llist_head(&dev_priv->atomic_helper.free_list);
16204 INIT_WORK(&dev_priv->atomic_helper.free_work,
16205 intel_atomic_helper_free_state_worker);
16207 intel_init_quirks(dev_priv);
16209 intel_fbc_init(dev_priv);
16211 intel_init_pm(dev_priv);
16214 * There may be no VBT; and if the BIOS enabled SSC we can
16215 * just keep using it to avoid unnecessary flicker. Whereas if the
16216 * BIOS isn't using it, don't assume it will work even if the VBT
16217 * indicates as much.
16219 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
16220 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16223 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16224 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16225 bios_lvds_use_ssc ? "en" : "dis",
16226 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16227 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16232 * Maximum framebuffer dimensions, chosen to match
16233 * the maximum render engine surface size on gen4+.
16235 if (INTEL_GEN(dev_priv) >= 7) {
16236 dev->mode_config.max_width = 16384;
16237 dev->mode_config.max_height = 16384;
16238 } else if (INTEL_GEN(dev_priv) >= 4) {
16239 dev->mode_config.max_width = 8192;
16240 dev->mode_config.max_height = 8192;
16241 } else if (IS_GEN(dev_priv, 3)) {
16242 dev->mode_config.max_width = 4096;
16243 dev->mode_config.max_height = 4096;
16245 dev->mode_config.max_width = 2048;
16246 dev->mode_config.max_height = 2048;
16249 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16250 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
16251 dev->mode_config.cursor_height = 1023;
16252 } else if (IS_GEN(dev_priv, 2)) {
16253 dev->mode_config.cursor_width = 64;
16254 dev->mode_config.cursor_height = 64;
16256 dev->mode_config.cursor_width = 256;
16257 dev->mode_config.cursor_height = 256;
16260 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16261 INTEL_INFO(dev_priv)->num_pipes,
16262 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
16264 for_each_pipe(dev_priv, pipe) {
16265 ret = intel_crtc_init(dev_priv, pipe);
16267 drm_mode_config_cleanup(dev);
16272 intel_shared_dpll_init(dev);
16273 intel_update_fdi_pll_freq(dev_priv);
16275 intel_update_czclk(dev_priv);
16276 intel_modeset_init_hw(dev);
16278 intel_hdcp_component_init(dev_priv);
16280 if (dev_priv->max_cdclk_freq == 0)
16281 intel_update_max_cdclk(dev_priv);
16283 /* Just disable it once at startup */
16284 i915_disable_vga(dev_priv);
16285 intel_setup_outputs(dev_priv);
16287 drm_modeset_lock_all(dev);
16288 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
16289 drm_modeset_unlock_all(dev);
16291 for_each_intel_crtc(dev, crtc) {
16292 struct intel_initial_plane_config plane_config = {};
16298 * Note that reserving the BIOS fb up front prevents us
16299 * from stuffing other stolen allocations like the ring
16300 * on top. This prevents some ugliness at boot time, and
16301 * can even allow for smooth boot transitions if the BIOS
16302 * fb is large enough for the active pipe configuration.
16304 dev_priv->display.get_initial_plane_config(crtc,
16308 * If the fb is shared between multiple heads, we'll
16309 * just get the first one.
16311 intel_find_initial_plane_obj(crtc, &plane_config);
16315 * Make sure hardware watermarks really match the state we read out.
16316 * Note that we need to do this after reconstructing the BIOS fb's
16317 * since the watermark calculation done here will use pstate->fb.
16319 if (!HAS_GMCH(dev_priv))
16320 sanitize_watermarks(dev);
16323 * Force all active planes to recompute their states. So that on
16324 * mode_setcrtc after probe, all the intel_plane_state variables
16325 * are already calculated and there is no assert_plane warnings
16328 ret = intel_initial_commit(dev);
16330 DRM_DEBUG_KMS("Initial commit in probe failed.\n");
16335 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
16337 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16338 /* 640x480@60Hz, ~25175 kHz */
16339 struct dpll clock = {
16349 WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
16351 DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
16352 pipe_name(pipe), clock.vco, clock.dot);
16354 fp = i9xx_dpll_compute_fp(&clock);
16355 dpll = DPLL_DVO_2X_MODE |
16356 DPLL_VGA_MODE_DIS |
16357 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
16358 PLL_P2_DIVIDE_BY_4 |
16359 PLL_REF_INPUT_DREFCLK |
16362 I915_WRITE(FP0(pipe), fp);
16363 I915_WRITE(FP1(pipe), fp);
16365 I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
16366 I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
16367 I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
16368 I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
16369 I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
16370 I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
16371 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
16374 * Apparently we need to have VGA mode enabled prior to changing
16375 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
16376 * dividers, even though the register value does change.
16378 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
16379 I915_WRITE(DPLL(pipe), dpll);
16381 /* Wait for the clocks to stabilize. */
16382 POSTING_READ(DPLL(pipe));
16385 /* The pixel multiplier can only be updated once the
16386 * DPLL is enabled and the clocks are stable.
16388 * So write it again.
16390 I915_WRITE(DPLL(pipe), dpll);
16392 /* We do this three times for luck */
16393 for (i = 0; i < 3 ; i++) {
16394 I915_WRITE(DPLL(pipe), dpll);
16395 POSTING_READ(DPLL(pipe));
16396 udelay(150); /* wait for warmup */
16399 I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
16400 POSTING_READ(PIPECONF(pipe));
16402 intel_wait_for_pipe_scanline_moving(crtc);
16405 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
16407 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16409 DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
16412 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
16413 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
16414 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
16415 WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE);
16416 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE);
16418 I915_WRITE(PIPECONF(pipe), 0);
16419 POSTING_READ(PIPECONF(pipe));
16421 intel_wait_for_pipe_scanline_stopped(crtc);
16423 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
16424 POSTING_READ(DPLL(pipe));
16428 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
16430 struct intel_crtc *crtc;
16432 if (INTEL_GEN(dev_priv) >= 4)
16435 for_each_intel_crtc(&dev_priv->drm, crtc) {
16436 struct intel_plane *plane =
16437 to_intel_plane(crtc->base.primary);
16438 struct intel_crtc *plane_crtc;
16441 if (!plane->get_hw_state(plane, &pipe))
16444 if (pipe == crtc->pipe)
16447 DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
16448 plane->base.base.id, plane->base.name);
16450 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16451 intel_plane_disable_noatomic(plane_crtc, plane);
16455 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16457 struct drm_device *dev = crtc->base.dev;
16458 struct intel_encoder *encoder;
16460 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16466 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16468 struct drm_device *dev = encoder->base.dev;
16469 struct intel_connector *connector;
16471 for_each_connector_on_encoder(dev, &encoder->base, connector)
16477 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16478 enum pipe pch_transcoder)
16480 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16481 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
16484 static void intel_sanitize_crtc(struct intel_crtc *crtc,
16485 struct drm_modeset_acquire_ctx *ctx)
16487 struct drm_device *dev = crtc->base.dev;
16488 struct drm_i915_private *dev_priv = to_i915(dev);
16489 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
16490 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
16492 /* Clear any frame start delays used for debugging left by the BIOS */
16493 if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
16494 i915_reg_t reg = PIPECONF(cpu_transcoder);
16497 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16500 if (crtc_state->base.active) {
16501 struct intel_plane *plane;
16503 /* Disable everything but the primary plane */
16504 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16505 const struct intel_plane_state *plane_state =
16506 to_intel_plane_state(plane->base.state);
16508 if (plane_state->base.visible &&
16509 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
16510 intel_plane_disable_noatomic(crtc, plane);
16514 * Disable any background color set by the BIOS, but enable the
16515 * gamma and CSC to match how we program our planes.
16517 if (INTEL_GEN(dev_priv) >= 9)
16518 I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
16519 SKL_BOTTOM_COLOR_GAMMA_ENABLE |
16520 SKL_BOTTOM_COLOR_CSC_ENABLE);
16523 /* Adjust the state of the output pipe according to whether we
16524 * have active connectors/encoders. */
16525 if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
16526 intel_crtc_disable_noatomic(&crtc->base, ctx);
16528 if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
16530 * We start out with underrun reporting disabled to avoid races.
16531 * For correct bookkeeping mark this on active crtcs.
16533 * Also on gmch platforms we dont have any hardware bits to
16534 * disable the underrun reporting. Which means we need to start
16535 * out with underrun reporting disabled also on inactive pipes,
16536 * since otherwise we'll complain about the garbage we read when
16537 * e.g. coming up after runtime pm.
16539 * No protection against concurrent access is required - at
16540 * worst a fifo underrun happens which also sets this to false.
16542 crtc->cpu_fifo_underrun_disabled = true;
16544 * We track the PCH trancoder underrun reporting state
16545 * within the crtc. With crtc for pipe A housing the underrun
16546 * reporting state for PCH transcoder A, crtc for pipe B housing
16547 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16548 * and marking underrun reporting as disabled for the non-existing
16549 * PCH transcoders B and C would prevent enabling the south
16550 * error interrupt (see cpt_can_enable_serr_int()).
16552 if (has_pch_trancoder(dev_priv, crtc->pipe))
16553 crtc->pch_fifo_underrun_disabled = true;
16557 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
16559 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
16562 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
16563 * the hardware when a high res displays plugged in. DPLL P
16564 * divider is zero, and the pipe timings are bonkers. We'll
16565 * try to disable everything in that case.
16567 * FIXME would be nice to be able to sanitize this state
16568 * without several WARNs, but for now let's take the easy
16571 return IS_GEN(dev_priv, 6) &&
16572 crtc_state->base.active &&
16573 crtc_state->shared_dpll &&
16574 crtc_state->port_clock == 0;
16577 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16579 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
16580 struct intel_connector *connector;
16581 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
16582 struct intel_crtc_state *crtc_state = crtc ?
16583 to_intel_crtc_state(crtc->base.state) : NULL;
16585 /* We need to check both for a crtc link (meaning that the
16586 * encoder is active and trying to read from a pipe) and the
16587 * pipe itself being active. */
16588 bool has_active_crtc = crtc_state &&
16589 crtc_state->base.active;
16591 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
16592 DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
16593 pipe_name(crtc->pipe));
16594 has_active_crtc = false;
16597 connector = intel_encoder_find_connector(encoder);
16598 if (connector && !has_active_crtc) {
16599 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16600 encoder->base.base.id,
16601 encoder->base.name);
16603 /* Connector is active, but has no active pipe. This is
16604 * fallout from our resume register restoring. Disable
16605 * the encoder manually again. */
16607 struct drm_encoder *best_encoder;
16609 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16610 encoder->base.base.id,
16611 encoder->base.name);
16613 /* avoid oopsing in case the hooks consult best_encoder */
16614 best_encoder = connector->base.state->best_encoder;
16615 connector->base.state->best_encoder = &encoder->base;
16617 if (encoder->disable)
16618 encoder->disable(encoder, crtc_state,
16619 connector->base.state);
16620 if (encoder->post_disable)
16621 encoder->post_disable(encoder, crtc_state,
16622 connector->base.state);
16624 connector->base.state->best_encoder = best_encoder;
16626 encoder->base.crtc = NULL;
16628 /* Inconsistent output/port/pipe state happens presumably due to
16629 * a bug in one of the get_hw_state functions. Or someplace else
16630 * in our code, like the register restore mess on resume. Clamp
16631 * things to off as a safer default. */
16633 connector->base.dpms = DRM_MODE_DPMS_OFF;
16634 connector->base.encoder = NULL;
16637 /* notify opregion of the sanitized encoder state */
16638 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
16640 if (INTEL_GEN(dev_priv) >= 11)
16641 icl_sanitize_encoder_pll_mapping(encoder);
16644 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
16646 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
16648 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16649 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16650 i915_disable_vga(dev_priv);
16654 void i915_redisable_vga(struct drm_i915_private *dev_priv)
16656 intel_wakeref_t wakeref;
16659 * This function can be called both from intel_modeset_setup_hw_state or
16660 * at a very early point in our resume sequence, where the power well
16661 * structures are not yet restored. Since this function is at a very
16662 * paranoid "someone might have enabled VGA while we were not looking"
16663 * level, just check if the power well is enabled instead of trying to
16664 * follow the "don't touch the power well if we don't need it" policy
16665 * the rest of the driver uses.
16667 wakeref = intel_display_power_get_if_enabled(dev_priv,
16672 i915_redisable_vga_power_on(dev_priv);
16674 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA, wakeref);
16677 /* FIXME read out full plane state for all planes */
16678 static void readout_plane_state(struct drm_i915_private *dev_priv)
16680 struct intel_plane *plane;
16681 struct intel_crtc *crtc;
16683 for_each_intel_plane(&dev_priv->drm, plane) {
16684 struct intel_plane_state *plane_state =
16685 to_intel_plane_state(plane->base.state);
16686 struct intel_crtc_state *crtc_state;
16687 enum pipe pipe = PIPE_A;
16690 visible = plane->get_hw_state(plane, &pipe);
16692 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16693 crtc_state = to_intel_crtc_state(crtc->base.state);
16695 intel_set_plane_visible(crtc_state, plane_state, visible);
16697 DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
16698 plane->base.base.id, plane->base.name,
16699 enableddisabled(visible), pipe_name(pipe));
16702 for_each_intel_crtc(&dev_priv->drm, crtc) {
16703 struct intel_crtc_state *crtc_state =
16704 to_intel_crtc_state(crtc->base.state);
16706 fixup_active_planes(crtc_state);
16710 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16712 struct drm_i915_private *dev_priv = to_i915(dev);
16714 struct intel_crtc *crtc;
16715 struct intel_encoder *encoder;
16716 struct intel_connector *connector;
16717 struct drm_connector_list_iter conn_iter;
16720 dev_priv->active_pipes = 0;
16722 for_each_intel_crtc(dev, crtc) {
16723 struct intel_crtc_state *crtc_state =
16724 to_intel_crtc_state(crtc->base.state);
16726 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16727 memset(crtc_state, 0, sizeof(*crtc_state));
16728 __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
16730 crtc_state->base.active = crtc_state->base.enable =
16731 dev_priv->display.get_pipe_config(crtc, crtc_state);
16733 crtc->base.enabled = crtc_state->base.enable;
16734 crtc->active = crtc_state->base.active;
16736 if (crtc_state->base.active)
16737 dev_priv->active_pipes |= BIT(crtc->pipe);
16739 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16740 crtc->base.base.id, crtc->base.name,
16741 enableddisabled(crtc_state->base.active));
16744 readout_plane_state(dev_priv);
16746 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16747 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16749 pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
16750 &pll->state.hw_state);
16752 if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
16753 pll->info->id == DPLL_ID_EHL_DPLL4) {
16754 pll->wakeref = intel_display_power_get(dev_priv,
16755 POWER_DOMAIN_DPLL_DC_OFF);
16758 pll->state.crtc_mask = 0;
16759 for_each_intel_crtc(dev, crtc) {
16760 struct intel_crtc_state *crtc_state =
16761 to_intel_crtc_state(crtc->base.state);
16763 if (crtc_state->base.active &&
16764 crtc_state->shared_dpll == pll)
16765 pll->state.crtc_mask |= 1 << crtc->pipe;
16767 pll->active_mask = pll->state.crtc_mask;
16769 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16770 pll->info->name, pll->state.crtc_mask, pll->on);
16773 for_each_intel_encoder(dev, encoder) {
16776 if (encoder->get_hw_state(encoder, &pipe)) {
16777 struct intel_crtc_state *crtc_state;
16779 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
16780 crtc_state = to_intel_crtc_state(crtc->base.state);
16782 encoder->base.crtc = &crtc->base;
16783 encoder->get_config(encoder, crtc_state);
16785 encoder->base.crtc = NULL;
16788 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16789 encoder->base.base.id, encoder->base.name,
16790 enableddisabled(encoder->base.crtc),
16794 drm_connector_list_iter_begin(dev, &conn_iter);
16795 for_each_intel_connector_iter(connector, &conn_iter) {
16796 if (connector->get_hw_state(connector)) {
16797 connector->base.dpms = DRM_MODE_DPMS_ON;
16799 encoder = connector->encoder;
16800 connector->base.encoder = &encoder->base;
16802 if (encoder->base.crtc &&
16803 encoder->base.crtc->state->active) {
16805 * This has to be done during hardware readout
16806 * because anything calling .crtc_disable may
16807 * rely on the connector_mask being accurate.
16809 encoder->base.crtc->state->connector_mask |=
16810 drm_connector_mask(&connector->base);
16811 encoder->base.crtc->state->encoder_mask |=
16812 drm_encoder_mask(&encoder->base);
16816 connector->base.dpms = DRM_MODE_DPMS_OFF;
16817 connector->base.encoder = NULL;
16819 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16820 connector->base.base.id, connector->base.name,
16821 enableddisabled(connector->base.encoder));
16823 drm_connector_list_iter_end(&conn_iter);
16825 for_each_intel_crtc(dev, crtc) {
16826 struct intel_bw_state *bw_state =
16827 to_intel_bw_state(dev_priv->bw_obj.state);
16828 struct intel_crtc_state *crtc_state =
16829 to_intel_crtc_state(crtc->base.state);
16830 struct intel_plane *plane;
16833 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16834 if (crtc_state->base.active) {
16835 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
16836 crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
16837 crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
16838 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
16839 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16842 * The initial mode needs to be set in order to keep
16843 * the atomic core happy. It wants a valid mode if the
16844 * crtc's enabled, so we do the above call.
16846 * But we don't set all the derived state fully, hence
16847 * set a flag to indicate that a full recalculation is
16848 * needed on the next commit.
16850 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
16852 intel_crtc_compute_pixel_rate(crtc_state);
16854 if (dev_priv->display.modeset_calc_cdclk) {
16855 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
16856 if (WARN_ON(min_cdclk < 0))
16860 drm_calc_timestamping_constants(&crtc->base,
16861 &crtc_state->base.adjusted_mode);
16862 update_scanline_offset(crtc_state);
16865 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
16866 dev_priv->min_voltage_level[crtc->pipe] =
16867 crtc_state->min_voltage_level;
16869 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
16870 const struct intel_plane_state *plane_state =
16871 to_intel_plane_state(plane->base.state);
16874 * FIXME don't have the fb yet, so can't
16875 * use intel_plane_data_rate() :(
16877 if (plane_state->base.visible)
16878 crtc_state->data_rate[plane->id] =
16879 4 * crtc_state->pixel_rate;
16882 intel_bw_crtc_update(bw_state, crtc_state);
16884 intel_pipe_config_sanity_check(dev_priv, crtc_state);
16889 get_encoder_power_domains(struct drm_i915_private *dev_priv)
16891 struct intel_encoder *encoder;
16893 for_each_intel_encoder(&dev_priv->drm, encoder) {
16894 struct intel_crtc_state *crtc_state;
16896 if (!encoder->get_power_domains)
16900 * MST-primary and inactive encoders don't have a crtc state
16901 * and neither of these require any power domain references.
16903 if (!encoder->base.crtc)
16906 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
16907 encoder->get_power_domains(encoder, crtc_state);
16911 static void intel_early_display_was(struct drm_i915_private *dev_priv)
16913 /* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
16914 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
16915 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
16918 if (IS_HASWELL(dev_priv)) {
16920 * WaRsPkgCStateDisplayPMReq:hsw
16921 * System hang if this isn't done before disabling all planes!
16923 I915_WRITE(CHICKEN_PAR1_1,
16924 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
16928 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
16929 enum port port, i915_reg_t hdmi_reg)
16931 u32 val = I915_READ(hdmi_reg);
16933 if (val & SDVO_ENABLE ||
16934 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
16937 DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n",
16940 val &= ~SDVO_PIPE_SEL_MASK;
16941 val |= SDVO_PIPE_SEL(PIPE_A);
16943 I915_WRITE(hdmi_reg, val);
16946 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
16947 enum port port, i915_reg_t dp_reg)
16949 u32 val = I915_READ(dp_reg);
16951 if (val & DP_PORT_EN ||
16952 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
16955 DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n",
16958 val &= ~DP_PIPE_SEL_MASK;
16959 val |= DP_PIPE_SEL(PIPE_A);
16961 I915_WRITE(dp_reg, val);
16964 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
16967 * The BIOS may select transcoder B on some of the PCH
16968 * ports even it doesn't enable the port. This would trip
16969 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
16970 * Sanitize the transcoder select bits to prevent that. We
16971 * assume that the BIOS never actually enabled the port,
16972 * because if it did we'd actually have to toggle the port
16973 * on and back off to make the transcoder A select stick
16974 * (see. intel_dp_link_down(), intel_disable_hdmi(),
16975 * intel_disable_sdvo()).
16977 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
16978 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
16979 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
16981 /* PCH SDVOB multiplex with HDMIB */
16982 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
16983 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
16984 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
16987 /* Scan out the current hw modeset state,
16988 * and sanitizes it to the current state
16991 intel_modeset_setup_hw_state(struct drm_device *dev,
16992 struct drm_modeset_acquire_ctx *ctx)
16994 struct drm_i915_private *dev_priv = to_i915(dev);
16995 struct intel_crtc_state *crtc_state;
16996 struct intel_encoder *encoder;
16997 struct intel_crtc *crtc;
16998 intel_wakeref_t wakeref;
17001 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
17003 intel_early_display_was(dev_priv);
17004 intel_modeset_readout_hw_state(dev);
17006 /* HW state is read out, now we need to sanitize this mess. */
17008 /* Sanitize the TypeC port mode upfront, encoders depend on this */
17009 for_each_intel_encoder(dev, encoder) {
17010 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
17012 /* We need to sanitize only the MST primary port. */
17013 if (encoder->type != INTEL_OUTPUT_DP_MST &&
17014 intel_phy_is_tc(dev_priv, phy))
17015 intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
17018 get_encoder_power_domains(dev_priv);
17020 if (HAS_PCH_IBX(dev_priv))
17021 ibx_sanitize_pch_ports(dev_priv);
17024 * intel_sanitize_plane_mapping() may need to do vblank
17025 * waits, so we need vblank interrupts restored beforehand.
17027 for_each_intel_crtc(&dev_priv->drm, crtc) {
17028 crtc_state = to_intel_crtc_state(crtc->base.state);
17030 drm_crtc_vblank_reset(&crtc->base);
17032 if (crtc_state->base.active)
17033 intel_crtc_vblank_on(crtc_state);
17036 intel_sanitize_plane_mapping(dev_priv);
17038 for_each_intel_encoder(dev, encoder)
17039 intel_sanitize_encoder(encoder);
17041 for_each_intel_crtc(&dev_priv->drm, crtc) {
17042 crtc_state = to_intel_crtc_state(crtc->base.state);
17043 intel_sanitize_crtc(crtc, ctx);
17044 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
17047 intel_modeset_update_connector_atomic_state(dev);
17049 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
17050 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
17052 if (!pll->on || pll->active_mask)
17055 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
17058 pll->info->funcs->disable(dev_priv, pll);
17062 if (IS_G4X(dev_priv)) {
17063 g4x_wm_get_hw_state(dev_priv);
17064 g4x_wm_sanitize(dev_priv);
17065 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17066 vlv_wm_get_hw_state(dev_priv);
17067 vlv_wm_sanitize(dev_priv);
17068 } else if (INTEL_GEN(dev_priv) >= 9) {
17069 skl_wm_get_hw_state(dev_priv);
17070 } else if (HAS_PCH_SPLIT(dev_priv)) {
17071 ilk_wm_get_hw_state(dev_priv);
17074 for_each_intel_crtc(dev, crtc) {
17077 crtc_state = to_intel_crtc_state(crtc->base.state);
17078 put_domains = modeset_get_crtc_power_domains(crtc_state);
17079 if (WARN_ON(put_domains))
17080 modeset_put_power_domains(dev_priv, put_domains);
17083 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
17085 intel_fbc_init_pipe_state(dev_priv);
17088 void intel_display_resume(struct drm_device *dev)
17090 struct drm_i915_private *dev_priv = to_i915(dev);
17091 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
17092 struct drm_modeset_acquire_ctx ctx;
17095 dev_priv->modeset_restore_state = NULL;
17097 state->acquire_ctx = &ctx;
17099 drm_modeset_acquire_init(&ctx, 0);
17102 ret = drm_modeset_lock_all_ctx(dev, &ctx);
17103 if (ret != -EDEADLK)
17106 drm_modeset_backoff(&ctx);
17110 ret = __intel_display_resume(dev, state, &ctx);
17112 intel_enable_ipc(dev_priv);
17113 drm_modeset_drop_locks(&ctx);
17114 drm_modeset_acquire_fini(&ctx);
17117 DRM_ERROR("Restoring old state failed with %i\n", ret);
17119 drm_atomic_state_put(state);
17122 static void intel_hpd_poll_fini(struct drm_device *dev)
17124 struct intel_connector *connector;
17125 struct drm_connector_list_iter conn_iter;
17127 /* Kill all the work that may have been queued by hpd. */
17128 drm_connector_list_iter_begin(dev, &conn_iter);
17129 for_each_intel_connector_iter(connector, &conn_iter) {
17130 if (connector->modeset_retry_work.func)
17131 cancel_work_sync(&connector->modeset_retry_work);
17132 if (connector->hdcp.shim) {
17133 cancel_delayed_work_sync(&connector->hdcp.check_work);
17134 cancel_work_sync(&connector->hdcp.prop_work);
17137 drm_connector_list_iter_end(&conn_iter);
17140 void intel_modeset_driver_remove(struct drm_device *dev)
17142 struct drm_i915_private *dev_priv = to_i915(dev);
17144 flush_workqueue(dev_priv->flip_wq);
17145 flush_workqueue(dev_priv->modeset_wq);
17147 flush_work(&dev_priv->atomic_helper.free_work);
17148 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
17151 * Interrupts and polling as the first thing to avoid creating havoc.
17152 * Too much stuff here (turning of connectors, ...) would
17153 * experience fancy races otherwise.
17155 intel_irq_uninstall(dev_priv);
17158 * Due to the hpd irq storm handling the hotplug work can re-arm the
17159 * poll handlers. Hence disable polling after hpd handling is shut down.
17161 intel_hpd_poll_fini(dev);
17163 /* poll work can call into fbdev, hence clean that up afterwards */
17164 intel_fbdev_fini(dev_priv);
17166 intel_unregister_dsm_handler();
17168 intel_fbc_global_disable(dev_priv);
17170 /* flush any delayed tasks or pending work */
17171 flush_scheduled_work();
17173 intel_hdcp_component_fini(dev_priv);
17175 drm_mode_config_cleanup(dev);
17177 intel_overlay_cleanup(dev_priv);
17179 intel_gmbus_teardown(dev_priv);
17181 destroy_workqueue(dev_priv->flip_wq);
17182 destroy_workqueue(dev_priv->modeset_wq);
17184 intel_fbc_cleanup_cfb(dev_priv);
17188 * set vga decode state - true == enable VGA decode
17190 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
17192 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17195 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17196 DRM_ERROR("failed to read control word\n");
17200 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17204 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17206 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17208 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17209 DRM_ERROR("failed to write control word\n");
17216 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
17218 struct intel_display_error_state {
17220 u32 power_well_driver;
17222 struct intel_cursor_error_state {
17227 } cursor[I915_MAX_PIPES];
17229 struct intel_pipe_error_state {
17230 bool power_domain_on;
17233 } pipe[I915_MAX_PIPES];
17235 struct intel_plane_error_state {
17243 } plane[I915_MAX_PIPES];
17245 struct intel_transcoder_error_state {
17247 bool power_domain_on;
17248 enum transcoder cpu_transcoder;
17261 struct intel_display_error_state *
17262 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17264 struct intel_display_error_state *error;
17265 int transcoders[] = {
17274 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
17276 if (!HAS_DISPLAY(dev_priv))
17279 error = kzalloc(sizeof(*error), GFP_ATOMIC);
17283 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17284 error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2);
17286 for_each_pipe(dev_priv, i) {
17287 error->pipe[i].power_domain_on =
17288 __intel_display_power_is_enabled(dev_priv,
17289 POWER_DOMAIN_PIPE(i));
17290 if (!error->pipe[i].power_domain_on)
17293 error->cursor[i].control = I915_READ(CURCNTR(i));
17294 error->cursor[i].position = I915_READ(CURPOS(i));
17295 error->cursor[i].base = I915_READ(CURBASE(i));
17297 error->plane[i].control = I915_READ(DSPCNTR(i));
17298 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17299 if (INTEL_GEN(dev_priv) <= 3) {
17300 error->plane[i].size = I915_READ(DSPSIZE(i));
17301 error->plane[i].pos = I915_READ(DSPPOS(i));
17303 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17304 error->plane[i].addr = I915_READ(DSPADDR(i));
17305 if (INTEL_GEN(dev_priv) >= 4) {
17306 error->plane[i].surface = I915_READ(DSPSURF(i));
17307 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17310 error->pipe[i].source = I915_READ(PIPESRC(i));
17312 if (HAS_GMCH(dev_priv))
17313 error->pipe[i].stat = I915_READ(PIPESTAT(i));
17316 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
17317 enum transcoder cpu_transcoder = transcoders[i];
17319 if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder])
17322 error->transcoder[i].available = true;
17323 error->transcoder[i].power_domain_on =
17324 __intel_display_power_is_enabled(dev_priv,
17325 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17326 if (!error->transcoder[i].power_domain_on)
17329 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17331 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17332 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17333 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17334 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17335 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17336 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17337 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17343 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17346 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17347 struct intel_display_error_state *error)
17349 struct drm_i915_private *dev_priv = m->i915;
17355 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
17356 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17357 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17358 error->power_well_driver);
17359 for_each_pipe(dev_priv, i) {
17360 err_printf(m, "Pipe [%d]:\n", i);
17361 err_printf(m, " Power: %s\n",
17362 onoff(error->pipe[i].power_domain_on));
17363 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17364 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17366 err_printf(m, "Plane [%d]:\n", i);
17367 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17368 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17369 if (INTEL_GEN(dev_priv) <= 3) {
17370 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17371 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17373 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17374 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17375 if (INTEL_GEN(dev_priv) >= 4) {
17376 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17377 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17380 err_printf(m, "Cursor [%d]:\n", i);
17381 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17382 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17383 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17386 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
17387 if (!error->transcoder[i].available)
17390 err_printf(m, "CPU transcoder: %s\n",
17391 transcoder_name(error->transcoder[i].cpu_transcoder));
17392 err_printf(m, " Power: %s\n",
17393 onoff(error->transcoder[i].power_domain_on));
17394 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17395 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17396 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17397 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17398 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17399 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17400 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);